Clock signal correction method and device, electronic equipment and storage medium

Abstract

The invention discloses a clock signal correction method and device, electronic equipment and a storage medium, and relates to the technical field of signal processing, and the method comprises the steps: obtaining a first duty ratio corresponding to a first clock signal, and carrying out the analysis according to the first duty ratio and a preset duty ratio threshold value, and logic operation indication information corresponding to the first clock signal is determined, that is, a corresponding adjustment mode is determined. In addition, according to the scheme, the first clock signal is subjected to phase delay processing by using the phase adjustment amount indication information, and the second clock signal is obtained. And on the basis of the logic operation indication information, the first clock signal is corrected through the second clock signal and the logic operation indication information, and the corrected first clock signal is obtained. And finally, through the third clock signal, the local clock signal can be accurately corrected, and the influence on the data processing process of the target equipment is avoided.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to a clock signal correction method, device, electronic device, and storage medium. Background Art

[0002] In the field of computer technology, when communicating between a master device and a slave device, due to the insufficient accuracy of the components that generate the clock signal inside the slave device, the master device usually needs to send a data packet to the slave device. The slave device generates a clock signal based on the data packet and then uses the generated clock signal to correct its own local clock signal.

[0003] However, when the data transmission rate is high, the data packets sent by the master device to the slave device may contain errors, causing the slave device to be unable to correctly identify the data packets and thus unable to generate an accurate clock signal, resulting in an inability to accurately correct the local clock signal. Summary of the Invention

[0004] The present application provides a clock signal correction method, device, electronic device, storage medium, and program product to solve the problem of being unable to accurately correct the local clock signal.

[0005] The present application provides a clock signal correction method, comprising:

[0006] In the current cycle, obtaining a first duty cycle corresponding to the first clock signal;

[0007] Determining logic operation indication information corresponding to the first clock signal according to the first duty cycle and a preset duty cycle threshold;

[0008] Obtaining phase adjustment amount indication information corresponding to the first clock signal;

[0009] performing a phase delay operation on the first clock signal according to the phase adjustment amount indication information to generate a second clock signal;

[0010] After performing arithmetic processing corresponding to the logic operation instruction information on the first clock signal and the second clock signal, a third clock signal is generated;

[0011] The local clock signal of the target device is corrected based on the third clock signal.

[0012] The present application also provides a clock signal correction device, comprising:

[0013] An acquisition module, configured to acquire a first duty cycle corresponding to the first clock signal in a current cycle;

[0014] a determination module, configured to determine logic operation indication information corresponding to the first clock signal based on the first duty cycle and a preset duty cycle threshold;

[0015] An acquisition module, configured to acquire phase adjustment amount indication information corresponding to the first clock signal;

[0016] a delay module, configured to perform a phase delay operation on the first clock signal according to the phase adjustment amount indication information to generate a second clock signal;

[0017] an operation module, configured to perform an operation corresponding to the logic operation indication information on the first clock signal and the second clock signal to generate a third clock signal;

[0018] The correction module is configured to correct a local clock signal of the target device based on the third clock signal.

[0019] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned clock signal correction methods when executing the computer program.

[0020] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned clock signal correction methods are implemented.

[0021] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned clock signal correction methods when executed by a processor.

[0022] According to the present application, since the first clock signal may be in an abnormal state, directly correcting the local clock signal of the target device based on the first clock signal may result in inaccurate correction of the local clock signal, thereby affecting the accuracy of data processing on the target device. Since the duty cycle indicates the ratio of the length of the high-level clock signal to the total length of the clock signal within a cycle, a duty cycle that is too large or too small can indicate an inaccurate clock signal. Therefore, the present solution first obtains a first duty cycle corresponding to the first clock signal, then analyzes the first duty cycle and a preset duty cycle threshold to determine logical operation indication information corresponding to the first clock signal, thereby determining the corresponding adjustment method. Furthermore, to reduce costs and improve the ease of adjustment, the present solution does not introduce additional signals or more complex logical processing. Instead, it utilizes the phase adjustment indication information to perform phase delay processing on the first clock signal itself to obtain a second clock signal. Based on the logical operation indication information, a logical operation is then performed on the first and second clock signals to generate a third clock signal. In other words, the first clock signal is corrected using the second clock signal and the logical operation indication information to obtain the corrected first clock signal. Finally, the local clock signal can be accurately corrected by the third clock signal to avoid affecting the data processing process of the target device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1 A schematic diagram of the architecture of a data transmission system provided in an embodiment of the present application;

[0025] Figure 2 A flowchart of a clock signal correction method provided in an embodiment of the present application;

[0026] Figure 3 A schematic diagram of the structure of a USB device provided in an embodiment of the present application;

[0027] Figure 4 A schematic diagram of generating a clock signal provided in an embodiment of the present application;

[0028] Figure 5 A schematic diagram of a circuit structure for correcting a clock signal provided in an embodiment of the present application;

[0029] Figure 6 A schematic diagram of a flow chart of a clock signal correction device provided in an embodiment of the present application;

[0030] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0032] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0033] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0034] The clock signal correction method provided in this application can be implemented by a data transmission system, such as Figure 1 As shown, the data transmission system may include a master device and a slave device. For example, the master device may be a computer device, and the slave device may be a Universal Serial Bus (USB) device. The master and slave devices may communicate via the USB Transceiver Macrocell Interface (UTMI) protocol. The master device is responsible for converting the USB physical layer electrical signals, including parallel-to-serial conversion, bit stuffing, and Non-Return-to-Zero Inverted (NRZI) decoding, and sending data to the USB bus. The slave device is responsible for performing NRZI decoding, bit stuffing removal, and serial-to-parallel conversion on the data to recover the data. Since the slave device generally uses a crystal oscillator as its own clock source to generate a local clock signal, the clock frequency offset is large when the data transmission rate is high. Therefore, to ensure the accuracy of service execution, the master device will periodically send a Start of Frame (SOF) packet to the slave device to synchronize the slave device's local clock signal.

[0035] The embodiment of the present application provides a clock signal correction method, which can be executed by a target device. For example, the target device can be the slave device mentioned above, such as Figure 2 As shown, the specific processing steps of the clock signal correction method may include:

[0036] Step S201: In a current cycle, a first duty cycle corresponding to a first clock signal is obtained.

[0037] Specifically, within the current cycle, the target device can receive a data packet sent by the master device. Each time the target device receives a data packet, it can perform a corresponding detection operation based on the current data transmission mode to determine whether the data packet is a data packet of a preset type. The data packet of the preset type can be a data packet related to a clock signal correction operation. For example, the data packet of the preset type can be the SOF data packet mentioned above. When it is determined that the data packet is a data packet of the preset type, the target device can flip its own reference clock signal, and then detect the lengths of the high-level clock signal and the low-level clock signal in the flipped reference clock signal, respectively. Then, based on the lengths of the high-level clock signal and the low-level clock signal, respectively, the first duty cycle is calculated.

[0038] The above-mentioned process of performing corresponding detection operations according to the current data transmission mode to determine whether the data packet is a data packet of a preset type may specifically include the following steps:

[0039] The total length of a data packet can be 32 bits, including the last 8 bits of valid data in the synchronization (SYNC) field, the 8-bit packet identifier (PID) field, the 11-bit frame number field, and the 5-bit cyclic redundancy check information. The data packet can also include a 2-bit end of packet (EOP) field, which is generally implemented by a change in the bus level signal and does not occupy any bits in the data packet. It is used to indicate the end of data packet transmission in the current frame. The synchronization field can also include 24 bits of padding bits or synchronization auxiliary signals, which do not participate in data calculations.

[0040] When the data transmission mode is full-speed data transmission mode or low-speed data transmission mode, the target device may first determine whether the last 8 bits of the synchronization field of the data packet are "KJKJKJKK". If so, the target device may continue to detect whether the PID field of the data packet is "8'Ha5". If so, it may determine that an SOF data packet has been detected. The period of the full-speed data transmission mode and the low-speed data transmission mode may both be 1 millisecond. The data transmission rate of the full-speed data transmission mode may be 12 Mbps, and the data transmission rate of the low-speed data transmission mode may be 1.5 Mbps.

[0041] When the data transmission mode is high-speed data transmission mode, the target device can determine whether the last 8 bits of the SYNC field of the data packet are "KJKJKJKK". If so, the target device can continue to detect whether the end of packet (EOP) field of the data packet is a preset value. If so, the target device can detect whether the PID field of the data packet is "8'Ha5". If so, it is determined that an SOF packet has been detected. The period of the high-speed data transmission mode can be 125 microseconds, and the data transmission rate of the high-speed data transmission mode can be 480Mbps.

[0042] The process of calculating the first duty cycle may include:

[0043] In the current cycle, the target device can detect the number of high-level clock signals and the number of low-level clock signals generated, and further calculate the length of the high-level clock signal based on the number of high-level clock signals and the preset length of the high-level clock signal, and calculate the length of the low-level clock signal based on the number of low-level clock signals and the preset length of the level signal, and then calculate the total length of the level signal of the current cycle based on the length of the high-level clock signal and the length of the low-level clock signal, and then, the ratio of the length of the high-level clock signal to the total length can be determined as the first duty cycle.

[0044] For example, the first duty cycle can be calculated using the following mathematical expression:

[0045]

[0046] Wherein, t1 is the length of the high-level clock signal, and t2 is the length of the low-level clock signal.

[0047] In some optional implementations, because the content of the data packet is more prone to errors in high-speed data transmission mode, the target device may be unable to accurately detect the correct values of the SYNC and PID fields, which in turn may result in the inability to timely generate a pulse to stimulate the flip of the reference clock signal, resulting in the inability to generate an accurate first clock signal, and ultimately, the inability to accurately correct the local clock signal. Therefore, before step S201, the target device may first determine whether the current data transmission mode is a high-speed data transmission mode. If so, the correction function of the first clock signal may be disabled, and the processing of steps S201 to S206 may not be performed. If not, the processing of steps S201 to S206 may be performed again. In this way, using this solution only in high-speed data transmission mode can save resources.

[0048] Step S202: Determine logic operation indication information corresponding to the first clock signal according to the first duty cycle and a preset duty cycle threshold.

[0049] The preset duty cycle threshold may include a first preset duty cycle threshold and a second preset duty cycle threshold, and the second preset duty cycle threshold may be smaller than the first preset duty cycle threshold. For example, the first preset duty cycle threshold may be 51%, and the second preset duty cycle threshold may be 49%.

[0050] Specifically, the target device may compare the first duty cycle with a preset duty cycle threshold value, and when determining that the first duty cycle is greater than the first preset duty cycle threshold value, use the "AND logic operation indication information" as the logic operation indication information corresponding to the first clock signal. Alternatively, when determining that the first duty cycle is less than a second preset duty cycle threshold value, use the "OR logic operation indication information" as the logic operation indication information corresponding to the first clock signal.

[0051] For example, the logical operation indication information can be a flag bit (Flag). When the flag bit is the first flag bit 1, it is used to indicate an AND logical operation. When the flag bit is the second flag bit 0, it is used to indicate an OR logical operation, where the first flag bit can be 1 and the second flag bit can be 0.

[0052] Since the first duty cycle is greater than the first preset duty cycle threshold, or the second duty cycle is less than the second preset duty cycle threshold, it means that the target device has not correctly detected all SOF packets, resulting in an inaccurate generated clock signal. In order to correct the clock signal so that the clock signal can be restored to an accurate state, it is specifically divided into two situations for processing. That is, when the first duty cycle is greater than the first preset duty cycle threshold, it means that the high-level clock signal accounts for a larger proportion and the low-level clock signal accounts for a smaller proportion. At this time, the "and logic operation indication information" can be used as the logic operation indication information corresponding to the first clock signal. When the first duty cycle is less than the first preset duty cycle threshold, it means that the low-level clock signal accounts for a larger proportion and the high-level clock signal accounts for a smaller proportion. At this time, the "or logic operation indication information" can be used as the logic operation indication information corresponding to the first clock signal.

[0053] In some optional embodiments, when it is determined that the first duty cycle is greater than or equal to a first preset duty cycle threshold and less than a second preset duty cycle threshold, it can be determined that the first clock signal is an accurate clock signal. At this time, the local clock signal of the target device can be corrected directly based on the first clock signal without the need for subsequent processing of the first clock signal.

[0054] The specific operation of correcting the local clock signal of the target device based on the first clock signal may be as follows:

[0055] The internal oscillator of the target device generates a local clock signal. The first frequency division coefficient can be calculated based on the period of the first clock signal and the frequency of the local clock signal, and then the local clock signal can be corrected according to the first frequency division coefficient using its own phase-locked loop (PLL).

[0056] Step S203: Acquire phase adjustment amount indication information corresponding to the first clock signal.

[0057] The phase adjustment amount indication information may be a capacitance load value, and the capacitance load value may be the number of capacitors or a capacitance value, etc.

[0058] Specifically, the target device may obtain the phase adjustment amount indication information corresponding to the first clock signal in the following two ways:

[0059] Method 1: Read the preset first capacitance load value from the target register.

[0060] The first capacitive load value is the phase adjustment amount indication information. The first capacitive load value may be a minimum capacitive load value. For example, when the capacitive load value is the number of capacitors, the first capacitive load value may be 1. When the capacitive load value is a capacitance value, the first capacitive load value may be the capacitance value of a single capacitor.

[0061] Specifically, a preset first capacitive load value can be preconfigured in the target register. Before performing the adjustment operation, the target device can read the first capacitive load value from its own target register. Generally, there is a certain error between the actual duty cycle of the clock signal and the duty cycle specified for the clock signal under normal conditions. However, this error is generally relatively small, and a phase delay with the minimum capacitive load value generally meets the requirements. Therefore, directly reading the first capacitive load value configured in the target register through method 1 is more convenient and can improve efficiency.

[0062] Method 2: determining a target phase difference based on the first duty cycle and a preset second duty cycle, and determining a target capacitive load value corresponding to the target phase difference based on the target phase difference and the correspondence between the phase difference and the capacitive load value.

[0063] The second duty cycle may be a duty cycle corresponding to the clock signal in a normal state, for example, may be 50%.

[0064] Specifically, the target device can multiply the absolute value of the difference between the first duty cycle and the second duty cycle by the cycle length to obtain a target phase difference (also called time delay). The target device can store a correspondence between the phase difference and the capacitance load value. After determining the target phase difference, the target capacitance load value can be determined based on the correspondence and the target phase difference. In this way, the target phase difference is directly determined by the actual first duty cycle and the duty cycle to be achieved. Based on this, the accurate target capacitance load value can be directly found. Based on the accurate target capacitance load value, the correction can be completed at one time without the need for verification operations and iterative adjustment operations, which can save resources and improve processing efficiency.

[0065] For example, the correspondence can be a correspondence table, which includes multiple phase differences and the capacitance load value corresponding to each phase difference. The target device can compare the target phase difference with each phase difference included in the correspondence table, and select the phase difference closest to the target phase difference from the correspondence table, and then determine the capacitance load value corresponding to the phase difference closest to the target phase difference as the target capacitance load value.

[0066] For another example, the corresponding relationship can be a mathematical expression. The target device can substitute the target phase difference into the mathematical expression and round the result to obtain the target capacitance load value. The target capacitance load value is the phase adjustment amount indication information. The mathematical expression can be the relationship between the delay time of a single capacitor, the phase difference, and the number of capacitors. The delay time of each capacitor is fixed. Therefore, after determining the target phase difference, the ratio of the target phase difference to the delay time of a single capacitor can be rounded to obtain the required number of capacitors, which is the target capacitance load value. The mathematical expression can be expressed as n=Round(T / t), where n is the number of capacitors, T is the phase difference, and t is the delay time of a single capacitor. Under this method, the target device only needs to store one mathematical expression to calculate the capacitance load values corresponding to all phase differences, which can save storage resources and is suitable for USB devices. When the target phase difference is 4ns and t is 2ns, the target capacitance load value is 2.

[0067] Step S204 : performing a phase delay operation on the first clock signal according to the phase adjustment amount indication information to generate a second clock signal.

[0068] Specifically, the target device may include a delay unit in its own circuit, and use the delay unit to perform a phase delay operation on the first clock signal according to the following steps. The delay unit may be a capacitor, an inductor, or other electronic components capable of performing phase delay.

[0069] The following description will be made by taking the delay unit as a capacitor as an example.

[0070] Step 1: Select a candidate capacitor corresponding to the phase adjustment amount indication information from at least one capacitor according to the phase adjustment amount indication information, and control each candidate capacitor to be in an on state.

[0071] Step 2: Process the first clock signal using each candidate capacitor in turn to generate a second clock signal.

[0072] The phase adjustment amount indication information may be a capacitance load value, for example, the capacitance load value may be the number of capacitors.

[0073] When the capacitance load value is the number of capacitors, the target device can select a number of candidate capacitors equal to the number of capacitors from at least one capacitor based on the number of capacitors, control each candidate capacitor to be in an on state, and use each candidate capacitor in turn to process the first clock signal to generate a second clock signal.

[0074] Specifically, when the phase adjustment amount indication information is the number of capacitors, the target device can select a number of candidate capacitors equal to the number of capacitors from at least one capacitor included in the target device (i.e., select candidate capacitors corresponding to the phase adjustment amount indication information), turn on the switch corresponding to each candidate capacitor, and connect the candidate capacitors to the first transmission link. In this way, the target device can input the first clock signal into the first transmission link, and after being processed by each candidate capacitor in the first transmission link, it can generate a second clock signal.

[0075] Alternatively, when the capacitance load value is a capacitance value, the target device can select a capacitor with a load value equal to the capacitance value as a candidate capacitor based on the capacitance value, and control the candidate capacitor to be in an on state, and use the candidate capacitor to process the first clock signal to generate a second clock signal.

[0076] In this way, after phase delaying the first clock signal, a second clock signal with an accurate duty cycle can be obtained, which facilitates subsequent adjustment of the first clock signal based on the second clock signal and logic operation indication information to generate an accurate third clock signal.

[0077] In some optional embodiments, the capacitors in the target device may be in the form of a binary metal capacitor array. Since the binary metal capacitor array has high precision and is less affected by process angle and temperature changes, the reliability of the circuit is improved, and the phase of the clock signal can be accurately adjusted.

[0078] Step S205 , performing arithmetic processing corresponding to the logic operation instruction information on the first clock signal and the second clock signal to generate a third clock signal.

[0079] Specifically, the target device may input the first clock signal and the second clock signal into a logic gate circuit corresponding to the logic operation indication information, and generate a third clock signal after performing a logic operation on the first clock signal and the second clock signal using the logic gate circuit corresponding to the logic operation indication information. Accordingly, step S205 may include the following steps:

[0080] Step 1: According to the logic operation indication information, a logic gate circuit corresponding to the logic operation indication information is selected from a plurality of logic gate circuits.

[0081] Step 2: Using a logic gate circuit corresponding to the logic operation indication information, perform operation processing on the first clock signal and the second clock signal to generate a third clock signal.

[0082] Specifically, the target device can select a logic gate circuit corresponding to the logic operation instruction information from multiple logic gate circuits based on the logic operation instruction information, and control the activation of the logic gate circuit corresponding to the logic operation instruction information. For example, the switch of the logic gate circuit corresponding to the logic operation instruction information can be turned on. In this way, when the logic operation instruction information is "AND logic operation instruction information," the target device can use the "AND logic gate circuit" to perform an AND logic operation on the first clock signal and the second clock signal to generate a third clock signal. Alternatively, when the logic operation instruction information is "OR logic operation instruction information," the target device can use the "OR logic gate circuit" to perform an OR logic operation on the first clock signal and the second clock signal to generate a third clock signal.

[0083] Step S206: Correct the local clock signal of the target device based on the third clock signal.

[0084] Specifically, the internal oscillator of the target device generates a local clock signal, and the second frequency division coefficient can be calculated according to the period of the third clock signal and the frequency of the local clock signal, and then the local clock signal is corrected according to the second frequency division coefficient using its own phase-locked loop.

[0085] In some optional implementations, since the phase adjustment amount indication information obtained through the above-described method 1 is a fixed value, the duty cycle of the clock signal may vary significantly in different cycles. The clock signal generated after selecting the candidate capacitor to process the clock signal using the fixed first capacitance load value may not necessarily be accurately corrected. Therefore, the target device may further verify the processed clock signal to ensure that the first clock signal is accurately corrected before correcting the local clock signal. Accordingly, the target device may perform the following steps:

[0086] Step 1: Obtain a third duty cycle corresponding to the third clock signal.

[0087] Step 2: Determine whether the first clock signal fails to be corrected based on the third duty cycle, the first preset duty cycle threshold, and the second preset duty cycle threshold.

[0088] Step three: when it is determined that the first clock signal calibration fails, the first capacitance load value is adjusted to a preset value to obtain a second capacitance load value, so as to re-perform the clock signal calibration operation on the first clock signal.

[0089] Step 4: until it is determined that the first clock signal is successfully corrected, the local clock signal is corrected based on the successfully corrected clock signal.

[0090] The preset value may be a minimum capacitance load value. For example, when the first capacitance load value is the number of capacitors, the preset value may be 1.

[0091] Specifically, the target device can detect the length of the high-level clock signal in the third clock signal, and then determine the ratio between the length of the high-level clock signal and the length of the third clock signal as the third duty cycle. Then, the target device can determine whether the third duty cycle is less than or equal to the first preset duty cycle threshold, and whether the third duty cycle is greater than or equal to the second preset duty cycle threshold. If the third duty cycle is less than or equal to the first preset duty cycle threshold, and the third duty cycle is greater than or equal to the second preset duty cycle threshold, the target device can determine that the first clock signal has been successfully corrected, and the local clock signal can be directly corrected based on the third clock signal. If the third duty cycle is greater than the first preset duty cycle threshold, and the third duty cycle is less than the second preset duty cycle threshold, it can be determined that the first clock signal has failed to be corrected, and further subsequent adjustment operations need to be performed.

[0092] In the event of a calibration failure, if the first duty cycle is greater than the first preset duty cycle threshold and the third duty cycle is also greater than the first preset duty cycle threshold, or if the first duty cycle is less than the second preset duty cycle threshold and the third duty cycle is also less than the first preset duty cycle threshold, the adjustment direction is correct and the target device can add the preset value to the first capacitive load value to obtain the second capacitive load value. If the first duty cycle is less than the second preset duty cycle threshold and the third duty cycle is also less than the first preset duty cycle threshold, the target device can add the preset value to the first capacitive load value to obtain the second capacitive load value.

[0093] When the first duty cycle is greater than the first preset duty cycle threshold and the third duty cycle is less than the first preset duty cycle threshold, or the first duty cycle is less than the first preset duty cycle threshold and the third duty cycle is greater than the first preset duty cycle threshold, it indicates that the first capacitive load value is too large, and the target device can reduce the first capacitive load value by a preset value, or reduce it by half to obtain a second capacitive load value.

[0094] In this way, the target device can select a number of candidate capacitors equal to the second capacitance load value based on the second capacitance load value, activate the candidate capacitors, re-phase-delay the first clock signal, and perform the operation corresponding to the logic operation indication information based on the clock signal after the re-phase delay and the first clock signal, re-complete the correction operation of the first clock signal, and verify the corrected first clock signal again. If it is determined that the first clock signal still fails to be corrected, the second capacitance load value can be adjusted to a preset value and the correction operation of the first clock signal can be performed again. This process is repeated until it is determined that the first clock signal has been successfully corrected, and the local clock signal is corrected using the successfully corrected first clock signal.

[0095] In the clock signal correction method of the embodiments of the present application, since the first clock signal may be in an abnormal state, directly correcting the local clock signal of the target device based on the first clock signal may result in inaccurate correction of the local clock signal, thereby affecting the accuracy of data processing on the target device. Since the duty cycle indicates the ratio of the length of the high-level clock signal to the total length of the clock signal within a cycle, a duty cycle that is too large or too small can indicate an inaccurate clock signal. Therefore, this solution first obtains a first duty cycle corresponding to the first clock signal, then analyzes the first duty cycle and a preset duty cycle threshold to determine the logical operation indication information corresponding to the first clock signal, thereby determining the corresponding adjustment method. Furthermore, to reduce costs and improve the ease of adjustment, this solution does not introduce additional signals or more complex logical processing. Instead, it utilizes the phase adjustment indication information to perform phase delay processing on the first clock signal itself to obtain a second clock signal. Based on the logical operation indication information, a logical operation is then performed on the first and second clock signals to generate a third clock signal. In other words, the first clock signal is corrected using the second clock signal and the logical operation indication information to obtain the corrected first clock signal. Finally, the local clock signal can be accurately corrected by the third clock signal to avoid affecting the data processing process of the target device.

[0096] like Figure 3As shown, a USB device may include multiple hardware modules, including a SOF packet detection module, a clock recovery module, a clock check module, a duty cycle calculation module, an internal oscillator, a clock multiplication module, and a control logic module. The following describes in detail how a USB device utilizes these multiple hardware modules to implement the aforementioned clock signal correction method.

[0097] First, when the SOF packet detection module receives the data packet sent by the main device through the positive differential (DP) signal line and the negative differential (DM) signal line of the USB interface, it can first detect whether the data packet is a SOF data packet. If it is, it can send a pulse to the clock recovery module. After the numerical recovery module detects the pulse, it flips the reference clock signal and sends the flipped reference clock signal to the clock verification module. The clock verification module sends the flipped reference clock signal (hereinafter referred to as the first clock signal) to the duty cycle calculation module. Figure 4 As shown, the upper part is the reference clock signal, and the lower part is the pulse generated when the SOF packet is detected. It can be seen that each time a SOF packet is detected, a pulse is generated, and the reference clock signal changes from a high level to a low level, or from a low level to a high level.

[0098] Then, the duty cycle calculation module calculates the first duty cycle of the first clock signal in the current cycle in the manner of calculating the first duty cycle in step S201. When it is determined that the first duty cycle is greater than the first preset duty cycle threshold, a first flag bit can be sent to the clock verification module. Alternatively, when it is determined that the duty cycle of the reference clock signal in the current cycle is less than the first preset duty cycle threshold, a second flag bit is sent to the clock verification module. The clock verification module can obtain the number of capacitors from the register and connect a number of capacitors equal to the obtained number of capacitors to the first transmission link. Based on the received flag bit, a phase adjustment operation corresponding to the flag bit is performed on the input reference clock signal to generate a clock signal after the phase is adjusted.

[0099] For example, the clock check module may include Figure 5 The circuit structure for correcting the clock signal shown includes a first clock buffer, a second clock buffer, a third clock buffer, a fourth clock buffer, an AND logic gate circuit, an OR logic gate circuit, a multiplexer (MUX), a capacitor array (including at least one capacitor, Figure 5In the figure, a capacitor array including three capacitors is used as an example for demonstration), and multiple switches are provided. One end of the switch is grounded, and the other end is connected to a capacitor in the capacitor array. The first clock buffer is connected to the second clock buffer, the second clock buffer is connected to an "OR logic gate circuit", the "OR logic gate circuit" is connected to a multiplexer, the third clock buffer is connected to the left side of the capacitor array, the right side of the capacitor array is connected to an "AND logic gate circuit", and the "AND logic gate circuit" is connected to the multiplexer.

[0100] In such Figure 5 In the circuit structure for correcting clock signals shown, when the clock verification module receives a flag bit and determines that the received flag bit is the first flag bit, it connects the link corresponding to the "AND logic gate circuit" in the multiplexer. When the clock verification module receives a flag bit and determines that the received flag bit is the second flag bit, it connects the link corresponding to the "OR logic gate circuit" in the multiplexer. Thus, when the link corresponding to the "AND logic gate circuit" in the multiplexer is connected, the first clock signal passes through the first clock buffer, the second clock buffer, and then the "AND logic gate circuit." Simultaneously, the first clock signal passes through the third clock buffer, the capacitors in the capacitor array whose switches are turned on, and the fourth clock buffer, becoming the second clock signal. The signal then enters the "AND logic gate circuit," which then completes the AND logic operation on the first and second clock signals to generate a third clock signal. Alternatively, when the link corresponding to the "OR logic gate circuit" in the multiplexer is connected, the first clock signal passes through the first clock buffer, the second clock buffer, and then the "OR logic gate circuit". At the same time, the first clock signal passes through the third clock buffer, the capacitor with the switch connected in the capacitor array, and the fourth clock buffer to become the second clock signal, and enters the "OR logic gate circuit". The "OR logic gate circuit" can complete the OR logic operation processing of the first clock signal and the second clock signal to generate a third clock signal.

[0101] The clock check module outputs the third clock signal after the logic operation to the clock multiplication module. The internal oscillator generates a local clock signal and then inputs the local clock signal into the clock multiplication module. The clock multiplication mode corrects the local clock signal based on the third clock signal after the logic operation and transmits the corrected local clock signal to the control logic module for data processing, such as data transmission and reception.

[0102] The function of each of the above-mentioned clock buffers is to enhance the clock signal or distribute the clock signal to different parts without affecting the phase of the clock signal.

[0103] The clock signal correction method of the embodiment of the present application divides different functions into different modules for processing through various functional modules, which is convenient for debugging and maintenance. In addition, based on the comparison result of the first duty cycle with the preset threshold, the appropriate logical operation (AND, OR) is automatically selected, which can flexibly respond to different duty cycle deviations, thereby improving the correction efficiency and accuracy. In addition, by switching different logic gate circuit links through a multiplexer, it can quickly respond to different correction requirements, simplifying the circuit design and improving flexibility.

[0104] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0105] The embodiment of the present application also provides a clock signal correction device, such as Figure 6 As shown, including:

[0106] An acquisition module 610 is configured to acquire a first duty cycle corresponding to a first clock signal in a current cycle;

[0107] a determination module 620, configured to determine logic operation indication information corresponding to the first clock signal based on the first duty cycle and a preset duty cycle threshold;

[0108] An acquisition module 610 is configured to acquire phase adjustment amount indication information corresponding to the first clock signal;

[0109] The delay module 630 is configured to perform a phase delay operation on the first clock signal according to the phase adjustment amount indication information to generate a second clock signal;

[0110] An operation module 640 is configured to perform an operation corresponding to the logic operation indication information on the first clock signal and the second clock signal to generate a third clock signal;

[0111] The correction module 650 is configured to correct the local clock signal of the target device based on the third clock signal.

[0112] In some optional embodiments, the preset duty cycle threshold includes a first preset duty cycle threshold and a second preset duty cycle threshold, and the second preset duty cycle threshold is smaller than the first preset duty cycle threshold;

[0113] The determination module 620 is specifically configured to:

[0114] When it is determined that the first duty cycle is greater than a first preset duty cycle threshold, using the logical operation indication information as the logical operation indication information corresponding to the first clock signal;

[0115] or,

[0116] When it is determined that the first duty cycle is less than the second preset duty cycle threshold, the OR logic operation indication information is used as the logic operation indication information corresponding to the first clock signal.

[0117] In some optional implementations, the acquisition module 610 is specifically configured to:

[0118] A preset first capacitance load value is read from the target register, wherein the first capacitance load value is phase adjustment amount indication information.

[0119] In some optional implementations, the acquisition module 610 is specifically configured to:

[0120] Determining a target phase difference according to the first duty cycle and a preset second duty cycle, wherein the second duty cycle is a duty cycle corresponding to the clock signal in a normal state;

[0121] According to the target phase difference and the corresponding relationship between the phase difference and the capacitive load value, a target capacitive load value corresponding to the target phase difference is determined, wherein the target capacitive load value is the phase adjustment amount indication information.

[0122] In some optional implementations, the delay module 630 is specifically configured to:

[0123] selecting, according to the phase adjustment amount indication information, a candidate capacitor corresponding to the phase adjustment amount indication information from at least one capacitor, and controlling each candidate capacitor to be in an on state;

[0124] The first clock signal is processed in sequence using each candidate capacitor to generate a second clock signal.

[0125] In some optional implementations, the operation module 640 is specifically configured to:

[0126] According to the logic operation indication information, selecting a logic gate circuit corresponding to the logic operation indication information from a plurality of logic gate circuits;

[0127] The first clock signal and the second clock signal are processed by a logic gate circuit corresponding to the logic operation indication information to generate a third clock signal.

[0128] In some optional implementations, the acquisition module 610 is further configured to acquire a third duty cycle corresponding to the third clock signal;

[0129] The determination module 620 is further configured to determine whether the first clock signal fails to be corrected based on the third duty cycle, the first preset duty cycle threshold, and the second preset duty cycle threshold;

[0130] The correction module 650 is also used to adjust the first capacitance load value to a preset value to obtain a second capacitance load value when it is determined that the correction of the first clock signal fails, so as to re-perform the clock signal correction operation on the first clock signal; until it is determined that the first clock signal is successfully corrected, the local clock signal is corrected based on the successfully corrected clock signal.

[0131] The acquisition module 610, determination module 620, delay module 630, operation module 640, and correction module 650 can be Figure 3 The SOF packet detection module, clock recovery module, clock verification module, duty cycle calculation module, internal oscillator, clock multiplication module, and multiple modules in the control logic module are re-divided and renamed.

[0132] For the description of the features in the embodiment corresponding to the clock signal correction device, please refer to the relevant description of the embodiment corresponding to the clock signal correction method, and no further details will be given here.

[0133] The embodiment of the present application also provides an electronic device, such as Figure 7 As shown, it includes a memory 10 and a processor 20. The memory 10 stores a computer program, and the processor 20 is configured to run the computer program to execute the steps in any of the above-mentioned clock signal correction method embodiments. The electronic device can be the above-mentioned slave device.

[0134] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned clock signal correction method embodiments when run.

[0135] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0136] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned clock signal correction method embodiments are implemented.

[0137] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, implementing the steps in any of the above-mentioned clock signal correction method embodiments.

[0138] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0139] The above is a detailed introduction to a clock signal correction method, device, electronic device, storage medium, and program product provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A clock signal correction method, characterized in that: include: In the current cycle, obtaining a first duty cycle corresponding to the first clock signal; determining logic operation indication information corresponding to the first clock signal according to the first duty cycle and a preset duty cycle threshold; Acquire phase adjustment amount indication information corresponding to the first clock signal; performing a phase delay operation on the first clock signal according to the phase adjustment amount indication information to generate a second clock signal; After performing a calculation corresponding to the logic operation instruction information on the first clock signal and the second clock signal, a third clock signal is generated; A local clock signal of the target device is corrected based on the third clock signal.

2. The clock signal correction method according to claim 1, wherein: The preset duty cycle threshold includes a first preset duty cycle threshold and a second preset duty cycle threshold, wherein the second preset duty cycle threshold is smaller than the first preset duty cycle threshold; The determining, according to the first duty cycle and a preset duty cycle threshold, logic operation indication information corresponding to the first clock signal includes: When it is determined that the first duty cycle is greater than a first preset duty cycle threshold, using the logic operation indication information as the logic operation indication information corresponding to the first clock signal; or, When it is determined that the first duty cycle is less than a second preset duty cycle threshold, the OR logic operation indication information is used as the logic operation indication information corresponding to the first clock signal.

3. The clock signal correction method according to claim 2, wherein: The acquiring phase adjustment amount indication information corresponding to the first clock signal includes: A preset first capacitance load value is read from the target register, wherein the first capacitance load value is the phase adjustment amount indication information.

4. The clock signal correction method according to claim 1, wherein: The acquiring phase adjustment amount indication information corresponding to the first clock signal includes: Determining a target phase difference according to the first duty cycle and a preset second duty cycle, wherein the second duty cycle is a duty cycle corresponding to the clock signal in a normal state; According to the target phase difference and the corresponding relationship between the phase difference and the capacitive load value, a target capacitive load value corresponding to the target phase difference is determined, wherein the target capacitive load value is the phase adjustment amount indication information.

5. The clock signal correction method according to any one of claims 1 to 4, characterized in that: The generating a second clock signal after performing a phase delay operation on the first clock signal according to the phase adjustment amount indication information includes: selecting, according to the phase adjustment amount indication information, a candidate capacitor corresponding to the phase adjustment amount indication information from at least one capacitor, and controlling each of the candidate capacitors to be in an on state; The first clock signal is processed in sequence using each of the candidate capacitors to generate the second clock signal.

6. The clock signal correction method according to any one of claims 1 to 4, characterized in that: The step of performing the operation corresponding to the logic operation indication information on the first clock signal and the second clock signal to generate a third clock signal includes: According to the logic operation indication information, selecting a logic gate circuit corresponding to the logic operation indication information from a plurality of logic gate circuits; The first clock signal and the second clock signal are processed by a logic gate circuit corresponding to the logic operation indication information to generate the third clock signal.

7. The clock signal correction method according to claim 3, wherein: After performing the operation corresponding to the logic operation instruction information on the first clock signal and the second clock signal to generate a third clock signal, the method further includes: Acquire a third duty cycle corresponding to the third clock signal; determining whether correction of the first clock signal fails according to the third duty cycle, the first preset duty cycle threshold, and the second preset duty cycle threshold; When it is determined that the first clock signal correction fails, adjusting the first capacitive load value by a preset value to obtain a second capacitive load value for re-performing a clock signal correction operation on the first clock signal; When it is determined that the first clock signal is successfully corrected, the local clock signal is corrected based on the successfully corrected clock signal.

8. A clock signal correction device, characterized in that: include: An acquisition module, configured to acquire a first duty cycle corresponding to the first clock signal in a current cycle; a determining module, configured to determine logic operation indication information corresponding to the first clock signal according to the first duty cycle and a preset duty cycle threshold; The acquisition module is configured to acquire phase adjustment amount indication information corresponding to the first clock signal; a delay module, configured to perform a phase delay operation on the first clock signal according to the phase adjustment amount indication information to generate a second clock signal; an operation module, configured to perform an operation corresponding to the logic operation instruction information on the first clock signal and the second clock signal to generate a third clock signal; A correction module is configured to correct a local clock signal of the target device based on the third clock signal.

9. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the clock signal correction method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the clock signal correction method according to any one of claims 1 to 7 are implemented.

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