Processor, processor control method, electronic device and storage medium

Abstract

The invention discloses a processor, a processor control method, electronic equipment and a storage medium. The processor comprises a first instruction processing unit group which comprises at least one instruction processing unit; the control module is configured to generate control signals, the control signals comprise a first control signal or a second control signal, and the first control signal is generated based on instruction flow; and the isolation and power supply module is configured to control the at least one instruction processing unit to be in a working state or a non-working state under the control of the control signal. The processor can improve the instruction processing capability, and gives consideration to both performance and power consumption.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a processor, a method for controlling a processor, an electronic device, and a storage medium. Background Art

[0002] The processor uses parallel processing units and architecture to achieve high-performance parallel computing, and its application range is wide, for example, it can be applied to scientific exploration, engineering and business research, and AI (Artificial Intelligence) fields.

[0003] Processors typically use their ability to process IEEE (Institute of Electrical and Electronics Engineers) floating-point numbers as a technical indicator. Processors can run various instructions, such as the Fused Multiply-Add Compute (FMAC) instruction. The instruction processing capacity of each compute node, or processor, is a bottleneck for high-performance computing. Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a processor, comprising: a first instruction processing unit group, comprising at least one instruction processing unit; a control module, configured to generate a control signal, wherein the control signal comprises a first control signal or a second control signal, and the first control signal is generated based on instruction flow; an isolation and power supply module, configured to control the at least one instruction processing unit to be in a working state or a non-working state under the control of the control signal.

[0005] For example, in the processor provided in at least some embodiments of the present disclosure, the isolation and power supply module includes: a power supply submodule configured to provide a power supply signal or not provide the power supply signal to the at least one instruction processing unit under the control of the control signal.

[0006] For example, in the processor provided in at least some embodiments of the present disclosure, the isolation and power supply module further includes an isolation sub-module, and after the power supply sub-module provides the power supply signal under the control of the control signal, the isolation sub-module is in an on state under the control of the control signal, so that the at least one instruction processing unit is in the working state; after the isolation sub-module is in a disconnected state under the control of the control signal, the power supply sub-module stops providing the power supply signal to the at least one instruction processing unit under the control of the control signal, wherein the at least one instruction processing unit is in the non-working state when the isolation sub-module is in the disconnected state.

[0007] For example, in the processor provided in at least some embodiments of the present disclosure, the isolation and power supply module further includes an isolation sub-module, and the isolation sub-module includes at least one isolation unit corresponding one-to-one to the at least one instruction processing unit. Each of the at least one isolation units receives the control signal and, under the control of the control signal, controls the corresponding instruction processing unit to be in a working state or a non-working state.

[0008] For example, the processor provided by at least some embodiments of the present disclosure also includes: a configuration module, configured to set the processor to a first operating mode or a second operating mode, wherein, in the first operating mode, the control module is configured to generate the first control signal based on the instruction flow, and the isolation and power supply module controls the at least one instruction processing unit to be in the working state or the non-working state under the control of the first control signal; in the second operating mode, the control module is configured to generate the second control signal, and the isolation and power supply module controls the at least one instruction processing unit to be in the working state under the control of the second control signal.

[0009] For example, the processor provided by at least some embodiments of the present disclosure also includes: a judgment module, configured to judge whether the processor exits the second working mode, wherein, when the judgment module determines that the processor does not exit the second working mode, the at least one instruction processing unit remains in the working state; when the judgment module determines that the processor exits the second working mode, in response to the at least one instruction processing unit completing the execution of the current instruction, the at least one instruction processing unit changes from the working state to the non-working state.

[0010] For example, the processor provided by at least some embodiments of the present disclosure also includes: a flow standard signal determination module, configured to determine the value of the flow standard signal according to the instruction flow in response to the processor being set to be in the first working mode, wherein the control module is configured to: in response to the value of the flow standard signal being a first value, set the value of the first control signal to a first control value, wherein, when the value of the first control signal is the first control value, the isolation and power supply module controls the at least one instruction processing unit to be in the working state under the control of the first control signal; the control module is also configured to: in response to the value of the flow standard signal being a second value, set the value of the first control signal to a second control value, wherein, when the value of the first control signal is the second control value, the isolation and power supply module controls the at least one instruction processing unit to be in the non-working state under the control of the first control signal.

[0011] For example, the processor provided by at least some embodiments of the present disclosure further includes: a detection module configured to detect, in response to the processor being in the first operating mode, multiple instruction flows corresponding to the multiple moments at multiple moments.

[0012] For example, in the processor provided in at least some embodiments of the present disclosure, the traffic compliance signal determination module includes: a calculation submodule, configured to calculate the number of clock cycles of at least one target clock cycle within multiple clock cycles based on the instruction traffic, wherein the number of instruction processing units required to be used for each of the at least one target clock cycle is greater than a unit number threshold; a comparison submodule, configured to compare the number of clock cycles with a first threshold to obtain a comparison result; and a setting submodule, configured to set the value of the traffic compliance signal according to the comparison result.

[0013] For example, in the processor provided by at least some embodiments of the present disclosure, the setting submodule includes: a first judgment unit, configured to obtain the current value of the first counter in response to the comparison result indicating that the number of clock cycles is greater than or equal to the first threshold, and determine the size relationship between the current value of the first counter and the second threshold; a first setting unit, configured to add a first value to the current value of the first counter to obtain an updated value in response to the current value of the first counter being less than the second threshold, wherein the first value is a positive integer; when it is determined that the updated value is equal to the second threshold, setting the value of the flow standard signal to the first value, wherein the initial value of the first counter is 0; in response to the current value of the first counter being greater than or equal to the second threshold or when it is determined that the updated value is not equal to the second threshold, keeping the value of the flow standard signal unchanged.

[0014] For example, in the processor provided in at least some embodiments of the present disclosure, the setting submodule also includes: a second judgment unit, configured to obtain the current value of the second counter in response to the comparison result indicating that the number of clock cycles is less than the first threshold, and determine the size relationship between the current value of the second counter and 0; a second setting unit, configured to subtract a second value from the current value of the second counter in response to the current value of the second counter being greater than 0 to obtain an updated value, wherein the initial value of the second counter is p, p is a positive integer, and the updated value is not less than 0; when it is determined that the updated value is equal to 0, setting the value of the flow standard signal to the second value; in response to the current value of the second counter being equal to 0 or when it is determined that the updated value is greater than 0, keeping the value of the flow standard signal unchanged.

[0015] For example, the processor provided by at least some embodiments of the present disclosure further includes: a decoding unit configured to determine the number of instructions to obtain the instruction flow.

[0016] For example, the processor provided by at least some embodiments of the present disclosure further includes: a second instruction processing unit group, wherein the second instruction processing unit group includes N instruction processing units, N is a positive integer, and the N instruction processing units are always in working state.

[0017] For example, in the processor provided by at least some embodiments of the present disclosure, all instruction processing units in the first instruction processing unit group are used to process the same type of instructions.

[0018] At least some embodiments of the present disclosure also provide a method for controlling a processor, wherein the processor includes a first instruction processing unit group, wherein the first instruction processing unit group includes at least one instruction processing unit, and the control method includes: generating a control signal, wherein the control signal includes a first control signal or a second control signal, and the first control signal is generated based on instruction flow; and controlling the at least one instruction processing unit to be in a working state or a non-working state through the control signal.

[0019] For example, in the control method provided in at least some embodiments of the present disclosure, the processor also includes an isolation and power supply module, and the isolation and power supply module includes a power supply sub-module and an isolation sub-module. The controlling of the at least one instruction processing unit to be in a working state or a non-working state by the control signal includes: after controlling the power supply sub-module to provide a power supply signal by the control signal, controlling the isolation sub-module to be in an on state by the control signal to put the at least one instruction processing unit in the working state, or after controlling the isolation sub-module to be in a disconnected state by the control signal, controlling the power supply sub-module to stop providing the power supply signal to the at least one instruction processing unit by the control signal to put the at least one instruction processing unit in the non-working state.

[0020] For example, the control method provided by at least some embodiments of the present disclosure also includes: setting the processor to a first working mode or a second working mode, wherein generating a control signal includes: in the first working mode, generating the first control signal based on the instruction flow; and in the second working mode, generating the second control signal; controlling the at least one instruction processing unit to be in the working state or the non-working state through the control signal includes: in the first working mode, controlling the at least one instruction processing unit to be in the working state or the non-working state through the first control signal; and in the second working mode, controlling the at least one instruction processing unit to be in the working state through the second control signal.

[0021] For example, the control method provided by at least some embodiments of the present disclosure also includes: judging whether the processor exits the second working mode, determining that the processor does not exit the second working mode, and maintaining the at least one instruction processing unit in the working state; determining that the processor exits the second working mode, and in response to the at least one instruction processing unit completing the execution of the current instruction, controlling the at least one instruction processing unit to change from the working state to the non-working state.

[0022] For example, in the control method provided in at least some embodiments of the present disclosure, in the first working mode, a first control signal is generated based on the instruction flow, including: determining the value of a flow compliance signal according to the instruction flow; in response to the value of the flow compliance signal being a first value, setting the value of the first control signal to a first control value, wherein, when the value of the first control signal is the first control value, the at least one instruction processing unit is in the working state under the control of the first control signal; in response to the value of the flow compliance signal being a second value, setting the value of the first control signal to a second control value, wherein, when the value of the first control signal is the second control value, the at least one instruction processing unit is in the non-working state under the control of the first control signal.

[0023] For example, in the control method provided in at least some embodiments of the present disclosure, in the first working mode, the at least one instruction processing unit is controlled to be in the working state or the non-working state by the first control signal, including: at a first moment, detecting and obtaining a first instruction flow, taking the first instruction flow as the instruction flow, and setting the value of a first flow compliance signal according to the instruction flow; in response to the value of the first flow compliance signal being a first value, using the first control signal to control the at least one instruction processing unit to be in the working state; in response to the value of the first flow compliance signal being a second value, using the first control signal to control the at least one instruction processing unit to be in the non-working state.

[0024] For example, in the control method provided in at least some embodiments of the present disclosure, in the first working mode, the first control signal is used to control the at least one instruction processing unit to be in the working state or the non-working state, and also includes: at a second moment, detecting and obtaining a second instruction flow, and using the second instruction flow as the instruction flow, wherein the second moment is after the first moment, and according to the instruction flow, setting the value of the second flow standard signal, in response to the value of the second flow standard signal being the first value, using the first control signal to control the at least one instruction processing unit to be in the working state; in response to the value of the second flow standard signal being the second value, after the at least one instruction processing unit completes the execution of the current instruction, controlling the at least one instruction processing unit to be in the non-working state.

[0025] For example, in the control method provided in at least some embodiments of the present disclosure, determining the value of the flow compliance signal based on the instruction flow includes: calculating the number of clock cycles of at least one target clock cycle within multiple clock cycles based on the instruction flow, wherein the number of instruction processing units required to be used for each of the at least one target clock cycle is greater than a unit number threshold; setting a first threshold; comparing the number of clock cycles and the first threshold to obtain a comparison result; and setting the value of the flow compliance signal based on the comparison result.

[0026] For example, in the control method provided in at least some embodiments of the present disclosure, setting the value of the flow standard signal according to the comparison result includes: in response to the comparison result indicating that the number of clock cycles is greater than or equal to the first threshold, judging the size relationship between the current value of the first counter and the second threshold; in response to the current value of the first counter being greater than or equal to the second threshold, keeping the value of the flow standard signal unchanged; in response to the current value of the first counter being less than the second threshold, adding the first value to the current value of the first counter to obtain an updated value, determining that the updated value is equal to the second threshold, and setting the value of the flow standard signal to the first value, wherein the initial value of the first counter is 0; determining that the updated value is not equal to the second threshold, and keeping the value of the flow standard signal unchanged.

[0027] For example, in the control method provided in at least some embodiments of the present disclosure, setting the value of the flow standard signal according to the comparison result includes: in response to the comparison result indicating that the number of clock cycles is less than the first threshold, judging the size relationship between the current value of the second counter and 0, and in response to the current value of the second counter being equal to 0, keeping the value of the flow standard signal unchanged; in response to the current value of the second counter being greater than 0, subtracting a second value from the current value of the second counter to obtain an updated value, wherein the initial value of the second counter is p, p is a positive integer, and the updated value is not less than 0; determining that the updated value is equal to 0, setting the value of the flow standard signal to the second value; determining that the updated value is greater than 0, keeping the value of the flow standard signal unchanged.

[0028] For example, the control method provided by at least some embodiments of the present disclosure also includes: decoding and generating microinstructions to determine the number of instructions corresponding to each of the multiple clock cycles; based on the number of instructions, determining the number of instruction processing units required to be used in each of the multiple clock cycles; wherein the instruction flow includes the number of instructions and the number of instruction processing units.

[0029] At least some embodiments of the present disclosure also provide an electronic device, comprising: at least one processor, a memory, and non-temporarily storing computer-readable instructions, wherein when the computer-readable instructions are executed by the at least one processor, the control method provided in accordance with any embodiment of the present disclosure is executed.

[0030] At least some embodiments of the present disclosure further provide a non-transitory storage medium that non-transitory stores computer-readable instructions. When the computer-readable instructions are executed by a computer, the control method provided according to any embodiment of the present disclosure is executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0032] Figure 1 A schematic diagram of the structure of a processor provided in some embodiments of the present disclosure;

[0033] Figure 2 A schematic diagram of the structure of the isolation and power supply module in the processor provided in some embodiments of the present disclosure;

[0034] Figure 3 A schematic structural diagram of a flow rate compliance signal determination module provided in some embodiments of the present disclosure;

[0035] Figure 4 A schematic diagram of the structure of a setting submodule provided in some embodiments of the present disclosure;

[0036] Figure 5 A schematic diagram of the structure of another processor provided in some embodiments of the present disclosure;

[0037] Figure 6 A schematic flowchart of a processor control method provided in some embodiments of the present disclosure;

[0038] Figure 7 A schematic flowchart of a processor in different operating modes provided in some embodiments of the present disclosure;

[0039] Figure 8 A schematic flow chart of setting a flow rate reaching target signal according to some embodiments of the present disclosure;

[0040] Figure 9 A schematic structural diagram of an electronic device provided in some embodiments of the present disclosure; and

[0041] Figure 10 A schematic diagram of a storage medium provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0043] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0044] The present disclosure is described below using several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numeral in each drawing.

[0045] At least one embodiment of the present disclosure provides a processor, which includes: a first instruction processing unit group, including at least one instruction processing unit; a control module, configured to generate a control signal, the control signal including a first control signal or a second control signal, the first control signal being generated based on the instruction flow; an isolation and power supply module, configured to control at least one instruction processing unit to be in a working state or a non-working state under the control of the control signal.

[0046] The processor provided by the above embodiments of the present disclosure sets a first instruction processing unit group and dynamically controls the instruction processing units in the first instruction processing unit group to be in a working state or a non-working state according to the instruction flow, so as to improve the processing capability for instructions and take into account both performance and power consumption.

[0047] The processor provided in the embodiments of the present disclosure may include, for example, a central processing unit (CPU), a microcontroller unit (MU), a digital signal processor (DSP), an intellectual property core (IP), and other devices that support out-of-order execution. The processor provided in the embodiments of the present disclosure may also be applied to scenarios including, for example, one or more multi-dispatch instructions, or single-threaded or multi-threaded scenarios.

[0048] Figure 1 A schematic diagram of the structure of a processor provided in some embodiments of the present disclosure.

[0049] like Figure 1 As shown, the processor 100 includes a first instruction processing unit group 10, a control module 20, and an isolation and power supply module 30. The first instruction processing unit group 10 includes at least one instruction processing unit ( Figure 1 (not shown in the figure), in some embodiments, the first instruction processing unit group 10 may include two instruction processing units. The control module 20 is configured to generate a control signal, which includes a first control signal and a second control signal, wherein the first control signal is generated based on the instruction flow. The isolation and power supply module 30 is configured to control at least one instruction processing unit to be in an operating state or a non-operating state under the control of the control signal.

[0050] For example, the control module 20 can be implemented in the form of a logic circuit, a digital circuit, etc. The control signal generated by the control module 20 can be transmitted to the isolation and power supply module 30, so that the isolation and power supply module 30 controls at least one instruction processing unit in the first instruction processing unit group 10 to be in an operating state or a non-operating state under the control of the control signal.

[0051] In the embodiment of the present disclosure, the instructions processed by the instruction processing unit in the processor may include data processing instructions, program control instructions, floating-point operation instructions (such as floating-point multiplication and accumulation instructions), etc. The embodiment of the present disclosure does not limit the type of instructions.

[0052] For example, in some embodiments, Figure 1 As shown, the processor 100 may further include a decoding unit 80, which is configured to determine the number of instructions to obtain instruction flow. For example, the decoding unit 80 may generate microinstructions by decoding to determine the number of instructions corresponding to each clock cycle, and then determine the number of instruction processing units required to be used in each clock cycle based on the number of instructions corresponding to each clock cycle, thereby obtaining the instruction flow corresponding to each clock cycle. In an embodiment of the present disclosure, the instruction flow includes the number of instructions in each clock cycle and / or the number of instruction processing units required to be used in each clock cycle.

[0053] It should be noted that, in the embodiment of the present disclosure, at least one instruction processing unit being in a working state or a non-working state means that part of the instruction processing units or all of the instruction processing units in the at least one instruction processing unit are in a working state or a non-working state. For example, if the number of the at least one instruction processing unit is 2, one of the two instruction processing units may be in a working state, and the other of the two instruction processing units may be in a non-working state; or, both of the two instruction processing units are in a working state; or, both of the two instruction processing units are in a non-working state. The instruction processing unit being in a working state can be understood as the instruction processing unit is participating in the operation flow of the processor and can execute the operation of the instruction, such as executing multiplication operations, accumulation operations, data loading and storage operations, etc. The instruction processing unit being in a non-working state can be understood as the instruction processing unit is not participating in any operation flow or not performing any operation.

[0054] In some embodiments, all instruction processing units in the first instruction processing unit group 10 can be used to process the same type of instructions. For example, at least one instruction processing unit in the first instruction processing unit group 10 can each build a pipeline in the processor 100, and the number of pipelines is equal to the number of instruction processing units, so as to improve the processing performance of the processor in an application scenario where such instructions have a higher priority or a larger number. For another example, multiple instruction processing units in the first instruction processing unit group 10 can be used to process different types of instructions to improve the processing performance of the processor for different instructions.

[0055] In some embodiments, as Figure 1 As shown, the processor 100 may further include a second instruction processing unit group 11. The second instruction processing unit group 11 may include N instruction processing units, where N is a positive integer. The N instruction processing units included in the second instruction processing unit group 11 are always in operation. For example, the second instruction processing unit group 11 may process microinstructions decoded by the decoding unit 80. For example, when N is 2, the second instruction processing unit group 11 includes two instruction processing units. These two instruction processing units may be used to process the same type of instructions, such as floating-point multiply-accumulate instructions. Two pipelines may be constructed in the processor 100 based on these two instruction processing units, resulting in two pipelines in the core of the processor 100 for executing floating-point multiply-accumulate instructions. The maximum number of instructions per cycle (IPC) for floating-point multiply-accumulate instructions is 2 per cycle. However, other instruction processing logic may be included in these two pipelines. For floating-point multiply-accumulate instructions, it is difficult to maintain an IPC of 2 per cycle, resulting in insufficient processing power for floating-point multiply-accumulate instructions. Even if the IPC is consistently maintained at 2 instructions per cycle, in tasks with a large number of floating-point multiplication and accumulation instructions, the processing capability of floating-point multiplication and accumulation instructions will become a performance bottleneck of the processor.

[0056] In an embodiment of the present disclosure, the instruction processing units in the first instruction processing unit group 10 and the instruction processing units in the second instruction processing unit group 11 can be used to process the same type of instructions, for example, floating-point multiply-accumulate instructions. When the first instruction processing unit group 10 includes two instruction processing units, there are four pipelines in the core of the processor 100 for executing floating-point multiply-accumulate instructions. Therefore, for the processor 100, the maximum IPC corresponding to the floating-point multiply-accumulate instruction is 4 per cycle, which can effectively improve the processor's parallel processing capability for floating-point multiply-accumulate instructions.

[0057] Figure 2 This is a schematic diagram of the structure of the isolation and power supply module in the processor provided in some embodiments of the present disclosure. Figure 2The isolation and power supply modules in the embodiments of the present disclosure are further described.

[0058] like Figure 2 As shown, the isolation and power module 30 may include a power submodule 301. The power submodule 301 is configured to provide a power signal or not provide a power signal to at least one instruction processing unit in the first instruction processing unit group 10 under the control of a control signal.

[0059] In the embodiment of the present disclosure, the second instruction processing unit group is always in a working state. For example, a power supply module different from the power supply submodule 301 used for the first instruction processing unit group can be used to always provide a power supply signal to the second instruction processing unit group. Figure 2 The power submodule 301 shown can provide a power signal or not provide a power signal to the first instruction processing unit group under the control of the control signal, that is, it can perform power management on the first instruction processing unit group and the second instruction processing unit group respectively, and dynamically control the power submodule to take into account the performance and power consumption of the processor.

[0060] In the embodiments of the present disclosure, Figure 2 As shown, the isolation and power module 30 may further include an isolation submodule 302. After the power submodule 301 provides a power signal under the control of a control signal, the isolation submodule 302 is in an on state under the control of the control signal, so that the power submodule 301 and the first instruction processing unit group 10 are conductive, so that the power signal provided by the power submodule 301 can be transmitted to at least one instruction processing unit in the first instruction processing unit group 10, so that at least one instruction processing unit in the first instruction processing unit group 10 is in a working state; after the isolation submodule 302 is in an off state under the control of a control signal, the power submodule 301 and the first instruction processing unit group 10 are not conductive, and the power submodule 301 stops providing a power signal to at least one instruction processing unit in the first instruction processing unit group 10 under the control of the control signal. When the isolation submodule 302 is in an off state, at least one instruction processing unit in the first instruction processing unit group 10 is in a non-working state.

[0061] In other words, the power submodule 301 and the isolation submodule 302 can jointly control the operation of the instruction processing units in the first instruction processing unit group 10. When the power submodule 301 provides a power signal and the isolation submodule 302 is turned on, at least one instruction processing unit in the first instruction processing unit group 10 is in an operating state; when the isolation submodule 302 is turned off, at least one instruction processing unit in the first instruction processing unit group 10 is in a non-operating state. Furthermore, operations on the power submodule 301 and the isolation submodule 302 must be performed in a specific order. When controlling at least one instruction processing unit in the first instruction processing unit group 10 to be in an operating state, the power submodule 301 must first be controlled to provide a power signal. After the power supply stabilizes, the isolation submodule 302 can be controlled to be turned on to protect the sensitive electronic components in the instruction processing unit and ensure normal startup of the instruction processing unit. When controlling at least one instruction processing unit in the first instruction processing unit group 10 to be in a non-operating state, the isolation submodule 302 can first be controlled to be turned off, and then the power submodule 301 can be controlled to stop providing a power signal to prevent data loss or damage in the instruction processing unit.

[0062] The isolation submodule 302 can be implemented in the form of a switch, for example, by implementing the control function of the switch through logic gates such as an AND gate, an OR gate, and a NOT gate. The embodiment of the present disclosure does not limit the specific implementation of the isolation submodule.

[0063] In some embodiments, the isolation submodule 302 may include at least one isolation unit corresponding one-to-one to at least one instruction processing unit in the first instruction processing unit group 10, and each of the at least one isolation units receives a control signal and, under the control of the control signal, controls the corresponding instruction processing unit to be in a working state or a non-working state.

[0064] In some embodiments, the isolation submodule 302 may also include a distributor (Demultiplexer, DEMUX), the input end of which receives a control signal, and the multiple output ends of the distributor are electrically connected to each of the at least one isolation units. The control signal is selected by the distributor and directed to the corresponding isolation unit to independently control each of the at least one isolation unit, and then independently control at least one instruction processing unit in the first instruction unit group 10.

[0065] The embodiments of the present disclosure can independently control each instruction processing unit in the first instruction processing unit group 10 by setting an isolation unit that corresponds one-to-one to the instruction processing unit in the first instruction processing unit group 10, so as to more accurately control the number of instruction processing units currently required according to the instruction flow, thereby avoiding wasting processor resources.

[0066] In some embodiments, the isolation submodule 302 may include only one isolation unit, which receives a control signal and, under the control of the control signal, controls all instruction processing units in the first instruction processing unit group 10 to be in an operating state or a non-operating state. Alternatively, the isolation submodule 302 may include multiple isolation units, each of which controls an equal or unequal number of instruction processing units in the first instruction processing unit group 10, that is, each isolation unit can control one or more instruction processing units in the first instruction processing unit group 10.

[0067] It should be noted that the present disclosure does not limit the number of isolation units in the isolation submodule. The correspondence between the isolation units and the instruction processing units in the first instruction processing unit group is also not limited. For example, one isolation unit may correspond to all instruction processing units in the first instruction processing unit group, or may correspond to one or more instruction processing units in the first instruction processing unit group. The specific situation can be set according to the needs of the actual scenario.

[0068] exist Figure 1 In the illustrated embodiment, the processor 100 may further include a configuration module 40. The configuration module 40 is configured to set the processor 100 to a first operating mode or a second operating mode. In the first operating mode, the control module 40 is configured to generate a first control signal based on the instruction flow, and the isolation and power supply module 30 controls at least one instruction processing unit in the first instruction processing unit group 10 to be in an operating state or a non-operating state under the control of the first control signal; in the second operating mode, the control module 40 is configured to generate a second control signal, and the isolation and power supply module 30 controls at least one instruction processing unit in the first instruction processing unit group 10 to be in an operating state under the control of the second control signal.

[0069] The configuration module 40 can set the processor 100 to be in the first working mode or the second working mode. For example, in an application scenario where the number of instructions changes in time periods, the configuration module 40 can set the processor to be in the first working mode. In the first working mode, the control module 20 can generate a first control signal based on the instruction flow, so that the isolation and power supply module 30 controls at least one instruction processing unit in the first instruction processing unit group 10 to be in a working state or in a non-working state under the control of the first control signal. For example, in an application scenario where the processor's ability to process instructions is high, there is no need to make a judgment based on the instruction flow. The configuration module 40 can directly set the processor to be in the second working mode. In the second working mode, the control module 20 can generate a second control signal so that the isolation and power supply module 30, under the control of the second control signal, continuously controls at least one instruction processing unit in the first instruction processing unit group 10 to be in a working state.

[0070] The configuration module 40 may include a circuit and a register of at least two bits, wherein the two-bit value in the register indicates the operating mode to which the processor is set. For example, setting the high bit of the register to 0 and the low bit to 1 through a digital circuit indicates that the processor is set to the first operating mode, and setting the high bit of the register to 1 indicates that the processor is set to the second operating mode.

[0071] For example, the first working mode can represent a dynamic management mode. In the dynamic management mode, the control module 20 can generate a first control signal based on the instruction flow to control at least one instruction processing unit in the first instruction processing unit group 10 to be in a working state or a non-working state, that is, dynamically control the working state of at least one instruction processing unit in the first instruction unit group 10 according to the instruction flow. In this mode, the performance and power consumption of the processor can be taken into account. The second working mode can represent a static management mode. In the static management mode, the control module 20 generates a second control signal to continuously control at least one instruction processing unit in the first instruction processing unit group 10 to be in a working state, so that the instruction processing capability of the processor is maintained at a high level.

[0072] The processor provided by the embodiments of the present disclosure has both a dynamic management mode and a static management mode. The static management mode can improve the processor's instruction processing capabilities to meet application requirements, while the dynamic management mode can control the operation of at least one instruction processing unit in the first instruction processing unit group based on instruction flow, taking into account the performance and power consumption requirements of the processor.

[0073] In some embodiments, the processor 100 may further include a determination module 50. The determination module 50 is configured to determine whether the processor has exited the second operating mode. When the determination module 50 determines that the processor has not exited the second operating mode, at least one instruction processing unit in the first instruction processing unit group 10 remains in an operating state. When the determination module 50 determines that the processor has exited the second operating mode, in response to at least one instruction processing unit in the first instruction processing unit group 10 completing execution of the current instruction, the at least one instruction processing unit in the first instruction processing unit group 10 changes from an operating state to an inoperative state.

[0074] When the processor is in the second working mode, it will generate higher power consumption. In order to prevent the processor from mistakenly entering the second working mode and avoid wasting power, the judgment module 50 can be used to determine whether the processor needs to exit the second working mode. For example, the configuration module 40 sets the processor to be in the first working mode or the second working mode. After determining that the processor is in the second working mode, the judgment module 50 determines whether the processor exits the second working mode, that is, the judgment module 50 verifies whether the processor needs to be in the second working mode. When exiting the second working mode, it is necessary to consider whether at least one instruction processing unit has completed the execution of the current instruction. If the current instruction has been executed, the second working mode can be exited directly; if the current instruction has not been executed, it is necessary to wait until the current instruction is executed before exiting the second working mode.

[0075] The judgment module 50 can again determine whether the processor is in the second working mode set by the configuration module, prevent the processor from mistakenly entering the second working mode when it is not set to the second working mode, accurately select the working mode of the processor, and thus avoid power consumption waste.

[0076] The judgment module in the embodiment of the present disclosure can be implemented in the form of, for example, a microcontroller, a programmable logic device, an integrated circuit, etc. It should be noted that the embodiment of the present disclosure does not limit the implementation form of the judgment module.

[0077] From the description of the embodiments of the present disclosure, it can be known that when the processor is in the first working mode, the isolation and power supply module controls the working condition of the instruction unit under the control of the first control signal, and the first control signal is generated based on the instruction flow. The following specifically explains how to determine the specific working condition of at least one instruction processing unit based on the instruction flow in the first working mode.

[0078] In some embodiments, as Figure 1 As shown, the processor 100 may further include a flow standard signal determination module 60. The flow standard signal determination module 60 is configured to determine the value of the flow standard signal according to the instruction flow in response to the processor being set to be in the first working mode. The control module 20 is configured to set the value of the first control signal to the first control value in response to the value of the flow standard signal being a first value. When the value of the first control signal is the first control value, the isolation and power supply module 30 controls at least one instruction processing unit in the first instruction processing unit group 10 to be in a working state under the control of the first control signal; the control module 20 is also configured to set the value of the first control signal to the second control value in response to the value of the flow standard signal being a second value. When the value of the first control signal is the second control value, the isolation and power supply module 30 controls at least one instruction processing unit in the first instruction processing unit group 10 to be in a non-working state under the control of the first control signal.

[0079] The flow standard signal determination module 60 can be configured to set the flow standard signal to a first value or a second value according to the instruction flow when the processor is in the first working mode. When the flow standard signal is the first value, the control module 20 sets the value of the first control signal to the first control value. At this time, the first control signal with the first control value can control the power submodule 301 in the isolation and power module 30 to provide a power signal and control the isolation submodule 302 in the isolation and power module 30 to be in an on state, thereby putting at least one instruction processing unit in the first instruction processing unit group 10 into an operating state. When the flow standard signal is the second value, the control module 20 sets the value of the first control signal to the second control value. At this time, the first control signal with the second control value can control the power submodule 301 in the isolation and power module 30 to provide a power signal and control the isolation submodule 302 in the isolation and power module 30 to be in an on state, thereby controlling at least one instruction processing unit in the first instruction processing unit group 10 to be in a non-operating state.

[0080] The first value and the second value are used only to distinguish different situations of the flow standard compliance signal. For example, the first value can be 1 and the second value can be 0. The embodiments of the present disclosure do not limit the specific values of the first value and the second value. Similarly, the first control value and the second control value are used to distinguish different situations of the first control signal when the flow standard compliance signal has different values. The embodiments of the present disclosure do not limit the representation of the first control signal and the second control signal.

[0081] The flow standard signal determination module can be implemented, for example, in the form of a digital circuit, with the digital circuit outputting signals "0" and "1" as different values of the flow standard signal. It should be noted that the embodiments of the present disclosure do not limit the implementation of the flow standard signal determination module or the value of the flow standard signal.

[0082] The flow standard signal determination module 60 can set different values of the flow standard signal according to the instruction flow. Different values of the flow standard signal correspond to different values of the first control signal. The working condition of the instruction unit is controlled by the first control signal, thereby realizing the control of the working condition of at least one instruction processing unit in the first instruction processing unit group 10 according to the instruction flow, so that the processor can flexibly meet the application scenarios of different instruction flows.

[0083] In some embodiments, the processor 100 may further include a detection module 70. The detection module 70 may be configured to detect, in response to the processor being in the first operating mode, a plurality of instruction flows corresponding to the plurality of time instants at a plurality of time instants.

[0084] To better meet the processor's instruction processing capabilities for current application scenarios, in the first operating mode, detection module 70 can be used to detect multiple instruction flows at multiple times. At each time, the operating status of the instruction processing unit is adjusted based on the detected instruction flows, thereby adapting the processor's instruction processing capabilities to the current instruction flow in real time. The time interval between two adjacent moments can be set according to actual needs and is not limited in this disclosure.

[0085] Figure 3 A structural diagram of a flow compliance signal determination module provided in some embodiments of the present disclosure.

[0086] like Figure 3 As shown, the traffic standard signal determination module 60 may include a calculation submodule 611, a comparison submodule 612, and a setting submodule 613. The calculation submodule 611 is configured to calculate the number of clock cycles (hereinafter referred to as "clock cycle number") of at least one target clock cycle within multiple clock cycles based on the instruction traffic, and the number of instruction processing units required for each at least one target clock cycle is greater than the unit number threshold. The comparison submodule 612 is configured to compare the clock cycle number with the first threshold to obtain a comparison result. The setting submodule 613 is configured to set the value of the traffic standard signal according to the comparison result.

[0087] In some embodiments, the calculation submodule 611 may be implemented by, for example, a Population Count (popcnt) method, where popcnt is used to calculate the number of clock cycles based on instruction flow.

[0088] The unit quantity threshold value can take a positive integer N, where N is the number of instruction processing units included in the aforementioned second instruction processing unit group. For example, when N is 2, it means that the second instruction processing unit group includes 2 instruction processing units. The calculation submodule 611 is capable of calculating the number of clock cycles in which the number of instruction processing units required to be used within multiple clock cycles is greater than 2, that is, the number of target clock cycles (i.e., the number of clock cycles). Multiple clock cycles can be set according to the duration of statistics and observations to be required, for example, multiple cycles can be set to 64 cycles. The first threshold value can be set as needed, for example, to 8, 16, 32, 48, etc. In some embodiments, the first threshold value can be configured by a control register.

[0089] The comparison submodule 612 can compare the number of clock cycles of the at least one target clock cycle obtained by the calculation submodule 611 with the first threshold to obtain a comparison result. The comparison result can be that the number of clock cycles is less than the first threshold, the number of clock cycles is greater than the first threshold, or the number of clock cycles is equal to the first threshold.

[0090] In some embodiments, the comparison submodule 612 may be implemented by a comparator.

[0091] Figure 4 A schematic diagram of the structure of a setting submodule provided in some embodiments of the present disclosure.

[0092] In some embodiments, as Figure 4 As shown, the setting submodule 613 may include a first judgment unit 6131 and a first setting unit 6132. The first judgment unit 6131 is configured to, in response to the comparison result indicating that the number of clock cycles is greater than or equal to the first threshold, obtain the current value of the first counter and determine the magnitude relationship between the current value of the first counter and the second threshold. The first setting unit 6132 is configured to, in response to the current value of the first counter being less than the second threshold, add a first value to the current value of the first counter to obtain an updated value of the first counter, where the first value is a positive integer; upon determining that the updated value of the first counter is equal to the second threshold, set the value of the flow standard compliance signal to the first value and the initial value of the first counter to 0; and, in response to the current value of the first counter being greater than or equal to the second threshold or upon determining that the updated value of the first counter is not equal to the second threshold, maintain the value of the flow standard compliance signal unchanged. For example, the first setting unit 6132 includes a first counter.

[0093] When the comparison result indicates that the number of clock cycles is greater than or equal to the first threshold, taking the unit quantity threshold as 2 as an example, it means that the number of instruction processing units required to be used is greater than 2 and the number of clock cycles is greater than or equal to the first threshold, that is, using only 2 instruction processing units in the second instruction processing unit group may not be able to fully cover the current instruction processing needs, but it may be due to other considerations, such as the need to take into account the processor power consumption, and there is no need to immediately control the instruction processing units in the first instruction processing unit group to be in a working state. In this case, a first counter and a second threshold can be set, and the specific time when the instruction processing units in the first instruction processing unit group enter the working state can be controlled by the size relationship between the value of the first counter and the second threshold.

[0094] The initial value of the first counter is 0. Whenever the number of clock cycles is greater than or equal to the first threshold, the value of the first counter is increased by a first value, for example, the first value may be 1. The value of the second threshold may also be set as needed, for example, to 4, 8, 16, 32, etc.

[0095] When the current value of the first counter is greater than or equal to the second threshold, the first setting unit 6132 keeps the value of the flow standard signal unchanged, that is, if the value of the flow standard signal is the first value (for example, 1), the value of the flow standard signal continues to remain at the first value; if the value of the flow standard signal is the second value (for example, 0), the value of the flow standard signal continues to remain at the second value.

[0096] When the current value of the first counter is less than the second threshold, the current value of the first counter is added to the first value to obtain the updated value of the first counter. The first value is a positive integer, for example, it can be 1, 2, 3, etc., and the embodiment of the present disclosure does not limit this.

[0097] In some embodiments, the first setting unit 6132 may further determine the relationship between the updated value of the first counter and the second threshold, and set the value of the flow standard compliance signal based on the determination result. When the updated value of the first counter is equal to the second threshold, the first setting unit 6132 sets the value of the flow standard compliance signal to the first value, ultimately placing at least one instruction processing unit in the first instruction processing unit group 10 in an operational state. When the updated value of the first counter is not equal to the second threshold, that is, the updated value of the first counter is still less than the second threshold, the first setting unit 6132 maintains the value of the flow standard compliance signal unchanged.

[0098] In some embodiments, the first counter can be cleared after the current value of the first counter is greater than or equal to the second threshold, or after the updated value of the first counter is greater than or equal to the second threshold, i.e., the value of the first counter can be set to the initial value. For example, the value of the first counter can be cleared as needed at the 4th, 8th, or 16th clock cycle after the current value or the updated value of the first counter is greater than or equal to the second threshold. The first determination unit 6131 and the first setting unit 6132 then perform the above-described operation again.

[0099] In other embodiments, the value of the flow standard attainment signal may be considered when determining the magnitude relationship between the updated value of the first counter and the second threshold. For example, when the updated value of the first counter is equal to the second threshold and the value of the flow standard attainment signal is the second value, the first setting unit 6132 sets the flow standard attainment signal to the first value. Otherwise, when the updated value of the first counter is less than the second threshold or the value of the flow standard attainment signal is the first value, the first setting unit 6132 maintains the value of the flow standard attainment signal unchanged.

[0100] In the present disclosure, the value of the flow standard signal is set by the relationship between the current value and the updated value of the first counter and the second threshold value, and the time it takes for the value of the first counter to increase to the second threshold value can be used to control the speed at which at least one instruction processing unit in the first instruction processing unit group enters the working state when the processor is in the first working mode. The smaller the second threshold value, the larger the first numerical value, the faster the updated value of the first counter reaches the second threshold value, the sooner the flow standard signal is set to the first value, and the faster at least one instruction processing unit in the first instruction processing unit group enters the working state as the instruction flow increases. Conversely, if you do not want at least one instruction processing unit in the first instruction processing unit group to enter the working state quickly, you can increase the second threshold value and decrease the first numerical value to slow down the speed at which the updated value of the first counter reaches the second threshold value, thereby making the flow standard signal maintain the second value for a longer time, and at least one instruction processing unit in the first instruction processing unit group enters the working state later as the instruction flow increases.

[0101] like Figure 4 As shown, in some embodiments, the setting submodule 613 may further include a second judgment unit 6133 and a second setting unit 6134. The second judgment unit 6133 is configured to, in response to the comparison result indicating that the number of clock cycles is less than the first threshold, obtain the current value of the second counter and determine the magnitude relationship between the current value of the second counter and 0. The second setting unit 6134 is configured to, in response to the current value of the second counter being greater than 0, subtract a second value from the current value of the second counter to obtain an updated value of the second counter, wherein the updated value of the second counter is not less than 0; set the value of the flow standard compliance signal to a second value when it is determined that the updated value of the second counter is equal to 0; and maintain the value of the flow standard compliance signal unchanged when the current value of the second counter is equal to 0 or when it is determined that the updated value of the second counter is greater than 0. For example, the second setting unit 6134 may include a second counter.

[0102] When the comparison result indicates that the clock cycle is less than the first threshold, continuing with the example of a unit number threshold of 2, this indicates that the number of clock cycles required to use more than 2 instruction processing units is less than the first threshold, and that using two instruction processing units in the second instruction processing unit group can meet the current instruction processing needs. Therefore, it is necessary to place at least one instruction processing unit in the first instruction processing unit group in a non-operating state. Similar to the above-described process of placing at least one instruction processing unit in the first instruction processing unit group in an operating state, the specific time at which the instruction processing units in the first instruction processing unit group enter the non-operating state is controlled by the relationship between the value of the second counter and the second numerical value.

[0103] For example, when the comparison result indicates that the number of clock cycles is less than the first threshold, the second determination unit 6133 obtains the current value of the second counter and determines the magnitude relationship between the current value of the second counter and 0.

[0104] When the current value of the second counter is equal to 0, the second setting unit 6134 keeps the value of the flow standard attainment signal unchanged.

[0105] When the current value of the second counter is greater than 0, the second value is subtracted from the current value of the second counter to obtain the updated value of the second counter, and the initial value of the second counter is p, p is a positive integer, and the updated value of the second counter is not less than 0, that is, the current value of the second counter cannot be less than 0.

[0106] When it is determined that the updated value of the second counter is greater than 0, the second setting unit 6134 keeps the value of the flow standard attainment signal unchanged.

[0107] When it is determined that the updated value of the second counter is equal to 0, the second setting unit 6134 sets the value of the flow standard attainment signal to a second value.

[0108] In some embodiments, the value of the second counter can be reset to the initial value of the second counter after the current value of the second counter is equal to 0 or the updated value of the second counter is equal to 0. For example, the value of the second counter can be set to the initial value at the 4th, 8th, or 16th clock cycle after the current value or the updated value of the second counter is equal to 0, as needed. The second determination unit 6133 and the second setting unit 6134 then perform the above operation again.

[0109] In other embodiments, when setting the value of the flow standard attainment signal, the second setting unit may not only consider the magnitude relationship between the updated value of the second counter and 0, but may also consider the value of the flow standard attainment signal. For example, when the updated value of the second counter is equal to 0 and the value of the flow standard attainment signal is the first value, the second setting unit 6134 sets the flow standard attainment signal to the second value. Otherwise, when the updated value of the second counter is greater than 0 or the value of the flow standard attainment signal is the second value, the second setting unit 6134 maintains the value of the flow standard attainment signal unchanged.

[0110] In an embodiment of the present disclosure, when the processor is in the first working mode, the value of the flow standard signal is set by the relationship between the current value and the updated value of the second counter and 0, and the speed at which at least one instruction processing unit in the first instruction processing unit group enters the non-working state can be controlled by the time when the value of the second counter decreases to 0. The larger the second value, the faster the updated value of the second counter decreases to 0, the earlier the flow standard signal is set to the second value, and the faster the at least one instruction processing unit in the first instruction processing unit group enters the non-working state as the instruction flow decreases. Conversely, if you do not want at least one instruction processing unit in the first instruction processing unit group to enter the non-working state quickly, you can reduce the second value to reduce the speed at which the updated value of the second counter decreases to 0, thereby making the flow standard signal maintain the first value for a longer time, and at least one instruction processing unit in the first instruction processing unit group enters the non-working state later as the instruction flow decreases.

[0111] The following example illustrates the operations performed by the first judgment unit 6131, the first setting unit 6132, the second judgment unit 6133, and the second setting unit 6134. In the following description, the processor is in the first operating mode, the first threshold is 8, the second threshold is 4, the first value is 1, and the second value is 2.

[0112] For example, a period of time is selected within multiple clock cycles to determine the value of the flow compliance signal, and this period of time can be used as an observation window. In the mth observation window, where m is a positive integer, the calculation submodule 611 calculates the number of clock cycles of the target clock cycle to be 10. For example, at this time, the current value of the first counter is the initial value of the first counter, that is, the current value of the first counter is 0. The comparison result obtained by the comparison submodule 612 is that the number of clock cycles (i.e., 10) is greater than the first threshold value (i.e., 8). The first judgment unit 6131 determines that the current value of the first counter (i.e., 0) is less than the second threshold value (i.e., 4). The current value of the first counter is incremented by 1, resulting in an updated value of 1. Since the updated value of the first counter is still less than the second threshold value, the value of the flow compliance signal is maintained. For example, if the value of the flow compliance signal is the second value, the control module 20 receives the flow compliance signal having the second value and sets the value of the first control signal to the second control value. At this time, at least one instruction processing unit in the first instruction processing unit group is in an inoperative state.

[0113] For example, in the m+1th observation window, the calculation submodule 611 calculates the number of clock cycles of the target clock cycle to be 9. At this time, the current value of the first counter is 1. The comparison result obtained by the comparison submodule 612 is that the number of clock cycles (i.e., 9) is greater than the first threshold (i.e., 8). The first judgment unit 6131 determines that the current value of the first counter (i.e., 1) is less than the second threshold (i.e., 4). The current value of the first counter is further increased by 1, and the updated value of the first counter is 2. Since the updated value of the first counter is still less than the second threshold, in this case, the processor may have a large demand for instruction processing units in some time periods, but the two instruction processing units in the second instruction processing unit group can meet the current instruction processing demand as a whole, thereby continuing to maintain the value of the flow standard signal. For example, if the value of the flow standard signal is the second value, the control module 20 receives the flow standard signal with the second value and sets the value of the first control signal to the second control value. At this time, at least one instruction processing unit in the first instruction processing unit group continues to be in a non-operating state, thereby saving power consumption.

[0114] Until the m+jth observation window, m and j are both positive integers, and the updated value of the first counter reaches 4. At this time, the updated value of the first counter is equal to the second threshold. In this case, the processor has a large long-term demand for instruction processing units, and the two instruction processing units in the second instruction processing unit group cannot meet the current instruction processing needs. Therefore, the first setting unit 6132 sets the flow standard signal to the first value, thereby ultimately controlling at least one instruction processing unit in the first instruction processing unit group to be in working state, thereby improving the parallel processing capability.

[0115] In some embodiments, the value of the first counter may be cleared after the updated value of the first counter in the m+jth observation window is equal to the second threshold. Alternatively, the value of the first counter may be cleared in the m+j+ath observation window, where a is a positive integer. Similar operations may then be performed for the m, m+1, and m+jth observation windows.

[0116] For example, in the m+2th observation window, the calculation submodule 611 calculates that the number of clock cycles of the target clock cycle is 7, and the comparison result obtained by the comparison submodule 612 is that the number of clock cycles (i.e., 7) is less than the first threshold value (i.e., 8). For example, the current value of the second counter is the initial value p of the second counter, and the initial value of the second counter is set to 6, that is, the current value of the second counter is 6, and the current value of the second counter is greater than 0, then the current value of the second counter is subtracted by 2, and the updated value of the second counter is obtained as 4. The updated value of the second counter is still greater than 0, and the value of the flow standard signal is maintained. For example, if the value of the flow standard signal is the first value, the control module 20 receives the flow standard signal having the first value and sets the value of the first control signal to the first control value. At this time, at least one instruction processing unit in the first instruction processing unit group is in working state.

[0117] Until the m+kth observation window, when m and k are both positive integers and the updated value of the second counter is 0, the flow standard signal is set to the second value, thereby ultimately controlling at least one instruction processing unit in the first instruction processing unit group to be in a non-working state, thereby saving power consumption.

[0118] In some embodiments, after the updated value of the second counter reaches 0 in the m+kth observation window, the value of the second counter may be reset to the initial value of the second counter. Alternatively, the value of the second counter may be set to the initial value of the second counter in the m+k+bth observation window, where b is a positive integer. Similar operations may then be performed for the m+2th and m+kth observation windows.

[0119] It should be noted that each time the processor is started, the first counter and the second counter may be reset to their initial values.

[0120] In an embodiment of the present disclosure, a first counter and a second counter are used to control the speed at which at least one instruction processing unit in the first instruction processing unit group enters a working state and a non-working state, respectively. For example, fast entry and slow exit or slow entry and fast exit can be achieved. Alternatively, the same counter can be used to implement the functions of the first counter and the second counter, and the same first and second values can be set. For example, a third counter can be used instead of the first and second counters. The following explanation is based on the example of the processor being in the first working mode, the first threshold being 8, the second threshold being 4, and the first and second values being 2.

[0121] In the m-th observation window, the calculation submodule 611 calculates that the number of clock cycles of the target clock cycle is 10. For example, at this time, the current value of the third counter is 0. The comparison result obtained by the comparison submodule 612 is that the number of clock cycles (i.e., 10) is greater than the first threshold value (i.e., 8). The first judgment unit 6131 determines that the current value of the third counter (i.e., 0) is less than the second threshold value (i.e., 4). Then, the current value of the third counter is added by 2, and the updated value of the third counter is obtained as 2. Since the updated value of the third counter is still less than the second threshold value, the first setting unit 6132 maintains the value of the flow standard signal. For example, if the value of the flow standard signal is the second value, the control module 20 receives the flow standard signal having the second value and sets the value of the first control signal to the second control value. At this time, at least one instruction processing unit in the first instruction processing unit group is in a non-working state.

[0122] In the above-mentioned m+1th observation window, the calculation submodule 611 calculates that the number of clock cycles of the target clock cycle is 9. At this time, the current value of the third counter is 1. The comparison result obtained by the comparison submodule 612 is that the number of clock cycles (i.e., 9) is greater than the first threshold (i.e., 8). The first judgment unit 6131 determines that the current value of the third counter (i.e., 2) is less than the second threshold (i.e., 4). The current value of the third counter continues to add 2, and the updated value of the third counter is 4. Since the updated value of the third counter is equal to the second threshold, the first setting unit 6132 sets the flow standard signal to the first value. The control module 20 receives the flow standard signal with the first value and sets the value of the first control signal to the first control value. At this time, at least one instruction processing unit in the first instruction processing unit group is in working state.

[0123] In the aforementioned (m+2)th observation window, the calculation submodule 611 calculates the number of clock cycles of the target clock cycle to be 7. The comparison result obtained by the comparison submodule 612 is that the number of clock cycles (i.e., 7) is less than the first threshold value (i.e., 8). The current value of the third counter is 4, so the current value of the third counter is subtracted by 2 to obtain the updated value of the third counter, which is 2. The updated value of the third counter is still greater than 0. The second setting unit 6134 maintains the value of the flow standard signal at the first value. The control module 20 receives the flow standard signal having the first value and sets the value of the first control signal to the first control value. At least one instruction processing unit in the first instruction processing unit group continues to be in an operating state.

[0124] In the (m+3)th observation window, the calculation submodule 611 calculates the number of clock cycles of the target clock cycle to be 6. The comparison result obtained by the comparison submodule 612 is that the number of clock cycles (i.e., 6) is less than the first threshold value (i.e., 8). The current value of the third counter is 2, so the current value of the third counter is subtracted by 2 to obtain the updated value of the third counter to be 0. The second setting unit 6134 maintains the value of the flow standard compliance signal at the second value. The control module 20 receives the flow standard compliance signal having the second value and sets the value of the first control signal to the second control value. At least one instruction processing unit in the first instruction processing unit group is in an inoperative state.

[0125] It should be noted that when the third counter is used instead of the first counter and the second counter, the first flow setting unit 6133 and the second flow setting unit 6134 can also be implemented by the same flow setting unit.

[0126] In an embodiment of the present disclosure, when the processor is in the first working mode, the speed at which at least one instruction processing unit in the first instruction processing unit group is in a working state is controlled by the time when the current value and the updated value of the third counter reach the second threshold; the speed at which at least one instruction processing unit in the first instruction processing unit group is in a non-working state is controlled by the time when the current value and the updated value of the third counter decrease to 0.

[0127] In the aforementioned (m+1)th observation window, the updated value of the third counter is 2, indicating that at least one instruction processing unit in the first instruction processing unit group is in an active state. In the (m+3)th observation window, the updated value of the third counter is 0, indicating that at least one instruction processing unit in the first instruction processing unit group is in an inactive state. In other words, the disclosed embodiment can dynamically control whether at least one instruction processing unit in the first instruction processing unit group is in an active or inactive state based on instruction traffic.

[0128] Figure 5 A schematic structural diagram of another processor provided for some embodiments of the present disclosure.

[0129] like Figure 5 As shown, the processor 200 includes an instruction fetch unit 01, a decoding unit 81, a renaming and scheduling unit 02, a configuration module 41, a control module 21, a physical register 03, multiplexers (MUX) 1-4, a second instruction processing unit group 13 and a first instruction processing unit group 12.

[0130] The instruction fetch unit 01 is used to fetch instructions from, for example, a cache or memory, and send them to the decoding unit 81. The decoding unit 81 can decode the instructions fetched by the instruction fetch unit 01 to generate microinstructions and output microinstructions to facilitate processing in subsequent stages. The renaming and scheduling unit 02 can solve data dependency problems to perform out-of-order operations and determine the execution order of instructions based on data availability and the idleness of the instruction execution unit. The physical register 03 is used to store intermediate results or variable values generated during operation, supporting fast data access and operation. The MUX can select one from multiple inputs as an output, Figure 2 The MUX1-4 shown in the figure can implement operations such as operand fetching and write-back between the instruction processing unit and the physical register 03, as well as operand selection between different instruction processing units.

[0131] For example, Figure 5 The diagram shows a case where the second instruction processing unit group 13 includes two instruction processing units 131 and 132. The instruction processing units 131 and 132 of the second instruction processing unit group 13 can process a variety of different types of instructions, such as data processing instructions, program control instructions, floating-point operation instructions, etc. The number of instruction processing units in the second instruction processing unit group 13 should not be regarded as a limitation of the present disclosure. The instruction processing units 131 and 132 of the second instruction processing unit group 13 are always in working state. The instruction processing unit 131 can form a pipeline with the instruction fetch unit 01, the decoding unit 81, the renaming and scheduling unit 02, the physical register 03, and the MUX1. Similarly, the instruction processing unit 132 can form another pipeline with related modules.

[0132] When the processor needs at least two pipelines to process instructions, such as processing floating-point multiplication and accumulation instructions, the two pipelines where the instruction processing units 131 and 132 of the second instruction processing unit group 13 are located can no longer meet the computing power requirements.

[0133] At this time, it may be considered to put the first instruction processing unit group 12 into a working state, that is, to enable the first instruction processing unit group 12 . Figure 5 The first instruction processing unit group 12 includes instruction processing units 121 and 122 , which can process various types of instructions, such as data processing instructions, program control instructions, floating-point operation instructions, etc. The number of instruction processing units included in the first instruction processing unit group should not be considered as a limitation of the present disclosure.

[0134] The configuration module 41 can set the processor 200 to be in the first working mode or the second working mode. In the first working mode, the control module 21 generates a first control signal based on the instruction flow decoded by the decoding unit 81, and the isolation and power supply module ( Figure 5(not shown) under the control of the first control signal, the instruction processing unit 121 and the instruction processing unit 122 of the first instruction processing unit group 12 are controlled to be in a working state or a non-working state.

[0135] In the second working mode, the control module 21 generates a second control signal, and the isolation and power supply module 31 controls the instruction processing unit 121 and the instruction processing unit 122 of the first instruction processing unit group 12 to be in a non-working state under the control of the second control signal.

[0136] The isolation and power module 31 includes a power submodule 311 and an isolation submodule ( Figure 5 (not shown), the isolation submodule includes isolation units 3121 and 3122, and the number of isolation units corresponds one-to-one to the number of instruction processing units in the first instruction processing unit group. The power submodule 311 can provide power signals to the instruction processing units 121 and 122 under the control of a first control signal generated by the control module 21, or not provide power signals under the control of a second control signal. Figure 5 What is shown is the situation of using one power submodule 311 to manage the power supply of the two instruction processing units 121 and 122 of the first instruction processing unit group 12. Multiple power submodules can also be used to manage the power supply of different instruction processing units. This disclosure does not limit this.

[0137] Taking the instruction processing unit 121 of the first instruction processing unit group 12 as an example, the following describes how the power submodule 311 and the isolation unit 3121 of the isolation submodule control the instruction processing unit 111 to be in an operating state or a non-operating state. For example, after the power submodule 311 provides a power signal under the control of a control signal, the isolation unit 3121 is turned on under the control of the control signal, thereby putting the instruction processing unit 121 in an operating state. After the isolation unit 3121 is turned off under the control of the control signal, the instruction processing unit 121 is put into a non-operating state, and the power submodule 311 stops providing the power signal to the instruction processing unit 121 under the control of the control signal.

[0138] The processor 200 can dynamically control the instruction processing units in the first instruction processing unit group 12 to be in a working state or a non-working state according to the instruction flow, thereby improving the processor's processing capability for instructions.

[0139] It should be noted that the various modules in the present disclosure may be implemented in the form of software, hardware, firmware, or any combination thereof.

[0140] Some embodiments of the present disclosure further provide a method for controlling a processor. The method for controlling a processor provided in the embodiments of the present disclosure and the processor provided in the embodiments of the present disclosure are based on the same inventive concept, so the repeated parts will not be repeated. Figure 6A schematic flow chart of a control method for a processor provided in some embodiments of the present disclosure. The processor includes a first instruction processing unit group, the first instruction processing unit group includes at least one instruction processing unit, and in some embodiments, the processor can be Figure 1 The processor 100 is shown. The control method includes steps S100-S200.

[0141] S100, generating a control signal.

[0142] The control signal in step S100 includes a first control signal or a second control signal, and the first control signal is generated based on the command flow rate.

[0143] S200 , controlling at least one instruction processing unit of the first instruction processing unit group to be in an operating state or a non-operating state through a control signal.

[0144] The control method provided by the embodiment of the present disclosure can dynamically control the instruction processing unit to be in a working state or a non-working state according to the instruction flow, so as to improve the processor's processing capability for instructions, and can take into account the performance and power consumption of the processor.

[0145] In some embodiments, the processor also includes an isolation and power supply module, the isolation and power supply module includes a power supply submodule and an isolation submodule, and step S200 may include step S210: after controlling the power supply submodule to provide a power supply signal through a control signal, controlling the isolation submodule to be in an on state through a control signal to put at least one instruction processing unit of the first instruction processing unit group in a working state, or after controlling the isolation submodule to be in an off state through a control signal, controlling the power supply submodule to stop providing a power supply signal to at least one instruction processing unit of the first instruction processing unit group through a control signal to put at least one instruction processing unit in a non-working state.

[0146] For example, a control signal can be first transmitted to the power submodule. After the power submodule begins providing power signals, the control signal can then be transmitted to the isolation submodule, turning the control submodule on. Similarly, to disable an instruction processing unit, a control signal can first be transmitted to the isolation submodule. After the isolation submodule is turned off, the control signal can then be transmitted to the power submodule, stopping the supply of power signals to at least one instruction processing unit.

[0147] In some embodiments, the isolation submodule can be controlled to be in the on state after the power supply is stable to protect sensitive electronic components in the instruction processing unit and ensure that the instruction processing unit starts normally; and the isolation submodule can be controlled to be in the off state first, and then the power submodule can be controlled to stop providing the power signal to avoid data loss or damage in the instruction processing unit.

[0148] In some embodiments, the control method may further include step S300.

[0149] S300: Setting the processor to a first operating mode or a second operating mode.

[0150] Step S100 may include step S110: generating a first control signal based on the command flow in the first working mode; and generating a second control signal in the second working mode.

[0151] Step S200 may include step S220: in a first working mode, controlling at least one instruction processing unit of the first instruction processing unit group to be in a working state or a non-working state through a first control signal; in a second working mode, controlling at least one instruction processing unit of the first instruction processing unit group to be in a working state through a second control signal.

[0152] The embodiments of the present disclosure can set the working mode of the processor according to requirements such as application scenarios, reasonably improve the processor's instruction parallel processing capability, and flexibly meet the requirements of different application scenarios.

[0153] Figure 7 The following is a schematic flow chart of the processor in different working modes provided in some embodiments of the present disclosure. Figure 7 The control method in the above embodiment is described.

[0154] like Figure 7 As shown, after the processor starts running, the processor is set to the first working mode or the second working mode according to step S300.

[0155] When the processor is in the second working mode, a second control signal is generated, and at least one instruction processing unit of the first instruction processing unit group is controlled to be in a working state through the second control signal.

[0156] In order to prevent configuration errors, it is determined whether the processor has exited the second working mode.

[0157] When it is determined that the processor does not exit the second operating mode, at least one instruction processing unit in the first instruction processing unit group is kept in an operating state.

[0158] When it is determined that the processor exits the second working mode, it is necessary to determine whether at least one instruction processing unit in the first instruction processing unit group has completed the execution of the current instruction. If at least one instruction processing unit in the first instruction processing unit group has completed the execution of the current instruction, or there is no instruction being executed, then at least one instruction processing unit in the first instruction processing unit group can be controlled to change from a working state to a non-working state. Otherwise, it is necessary to keep at least one instruction processing unit in the first instruction processing unit group in a working state until the current instruction is executed. Only then can at least one instruction processing unit in the first instruction processing unit group be controlled to change from a working state to a non-working state.

[0159] The above embodiment can determine again whether the processor is in the second working mode set by the configuration module by judging whether the processor has exited the second working mode, prevent the processor from mistakenly entering the second working mode when it is not set to the second working mode, accurately select the working mode of the processor, and thus avoid power consumption waste.

[0160] When the processor is in the first operating mode, the instruction flow can be detected and a first control signal can be generated based on the instruction flow. For example, a value of a flow compliance signal can be determined based on the instruction flow to determine the operating status of at least one instruction processing unit of the first instruction processing unit group.

[0161] When the flow rate reaching signal is the first value, the value of the first control signal is set to the first control value. At this time, at least one instruction processing unit of the first instruction processing unit group is in working state under the control of the first control signal.

[0162] Otherwise, when the flow standard signal is the second value, the value of the first control signal is set to the second control value, and at least one instruction processing unit of the first instruction processing unit group is in a non-working state under the control of the first control signal.

[0163] Similar to when the processor exits the second working mode, in the first working mode, before at least one instruction processing unit in the first instruction processing unit group becomes a non-working state, it is necessary to first determine whether at least one instruction processing unit in the first instruction processing unit group has completed the execution of the current instruction. After at least one instruction processing unit in the first instruction processing unit group completes the execution of the current instruction, control at least one instruction processing unit to change from a working state to a non-working state.

[0164] In order to more accurately control the timing when at least one instruction processing unit in the first instruction processing unit group is in a working state and a non-working state, so that the processor can flexibly meet application scenarios with different instruction flows, the instruction flow can be checked at different times to adjust the working status of at least one instruction processing unit in the first instruction processing unit group in real time according to the instruction flow.

[0165] For example, in the first working mode, controlling at least one instruction processing unit of the first instruction processing unit group to be in a working state or a non-working state through a first control signal includes: performing the above-mentioned detection operation at a first moment to obtain a first instruction flow, using the first instruction flow as the instruction flow, setting the value of the first flow standard signal according to the first instruction flow, when the value of the first flow standard signal is a first value, setting and using the first control signal according to the first flow standard signal with the first value to control at least one instruction processing unit in the first instruction processing unit group to be in a working state; when the value of the first flow standard signal is a second value, setting and using the first control signal according to the first flow standard signal with the second value to control at least one instruction processing unit in the first instruction processing unit group to be in a non-working state.

[0166] The first flow standard signal is the flow standard signal at the first moment, and the process of setting the value of the first flow standard signal according to the first instruction flow is the same as the aforementioned operation of setting the value of the flow standard signal according to the instruction flow.

[0167] The same operation as at the first moment can be performed again at a second moment after the first moment. For example, in the first working mode, controlling at least one instruction processing unit to be in a working state or a non-working state by using a first control signal also includes: detecting a second instruction flow at the second moment, using the second instruction flow as the instruction flow, setting the value of a second flow standard signal according to the second instruction flow, and when the value of the second flow standard signal is a first value, setting and using the first control signal according to the second flow standard signal having the first value to control at least one instruction processing unit in the first instruction processing unit group to be in a working state; when the value of the second flow standard signal is a second value, setting and using the first control signal according to the second flow standard signal having the second value to control at least one instruction processing unit in the first instruction processing unit group to be in a non-working state. The second flow standard signal is the flow standard signal at the second moment.

[0168] For example, Figure 7 As shown, at a first moment, the command flow rate is detected, the detected first command flow rate is used as the command flow rate, and a first flow standard compliance signal is set based on the command flow rate. Next, a determination is made as to whether the first flow standard compliance signal is a first value. If the first flow standard compliance signal is the first value, at least one command processing unit of the first command processing unit group is controlled to be in an operating state. If the first flow standard compliance signal is not the first value, the command flow rate may be further detected, and the above-described operation may be repeated until at least one command processing unit of the first command processing unit group is in an operating state.

[0169] At a second moment after the first moment, when the instruction processing units in the first instruction unit group are already in an operating state, the instruction flow rate is detected again, the second instruction flow rate detected is used as the instruction flow rate, and a second flow rate attainment signal is set based on the instruction flow rate. If the value of the second flow rate attainment signal is still the first value, at least one instruction processing unit in the first instruction processing unit group is controlled to be in an operating state. If the value of the second flow rate attainment signal is not the first value, then after at least one instruction processing unit in the first instruction processing unit group completes execution of the current instruction, at least one instruction processing unit in the first instruction processing unit group is controlled to be in a non-operating state.

[0170] When at least one instruction processing unit in the first instruction processing unit group is controlled to be in a non-working state, the instruction flow can be detected again, and a flow standard signal can be set according to the instruction flow, so as to realize real-time control of the instruction processing units in the first instruction processing unit group to be in a working state or a non-working state according to the flow standard signal.

[0171] In some embodiments, determining the value of the flow rate compliance signal according to the command flow rate may include steps S400-S700.

[0172] S400 , calculating the number of clock cycles of at least one target clock cycle within a plurality of clock cycles based on instruction flow.

[0173] In step S400, the number of instruction processing units required to be used in each of at least one target clock cycle is greater than a unit number threshold, which may be equal to the number N of instruction processing units in the second instruction processing unit.

[0174] S500: Set a first threshold.

[0175] S600 , comparing the number of clock cycles with a first threshold to obtain a comparison result.

[0176] S700: Set the value of the flow rate reaching standard signal according to the comparison result.

[0177] In step S700, the value of the flow standard attainment signal may include a first value and a second value. The first value of the flow standard attainment signal indicates that at least one instruction processing unit in the first instruction processing unit group is controlled to be in an operating state, and the second value of the flow standard attainment signal indicates that at least one instruction processing unit in the first instruction processing unit group is controlled to be in a non-operating state.

[0178] Figure 8 A schematic flow chart of setting a flow rate reaching signal according to some embodiments of the present disclosure is provided below. Figure 8 Steps S400 to S700 are described.

[0179] For example, before performing step S400, the control method may further include: decoding generated microinstructions to determine the number of instructions corresponding to each of a plurality of clock cycles; and determining the number of instruction processing units required for each of the plurality of clock cycles based on the number of instructions. The instruction flow may include the number of instructions corresponding to each of the plurality of clock cycles and the number of instruction processing units required for each of the plurality of clock cycles.

[0180] Afterwards, step S400 may be performed to calculate the number of clock cycles of at least one target clock cycle within a plurality of clock cycles based on the instruction flow. The plurality of clock cycles may be set to, for example, 64 clock cycles.

[0181] Then, the relationship between the number of clock cycles and the first threshold is compared. The first threshold can be set to 8, 16, 32, 48, etc. as needed. For example, when the unit quantity threshold is equal to the number N of instruction processing units in the second instruction processing unit group, when the comparison result is that the number of clock cycles is less than the first threshold, it means that the instruction processing units in the second instruction processing unit group can meet the instruction processing requirements or the impact of using only the instruction processing units in the second instruction processing unit group on performance is acceptable; when the comparison result is that the number of clock cycles is greater than or equal to the first threshold, it means that using only the instruction processing units in the second instruction processing unit group cannot meet the instruction processing requirements or the impact of using only the instruction processing units in the second instruction processing unit group on performance is unacceptable.

[0182] In step S700, specifically, Figure 8 As shown, when the comparison result indicates that the number of clock cycles is greater than or equal to the first threshold, the relationship between the current value of the first counter and the second threshold is determined. The initial value of the first counter is 0. The value of the second threshold can be set as needed, for example, to 4, 8, 16, 32, etc.

[0183] When the current value of the first counter is less than the second threshold, the current value of the first counter is added to the first value to obtain an updated value of the first counter. The first value may be a positive integer, for example, 1, 2, 3, etc.

[0184] The relationship between the updated value of the first counter and the second threshold is determined, and when it is determined that the updated value of the first counter is equal to the second threshold, the value of the flow standard compliance signal is set to the first value. When it is determined that the updated value of the first counter is still less than the second threshold, that is, the updated value of the first counter is not equal to the second threshold, the value of the flow standard compliance signal remains unchanged.

[0185] When the current value of the first counter is greater than or equal to the second threshold, the value of the flow rate reaching standard signal is kept unchanged.

[0186] In step S700, Figure 8As shown, when the comparison result indicates that the number of clock cycles is less than the first threshold, it is necessary to determine the magnitude relationship between the current value of the second counter and 0.

[0187] When the current value of the second counter is equal to 0, the flow rate reaching standard signal is kept unchanged.

[0188] When the value of the second counter is greater than 0, the second value is subtracted from the current value of the second counter to obtain an updated value of the second counter. The initial value of the second counter may be q, where q is a positive integer. The updated value of the second counter is not less than 0, i.e., the current value of the second counter is also not less than 0. The second value may be a positive integer, for example, the first value may be 1, 2, 3, etc.

[0189] The relationship between the updated value of the second counter and 0 is determined, and when it is determined that the updated value of the second counter is equal to 0, the value of the flow standard compliance signal is set to the second value. When it is determined that the updated value of the second counter is still greater than 0, the value of the flow standard compliance signal is maintained unchanged.

[0190] In an embodiment of the present disclosure, a first counter and a second counter are used respectively to control the speed at which at least one instruction processing unit in the first instruction processing unit group enters a working state and a non-working state. Alternatively, one counter can be used as both the first counter and the second counter, and the same first value and second value are set.

[0191] For example, a third counter is used instead of the first counter and the second counter, and a third value is used instead of the first value and the second value.

[0192] When the comparison result indicates that the number of clock cycles is greater than or equal to the first threshold, the magnitude relationship between the current value of the third counter and the second threshold is determined.

[0193] When the current value of the third counter is less than the second threshold, the current value of the third counter is added to the third value to obtain an updated value of the third counter. The third value can be a positive integer. For example, the third value can be 1, 2, 3, etc.

[0194] The relationship between the updated value of the third counter and the second threshold is determined, and when it is determined that the updated value of the third counter is equal to the second threshold, the value of the flow standard compliance signal is set to the first value. When it is determined that the updated value of the third counter is still less than the second threshold, that is, the updated value of the third counter is not equal to the second threshold, the value of the flow standard compliance signal remains unchanged.

[0195] When the current value of the third counter is greater than or equal to the second threshold, the value of the flow rate reaching standard signal is kept unchanged.

[0196] When the comparison result indicates that the number of clock cycles is less than the first threshold, it is necessary to determine the magnitude relationship between the current value of the third counter and 0.

[0197] When the current value of the third counter is equal to 0, the flow rate reaching standard signal is kept unchanged.

[0198] When the value of the third counter is greater than 0, the third value is subtracted from the current value of the third counter to obtain an updated value of the third counter. The updated value of the third counter is not less than 0.

[0199] The relationship between the updated value of the third counter and 0 is determined, and when it is determined that the updated value of the third counter is equal to 0, the value of the flow standard compliance signal is set to the second value. When it is determined that the updated value of the third counter is still greater than 0, the value of the flow standard compliance signal is maintained unchanged.

[0200] Thus, when the processor is in the first working mode, the speed at which at least one instruction processing unit in the first instruction processing unit group is in the working state can be controlled by the time when the current value and the updated value of the third counter reach the second threshold; and the speed at which at least one instruction processing unit in the first instruction processing unit group is in the non-working state can be controlled by the time when the current value and the updated value of the third counter decrease to 0.

[0201] Figure 9 A schematic diagram of the structure of an electronic device provided in some embodiments of the present disclosure. The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), and in-vehicle terminals (e.g., in-vehicle navigation terminals), as well as fixed terminals such as digital TVs and desktop computers. Figure 9 The electronic device shown is only an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0202] like Figure 9 As shown, the electronic device 300 may include a processing device (e.g., one or more central processing units, one or more graphics processing units, etc.) 310, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 320 or a program loaded from a storage device 380 into a random access memory (RAM) 330. The processing device 310 includes a processor according to any embodiment of the present disclosure. Various executable programs and data required for the operation of the electronic device 300 are also stored in the RAM 330. The processing device 310, the ROM 320, and the RAM 330 are connected to each other via a bus 340. An input / output (I / O) interface 350 is also connected to the bus 340.

[0203] Typically, the following devices may be connected to the I / O interface 350: an input device 360 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, or a gyroscope; an output device 370 including, for example, a liquid crystal display (LCD), a speaker, or a vibrator; a storage device 380 including, for example, a magnetic tape, a hard disk, and the like; and a communication device 390. The communication device 390 may allow the electronic device 300 to communicate with other electronic devices wirelessly or by wire to exchange data. Figure 9 The electronic device 300 is shown to include various devices, but it should be understood that it is not required to implement or possess all of the devices shown, and the electronic device 300 may instead implement or possess more or fewer devices.

[0204] For example, according to an embodiment of the present disclosure, the control method of the processor described above may be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product including a computer program carried on a non-transitory computer-readable medium, the computer program including program code for executing the control method of the processor described above.

[0205] In at least one embodiment of the present disclosure, the computer program can be downloaded and installed from the network through the communication device 390, or installed from the above-mentioned storage device 380, or installed from the ROM 320. When the computer program is executed by the processing device 310, the functions defined in the processor control method provided in the embodiment of the present disclosure can be performed.

[0206] Some embodiments of the present disclosure also provide a non-transitory storage medium for storing non-transitory computer program executable code (e.g., computer executable instructions). When the non-transitory computer program executable code is executed by a computer (e.g., including one or more processors), the processor control method of any embodiment of the present disclosure can be implemented.

[0207] Figure 10 A schematic diagram of a non-transitory storage medium provided in some embodiments of the present disclosure. Figure 10 As shown, the non-transitory storage medium 400 non-transitory stores computer-readable instructions 401. For example, when the computer-readable instructions 401 are executed by a computer (eg, including one or more processors), the processor control method provided according to the embodiment of the present disclosure can be executed.

[0208] For example, the non-transitory storage medium 400 may be applied to the electronic device 300. Figure 9 The memory 320 in the electronic device 300 is shown. For example, the description of the non-transitory storage medium 400 can be referred to Figure 9The corresponding description of the memory 320 in the electronic device 300 is not repeated here.

[0209] Although the present disclosure has been described in detail above using general descriptions and specific embodiments, it will be apparent to those skilled in the art that modifications or improvements may be made based on the embodiments of the present disclosure. Therefore, such modifications or improvements, as long as they do not depart from the spirit of the present disclosure, are within the scope of protection claimed by the present disclosure.

[0210] Regarding this disclosure, the following points need to be explained:

[0211] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0212] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale.

[0213] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0214] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A processor, comprising: A first instruction processing unit group, comprising at least one instruction processing unit; a control module configured to generate a control signal, wherein the control signal includes a first control signal or a second control signal, and the first control signal is generated based on a command flow rate; The isolation and power supply module is configured to control the at least one instruction processing unit to be in a working state or a non-working state under the control of the control signal.

2. The processor according to claim 1, wherein: The isolation and power supply module includes: a power supply submodule configured to provide a power supply signal or not provide the power supply signal to the at least one instruction processing unit under the control of the control signal.

3. The processor according to claim 2, wherein: The isolation and power module also includes an isolation submodule, After the power submodule provides the power signal under the control of the control signal, the isolation submodule is in an on state under the control of the control signal, so that the at least one instruction processing unit is in the working state; After the isolation submodule is in the disconnected state under the control of the control signal, the power submodule stops providing the power signal to the at least one instruction processing unit under the control of the control signal, wherein the at least one instruction processing unit is in the non-working state when the isolation submodule is in the disconnected state.

4. The processor according to claim 1, wherein: The isolation and power supply module further includes an isolation submodule, wherein the isolation submodule includes at least one isolation unit corresponding to the at least one instruction processing unit. Each of the at least one isolation units receives the control signal and, under the control of the control signal, controls the corresponding instruction processing unit to be in a working state or a non-working state.

5. The processor of claim 1 , further comprising: a configuration module configured to set the processor to a first operating mode or a second operating mode, Wherein, in the first working mode, the control module is configured to generate the first control signal based on the instruction flow, and the isolation and power supply module controls the at least one instruction processing unit to be in the working state or the non-working state under the control of the first control signal; In the second working mode, the control module is configured to generate the second control signal, and the isolation and power supply module controls the at least one instruction processing unit to be in the working state under the control of the second control signal.

6. The processor of claim 5 , further comprising: A judging module is configured to judge whether the processor exits the second working mode, wherein: When the judgment module determines that the processor does not exit the second working mode, the at least one instruction processing unit remains in the working state; When the judgment module determines that the processor exits the second working mode, in response to the at least one instruction processing unit completing the execution of the current instruction, the at least one instruction processing unit changes from the working state to the non-working state.

7. The processor of claim 5, further comprising: The flow standard signal determination module is configured to determine the value of the flow standard signal according to the instruction flow in response to the processor being set to be in the first working mode, wherein: The control module is configured to: in response to the value of the flow standard reaching signal being a first value, set the value of the first control signal to a first control value, wherein when the value of the first control signal is the first control value, the isolation and power supply module controls the at least one instruction processing unit to be in the working state under the control of the first control signal; The control module is further configured to: in response to the value of the flow standard signal being a second value, set the value of the first control signal to a second control value, wherein when the value of the first control signal is the second control value, the isolation and power supply module controls the at least one instruction processing unit to be in the non-working state under the control of the first control signal.

8. The processor of claim 7, further comprising: The detection module is configured to detect, in response to the processor being in the first working mode, at multiple moments and obtain multiple instruction flows corresponding to the multiple moments respectively.

9. The processor according to claim 7, wherein: The flow standard signal determination module includes: a calculation submodule configured to calculate, based on the instruction flow, a number of clock cycles of at least one target clock cycle within a plurality of clock cycles, wherein a number of instruction processing units required to be used in each of the at least one target clock cycle is greater than a unit number threshold; a comparison submodule, configured to compare the number of clock cycles with a first threshold to obtain a comparison result; The setting submodule is configured to set the value of the flow standard reaching signal according to the comparison result.

10. The processor of claim 9, wherein: The setting submodule includes: a first determining unit configured to, in response to the comparison result indicating that the number of clock cycles is greater than or equal to the first threshold, obtain a current value of the first counter, and determine a magnitude relationship between the current value of the first counter and the second threshold; The first setting unit is configured to, in response to the current value of the first counter being less than the second threshold, add a first numerical value to the current value of the first counter to obtain an updated value, wherein the first numerical value is a positive integer; when it is determined that the updated value is equal to the second threshold, set the value of the flow standard signal to the first value, wherein the initial value of the first counter is 0; in response to the current value of the first counter being greater than or equal to the second threshold or when it is determined that the updated value is not equal to the second threshold, maintain the value of the flow standard signal unchanged.

11. The processor according to claim 10, wherein: The setting submodule also includes: a second judgment unit configured to, in response to the comparison result indicating that the number of clock cycles is less than the first threshold, obtain a current value of a second counter, and determine a magnitude relationship between the current value of the second counter and 0; The second setting unit is configured to, in response to the current value of the second counter being greater than 0, subtract a second value from the current value of the second counter to obtain an updated value, wherein the initial value of the second counter is p, p is a positive integer, and the updated value is not less than 0; when it is determined that the updated value is equal to 0, set the value of the flow standard signal to the second value; in response to the current value of the second counter being equal to 0 or when it is determined that the updated value is greater than 0, keep the value of the flow standard signal unchanged.

12. The processor of claim 1 , further comprising: The decoding unit is configured to determine the number of instructions to obtain the instruction flow.

13. The processor of claim 1 , further comprising: A second instruction processing unit group, wherein the second instruction processing unit group includes N instruction processing units, N is a positive integer, and the N instruction processing units are always in a working state.

14. The processor according to any one of claims 1 to 13, wherein: All instruction processing units in the first instruction processing unit group are used to process instructions of the same type.

15. A method for controlling a processor, wherein: The processor includes a first instruction processing unit group, the first instruction processing unit group includes at least one instruction processing unit, The control method includes: generating a control signal, wherein the control signal comprises a first control signal or a second control signal, and the first control signal is generated based on a command flow rate; The at least one instruction processing unit is controlled to be in a working state or a non-working state by the control signal.

16. The control method according to claim 15, wherein: The processor further includes an isolation and power supply module, the isolation and power supply module including a power supply submodule and an isolation submodule, and the controlling of the at least one instruction processing unit to be in a working state or a non-working state by the control signal includes: After controlling the power submodule to provide a power signal through the control signal, controlling the isolation submodule to be in an on state through the control signal to put the at least one instruction processing unit in the working state, or After the isolation submodule is controlled to be in the disconnected state by the control signal, the power submodule is controlled by the control signal to stop providing the power signal to the at least one instruction processing unit, so that the at least one instruction processing unit is in the non-working state.

17. The control method according to claim 15, further comprising: Setting the processor to a first operating mode or a second operating mode, Wherein, generating a control signal includes: In the first operating mode, generating the first control signal based on the instruction flow; and In the second operating mode, generating the second control signal; The controlling the at least one instruction processing unit to be in the working state or the non-working state by the control signal includes: In the first working mode, controlling the at least one instruction processing unit to be in the working state or the non-working state through the first control signal; In the second working mode, the at least one instruction processing unit is controlled to be in a working state by the second control signal.

18. The control method according to claim 17, further comprising: determining whether the processor exits the second operating mode, Determining that the processor does not exit the second operating mode, and maintaining the at least one instruction processing unit in the operating state; Determining that the processor exits the second working mode, and in response to the at least one instruction processing unit completing execution of a current instruction, controlling the at least one instruction processing unit to change from the working state to the non-working state.

19. The control method according to claim 17, wherein: The step of generating a first control signal based on the instruction flow in the first working mode includes: Determining the value of the flow rate compliance signal according to the command flow rate; In response to the value of the flow standard reaching signal being a first value, setting the value of the first control signal to a first control value, wherein when the value of the first control signal is the first control value, the at least one instruction processing unit is in the working state under the control of the first control signal; In response to the value of the flow standard signal being a second value, the value of the first control signal is set to a second control value, wherein when the value of the first control signal is the second control value, the at least one instruction processing unit is in the non-working state under the control of the first control signal.

20. The control method according to claim 19, wherein: In the first working mode, controlling the at least one instruction processing unit to be in the working state or the non-working state by the first control signal includes: At a first moment, a first instruction flow is detected and taken as the instruction flow. According to the command flow rate, setting the value of the first flow rate reaching standard signal; In response to the value of the first flow standard reaching signal being a first value, controlling the at least one instruction processing unit to be in an operating state using the first control signal; In response to the value of the first flow standard attainment signal being a second value, the first control signal is used to control the at least one instruction processing unit to be in a non-working state.

21. The control method according to claim 20, wherein: The step of controlling the at least one instruction processing unit to be in the working state or the non-working state using the first control signal in the first working mode further includes: At a second moment, a second instruction flow is detected and taken as the instruction flow, wherein the second moment is after the first moment, According to the command flow, the value of the second flow standard reaching signal is set, In response to the value of the second flow rate reaching standard signal being the first value, using the first control signal to control the at least one instruction processing unit to be in an operating state; In response to the value of the second flow standard reaching signal being the second value, after the at least one instruction processing unit completes execution of the current instruction, the at least one instruction processing unit is controlled to be in a non-working state.

22. The control method according to claim 19, wherein: Determining the value of the flow standard reaching signal according to the command flow includes: Calculating, based on the instruction flow, a number of clock cycles of at least one target clock cycle within a plurality of clock cycles, wherein a number of instruction processing units required to be used in each of the at least one target clock cycle is greater than a unit number threshold; Setting a first threshold; comparing the number of clock cycles with the first threshold to obtain a comparison result; The value of the flow standard reaching signal is set according to the comparison result.

23. The control method according to claim 22, wherein: The step of setting the value of the flow standard reaching signal according to the comparison result includes: In response to the comparison result indicating that the number of clock cycles is greater than or equal to the first threshold, determining a magnitude relationship between a current value of the first counter and a second threshold; In response to the current value of the first counter being greater than or equal to the second threshold, maintaining the value of the flow standard attainment signal unchanged; In response to the current value of the first counter being less than the second threshold, adding a first value to the current value of the first counter to obtain an updated value, Determining that the updated value is equal to the second threshold, setting the value of the flow standard reaching signal to the first value, wherein the initial value of the first counter is 0; Determine that the updated value is not equal to the second threshold, and keep the value of the flow standard compliance signal unchanged.

24. The control method according to claim 22, wherein: The step of setting the value of the flow standard reaching signal according to the comparison result includes: In response to the comparison result indicating that the number of clock cycles is less than the first threshold, determining a magnitude relationship between a current value of the second counter and 0, In response to the current value of the second counter being equal to 0, maintaining the value of the flow standard attainment signal unchanged; In response to a current value of the second counter being greater than 0, subtracting a second value from the current value of the second counter to obtain an updated value, wherein the initial value of the second counter is p, p is a positive integer, and the updated value is not less than 0; Determine that the updated value is equal to 0, and set the value of the flow standard signal to the second value; determine that the updated value is greater than 0, and keep the value of the flow standard signal unchanged.

25. The control method according to claim 23 or 24, further comprising: Decoding and generating microinstructions to determine the number of instructions corresponding to each of the plurality of clock cycles; Determining, based on the number of instructions, a number of instruction processing units to be used in each of the plurality of clock cycles; The instruction flow includes the number of instructions and the number of instruction processing units.

26. An electronic device comprising: at least one processor, A memory non-transitorily stores computer-readable instructions, wherein when the computer-readable instructions are executed by the at least one processor, the control method according to any one of claims 15 to 25 is performed.

27. A non-transitory storage medium that non-transitory stores computer-readable instructions, wherein: When the computer-readable instructions are executed by a computer, the control method according to any one of claims 15 to 25 is performed.

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