Instruction execution method and device and vector processor

Abstract

The invention discloses an instruction execution method and device and a vector processor, the vector processor comprises a plurality of function units, each function unit corresponds to an instruction slot, and the method comprises the following steps: obtaining a delay beat number corresponding to each operation instruction in a to-be-executed instruction packet, and executing the to-be-executed instruction packet according to the delay beat number and the instruction slot corresponding to each operation instruction; a wait instruction is generated in the instruction fetching queue of each instruction slot; according to the order of the instructions in each instruction fetching queue, pressing the instructions in each instruction fetching queue into a distribution queue of a corresponding instruction slot; and distributing the instruction in the distribution queue of each instruction slot to the corresponding functional unit, and executing the instruction through the functional unit. According to the technical scheme, the problem that in the prior art, when a plurality of function units execute instructions in parallel, conflicts occur in the execution process can be avoided, so that the time consumed for instruction execution is saved, and the execution efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an instruction execution method, device and vector processor. Background Art

[0002] In the prior art, when a vector processor executes instructions, multiple operation instructions are usually stored in the same instruction packet, and the instructions are executed in parallel by multiple functional units.

[0003] In the scenario of parallel execution, since subsequent instructions may use the execution results of previous instructions, it is easy for the instruction execution cycles to be different, resulting in conflicts in the instruction execution process. Summary of the Invention

[0004] The present invention provides an instruction execution method, device and vector processor, which can avoid the problem of execution process conflicts when multiple functional units execute instructions in parallel in the prior art, thereby saving instruction execution time and improving execution efficiency.

[0005] According to one aspect of the present invention, an instruction execution method is provided, which is applied to a vector processor, wherein the vector processor includes multiple functional units, each functional unit corresponding to an instruction slot, and the method includes:

[0006] Obtaining the delay count corresponding to each operation instruction in the instruction packet to be executed, and generating a wait instruction in the instruction fetch queue of each instruction slot according to the delay count and the instruction slot corresponding to each operation instruction;

[0007] According to the order of instructions in each instruction fetch queue, push the instructions in each instruction fetch queue into the dispatch queue of the corresponding instruction slot;

[0008] The instructions in the dispatch queue of each instruction slot are dispatched to the corresponding functional unit, and the instructions are executed by the functional unit.

[0009] Optionally, obtain the delay count corresponding to each operation instruction in the instruction packet to be executed, including:

[0010] Get the preset wait immediate instruction corresponding to each operation instruction;

[0011] According to the target bit in the wait immediate instruction, the delay beat number corresponding to the operation instruction is obtained.

[0012] Optionally, obtain the delay count corresponding to each operation instruction in the instruction packet to be executed, including:

[0013] Get the preset wait register instruction corresponding to each operation instruction;

[0014] According to the wait register instruction and the instruction slot corresponding to the operation instruction, query the target register storing the delay beat number in a pre-built delay beat number mapping table;

[0015] The delay count corresponding to the operation instruction is obtained according to the target bit corresponding to the target register in the delay count mapping table.

[0016] Optionally, push the instructions in each instruction fetch queue into the dispatch queue of the corresponding instruction slot, including:

[0017] In each instruction fetch queue, one instruction to be dispatched is obtained in sequence as the current instruction.

[0018] If the current instruction is a wait instruction, the current wait instruction and the matching empty instruction are pushed into the dispatch queue of the corresponding instruction slot according to the delay beat number corresponding to the current wait instruction.

[0019] Optionally, according to the delay count corresponding to the current wait instruction, the current wait instruction and the matching empty instruction are pushed into the dispatch queue of the corresponding instruction slot, and further comprising:

[0020] If there is a subsequent wait instruction after the current wait instruction in the instruction fetch queue, comparing the first delay beat number corresponding to the subsequent wait instruction with the second delay beat number corresponding to the current wait instruction;

[0021] According to the comparison result of the first delay beat number and the second delay beat number, the instruction push strategy after the current wait instruction is determined.

[0022] Optionally, determining a strategy for pushing an instruction following the current wait instruction according to a comparison result of the first delay beat count and the second delay beat count includes:

[0023] Determine whether the first delay beat number is greater than the second delay beat number;

[0024] If yes, the difference between the first delay beat number and the second delay beat number is used as the number of empty instructions to be pushed into the dispatch queue corresponding to the subsequent wait instruction;

[0025] If not, determine whether the first delay beat number is zero;

[0026] If it is zero, all instructions following the subsequent wait instruction are determined to be invalid instructions, and the invalid instructions are discarded;

[0027] If it is not zero, invalid instructions are screened out from the instructions following the subsequent wait instruction according to the difference between the second delay beat number and the first delay beat number, and the invalid instructions are discarded.

[0028] Optionally, after determining whether the first delay beat number is zero, the method further includes:

[0029] If the first delay beat number is zero, and the subsequent wait instruction also carries a core wait instruction, then all instructions after the subsequent wait instruction are determined to be valid instructions.

[0030] Optionally, before pushing the instructions in each instruction fetch queue into the dispatch queue of the corresponding instruction slot, the process further includes:

[0031] In all instruction fetch queues of all instruction slots, determine whether there is a core wait instruction in the current instruction to be dispatched;

[0032] If so, the wait instructions in all instruction fetch queues are aligned according to the core wait instruction and the delay beat number corresponding to the wait instruction in each instruction fetch queue, so that subsequent instructions after the wait instruction are distributed at the same time.

[0033] Optionally, according to the core wait instruction and the delay count corresponding to the wait instruction in each instruction fetch queue, aligning the wait instructions in all instruction fetch queues includes:

[0034] In all instruction fetch queues of all instruction slots, determine whether the current instruction to be dispatched includes a wait instruction;

[0035] If not, the number of empty instructions pushed into each instruction slot is determined based on the difference between the maximum delay beats of wait instructions in all instruction fetch queues and the delay beats of wait instructions in each instruction fetch queue.

[0036] According to the number of empty instructions pushed into each instruction slot, the corresponding empty instructions are pushed into the dispatch queue of each instruction slot.

[0037] Optionally, after determining whether the current instruction to be dispatched includes a wait instruction in all instruction fetch queues of all instruction slots, the following steps are further included:

[0038] If yes, and the delay beat number of the current wait instruction is less than the maximum delay beat number, then determining the difference between the current wait instruction and the subsequent wait instruction;

[0039] Selecting the maximum difference as the target delay beat number, and determining the number of empty instructions to be pushed into each instruction slot according to the target delay beat number and the differences;

[0040] According to the number of empty instructions pushed into each instruction slot, the corresponding empty instructions are pushed into the dispatch queue of each instruction slot.

[0041] According to another aspect of the present invention, an instruction execution device is provided, which is applied to a vector processor. The vector processor includes multiple functional units, each functional unit corresponding to an instruction slot, and the device includes:

[0042] An instruction generation module is used to obtain the delay beat number corresponding to each operation instruction in the instruction packet to be executed, and generate a wait instruction in the instruction fetch queue of each instruction slot according to the delay beat number and the instruction slot corresponding to each operation instruction;

[0043] An instruction push module is used to push the instructions in each instruction fetch queue into the dispatch queue of the corresponding instruction slot according to the order of the instructions in each instruction fetch queue;

[0044] The instruction dispatch module is used to dispatch the instructions in the dispatch queue of each instruction slot to the corresponding functional unit, and execute the instructions through the functional unit.

[0045] According to another aspect of the present invention, a vector processor is provided, the vector processor comprising:

[0046] at least one processing core; and

[0047] a memory communicatively connected to the at least one processing core; wherein,

[0048] The memory stores a computer program that can be executed by the at least one processing core. The computer program is executed by the at least one processing core so that the at least one processing core can perform the instruction execution method described in any embodiment of the present invention.

[0049] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processing core to implement the instruction execution method described in any embodiment of the present invention when executed.

[0050] The technical solution provided by the embodiment of the present invention obtains the delay beat number corresponding to each operation instruction in the instruction package to be executed, and generates a wait instruction in the instruction fetch queue of each instruction slot according to the delay beat number and the instruction slot corresponding to each operation instruction, and pushes the instructions in each instruction fetch queue into the distribution queue of the corresponding instruction slot according to the order of instructions in each instruction fetch queue, distributes the instructions in the distribution queue of each instruction slot to the corresponding functional unit, and executes the instructions by the functional unit. This technical solution can realize the delayed distribution of the instructions to be executed, avoid the problem of conflict in the execution process when multiple functional units execute instructions in parallel in the prior art, thereby saving the time spent on instruction execution and improving execution efficiency.

[0051] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0053] Figure 1 is a flowchart of an instruction execution method provided according to an embodiment of the present invention;

[0054] Figure 2 is a flowchart of another instruction execution method provided according to an embodiment of the present invention;

[0055] Figure 3 is a flowchart of another instruction execution method provided according to an embodiment of the present invention;

[0056] Figure 4 is a structural diagram of an instruction execution device provided according to an embodiment of the present invention;

[0057] Figure 5 It is a structural diagram of a vector processor that implements the instruction execution method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0058] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0059] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0060] Figure 1 This is a flowchart of an instruction execution method provided by an embodiment of the present invention. This embodiment is applicable to the case where a vector processor executes instructions. The vector processor includes multiple functional units, each functional unit corresponds to an instruction slot. The method can be executed by an instruction execution device, which can be configured in the vector processor. Figure 1 As shown, the method includes:

[0061] Step 110: Obtain the delay count corresponding to each operation instruction in the instruction packet to be executed, and generate a wait instruction in the instruction fetch queue of each instruction slot according to the delay count and the instruction slot corresponding to each operation instruction.

[0062] In this embodiment, the vector processor executes instructions in the following stages:

[0063] Fetch (FT): In the instruction fetch phase, the instruction word is read from the memory. The address is the value of the program counter (PC). The length of the very long instruction word (VLIW) instruction packet is determined based on the description segment in the fetched instruction word.

[0064] Decode (DC): Decoding stage, which determines which functional units have instructions and which functional units are empty according to the description segment in the instruction word;

[0065] Dispatch (DP): Instruction distribution, distributing instructions to various functional units;

[0066] Execution (EX): Instruction execution, at this stage the functional unit identifies what instruction to be executed, reads the source operand in the register, performs the operation or accesses the memory, and finally writes the result back.

[0067] To address the existing issue of execution conflicts when multiple functional units execute instructions concurrently, this embodiment provides a method for generating wait instructions for corresponding instruction slots based on the delay count of each instruction in an instruction packet before dispatching the instruction. The delay count for each instruction can be pre-configured based on the dependencies between the instructions and the execution cycle of each instruction.

[0068] In a specific embodiment, assuming that the instruction packet to be executed includes operation instructions A, operation instructions B, and operation instructions C, and that the execution result of operation instruction A is required for the execution of operation instruction B, and the execution result of operation instruction B is required for the execution of operation instruction C. Assuming that operation instruction A requires three execution cycles and operation instruction B requires two execution cycles, it can be determined that the delay number corresponding to operation instruction B is 3, and the delay number corresponding to operation instruction C is 5. Therefore, a wait3 may be generated in the instruction fetch queue of the instruction slot corresponding to operation instruction B, and a wait5 may be generated in the instruction fetch queue of the instruction slot corresponding to operation instruction C.

[0069] Step 120 : According to the order of the instructions in each instruction fetch queue, push the instructions in each instruction fetch queue into the dispatch queue of the corresponding instruction slot.

[0070] In this step, each instruction can be pushed into the distribution queue of the corresponding instruction slot according to the order of instructions in the instruction fetch queue of each instruction slot. The wait instruction is used to delay the distribution of the instructions of the corresponding instruction slot. When the delay count is zero, the pipeline of the corresponding instruction slot returns to normal.

[0071] Step 130: Distribute the instructions in the dispatch queue of each instruction slot to the corresponding functional unit, and execute the instructions through the functional unit.

[0072] In this embodiment, each functional unit can only execute one instruction at the same time, and the instruction may be a wait instruction or other operation instruction (such as a calculation instruction, including addition and subtraction instructions, etc.).

[0073] The technical solution provided by the embodiment of the present invention obtains the delay beat number corresponding to each operation instruction in the instruction package to be executed, and generates a wait instruction in the instruction fetch queue of each instruction slot according to the delay beat number and the instruction slot corresponding to each operation instruction, and pushes the instructions in each instruction fetch queue into the distribution queue of the corresponding instruction slot according to the order of instructions in each instruction fetch queue, distributes the instructions in the distribution queue of each instruction slot to the corresponding functional unit, and executes the instructions by the functional unit. This technical solution can realize the delayed distribution of the instructions to be executed, avoid the problem of conflict in the execution process when multiple functional units execute instructions in parallel in the prior art, thereby saving the time spent on instruction execution and improving execution efficiency.

[0074] Figure 2 A flowchart of another instruction execution method provided by an embodiment of the present invention is shown in FIG. Figure 2 As shown, the method includes:

[0075] Step 210: Obtain the delay count corresponding to each operation instruction in the instruction packet to be executed, and generate a wait instruction in the instruction fetch queue of each instruction slot according to the delay count and the instruction slot corresponding to each operation instruction.

[0076] In one implementation of this embodiment, obtaining the delay count corresponding to each operation instruction in the instruction package to be executed includes: obtaining a preset wait immediate instruction corresponding to each operation instruction; and obtaining the delay count corresponding to the operation instruction based on the target bit in the wait immediate instruction.

[0077] Among them, the high bits (34-39) in the wait immediate instruction are used to identify the wait instruction, and the low bits are used to identify the immediate number of delays, and the immediate number can be represented by 7-bit data.

[0078] In another implementation of this embodiment, obtaining the delay count corresponding to each operation instruction in the instruction package to be executed includes: obtaining a preset wait register instruction corresponding to each operation instruction; querying the target register storing the delay count in a pre-built delay count mapping table based on the wait register instruction and the instruction slot corresponding to the operation instruction; obtaining the delay count corresponding to the operation instruction based on the target bit corresponding to the target register in the delay count mapping table.

[0079] The pre-built delay beat number mapping table is shown in Table 1:

[0080] Table 1

[0081] Instruction slots Register y [m:n] BIU0 Register 8 [6:0] BIU1 Register 8 [14:8] BIU2 Register 8 [22:16] BIU3 Register 8 [30:24] SHU0 Register 9 [6:0] SHU1 Register 9 [14:8] SHU2 Register 9 [22:16] SHU3 Register 9 [30:24] IMA0 Register 10 [6:0] IMA1 Register 10 [14:8] IMA2 Register 10 [22:16] IMA3 Register 10 [30:24] R0 Register 11 [6:0] R1 Register 11 [14:8] R2 Register 11 [22:16] R3 Register 11 [30:24] R4 Register 12 [6:0] R5 Register 12 [14:8] R6 Register 12 [22:16] R7 Register 12 [30:24]

[0082] As shown in Table 1, the delay count mapping table includes the mapping between instruction slots, registers, and bits. The wait register instruction queries the delay count mapping table to obtain the delay count corresponding to the current instruction slot. The specific delay count is specified by register y[m:n], where y indicates the register to use and m:n indicates the bits in the register to use. Each register is 32 bits, and the wait register instruction uses a specific 7 bits as the delay count for the wait instruction.

[0083] Specifically, the mapping relationship between each operation instruction and the corresponding delay beat number can be defined by the delay beat number mapping table, or can be defined in other forms, such as key-value pairs, enumerated values, or logical functions. In addition to being implemented in the form shown in Table 1, the delay beat number mapping table can also be implemented using other mapping rules (e.g., different function rules), which is not limited in this embodiment.

[0084] Step 220 : In each instruction fetch queue, sequentially obtain an instruction to be dispatched as the current instruction according to the instruction sequence.

[0085] Step 230: If the current instruction is a wait instruction, the current wait instruction and the matching empty instruction are pushed into the dispatch queue of the corresponding instruction slot according to the delay count corresponding to the current wait instruction.

[0086] In this step, the number of empty instructions corresponds to the delay count defined by the wait instruction. Specifically, assuming the current wait instruction is wait18 (i.e., the delay count is 18), the wait instruction and 18 NOPs can be pushed into the dispatch queue to delay the dispatch of the operation instruction following the wait instruction by 18 counts.

[0087] In one implementation of this embodiment, according to the delay count corresponding to the current wait instruction, the current wait instruction and the matching empty instruction are pushed into the distribution queue of the corresponding instruction slot, and it also includes: if there is a subsequent wait instruction located after the current wait instruction in the instruction fetch queue, the first delay count corresponding to the subsequent wait instruction is compared with the second delay count corresponding to the current wait instruction; according to the comparison result of the first delay count and the second delay count, the instruction push strategy located after the current wait instruction is determined.

[0088] Among them, according to the comparison result of the first delay beat number and the second delay beat number, the instruction push strategy after the current wait instruction is determined, including: judging whether the first delay beat number is greater than the second delay beat number; if so, taking the difference between the first delay beat number and the second delay beat number as the number of empty instructions to be pushed into the distribution queue corresponding to the subsequent wait instruction; if not, judging whether the first delay beat number is zero; if it is zero, determining that all instructions after the subsequent wait instruction are invalid instructions, and discarding the invalid instructions; if it is not zero, filtering invalid instructions among the instructions after the subsequent wait instruction according to the difference between the second delay beat number and the first delay beat number, and discarding the invalid instructions.

[0089] In a specific embodiment, for one instruction slot, when distributing instructions in an instruction fetch queue, if the instruction fetch queue includes multiple wait instructions, the delay counts corresponding to the wait instructions can be compared, and a strategy for pushing instructions following the current wait instruction can be determined based on the comparison result. This involves the following scenarios:

[0090] Scenario 1: If the delay number corresponding to the subsequent wait instruction is greater than the delay number corresponding to the current wait instruction, the difference between the two can be used as the number of NOPs to be pushed corresponding to the subsequent wait instruction.

[0091] For example, assuming that the current wait instruction is wait18 and the subsequent wait instruction is wait28, after the wait28 instruction is pushed into the dispatch queue, 10 NOPs may also be pushed into the dispatch queue.

[0092] Scenario 2: If the subsequent wait instruction is wait0, all instructions after the wait0 instruction can be considered to be invalid. In this case, all instructions after the wait0 instruction can be discarded without being distributed.

[0093] Scenario 3: If the subsequent wait instruction is not wait0 and the corresponding delay beat number is less than the delay beat number corresponding to the current wait instruction, invalid instructions that need to be discarded can be filtered based on the difference between the two.

[0094] For example, assuming that the current wait instruction is wait28 and the subsequent wait instruction is wait20, after the wait20 instruction is pushed into the dispatch queue, the 8 instructions after the wait20 instruction can be discarded, and the 9th instruction can be pushed into the dispatch queue.

[0095] In this embodiment, preferably, after determining whether the first delay beat number is zero, the method further includes: if the first delay beat number is zero and the subsequent wait instruction also carries a core wait instruction, determining that all instructions after the subsequent wait instruction are valid instructions.

[0096] In the second scenario above, if the subsequent wait0 instruction also carries a core wait instruction, the instructions following the wait0 instruction may not be discarded, but may be operated according to the normal instruction dispatching logic.

[0097] Step 240: If the current instruction is an operation instruction other than the wait instruction, push the current instruction into the dispatch queue of the corresponding instruction slot.

[0098] In this step, the other operation instructions may be operation instructions other than wait instructions, such as operation instructions (including vector operations, integer operations, floating-point operations, etc.), data transfer instructions, control flow instructions, special function instructions, etc. This embodiment does not limit this.

[0099] Step 250: Distribute the instructions in the dispatch queue of each instruction slot to the corresponding functional unit, and execute the instructions through the functional unit.

[0100] The technical solution provided by the embodiment of the present invention obtains the delay beat number corresponding to each operation instruction in the instruction package to be executed, generates a wait instruction in the instruction fetch queue of each instruction slot according to the delay beat number and the instruction slot corresponding to each operation instruction, and obtains an instruction to be distributed as the current instruction in each instruction fetch queue in sequence according to the order of instructions. If the current instruction is a wait instruction, the current wait instruction and the matching empty instruction are pushed into the distribution queue of the corresponding instruction slot according to the delay beat number corresponding to the current wait instruction. If the current instruction is an operation instruction other than the wait instruction, the current instruction is pushed into the distribution queue of the corresponding instruction slot, and the instructions in the distribution queue of each instruction slot are distributed to the corresponding functional units. The technical means of executing instructions by the functional units can realize delayed distribution of the instructions to be executed, avoid the problem of conflict in the execution process when multiple functional units execute instructions in parallel in the prior art, thereby saving instruction execution time and improving execution efficiency.

[0101] Figure 3 A flowchart of another instruction execution method provided by an embodiment of the present invention is shown in FIG. Figure 3 As shown, the method includes:

[0102] Step 310: Obtain the delay count corresponding to each operation instruction in the instruction packet to be executed, and generate a wait instruction in the instruction fetch queue of each instruction slot according to the delay count and the instruction slot corresponding to each operation instruction.

[0103] Step 320: In all instruction fetch queues of all instruction slots, determine whether there is a core wait instruction in the current instructions to be dispatched.

[0104] Step 330: If it exists, align the wait instructions in all instruction fetch queues according to the core wait instruction and the delay beat number corresponding to the wait instruction in each instruction fetch queue, so that subsequent instructions after the wait instruction are distributed at the same time.

[0105] In this embodiment, for multiple instruction slots, the core wait instruction is used to align the wait instructions corresponding to each instruction slot, that is, to level the delay beats corresponding to each wait instruction, thereby refreshing the pipeline of the instruction slot so that the subsequent instructions of each instruction slot start to be distributed at the same time.

[0106] In one implementation of this embodiment, the wait instructions in all instruction fetch queues are aligned based on the core wait instruction and the delay count corresponding to the wait instruction in each instruction fetch queue, involving the following scenarios:

[0107] Assume there are three instruction slots A, B, and C. The instruction fetch queue of instruction slot A contains the wait3 instruction, the instruction fetch queue of instruction slot B contains the wait5 instruction, and the instruction fetch queue of instruction slot C contains the wait8 instruction:

[0108] Scenario (1): In all instruction fetch queues of all instruction slots, determine whether the current instruction to be distributed includes a wait instruction; if not, determine the number of empty instructions corresponding to each instruction slot based on the difference between the maximum delay beat number of wait instructions in all instruction fetch queues and the delay beat number of wait instructions in each instruction fetch queue; based on the number of empty instructions corresponding to each instruction slot, push the corresponding empty instruction into the distribution queue of each instruction slot.

[0109] If the current instructions in the instruction fetch queues of the three instruction slots do not include wait instructions, but include core wait instructions, it can be determined that the maximum delay number corresponding to the three instruction slots is 8. Therefore, 5 NOPs can be pushed into the dispatch queue of instruction slot A, 3 NOPs can be pushed into the dispatch queue of instruction slot B, and no NOPs can be pushed into the dispatch queue of instruction slot C. This can achieve instruction slot pipeline alignment so that subsequent instructions can be issued normally at the same time.

[0110] Scenario (2): If the current instruction of one of the three instruction slots is a wait instruction and also carries a core wait instruction, and the delay count of the wait instruction is greater than the maximum delay count of 8, then the wait instruction can be considered invalid and processed according to the above scenario (1).

[0111] For example, assuming that the current instruction in the instruction fetch queue of instruction slot A is wait20|core wait0, then 5 NOPs are still pushed into the dispatch queue of instruction slot A, 3 NOPs are pushed into the dispatch queue of instruction slot B, and no NOPs are pushed into instruction slot C.

[0112] Scenario (3): In all instruction fetch queues of all instruction slots, the current instruction to be dispatched is a wait instruction and also carries a core wait instruction, and the delay beat number of the current wait instruction is less than the maximum delay beat number, then the difference between the current wait instruction and the subsequent wait instruction is determined; the maximum difference is selected as the target delay beat number, and the number of empty instructions pushed into each instruction slot is determined based on the target delay beat number and each difference; based on the number of empty instructions pushed into each instruction slot, the corresponding empty instructions are pushed into the dispatch queue of each instruction slot.

[0113] For example, assuming that the current instruction in the instruction fetch queue of instruction slot A is wait1|core wait0, and the current instruction in the instruction fetch queue of instruction slot B is wait2|core wait0, then the difference between wait1 and wait3 in instruction slot A can be calculated to be 2, the difference between wait2 and wait5 in instruction slot B can be calculated to be 3, and the current instruction in instruction slot C is other operation instructions, and the difference can be set to 0, thereby determining the maximum difference of 3 as the target delay beat number.

[0114] The difference between the target delay beat number and the corresponding difference value of 2 for instruction slot A is 1, the difference between the target delay beat number and the corresponding difference value of 3 for instruction slot B is 0, and the difference between the target delay beat number and the corresponding difference value of 0 for instruction slot C is 3. Therefore, 1 NOP can be pushed into the dispatch queue of instruction slot A, and no NOP can be pushed into the dispatch queue of instruction slot B. However, 3 NOPs can be pushed into the dispatch queue of instruction slot C.

[0115] The advantage of this setting is that the delay beats corresponding to each wait instruction can be flattened, the instruction slot pipeline can be refreshed, and the subsequent instructions of each instruction slot can be distributed at the same time.

[0116] Step 340: Push the instructions in each instruction fetch queue into the dispatch queue of the corresponding instruction slot according to the order of the instructions in each instruction fetch queue.

[0117] Step 350: Distribute the instructions in the dispatch queue of each instruction slot to the corresponding functional unit, and execute the instructions through the functional unit.

[0118] The technical solution provided by the embodiment of the present invention obtains the delay beat number corresponding to each operation instruction in the instruction package to be executed, and generates a wait instruction in the instruction fetch queue of each instruction slot according to the delay beat number and the instruction slot corresponding to each operation instruction, and judges whether there is a corewait instruction in all the instruction fetch queues of all the instruction slots. If so, the wait instructions in all the instruction fetch queues are aligned according to the core wait instruction and the delay beat number corresponding to the wait instruction in each instruction fetch queue, so that subsequent instructions after the wait instruction are distributed at the same time, and according to the order of instructions in each instruction fetch queue, the instructions in each instruction fetch queue are pushed into the distribution queue of the corresponding instruction slot, and the instructions in the distribution queue of each instruction slot are distributed to the corresponding functional unit, and the technical means of executing the instructions by the functional unit can avoid the problem of conflict in the execution process when multiple functional units execute instructions in parallel in the prior art, thereby saving the time consumed in instruction execution and improving the execution efficiency.

[0119] Figure 4 This is a schematic diagram of the structure of an instruction execution device provided by an embodiment of the present invention, wherein the device is applied to a vector processor, wherein the vector processor includes multiple functional units, each functional unit corresponding to an instruction slot, such as Figure 4 As shown, the device includes: an instruction generation module 410, an instruction push module 420 and an instruction distribution module 430.

[0120] The instruction generation module 410 is configured to obtain a delay count corresponding to each operation instruction in the instruction packet to be executed, and generate a wait instruction in the instruction fetch queue of each instruction slot according to the delay count and the instruction slot corresponding to each operation instruction;

[0121] An instruction push module 420 is configured to push instructions in each instruction fetch queue into a dispatch queue of a corresponding instruction slot according to the order of instructions in each instruction fetch queue;

[0122] The instruction dispatch module 430 is configured to dispatch the instructions in the dispatch queue of each instruction slot to the corresponding functional unit, and execute the instructions through the functional unit.

[0123] The technical solution provided by the embodiment of the present invention obtains the delay beat number corresponding to each operation instruction in the instruction package to be executed, and generates a wait instruction in the instruction fetch queue of each instruction slot according to the delay beat number and the instruction slot corresponding to each operation instruction, and pushes the instructions in each instruction fetch queue into the distribution queue of the corresponding instruction slot according to the order of instructions in each instruction fetch queue, distributes the instructions in the distribution queue of each instruction slot to the corresponding functional unit, and executes the instructions by the functional unit. This technical solution can realize the delayed distribution of the instructions to be executed, avoid the problem of conflict in the execution process when multiple functional units execute instructions in parallel in the prior art, thereby saving the time spent on instruction execution and improving execution efficiency.

[0124] Based on the above embodiment, the instruction generation module 410 includes:

[0125] An immediate number acquisition unit is used to acquire a preset wait immediate number instruction corresponding to each operation instruction; and acquire a delay beat number corresponding to the operation instruction according to a target bit in the wait immediate number instruction;

[0126] A register instruction acquisition unit is used to obtain a preset wait register instruction corresponding to each operation instruction; based on the wait register instruction and the instruction slot corresponding to the operation instruction, query the target register storing the delay beat number in a pre-built delay beat number mapping table; based on the target bit corresponding to the target register in the delay beat number mapping table, obtain the delay beat number corresponding to the operation instruction.

[0127] The instruction push module 420 includes:

[0128] The instruction fetch unit is used to fetch one instruction to be dispatched as the current instruction in each instruction fetch queue in the order of instructions.

[0129] An instruction push unit, configured to push the current wait instruction and a matching empty instruction into a dispatch queue of a corresponding instruction slot according to the delay count corresponding to the current wait instruction if the current instruction is a wait instruction;

[0130] a delay comparison unit configured to compare a first delay beat number corresponding to the subsequent wait instruction with a second delay beat number corresponding to the current wait instruction if a subsequent wait instruction exists in the instruction fetch queue and determine a push strategy for instructions following the current wait instruction based on the comparison result of the first delay beat number and the second delay beat number;

[0131] The delay processing unit is configured to determine whether the first delay beat number is greater than the second delay beat number; if so, use the difference between the first delay beat number and the second delay beat number as the number of empty instructions to be pushed into the dispatch queue corresponding to the subsequent wait instruction; if not, determine whether the first delay beat number is zero; if it is zero, determine that all instructions following the subsequent wait instruction are invalid instructions and discard the invalid instructions; if it is not zero, filter invalid instructions from the instructions following the subsequent wait instruction based on the difference between the second delay beat number and the first delay beat number, and discard the invalid instructions;

[0132] The instruction judgment unit is configured to determine that all instructions following the subsequent wait instruction are valid instructions if the first delay beat number is zero and the subsequent wait instruction also carries a corewait instruction.

[0133] The device further comprises:

[0134] An instruction alignment module is configured to determine whether a core wait instruction exists in the current instructions to be dispatched in all instruction fetch queues of all instruction slots; if so, align the wait instructions in all instruction fetch queues based on the core wait instruction and the delay counts corresponding to the wait instructions in each instruction fetch queue, so that subsequent instructions following the wait instruction are dispatched at the same time;

[0135] The instruction alignment module is further configured to determine whether the current instructions to be dispatched include a wait instruction in all instruction fetch queues of all instruction slots; if not, determine the number of empty instructions to be pushed into each instruction slot based on the difference between the maximum delay beat number of wait instructions in all instruction fetch queues and the delay beat number of wait instructions in each instruction fetch queue; and push the corresponding empty instruction into the dispatch queue of each instruction slot based on the number of empty instructions pushed into each instruction slot;

[0136] The instruction alignment module is also used to determine whether the current instruction to be distributed includes a wait instruction in all instruction fetch queues of all instruction slots; if so, and the delay beat number of the current wait instruction is less than the maximum delay beat number, then determine the difference between the current wait instruction and the subsequent wait instruction; select the maximum difference as the target delay beat number, and determine the number of empty instructions pushed into each instruction slot based on the target delay beat number and each difference; based on the number of empty instructions pushed into each instruction slot, push the corresponding empty instruction into the distribution queue of each instruction slot.

[0137] The above device can execute the methods provided by all the above embodiments of the present invention, and has the corresponding functional modules and beneficial effects of executing the above methods. For technical details not fully described in the embodiments of the present invention, please refer to the methods provided by all the above embodiments of the present invention.

[0138] Figure 5 FIG. 1 shows a schematic structural diagram of a vector processor 10 that can be used to implement an embodiment of the present invention.

[0139] like Figure 5 As shown, the vector processor 10 includes at least one processing core 11 and a memory, such as a read-only memory (ROM) 12 and a random access memory (RAM) 13, communicatively connected to the at least one processing core 11. The memory stores a computer program that can be executed by the at least one processing core. The processing core 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 into the random access memory (RAM) 13. Various programs and data required for the operation of the vector processor 10 can also be stored in the RAM 13. The processing core 11, ROM 12, and RAM 13 are connected to each other via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0140] Various components in the vector processor 10 are connected to an I / O interface 15, including an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the vector processor 10 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0141] The processing core 11 can be a variety of general and / or special processing components with processing and computing capabilities. The processing core 11 performs the various methods and processes described above, such as the instruction execution method. In some embodiments, the instruction execution method can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the vector processor 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processing core 11, one or more steps of the instruction execution method described above can be performed. Alternatively, in other embodiments, the processing core 11 can be configured to execute the instruction execution method by any other appropriate means (for example, by means of firmware).

[0142] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0143] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the computer program is executed by the processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer program may be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0144] In the context of the present invention, computer-readable storage media can be tangible media that can contain or store a computer program for use with an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. Computer-readable storage media can include but are not limited to electronic, magnetic, optical, electromagnetic, infrared or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, computer-readable storage media can be machine-readable signal media. More specific examples of machine-readable storage media can include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0145] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0146] A computing system may include clients and servers. The clients and servers are typically remote from each other and typically interact via a communication network. This client-server relationship arises through computer programs running on the respective computers, creating a client-server relationship. The server may be a cloud server, also known as a cloud computing server or cloud host. This server is a hosting product within the cloud computing service ecosystem that addresses the management difficulties and limited scalability of traditional physical hosting and VPS services.

[0147] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0148] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A method for executing an instruction, characterized in that: Applied to a vector processor, the vector processor includes multiple functional units, each functional unit corresponds to an instruction slot, and the method includes: Obtaining the delay count corresponding to each operation instruction in the instruction packet to be executed, and generating a wait instruction in the instruction fetch queue of each instruction slot according to the delay count and the instruction slot corresponding to each operation instruction; According to the order of instructions in each instruction fetch queue, push the instructions in each instruction fetch queue into the dispatch queue of the corresponding instruction slot; The instructions in the dispatch queue of each instruction slot are dispatched to the corresponding functional unit, and the instructions are executed by the functional unit.

2. The method according to claim 1, characterized in that Get the delay count corresponding to each operation instruction in the instruction package to be executed, including: Get the preset wait immediate instruction corresponding to each operation instruction; According to the target bit in the wait immediate instruction, the delay beat number corresponding to the operation instruction is obtained.

3. The method according to claim 1, characterized in that Get the delay count corresponding to each operation instruction in the instruction package to be executed, including: Get the preset wait register instruction corresponding to each operation instruction; According to the wait register instruction and the instruction slot corresponding to the operation instruction, query the target register storing the delay beat number in a pre-built delay beat number mapping table; The delay count corresponding to the operation instruction is obtained according to the target bit corresponding to the target register in the delay count mapping table.

4. The method according to claim 1, wherein According to the order of instructions in each instruction fetch queue, the instructions in each instruction fetch queue are pushed into the dispatch queue of the corresponding instruction slot, including: In each instruction fetch queue, one instruction to be dispatched is obtained in sequence as the current instruction. If the current instruction is a wait instruction, the current wait instruction and the matching empty instruction are pushed into the dispatch queue of the corresponding instruction slot according to the delay beat number corresponding to the current wait instruction.

5. The method according to claim 4, characterized in that According to the delay count corresponding to the current wait instruction, the current wait instruction and the matching empty instruction are pushed into the dispatch queue of the corresponding instruction slot, and the following steps are also included: If there is a subsequent wait instruction after the current wait instruction in the instruction fetch queue, comparing the first delay beat number corresponding to the subsequent wait instruction with the second delay beat number corresponding to the current wait instruction; According to the comparison result of the first delay beat number and the second delay beat number, the instruction push strategy after the current wait instruction is determined.

6. The method according to claim 5, characterized in that Determining a push strategy for an instruction following the current wait instruction based on a comparison result of the first delay beat count and the second delay beat count includes: Determine whether the first delay beat number is greater than the second delay beat number; If yes, the difference between the first delay beat number and the second delay beat number is used as the number of empty instructions to be pushed into the dispatch queue corresponding to the subsequent wait instruction; If not, determine whether the first delay beat number is zero; If it is zero, all instructions following the subsequent wait instruction are determined to be invalid instructions, and the invalid instructions are discarded; If it is not zero, invalid instructions are screened out from the instructions following the subsequent wait instruction according to the difference between the second delay beat number and the first delay beat number, and the invalid instructions are discarded.

7. The method according to claim 6, characterized in that After determining whether the first delay beat number is zero, the method further includes: If the first delay beat number is zero, and the subsequent wait instruction also carries a core wait instruction, then all instructions after the subsequent wait instruction are determined to be valid instructions.

8. The method according to claim 1, characterized in that Before pushing the instructions in each instruction fetch queue into the dispatch queue of the corresponding instruction slot according to the order of the instructions in each instruction fetch queue, the method further includes: In all instruction fetch queues of all instruction slots, determine whether there is a core wait instruction in the current instruction to be dispatched; If so, the wait instructions in all instruction fetch queues are aligned according to the core wait instruction and the delay beat number corresponding to the wait instruction in each instruction fetch queue, so that subsequent instructions after the wait instruction are distributed at the same time.

9. The method according to claim 8, characterized in that According to the core wait instruction and the delay count corresponding to the wait instruction in each instruction fetch queue, the wait instructions in all instruction fetch queues are aligned, including: In all instruction fetch queues of all instruction slots, determine whether the current instruction to be dispatched includes a wait instruction; If not, the number of empty instructions pushed into each instruction slot is determined based on the difference between the maximum delay beats of wait instructions in all instruction fetch queues and the delay beats of wait instructions in each instruction fetch queue. According to the number of empty instructions pushed into each instruction slot, the corresponding empty instructions are pushed into the dispatch queue of each instruction slot.

10. The method according to claim 9, characterized in that In all instruction fetch queues of all instruction slots, after determining whether the current instruction to be dispatched includes a wait instruction, the following steps are also performed: If yes, and the delay beat number of the current wait instruction is less than the maximum delay beat number, then determining the difference between the current wait instruction and the subsequent wait instruction; Selecting the maximum difference as the target delay beat number, and determining the number of empty instructions to be pushed into each instruction slot according to the target delay beat number and the differences; According to the number of empty instructions pushed into each instruction slot, the corresponding empty instructions are pushed into the dispatch queue of each instruction slot.

11. An instruction execution device, characterized in that: Applied to a vector processor, the vector processor includes multiple functional units, each functional unit corresponds to an instruction slot, and the device includes: An instruction generation module is used to obtain the delay beat number corresponding to each operation instruction in the instruction packet to be executed, and generate a wait instruction in the instruction fetch queue of each instruction slot according to the delay beat number and the instruction slot corresponding to each operation instruction; An instruction push module is used to push the instructions in each instruction fetch queue into the dispatch queue of the corresponding instruction slot according to the order of the instructions in each instruction fetch queue; The instruction dispatch module is used to dispatch the instructions in the dispatch queue of each instruction slot to the corresponding functional unit, and execute the instructions through the functional unit.

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