Timing control method and related equipment

Abstract

The embodiment of the invention discloses a timing control method and related equipment, the method is applied to computing equipment, the computing equipment comprises a first chip and a second chip, and the first chip can obtain a to-be-timed statement in a to-be-compiled microcode as a timing object based on a pre-prepared configuration file; and according to the timing object, automatically writing a sampling IR for timing into the to-be-compiled microcode in the process of compiling the to-be-compiled microcode so as to compile and obtain a microcode program with a timing function. Therefore, the second chip can acquire the running time consumption information of the statement to be timed by running the microcode program. According to the embodiment of the invention, different timing interfaces do not need to be written for parameters of different statements to be timed, the microcode timing function can be realized, and the realization process is simple and high in efficiency.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a timing control method and related equipment. Background Art

[0002] Data processing units (DPUs) are mainly used in business scenarios such as cloud computing, storage, and intelligent computing. They can provide computing power for storage or networks, saving the general computing power of computing devices, such as the resources of the central processing unit (CPU).

[0003] Microcode is a crucial component that supports the DPU's various business functions. Microcode programming allows users to customize the DPU's business functions. The microcode runtime environment in the DPU lacks an operating system (OS) and timing capabilities. When debugging microcode, it may be necessary to obtain the actual execution time of the microcode's functions in the DPU. Currently, the implementation of microcode timing functionality relies on the user manually writing sampling point statements into the microcode to be compiled. The compiler then compiles the microcode with the sampling point statements into a microcode program with timing capabilities, allowing the DPU to execute this microcode program and obtain the corresponding function's execution time information.

[0004] However, in order to implement the microcode timing function, the user needs to write a timing interface for the parameters of the to-be-timed function in the microcode to be compiled before compiling the microcode, and then write sampling point statements into the microcode to be compiled. This implementation process is complex and inefficient. Summary of the Invention

[0005] The embodiments of the present application provide a timing control method and related equipment, which can simplify the process of implementing the microcode timing function and improve efficiency.

[0006] In a first aspect, an embodiment of the present application provides a timing control method, which is applied to a computing device comprising a first chip and a second chip. Specifically, the method is executed by the first chip and the second chip. The execution process of the method is as follows:

[0007] First, the first chip can obtain the microcode to be compiled and the configuration file of the microcode to be compiled; the microcode to be compiled is the microcode corresponding to the business function of the second chip, and the microcode program corresponding to the microcode to be compiled can realize the business function of the second chip when running on the second chip; the configuration file is used to provide a unified interface to the user, so that the user can directly indicate the timing object in the microcode to be compiled through the configuration file, without the need to write a timing interface for the parameters of the statement to be timed in the microcode to be compiled to indicate the timing object.

[0008] The microcode to be compiled includes one or more business modules, each business module includes one or more functions, and each function includes one or more lines of statements. The configuration file includes information indicating timing objects in the microcode to be compiled, where a timing object is a single line of statement or multiple consecutive lines of statements in the same business module in the microcode to be compiled; these statements are the statements to be timed. It is understood that the user updates the corresponding fields in the configuration file template or the existing configuration file precisely for the purpose of obtaining execution time information of the timing object on the second chip, thereby obtaining a configuration file corresponding to the microcode to be compiled.

[0009] Optionally, the indication information includes first indication information, where the first indication information is used to indicate that all functions in the corresponding business module serve as a timing object.

[0010] Optionally, the indication information includes second indication information, and the second indication information is used to indicate that each function in the corresponding business module serves as a timing object.

[0011] Optionally, the indication information includes a function name and a line number; the function name and line number are used to determine at least one group of statements in the microcode to be compiled, each group of statements includes two lines of statements; the two lines of statements are used to indicate that the statements between the two lines of statements are timing objects.

[0012] The timing object may include the statement indicated by the function name and line number, or may not include these statements.

[0013] Optionally, the configuration file includes timing path information, where the timing path information is used to indicate a timing path, where the timing path includes one or more nodes, and each node is a timing object. The timing path information may include indication information of the timing object.

[0014] Optionally, timing objects belonging to the same business module serve as nodes of the same timing path.

[0015] Then, the first chip may write a sampled intermediate representation (IR) into the microcode to be compiled according to the instruction information in the configuration file. Specifically, the first chip may write a sampled IR into the microcode to be compiled when compiling the microcode to be compiled.

[0016] IR is a data structure used internally by the compiler to represent the semantic information of the microcode to be compiled. IR serves as an intermediate representation during the compiler's conversion of the microcode to be compiled into a microcode program. The compiler can then compile the microcode program corresponding to the semantic information based on the IR. Specifically, the sampled IR is used to compile and generate timing machine code, which is used to measure the execution time of the target machine code in the second chip. The target machine code is the machine code generated by compiling the timing target.

[0017] It can be understood that the microcode program is a machine code that can be directly executed by hardware, and its specific form can be a binary file that can be executed by the second chip.

[0018] Specifically, after determining the timing object in the microcode to be compiled according to the indication information, the first chip can write sampling IR before and after the timing object respectively, so that the second chip starts timing based on the timing machine code before starting to execute the target machine code; after the target machine code ends execution, the running time information of the target machine code is obtained based on the timing machine code.

[0019] Afterwards, the first chip compiles the microcode to be compiled after writing the sampled IR into a microcode program, and sends the microcode program and the trigger instruction to the second chip.

[0020] Among them, the microcode program includes the timing machine code and the target machine code; the trigger instruction can be used to trigger the second chip to execute the timing machine code and the target machine code, and can also be used to trigger the second chip to execute the machine code corresponding to the business module where the timing object is located, and can also be used to trigger the second chip to execute the entire microcode program.

[0021] Finally, after receiving the trigger instruction and the microcode program, the second chip executes the microcode program according to the trigger instruction to obtain the running time consumption information of the target machine code.

[0022] In an embodiment of the present application, the first chip can directly obtain the timing object in the microcode to be compiled through a pre-prepared configuration file, and automatically write the corresponding sampling IR to the microcode to be compiled during the compilation stage according to the timing object, and then compile the microcode to be compiled to obtain a microcode program with a timing function; there is no need to write different timing interfaces for the parameters of different timing objects, and the implementation process is simple and efficient.

[0023] In one possible implementation, the configuration file also includes information about a storage area, which is an area in the cache of the second chip used to store the execution time information; the timing machine code is specifically used to obtain the execution time information and output the execution time information to the storage area based on the information of the storage area.

[0024] The second chip includes a cache memory, which is an on-chip memory of the second chip. A storage area is divided in the cache memory, and the storage area is used to store the operation time-consuming information.

[0025] Optionally, the cache is a single-port random access memory (SPRAM).

[0026] In an embodiment of the present application, by outputting the running time information to a specific storage area in the cache, on the one hand, it is possible to avoid conflicts with other businesses that may cause the running time information to be lost. On the other hand, there is no need to output the running time information to the external memory of the computing device in the form of a printed log every time the running time information is obtained. This can avoid the impact of frequent log printing on business logic and improve timing accuracy.

[0027] In one possible implementation, the indication information of the timing object includes the line number of the start timing statement and the line number of the first output statement of the timing object, and the sampling IR includes the start timing IR and the first output IR; the first chip writes the sampling IR to the microcode to be compiled according to the indication information of the timing object, including: the first chip writes the start timing IR to the microcode to be compiled according to the line number of the start timing statement, and the start timing IR is used to compile and generate a start timing machine code, and the start timing machine code is used to start the running time test of the target machine code; the first chip writes the first output IR to the microcode to be compiled according to the line number of the first output statement, and the first output IR is used to compile and generate a first output machine code, and the first output machine code is used to obtain the result of the running time test, and output the result as the running time information to the storage area.

[0028] It's understood that if two non-consecutive statements in the same business module need to be timed, each statement will be treated as a separate timing object. Therefore, to time this timing object, the user can directly specify the line number of the start timing statement and the line number of the first output statement in the configuration file. This will allow the second chip to obtain the elapsed time from executing the machine code corresponding to the start timing statement to executing the machine code corresponding to the first output statement, which will serve as the execution timing information.

[0029] Optionally, the line number of the start timing statement is the line number of the first statement of the timing object, and the line number of the first output statement is the line number of the last statement of the timing object. In this case, the first chip can insert the start timing IR between the start timing statement and the next line, or between the start timing statement and the previous line; and insert the first output IR between the first output statement and the next line.

[0030] Optionally, the line number of the start timing statement is the line number of the previous line of the timing object, and the line number of the first output statement is the line number of the next line of the timing object. In this case, the first chip can insert the start timing IR between the start timing statement and the next line, and insert the first output IR between the first output statement and the previous line.

[0031] Optionally, the configuration file also includes the function name of the function where the start timing statement is located, and the function name of the function where the first output statement is located; the first chip can first traverse all functions in the microcode to be compiled based on the function name, and determine the function where the start timing statement is located, and the function where the first output statement is located; then, based on the line number, determine the start timing statement and the first output statement from the statements of the corresponding function.

[0032] The function name can be used as a unique identifier of the function in the entire microcode to be compiled. By first determining the function and then the statement, the start timing statement and the first output statement can be located with higher efficiency.

[0033] In some other possible implementations, the configuration file may further include the function name, file name, and line number of the function containing the start timing statement and the first output statement, and a combination of these three elements serves as a unique identifier. This embodiment of the application does not specifically limit the format of the configuration file indicating the start timing statement and the first output statement, as long as the specific statements can be accurately indicated.

[0034] In an embodiment of the present application, by using the line number as indication information, the timing object can be directly indicated, which is more flexible; combining the function name and the line number to indicate the timing object can improve the efficiency of locating the start timing statement and the first output statement.

[0035] In one possible implementation, the second chip executes the microcode program according to the trigger instruction, including: the second chip executes the start timing machine code according to the trigger instruction, controlling the clock cycle counter of the second chip to count from zero; the second chip executes the first output machine code according to the trigger instruction, and after the target machine code is executed, obtains the count value of the clock cycle counter, and outputs the count value as the running time information to the storage area.

[0036] The second chip can set a relevant control register of the clock cycle counter or partially power on or off the clock cycle counter so that the clock cycle counter starts counting from zero.

[0037] The second chip sequentially executes the start timing machine code, the target machine code, and the first output machine code. The count value is the clock cycle elapsed from the second chip executing the start timing machine code to the first output machine code, i.e., the clock cycle elapsed during the execution of the target machine code. The duration of this clock cycle is the reciprocal of the operating frequency of the second chip.

[0038] In an embodiment of the present application, when the second chip executes the start timing machine code, it controls the clock cycle counter to start counting from zero, so that when executing the first output machine code, only one count value needs to be output as the running time information, without the need for additional calculations or recording of multiple count values, which is more efficient.

[0039] In another possible implementation, the second chip executes the microcode program according to the trigger instruction, including: the second chip executes the start timing machine code according to the trigger instruction, and obtains the first count value of the clock cycle counter of the second chip; the second chip executes the first output machine code according to the trigger instruction, and after the target machine code is executed, obtains the second count value of the clock cycle counter, and outputs the difference between the first count value and the second count value as the running time information to the storage area.

[0040] After obtaining the first count value, the second chip may output the first count value to the cache; and after obtaining the second count value, the second chip may calculate the difference between the first count value and the second count value and output the difference to the storage area.

[0041] In the embodiment of the present application, the second chip can obtain two count values and calculate the difference between the two as the operation time information, without setting the relevant control register of the clock cycle counter or locally powering on and off.

[0042] In one possible implementation, the clock cycle counter is a performance monitor unit (PMU).

[0043] In one possible implementation, the configuration file also includes the line number of the second output statement of the business module, and the business module corresponds to one or more timing objects; the sampling IR includes the second output IR; after the first chip obtains the microcode to be compiled and the configuration file of the microcode to be compiled, the method also includes: the first chip writes the second output IR to the microcode to be compiled according to the line number of the second output statement, and the second output IR is used to compile and generate a second output machine code, and the second output machine code is used to output the running time information corresponding to the business module in the storage area.

[0044] Among them, in the above possible implementation, the second chip outputs the running time information corresponding to the timing object to the storage area of the cache; finally, the second chip needs to output this running time information to the external memory of the computing device so that the user can obtain the running time information through the first chip.

[0045] The business module with timing requirements corresponds to one or more timing objects. The second chip can output all the running time information corresponding to a business module to the external memory of the computing device when all the running time information corresponding to the business module is output to the storage area of the cache. Specifically, the running time information corresponding to the business module refers to the collection of running time information corresponding to all timing objects in the business module.

[0046] Therefore, the user can indicate the second output statement of the business module with timing requirements in the configuration file to control the second chip to output the running time information corresponding to the business module to the time node of the external memory.

[0047] Specifically, the first chip may insert the second output IR between the second output statement and its previous line, or between the second output statement and its next line.

[0048] In an embodiment of the present application, by indicating the line number of the second output statement in the configuration file, the second chip can be controlled to output the time node of the operation time consumption information corresponding to the business module to the external memory of the computing device.

[0049] In one possible implementation, after the first chip writes the first output IR to the microcode to be compiled according to the line number of the first output statement, the method further includes: when the first output IRs corresponding to all timing objects of the business module have been written, the first chip writes the second output IR at a position after the last written first output IR in the microcode to be compiled.

[0050] Among them, if the user does not control the output time node of the running time information by indicating the second output statement in the configuration file, the first chip can detect whether the first output IR corresponding to the current business module has been fully written after each completion of writing the first output IR; if so, the first chip can write the second output IR after the last written first output IR; if not, the first chip will continue to write the first output IR.

[0051] It can be understood that each timing object corresponds to a start timing IR and a first output IR.

[0052] Optionally, the first chip may insert a second output IR between the row where the first output IR is located and the next row.

[0053] In an embodiment of the present application, when the user does not indicate the output time node of the operation timing information corresponding to the business module, the first chip can write the second output IR at the default position after the last first output IR of the business module to ensure that the second chip can output all the operation timing information corresponding to the business module through the first output machine code corresponding to the first output IR to the external memory through the second output machine code corresponding to the second output IR.

[0054] In one possible implementation, the configuration file includes timing path information, where the timing path information is used to indicate one or more timing paths, each timing path including one or more timing objects; the timing path information includes a line number of a second output statement of the timing path; and the first chip can write a second output IR to the microcode to be compiled based on the line number of the second output statement.

[0055] In another possible implementation, the configuration file includes timing path information but does not include the line number of the second output statement; in this case, for each timing path, the first chip can write the second output IR after the first output IR corresponding to the last timing object of the timing path.

[0056] In the embodiment of the present application, the user can indicate a timing path including one or more timing objects, so that the second chip can output the operation time information in units of the timing path, which is more flexible.

[0057] In one possible implementation, the second chip executes the microcode program according to the trigger instruction, including: the second chip executes the second output machine code according to the trigger instruction, and outputs the running time information corresponding to the business module in the storage area to the external memory of the computing device.

[0058] In an embodiment of the present application, after obtaining all the running time information corresponding to the business module, the second chip can execute the second output machine code to output all the running time information to the external memory, so that the user can obtain these running time information from the external memory through the first chip.

[0059] In one possible implementation, the configuration file also includes a timing switch item; before the first chip writes the sampled IR to the microcode to be compiled according to the indication information of the timing object, the method also includes: the first chip determines whether the timing switch item is turned on; if so, triggering the step of the first chip writing the sampled IR to the microcode to be compiled according to the indication information of the timing object.

[0060] When compiling the microcode to be compiled, the first chip can determine whether to execute the step of writing the sampled IR based on the timing switch item. In the microcode debugging scenario, the user can modify the corresponding field in the configuration file to enable the timing switch item, so that the first chip compiles the microcode to be compiled to obtain a microcode program with a timing function, and then obtains the runtime information obtained by the second chip actually executing the microcode program; then debugs the microcode to be compiled based on the runtime information; and repeats the above two steps until the debugging of the microcode to be compiled is completed.

[0061] Afterwards, the user can turn off the timing switch item in the configuration file, compile the debugged microcode to be compiled, obtain the target microcode program, and finally send the target microcode program to the second chip to complete the tuning of the business function code of the second chip.

[0062] In an embodiment of the present application, the compilation process can be controlled by the timing switch item, and after the debugging of the microcode is completed, there is no need to manually delete the sampling IR and / or timing interface in the microcode. It is only necessary to close the modified timing switch item in the configuration file to compile the microcode to obtain a microcode program that does not include the timing machine code.

[0063] In a possible implementation, the first chip is a central processing unit (CPU), which is also called a general-purpose processor; the second chip is a data processing unit (DPU).

[0064] In a possible implementation, the format of the configuration file includes JavaScript object notation (JSON) format, text document (TXT) format, or device information file (INF) format.

[0065] In a second aspect, an embodiment of the present application further provides a computing device, the computing device comprising a first chip and a second chip;

[0066] The first chip is used to obtain a microcode to be compiled and a configuration file of the microcode to be compiled, wherein the configuration file includes indication information of a timing object in the microcode to be compiled, where the timing object is a line of statement or multiple consecutive lines of statements in the same service module in the microcode to be compiled;

[0067] The first chip is further configured to write a sample intermediate representation (IR) into the microcode to be compiled according to the instruction information of the timing object, wherein the sample intermediate representation (IR) is used to compile and generate timing machine code, and the timing machine code is used to test the execution time of the target machine code in the second chip, wherein the target machine code is the machine code obtained by compiling the timing object;

[0068] The first chip is further configured to compile the microcode to be compiled after writing the sampled IR into a microcode program;

[0069] The first chip is further configured to send the microcode program and the trigger instruction to the second chip;

[0070] The second chip is used to execute the microcode program according to the trigger instruction to obtain the running time consumption information corresponding to the target machine code.

[0071] In one possible implementation, the configuration file also includes information about a storage area, which is an area in the cache of the second chip used to store the execution time information; the timing machine code is specifically used to obtain the execution time information and output the execution time information to the storage area based on the information of the storage area.

[0072] In one possible implementation, the indication information of the timing object includes the line number of the start timing statement and the line number of the first output statement of the timing object, and the sampling IR includes the start timing IR and the first output IR; the first chip is specifically used to write the start timing IR to the microcode to be compiled according to the line number of the start timing statement, and the start timing IR is used to compile and generate a start timing machine code, and the start timing machine code is used to start the running timing test of the target machine code; the first chip is specifically used to write the first output IR to the microcode to be compiled according to the line number of the first output statement, and the first output IR is used to compile and generate a first output machine code, and the first output machine code is used to obtain the result of the running timing test and output the result as the running timing information to the storage area.

[0073] In one possible implementation, the second chip is specifically used to execute the start timing machine code according to the trigger instruction, and control the clock cycle counter of the second chip to start counting from zero; the second chip is specifically used to execute the first output machine code according to the trigger instruction, and after the target machine code is executed, obtain the count value of the clock cycle counter, and output the count value as the running time information to the storage area.

[0074] In one possible implementation, the configuration file also includes the line number of the second output statement of the business module, and the business module corresponds to one or more of the timing objects; the sampling IR includes the second output IR; the first chip is also used to write the second output IR to the microcode to be compiled according to the line number of the second output statement, and the second output IR is used to compile and generate a second output machine code, and the second output machine code is used to output the running time information corresponding to the business module in the storage area.

[0075] In one possible implementation, the first chip is also used to write the second output IR at a position after the last written first output IR in the microcode to be compiled when the first output IRs corresponding to all timing objects of the business module have been written.

[0076] In one possible implementation, the configuration file includes timing path information, where the timing path information is used to indicate one or more timing paths, each timing path including one or more timing objects; the timing path information includes a line number of a second output statement of the timing path; and the first chip can write a second output IR to the microcode to be compiled based on the line number of the second output statement.

[0077] In another possible implementation, the configuration file includes timing path information but does not include the line number of the second output statement; in this case, for each timing path, the first chip can write the second output IR after the first output IR corresponding to the last timing object of the timing path.

[0078] In a possible implementation, the second chip is specifically configured to execute the second output machine code according to the trigger instruction, and output the running time information corresponding to the business module in the storage area to the external memory of the computing device.

[0079] In a possible implementation, the first chip is a CPU, and the second chip is a DPU.

[0080] In one possible implementation, the clock cycle counter is a PMU.

[0081] In one possible implementation, the configuration file also includes a timing switch item; before the first chip writes the sampled IR to the microcode to be compiled according to the indication information of the timing object, the method also includes: the first chip determines whether the timing switch item is turned on; if so, triggering the step of the first chip writing the sampled IR to the microcode to be compiled according to the indication information of the timing object.

[0082] In a possible implementation, the format of the configuration file includes JavaScript object notation (JSON) format, text document (TXT) format, or device information file (INF) format.

[0083] The third aspect of the present application further provides a computing device, comprising a processor and a memory, wherein the memory stores computer instructions, and when the computer instructions are executed by the processor, the computing device executes any one of the methods described in the first aspect.

[0084] A fourth aspect of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the method according to any one of the first aspects is implemented.

[0085] A fifth aspect of the present application further provides a computer program product, which contains computer-executable instructions, and when the computer-executable instructions are executed, implement any method described in the first aspect.

[0086] It should be understood that the beneficial effects of the above-mentioned various aspects can be referenced to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0087] Figure 1 A schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0088] Figure 2 A data flow diagram for a microcode debugging scenario provided by an embodiment of the present application;

[0089] Figure 3 A flowchart of a timing control method provided in an embodiment of the present application;

[0090] Figure 4 A flowchart of another timing control method provided in an embodiment of the present application;

[0091] Figure 5 A schematic diagram of a process of writing a sampled IR according to an embodiment of the present application;

[0092] Figure 6 A schematic diagram of the structure of another computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0093] In order to make the purpose, technical solutions and advantages of this application more clear, the embodiments of this application are described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only embodiments of a part of this application, rather than all embodiments. It is known to those skilled in the art that with the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0094] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the descriptions used in this way can be interchangeable where appropriate so that the embodiments can be implemented in a sequence other than that illustrated or described in this application. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or modules is not necessarily limited to those steps or modules clearly listed, but may include other steps or modules that are not clearly listed or that are inherent to these processes, methods, products or devices. The naming or numbering of steps in this application does not mean that the steps in the method flow must be executed in the time / logical sequence indicated by the naming or numbering. The named or numbered process steps can change the execution order according to the technical purpose to be achieved, as long as the same or similar technical effects can be achieved. The division of units in this application is a logical division. In actual application, there may be other division methods. For example, multiple units can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, and the indirect coupling or communication connection between units can be electrical or other similar forms, which are not limited in this application. Moreover, the units or sub-units described as separate components may or may not be physically separated, may or may not be physical units, or may be distributed into multiple circuit units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this application.

[0095] With the growing demand for network bandwidth and the increasing diversification of network applications, network devices such as routers, which rely on application-specific integrated circuit (ASIC) technology, have become a bottleneck for the further development and application of network technology. To address this bottleneck, network processors (NPs), based on application-specific instruction set processor (ASIP) technology and offering greater programmability and flexibility, have rapidly developed and are widely used in various network devices.

[0096] The network device can be a smart network interface card (SmartNIC), a router, a network switch, a packet transport network (PTN) device, a firewall, a load balancer, a data center, or a wavelength-division multiplexing (WDM) device. The NP is integrated into these network devices in the form of a processing core or other circuit hardware unit, and in this case, the NP can also be called a network processor unit (NPU).

[0097] It is understandable that different manufacturers may have different names for the Smart NICs they produce. For example, some manufacturers call the Smart NICs they produce data processing units (DPUs), while other manufacturers call the Smart NICs they produce infrastructure processors (IPUs).

[0098] This application document describes the DPU as a network device. The DPU requires different microcodes to execute different services. Microcode, also known as microinstructions, is a series of relatively simple instructions that a computing device decomposes when running complex instructions. The microcode in the DPU consists of one or more service modules, each of which consists of one or more functions, and each function consists of one or more lines of statements.

[0099] To achieve higher processing performance, microcode typically runs in a DPU without an operating system (OS). This makes it difficult to obtain timing information when debugging microcode and determining the execution time of the microcode. Current solutions require users to find the functions that require timing in the microcode, write timing interfaces for these function parameters, write sampling statements in the microcode, and then compile the microcode with a compiler to create a microcode program with timing functionality. Finally, the microcode program with timing functionality is run on the DPU to obtain the corresponding function's execution time information.

[0100] However, since different functions may have different parameters, users need to write different timing interfaces for different functions. After obtaining the timing information, they also need to manually delete the written timing interfaces and sampling statements to avoid executing unnecessary timing operations when the DPU runs the debugged microcode.

[0101] In order to solve the above problems, the embodiments of the present application provide a timing control method and related equipment, which can simplify the process of implementing the microcode timing function and improve efficiency.

[0102] See also Figure 1 , Figure 1 A schematic diagram of the structure of a computing device provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the computing device 10 includes a first chip 101, a second chip 102, and an external memory 103. The first chip 101 is connected to the second chip 102 and the external memory 103, respectively, and the second chip 102 is connected to the external memory 103. The first chip 101 can communicate with the second chip 102 and the external memory 103 via the peripheral component interconnect express (PCIe) protocol; the second chip 102 can communicate with the external memory 103 via the PCIe protocol.

[0103] The first chip 101 is used to run a compiler 1011, which can be used to compile a microcode program from the microcode. The first chip 101 can send the compiled microcode program to the second chip 102. The microcode program can be executed by the second chip 102 to implement certain business functions. In some embodiments, the computing device 10 may include one or more first chips 101.

[0104] Among them, the second chip 102 includes a cache 1021 and a counter 1022. The cache 1021 can be used to cache the intermediate results calculated by the second chip 102, and the counter 1022 can be used to count the clock cycles of the second chip 102, and the corresponding clock cycle count value can be used for timing; the second chip 102 can execute the microcode program sent by the first chip 101. When the microcode has a timing function, the second chip 102 can start the counter 1022 for timing according to the microcode, and output the timing result to the cache 1021.

[0105] The external memory 103 is used to store data, and the data stored in the external memory 103 will not be lost due to power failure. The first chip 101 and the second chip 102 can read and write to the external memory 103 via the PCIe protocol. More specifically, the second chip 102 can output the data in the cache 1021 to the external memory 103 in the form of a printed log via the PCIe protocol.

[0106] In the embodiment of the present application, the computing device 10 may be a terminal, a server, a data center, or other computing devices capable of implementing embedded development.

[0107] In the embodiment of the present application, the first chip 101 may be a central processing unit (CPU), a micro-controller unit (MCU), or other chips or chipsets capable of running a compiler and transmitting and receiving data.

[0108] In the embodiment of the present application, the second chip 102 may be a DPU, or may be other chips that implement business functions based on embedded development.

[0109] Optionally, the cache 1021 in the second chip 102 is a single-port random access memory (SPRAM).

[0110] Optionally, the counter 1022 in the second chip 102 is a performance monitoring unit (PMU).

[0111] In the embodiment of the present application, the external memory 103 is a non-volatile storage medium, which can specifically be a hard disk memory, a floppy disk memory, an optical disk memory or a USB flash drive.

[0112] In some embodiments, the first chip 101, the second chip 102, and the external memory 103 may be in a single device, i.e., the computing device 10, or they may be distributed across different devices, or two of them may belong to the same device, while the other may belong to another device. For example, the first chip 101 and the external memory 103 may belong to one device, while the second chip 102 may belong to another device; or the second chip 102 and the external memory 103 may belong to the same device, while the first chip 101 may be a separate device, etc., and this application does not impose any specific limitations.

[0113] It is understandable that Figure 1 The number of the first chip 101 , the second chip 102 and the external memory 103 shown is for example only and is not limiting. In actual applications, the computing device 10 may include more first chips 101 , second chips 102 and / or external memories 103 .

[0114] It is worth noting that Figure 1 It is just a schematic diagram of the structural framework. Figure 1 The positional relationship between the devices, components, modules, etc. shown in the figure does not constitute any limitation.

[0115] Based on the structure of the computing device 10 described above, the application scenarios of the embodiments of the present application are illustrated below.

[0116] The embodiments of the present application can be applied to scenarios of high-performance service tuning of microcode, microcode testing scenarios, or other scenarios requiring high-precision timing in embedded development processes, such as debugging the microcode source code corresponding to the microcode program executed by the DPU in the server (that is, the microcode to be compiled below), so that the rate at which the DPU runs the service is within a preset range. For details, please refer to Figure 2 , Figure 2 A data flow diagram for a microcode debugging scenario provided in an embodiment of the present application.

[0117] like Figure 2 As shown, the user first needs to prepare the microcode to be compiled and the configuration file, and write the relevant timing configuration items in the configuration file; then the first chip 101 can run the compiler 1011, the compiler 1011 obtains the microcode to be compiled and the configuration file, and compiles the microcode to be compiled based on the configuration file to obtain the microcode program.

[0118] Among them, the microcode to be compiled and the configuration file can be stored in the external memory 103, or can be written or configured by the user in real time and stored in the memory of the computing device 10; the first chip 101 can obtain the microcode to be compiled and the configuration file from the external memory 103 or the memory of the computing device 10.

[0119] The configuration file is used to indicate the timing object in the microcode to be compiled, so that the compiler 1011 can add a sampling statement for timing the timing object to the microcode to be compiled and compile it when compiling the microcode to be compiled.

[0120] It is understandable that the specific implementation of the compiler 1011 adding the sampling statement and compiling it will be described in detail in the timing control method below, and will not be repeated here.

[0121] Therefore, the microcode program output by the compiler 1011 has a timing function, which can test and calculate the execution time of the target machine code corresponding to the timing object in the second chip 102. The microcode program is a binary machine code. After the first chip 101 sends the microcode to the second chip 102, the processing core in the second chip 102 can directly execute the microcode program.

[0122] Then, in the process of executing the microcode program, the second chip 102 executes the target machine code corresponding to the timing object and the timing machine code corresponding to the timing microcode; based on the timing machine code, the second chip 102 can control the counter 1022 to count the clock cycles of the process of executing the target machine code, and then after executing the target machine code, the count value of the counter 1022 is output to the cache 1021, and the count value is used to represent the running time of the target machine code.

[0123] After the second chip 102 outputs the execution time information of all target machine codes in the microcode program to the cache 1021 , the second chip 102 may output the execution time information in the cache 1021 to the external memory 103 .

[0124] Afterwards, the first chip 101 can obtain the running time information from the external memory 103 and output the running time information through a display device connected to the computing device 10, so that the user can know the running time information and control the first chip to perform debugging operations on the compiled microcode based on the running time information.

[0125] The user can determine whether the microcode to be compiled needs to be debugged based on the running time information. If necessary, after the user debugs the microcode to be compiled, the above process is repeated until it is determined that the microcode to be compiled does not need to be debugged.

[0126] If not needed, the user can obtain the debugged microcode to be compiled, then update the timing switch item in the configuration file to turn it off, and then compile the debugged microcode to be compiled into a target microcode program through the first chip 101; finally, the first chip 101 can send the target microcode program to the second chip 102, and instruct the second chip 102 to write the target microcode program into its own flash memory.

[0127] In the embodiment of the present application, the user can uniformly indicate the timing object in the microcode to be compiled based on the configuration file, without having to write an additional timing interface for the function parameters to indicate the timing object; and the compiler 1011 can directly generate the corresponding timing machine code based on the timing object, without having to manually write or delete the sampling statements or timing statements in the microcode to be compiled, thereby improving the efficiency of implementing the microcode timing function and obtaining the running time information of the function in the microcode.

[0128] In addition, when the second chip 102 executes the microcode program, it can use the hardware counter 1022 to count the clock cycles taken to execute the microcode program, and use the clock cycle count value to represent the running time, so that in the microcode running environment without an operating system in the second chip 102 or other embedded development-based chips, a higher-precision timing result can be obtained; the second chip 102 also temporarily stores the running time information obtained during the execution process in the cache 1021, and after obtaining the running time information corresponding to multiple timing objects, it uniformly outputs it to the external memory 103, thereby avoiding the problem of frequently outputting the running time information to the external memory 103, which affects the business logic.

[0129] After understanding the above-mentioned application devices and application scenarios of the embodiments of the present application, the timing control method provided by the embodiments of the present application is described below.

[0130] See Figure 3 , Figure 3 A flow chart of a timing control method provided in an embodiment of the present application is shown as follows: Figure 3 As shown, the method is applied to a computing device, which includes a first chip, a second chip, and an external memory. The method includes the following steps:

[0131] S101: A first chip obtains microcode to be compiled and a configuration file of the microcode to be compiled.

[0132] The microcode to be compiled is a microcode with timing requirements. The microcode with timing requirements may be a microcode that needs to be tested and debugged before being put into commercial use, or a microcode that needs to be tuned during the update and iteration process.

[0133] The microcode to be compiled includes one or more business modules, each of which includes one or more functions, and each of which includes one or more statements. In different application scenarios, users need to test the execution time of the functions or statements in the microcode to be compiled on the second chip to determine whether the microcode can be tuned or whether it can run stably at the expected speed.

[0134] The configuration file is used to instruct the compiler running on the first chip to add statements corresponding to the timing function to the microcode to be compiled during the compilation process. Specifically, the configuration file includes indication information of a timing object, where the timing object is a line of statements or multiple consecutive lines of statements in the same business module in the microcode to be compiled.

[0135] Optionally, the indication information may indicate the service module where the timing object is located, and the timing object.

[0136] Exemplarily, the indication information includes first indication information, where the first indication information is used to indicate that all functions in the corresponding business module serve as a timing object.

[0137] Exemplarily, the indication information includes second indication information, and the second indication information is used to indicate that each function in the corresponding business module serves as a timing object.

[0138] Optionally, the indication information uniformly indicates all timing objects in the microcode to be compiled.

[0139] Exemplarily, the indication information includes third indication information, and the third indication information is used to indicate that each function of each business module is used as a timing object.

[0140] Exemplarily, the indication information includes fourth indication information, and the fourth indication information is used to indicate that all functions of each business module serve as a timing object.

[0141] Optionally, the indication information includes function name and line number information, which is used to locate the start timing statement and the first output statement; and indicates that the statement between the start timing statement and the first output statement is used as a timing object.

[0142] Optionally, the format of the configuration file includes JavaScript object notation (JSON) format, text document (TXT) format or device information file (INF) format.

[0143] It is understandable that the format of the configuration file may also be other formats. This is only an example and not a limitation, and the embodiments of the present application do not make specific limitations on this.

[0144] Before the first chip executes step S101, the user can modify the corresponding timing configuration fields in the configuration file template or existing configuration file based on business requirements to add indication information of the timing objects in the microcode to be compiled. The user can then store the new configuration file and the microcode to be compiled in the memory or external storage of the computing device. In this way, when the first chip executes step S101, it can read the microcode to be compiled and the configuration file from the memory or external storage of the computing device.

[0145] S102: The first chip writes a sampled IR into the microcode to be compiled according to the instruction information of the timing object in the configuration file.

[0146] After obtaining the configuration file, the first chip can determine the timing object in the microcode to be compiled based on the timing object's indication information in the configuration file. After determining the timing object, the first chip can add a statement to the microcode to be compiled to implement the function of testing the execution time of the timing object. Specifically, the first chip can add a statement to start timing before the timing object and a statement to obtain timing information after the timing object.

[0147] Among them, the first chip can add statements for timing by writing sampling IR. The sampling IR has the semantic characteristics of the microcode to be compiled and can be fully and accurately compiled to obtain the target code with corresponding semantic information (binary machine code in the embodiment of this application).

[0148] Specifically, the sampled IR is used to compile and generate timing machine code, which is used to test the execution time of the target machine code in the second chip. The target machine code is the machine code obtained by compiling the timing object by the compiler running on the first chip.

[0149] Specifically, the sampling IR includes a start timing IR and a first output IR. The start timing IR is used to compile and generate a start timing machine code, and the start timing machine code is used to start the running timing test of the target machine code; the first output IR is used to compile and generate a first output machine code, and the first output machine code is used to obtain the timing information obtained by the running timing test, that is, the running timing information of the target machine code.

[0150] Optionally, the first chip may insert a start timing IR between the first statement line in the timing object and the previous line; and insert a first output IR between the last statement line in the timing object and the next line.

[0151] The second chip further includes a cache memory, which is an on-chip memory of the second chip;

[0152] Optionally, the configuration file also includes information about a storage area, which is an area in the cache of the second chip used to store the operation timing information; the timing machine code is specifically used to obtain the operation timing information and output the operation timing information to the storage area based on the information of the storage area.

[0153] The second chip may allocate an area in its cache to store the execution time information.

[0154] Optionally, when the configuration file does not include information about the storage area, the timing machine code is specifically used to obtain the execution time information and output the execution time information to the default storage area of the cache.

[0155] The default storage area is used to preferentially store or only store the running time information.

[0156] Optionally, the cache is a single-port random access memory (SPRAM).

[0157] By outputting the running time information to a specific storage area in the cache, on the one hand, it is possible to avoid conflicts with other businesses that may cause the running time information to be lost. On the other hand, there is no need to output the running time information to the external memory of the computing device in the form of a printed log every time the running time information is obtained. Instead, the running time information is output to the storage area first after each acquisition, and the running time information in the storage area is uniformly output to the external memory after multiple acquisitions. This can avoid the impact of frequent log printing on business logic and improve timing accuracy.

[0158] S103 , the first chip compiles the microcode to be compiled after writing the sampled IR into a microcode program.

[0159] The microcode to be compiled needs to be compiled into a binary microcode program, which will serve as the service code of the second chip, enabling the second chip to implement various services. Therefore, the microcode to be compiled can be in various high-level programming languages, such as C and C++, which are not specifically limited in this embodiment of the present application. In actual applications, the type of microcode to be compiled can be determined by the user's preference and the support of the compilation tool.

[0160] Among them, after writing the sampled IR to the microcode to be compiled, the compiler needs to compile the microcode to be compiled itself into binary machine code, which contains the target machine code corresponding to the timing object; on the other hand, it needs to generate the corresponding timing machine code based on the semantic information of the sampled IR.

[0161] S104: The first chip sends the microcode program and the trigger instruction to the second chip.

[0162] The trigger instruction may be an instruction instructing the second chip to run a service, and specifically may be used to trigger the second chip to execute the microcode program to run or support the service. For example, the trigger instruction may trigger the second chip to execute the timing machine code and the target machine code, or may trigger the second chip to execute the machine code corresponding to the service module where the timing target is located, or may trigger the second chip to execute the entire microcode.

[0163] Since the operating environment of the microcode in the second chip does not have an OS, the second chip implements its business by executing the microcode program in a specific memory; therefore, after receiving the microcode program, the second chip needs to first erase the original corresponding microcode program in the memory, and then write the microcode program obtained in step S103 into the memory. Among them, the corresponding microcode program refers to a microcode program used to implement the same or similar business functions as the microcode program obtained in step S103. For example, in the microcode tuning scenario, the microcode program before tuning is stored in the memory, and the microcode program obtained in step S103 is obtained during the tuning process.

[0164] It is understandable that when the corresponding microcode program does not exist in the memory, the second chip can directly write the microcode program obtained in step S103 into the memory.

[0165] Optionally, the first chip may directly burn the microcode program into a corresponding memory in the second chip.

[0166] Optionally, the first chip may send the microcode program to an external memory of the computing device, and the second chip obtains the microcode program from the external memory and writes the microcode program into a corresponding memory in the second chip.

[0167] Optionally, the memory for storing the microcode program in the second chip is a flash memory.

[0168] S105 : The second chip executes the microcode program according to the trigger instruction to obtain the running time information of the target machine code in the microcode program.

[0169] After the second chip receives the trigger instruction and the microcode program and writes the microcode program into the corresponding memory, the second chip can execute the target machine code and timing machine code in the microcode program according to the trigger instruction, thereby obtaining the running time information of the target machine code.

[0170] Then, after obtaining the operation time information, the second chip can output the operation time information to the external memory, so that the first chip can obtain the operation time information and present the operation time information to the user through a display device that the user can perceive.

[0171] Optionally, after obtaining the operation time information each time, the second chip can temporarily store the operation time information in the cache of the second chip; and after obtaining the operation time information multiple times, the operation time information obtained multiple times can be uniformly output to the external memory of the computing device.

[0172] In an embodiment of the present application, the first chip can directly obtain the timing object in the microcode to be compiled through a pre-prepared configuration file, and automatically write the corresponding sampling IR to the microcode to be compiled during the compilation stage based on the timing object, and then compile to obtain a microcode program with a timing function; there is no need to write different timing interfaces for the parameters of the timing objects in different business modules, and the implementation process is simple and efficient.

[0173] The timing control method provided in the embodiment of the present application will be described below through a more specific embodiment.

[0174] See Figure 4 , Figure 4 This is a flow chart of another timing control method provided in an embodiment of the present application. The method is applied to a computing device comprising a first chip, a second chip, and an external memory. In this embodiment, the first chip is a CPU, the second chip is a DPU, and the external memory is a hard disk.

[0175] like Figure 4 As shown, the method includes the following steps:

[0176] S201. The CPU obtains the microcode to be compiled and the configuration file of the microcode to be compiled.

[0177] A compiler is running on the CPU, and the compiler can obtain the microcode to be compiled and a configuration file of the microcode to be compiled from a hard disk or a memory of the computing device.

[0178] The configuration file includes a timer switch item, information indicating a timer object, and information about a storage area in the second chip's cache for storing execution time information. It is understood that these three items of information are pre-configured by the user. The user can modify the corresponding fields in the configuration file based on business requirements and then store the modified configuration file in the computing device's memory or hard disk.

[0179] Specifically, the timing switch is used to determine whether additional timing statements need to be written into the microcode to be compiled during the compilation process, thereby obtaining microcode with timing functionality. When the timing switch is on, the CPU will execute the compiler to perform steps S202 to S205; when the timing switch is off, the CPU will execute the compiler and directly execute step S205.

[0180] It is understandable that the user can turn on the timing switch item, and the computing device executes the method of this embodiment to obtain the running time information of the corresponding timing object; after completing the debugging or testing based on the running time information, the user can turn off the timing switch item in the configuration file, and the CPU can compile the microcode to be compiled after the debugging or testing is completed to obtain the target microcode that does not include the timing machine code; then the CPU writes the target microcode after the debugging or testing is completed into the DPU as the business code of the DPU.

[0181] Specifically, the indication information of the timing object may include the line number of the start timing statement of the timing object and the line number of the first output statement.

[0182] For example, a business module includes 10 functions, the function names of the 10 functions are fun1 to fun10, and the running order of the 10 functions is fun1 to fun10; the user needs to test the running time of function fun2 and functions fun5 to fun6.

[0183] At this time, the indication information of the timing object corresponding to the business module in the configuration file can be as follows:

[0184] 1.start_function:"fun2" / start_line_after:15 / stop_function:"fun2" / stop_line_after:20

[0185] 2.start_function:"fun5" / start_line_after:50 / stop_function:"fun6" / stop_line_after:66

[0186] Among them, start_function and stop_function are used to indicate the function names of the start timing statement and the first output statement respectively; start_line_after is used to indicate the line number of the start timing statement, and stop_line_after is used to indicate the line number of the first output statement.

[0187] Specifically, start_line_after: 15 means that the line number of the start timing statement is the line after line 15. In some possible implementations, start_line_before may also be used to indicate the line number of the start timing statement, specifically indicating that the line number of the start timing statement is the line before the specified line.

[0188] Optionally, the configuration file includes timing path information, which includes indication information of timing objects. For example, the information of timing path 1 in the configuration file may include indication information 1 and 2 in the above example, that is, timing objects 1 and 2 indicated by the indication information are nodes of timing path 1.

[0189] Specifically, the information of the storage area in the cache of the second chip for storing the execution time-consuming information may include the starting address and length of the storage area.

[0190] The user can pre-set a storage area in the cache to store this runtime information. Other services running on the DPU cannot read or write to this storage area. The user can then configure the specific information for this storage area in the configuration file. For example, the cache has a storage space of 4KB, the starting address of this storage area can be the 1025th byte of the cache, and the length can be 100 bytes. This means that the storage area is from bytes 1025 to 1124 of the cache.

[0191] S202. The CPU writes a start timing IR to the microcode to be compiled according to the instruction information of the timing object in the configuration file.

[0192] When the timing switch item in the configuration file is turned on, the compiler on the CPU can execute steps S202 to S205. Specifically, the compiler can use the following method: Figure 5 The process shown writes the sampled IR, and the process includes steps S301 to S303.

[0193] S301: The CPU determines a timing object in the microcode to be compiled.

[0194] Among them, the indication information of the timing object in the configuration file also includes the function name of the function where the start timing statement and the first output statement are located; the compiler can traverse the functions in the microcode to be compiled, and determine the function where the start timing statement matching the function name is located in the microcode to be compiled, and the function where the first output statement is located; then, based on the line number of the start timing statement and the line number of the first output statement, determine the start timing statement and the first output statement in the statements of these two functions; finally, determine that the statement between the start timing statement and the first output statement is the timing object.

[0195] Optionally, the timing object may include the start timing statement and / or the first output statement, or may not include the start timing statement and the first output statement.

[0196] In the embodiment of the present application, by first matching the function name and then matching the line number, the efficiency of locating the start timing statement and the first output statement can be improved.

[0197] S302. The CPU determines the write position of the sampled IR.

[0198] After determining the timing object, the sampled IR can be written based on the line number of the start timing statement and the line number of the first output statement in the configuration file. It should be understood that each timing object corresponds to a start timing statement and a first output statement. More specifically, the statements between the start timing statement and the first output statement are the timing objects, or the statements from the start timing statement to the first output statement are the timing objects.

[0199] When the start timing statement is the first line of the timing object, the corresponding line number indication information in the configuration file can be before; the compiler can determine that the corresponding write position is between the start timing statement and the previous line of statement; when the start timing statement is the previous line of statement of the timing object, the corresponding line number indication information in the configuration file can be after; the compiler can determine that the corresponding write position is between the start timing statement and the next line of statement.

[0200] When the first output statement is the last line of the timing object, the corresponding line number indication information in the configuration file may be "after"; the compiler may determine that the corresponding write position is between the first output statement and the next line of the statement; when the first output statement is the next line of the timing object, the corresponding line number indication information in the configuration file may be "before"; the compiler may determine that the corresponding write position is between the first output statement and the previous line of the statement.

[0201] S303 , the CPU writes the sampled IR.

[0202] After determining the write position, the compiler can determine whether the start timing IR or the first output IR needs to be written based on the start_line or stop_line in the line number indication information; when the line number indication information includes start_line, the compiler can write the start timing IR to the corresponding write position; when the line number indication information includes stop_line, the compiler can write the first output IR to the corresponding write position.

[0203] The start timing IR is used to compile and generate a start timing machine code, and the start timing machine code is used to start a running time consumption test of the target machine code.

[0204] Among them, the first output IR is used to compile and generate the first output machine code, and the first output machine code is used to obtain the result of the running time test started by the start timing machine code, and use the result as the running time information, and output the running time information to the storage area indicated in the configuration file.

[0205] Optionally, the configuration file also includes the line number of the second output statement of the business module where the timing object is located. Exemplarily, the indication information of the second output statement may be as follows:

[0206] print_cycles_at:"fun10" / print_cycles_at_line_after:99

[0207] Similarly, the compiler can determine the write location based on the line number indication information after and the specific line number; and then determine that the second output IR needs to be written to the write location based on print_cycles_at_line.

[0208] The second output IR is used to compile and generate a second output machine code, and the second output machine code is used to output the running time information corresponding to the business module in the storage area.

[0209] Specifically, a business module may include one or more timing objects. After acquiring each execution time information, the second chip can first output it to a storage area in its cache. Once all execution time information corresponding to a business module has been acquired, the chip can then output all of this information to the hard disk. This prevents excessive output of this execution time information to the hard disk, which could affect business logic and the accuracy of timing results.

[0210] Optionally, the compiler may preset a sample IR corresponding to the compilation from the microcode to be compiled to the microcode. After determining the write position, the compiler may directly write the corresponding sample IR at the write position.

[0211] Optionally, the compiler may construct and generate corresponding sampling IR based on the semantic information of the sampling IR required for different write locations, and write the corresponding sampling IR into the corresponding write locations.

[0212] S203: The CPU writes a first output IR to the microcode to be compiled according to the instruction information of the timing object in the configuration file.

[0213] S204 : The CPU writes a second output IR to the microcode to be compiled according to the instruction information of the timing object in the configuration file.

[0214] In one possible implementation, the user configures the line number of the second output statement of one or more business modules in the configuration file; at this time, for these business modules, the CPU can write the second output IR to the microcode to be compiled according to the line number of the second output statement.

[0215] In another possible implementation, the user does not configure the line number of the second output statement in the configuration file; for a business module that includes a timing object, the CPU can write the second output IR at a position after the last written first output IR in the microcode to be compiled after all the first output IRs corresponding to the timing objects of the business module are written.

[0216] In addition to the above possibility of outputting running time information by business module, users can also write timing path information in the configuration file to enable the DPU to output running time information by timing path:

[0217] In one possible implementation, the configuration file includes timing path information, which is used to indicate one or more timing paths, each timing path including one or more timing objects; the timing path information includes the line number of the second output statement of the timing path; the CPU can write the second output IR to the microcode to be compiled based on the line number of the second output statement, so that when the DPU runs the corresponding second output machine code, it can output the running time information of each node (timing object) on the timing path to the hard disk.

[0218] In another possible implementation, the configuration file includes timing path information but does not include the line number of the second output statement; in this case, for each timing path, the CPU may write the second output IR after the first output IR corresponding to the last timing object of the timing path.

[0219] The manner of writing the sampled IR in steps S203 and S204 is the same as the implementation of step S202 in this embodiment, and will not be repeated here.

[0220] S205 , the CPU compiles the microcode to be compiled into a microcode program.

[0221] When the timing switch in the configuration file is enabled, the compiler running on the CPU compiles the microcode to be compiled written into the sampled IR into a microcode program. This microcode program now includes timing machine code and target machine code. The timing machine code is the machine code obtained by compiling the sampled IR, and the target machine code is the machine code obtained by compiling the timing target. At this point, the CPU executes step S206, causing subsequent steps S207 to S212 to be executed.

[0222] When the timing switch item is closed, the compiler compiles the microcode to be compiled that has not been written into the sampled IR into a microcode program. At this time, the CPU sends the microcode program to the DPU, and the DPU uses the microcode program as its business function code.

[0223] S206. The CPU sends the microcode program and the trigger instruction to the DPU.

[0224] The implementation of step S206 in this embodiment is similar to Figure 3 The implementation of step S104 in the illustrated embodiment is similar and will not be described again here.

[0225] S207 . The DPU executes the start timing machine code in the microcode program according to the trigger instruction.

[0226] When the DPU starts timing the machine code according to the timing execution, the DPU may control the PMU in the DPU to count from zero to start the running time test of the target machine code.

[0227] In some other possible implementations, the PMU may start counting in a continuous cycle after power-on; when the DPU executes a machine code to start timing, the DPU may directly read the first count value of the PMU and cache it in the storage area.

[0228] S208. The DPU executes the target machine code in the microcode program according to the trigger instruction.

[0229] After starting the running time test, the DPU may start executing the target machine code according to the execution order of different code parts in the microcode program.

[0230] S209 . The DPU executes the first output machine code in the microcode program according to the trigger instruction.

[0231] After the target machine code is executed, the DPU may execute the first output machine code to obtain the count value of the PMU.

[0232] At this time, if the DPU controls the PMU to start counting from zero when executing the start timing machine code, the DPU can output the count value as the running time information of the target machine code to the storage area; specifically, the count value represents the clock cycle taken by the second chip to execute the target machine code, and the length of one clock cycle is the inverse of the operating frequency of the second chip.

[0233] If the DPU obtains the first count value when executing the start timing machine code, the DPU can obtain the second count value when executing the first output machine code, and use the difference between the first count value and the second count value as the running time information, and output the running time information to the storage area.

[0234] S210 . The DPU executes the second output machine code in the microcode program according to the trigger instruction.

[0235] When the DPU executes the second output machine code, the DPU may output the execution time information corresponding to the target business module or target timing path in the storage area to the hard disk of the computing device. Specifically, the business module corresponding to the second output IR corresponding to the second output machine code may be referred to as the target business module, and the corresponding timing path may be referred to as the target timing path. The corresponding execution time information refers to the execution time information of the target machine code corresponding to the timing object in the target business module or target timing path in the second chip.

[0236] By outputting the second machine code, the user can control the time node for outputting the execution time information, which is more flexible.

[0237] S211. The CPU obtains operation time consumption information from the hard disk.

[0238] After the DPU outputs the running time information to the hard disk, the CPU can receive a control instruction input by the user and obtain the running time information from the hard disk according to the control instruction.

[0239] S212: The CPU outputs the operation time-consuming information to a display device.

[0240] Among them, after the CPU obtains the running time information, the CPU can calculate the specific running time of each timing object in the DPU based on the running time information (number of clock cycles) and the running frequency of the DPU, and output the running time of each timing object to the display device so that the user can know the running time.

[0241] Optionally, the CPU may further generate a graphic report based on the running time of each timing object, and then display the graphic report through a display device.

[0242] In an embodiment of the present application, when the DPU executes the microcode program, it uses the hardware PMU to count the clock cycles taken to execute the target machine code, thereby being able to obtain high-precision timing results in an operating environment without an operating system; the DPU also temporarily stores the obtained running time information in a storage area in the cache, and after obtaining all the running time information corresponding to the business module, outputs the running time information to the hard disk in units of business modules, thereby avoiding the problem of frequent output of running time information affecting the business logic.

[0243] In addition, the user can control the compilation process through the timing switch item, and after debugging the microcode, there is no need to manually delete the timing-related code in the microcode. The microcode can be directly compiled to obtain a microcode program that does not include the timing machine code.

[0244] See also Figure 6 , Figure 6 A possible logical structure diagram of a computing device 600 provided in an embodiment of the present application. The computing device 600 includes: a processor 601, a memory 602, and a bus 603. The processor 601 and the memory 602 are interconnected via the bus 603. In the embodiment of the present application, the processor 601 is used to control and manage the actions of the computing device 600. For example, the processor 601 is used to execute Figure 3 、 Figure 4 or Figure 5 The technical process described in the embodiment. The memory 602 is used to store program codes and data of the computing device 600.

[0245] Among them, the processor 602 can be a central processing unit, a data processor, an infrastructure processor, an intelligent network card, a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component or any combination thereof. It can implement or execute the various exemplary logic blocks, modules and circuits described in conjunction with the disclosure of this application. The processor 602 can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, and so on. The bus 603 can be a Peripheral Component Interconnect (PCI) bus, a PCIe bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 6 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0246] In another embodiment of the present application, a computer-readable storage medium is further provided, wherein the computer-readable storage medium stores computer-executable instructions. When at least one processor of the device executes the computer-executable instructions, the device executes the above-mentioned Figure 3 、 Figure 4 or Figure 5 The timing control method described in some embodiments.

[0247] In another embodiment of the present application, a computer program product is further provided. The computer program product includes computer-executable instructions, which are stored in a computer-readable storage medium. At least one processor of the device can read the computer-executable instructions from the computer-readable storage medium, and at least one processor executes the computer-executable instructions so that the device performs the above-mentioned Figure 3 、 Figure 4 or Figure 5 The timing control method described in some embodiments.

[0248] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0249] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0250] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0251] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0252] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, read-only memory), random access memory (RAM, random access memory), disk or optical disk, and other media that can store program code.

Claims

1. A timing control method, characterized in that: Applied to a computing device, the computing device includes a first chip and a second chip; the method includes: The first chip obtains a microcode to be compiled and a configuration file of the microcode to be compiled, wherein the configuration file includes indication information of a timing object in the microcode to be compiled, and the timing object is a line of statement or multiple consecutive lines of statements in the same service module in the microcode to be compiled; The first chip writes a sample intermediate representation (IR) into the microcode to be compiled according to the instruction information of the timing object, wherein the sample intermediate representation (IR) is used to compile and generate timing machine code, and the timing machine code is used to test the execution time of the target machine code in the second chip, wherein the target machine code is the machine code obtained by compiling the timing object; The first chip compiles the microcode to be compiled after being written into the sampled IR into a microcode program; The first chip sends the microcode program and trigger instruction to the second chip; The second chip executes the microcode program according to the trigger instruction to obtain the running time consumption information of the target machine code.

2. The method according to claim 1, characterized in that The configuration file also includes information about a storage area, which is an area in the cache of the second chip used to store the operation time information; the timing machine code is specifically used to obtain the operation time information and output the operation time information to the storage area based on the information of the storage area.

3. The method according to claim 2, characterized in that The indication information of the timing object includes the line number of the start timing statement and the line number of the first output statement of the timing object, and the sampled IR includes the start timing IR and the first output IR; The first chip writes a sampled IR into the microcode to be compiled according to the instruction information of the timing object, including: The first chip writes the start timing IR into the microcode to be compiled according to the line number of the start timing statement, wherein the start timing IR is used to compile and generate a start timing machine code, and the start timing machine code is used to start the running time consumption test of the target machine code; The first chip writes the first output IR to the microcode to be compiled according to the line number of the first output statement. The first output IR is used to compile and generate a first output machine code. The first output machine code is used to obtain the result of the running time test and output the result as the running time information to the storage area.

4. The method according to claim 3, characterized in that The second chip executes the microcode program according to the trigger instruction, including: The second chip executes the start timing machine code according to the trigger instruction, and controls the clock cycle counter of the second chip to start counting from zero; The second chip executes the first output machine code according to the trigger instruction, obtains the count value of the clock cycle counter after the target machine code is executed, and outputs the count value as the execution time information to the storage area.

5. The method according to any one of claims 2 to 4, characterized in that The configuration file further includes a line number of a second output statement of the business module, the business module corresponding to one or more timing objects; the sampled IR includes a second output IR; After the first chip obtains the microcode to be compiled and the configuration file of the microcode to be compiled, the method further includes: The first chip writes the second output IR to the microcode to be compiled according to the line number of the second output statement, and the second output IR is used to compile and generate a second output machine code, and the second output machine code is used to output the running time information corresponding to the business module in the storage area.

6. The method according to claim 3 or 4, characterized in that The service module corresponds to one or more timing objects, the sampled IR includes a second output IR; after the first chip writes the first output IR to the microcode to be compiled according to the line number of the first output statement, the method further includes: When the first output IRs corresponding to all timing objects of the business module are written, the first chip writes the second output IR at a position after the last written first output IR in the microcode to be compiled.

7. The method according to claim 5 or 6, characterized in that The second chip executes the microcode program according to the trigger instruction, including: The second chip executes the second output machine code according to the trigger instruction, and outputs the running time consumption information corresponding to the business module in the storage area to the external memory of the computing device.

8. The method according to any one of claims 1 to 7, characterized in that The first chip is a central processing unit (CPU), and the second chip is a data processing unit (DPU).

9. The method according to claim 4, characterized in that The clock cycle counter is a performance monitoring unit PMU.

10. A computing device, characterized in that The computing device includes a first chip and a second chip; The first chip is used to obtain a microcode to be compiled and a configuration file of the microcode to be compiled, wherein the configuration file includes indication information of a timing object in the microcode to be compiled, and the timing object is a line of statement or multiple consecutive lines of statements in the same service module in the microcode to be compiled; The first chip is further configured to write a sample intermediate representation (IR) into the microcode to be compiled according to the instruction information of the timing object, wherein the sample intermediate representation (IR) is used to compile and generate timing machine code, and the timing machine code is used to test the execution time of the target machine code in the second chip, wherein the target machine code is the machine code obtained by compiling the timing object; The first chip is further configured to compile the microcode to be compiled after being written into the sampled IR into a microcode program; The first chip is further configured to send the microcode program and trigger instruction to the second chip; The second chip is used to execute the microcode program according to the trigger instruction to obtain the running time consumption information of the target machine code.

11. The computing device according to claim 10, wherein: The configuration file also includes information about a storage area, which is an area in the cache of the second chip used to store the execution time information; the timing machine code is specifically used to obtain the execution time information and output the execution time information to the storage area based on the information of the storage area.

12. The computing device according to claim 11, wherein: The indication information of the timing object includes the line number of the start timing statement and the line number of the first output statement of the timing object, and the sampled IR includes the start timing IR and the first output IR; The first chip is specifically configured to write the start timing IR into the microcode to be compiled according to the line number of the start timing statement, wherein the start timing IR is used to compile and generate a start timing machine code, and the start timing machine code is used to start the running time consumption test of the target machine code; The first chip is specifically used to write the first output IR to the microcode to be compiled according to the line number of the first output statement, the first output IR is used to compile and generate the first output machine code, the first output machine code is used to obtain the result of the running time test, and output the result as the running time information to the storage area.

13. The computing device according to claim 12, wherein: The second chip is specifically configured to execute the timing start machine code according to the trigger instruction, and control the clock cycle counter of the second chip to start counting from zero; The second chip is specifically configured to execute the first output machine code according to the trigger instruction, obtain a count value of the clock cycle counter after the target machine code is executed, and output the count value as the execution time information to the storage area.

14. The computing device according to any one of claims 11 to 13, characterized in that The configuration file further includes a line number of a second output statement of the business module, the business module corresponding to one or more timing objects; the sampled IR includes a second output IR; The first chip is also used to write a second output IR to the microcode to be compiled according to the line number of the second output statement, and the second output IR is used to compile and generate a second output machine code, and the second output machine code is used to output the running time information corresponding to the business module in the storage area.

15. The computing device according to any one of claims 12 or 13, characterized in that The business module corresponds to one or more timing objects, and the sampled IR includes a second output IR; The first chip is further configured to write the second output IR at a position following the last written first output IR in the microcode to be compiled after all first output IRs corresponding to all timing objects of the business module are written.

16. The computing device according to claim 14 or 15, characterized in that The second chip is specifically configured to execute the second output machine code according to the trigger instruction, and output the running time information corresponding to the business module in the storage area to the external memory of the computing device.

17. The computing device according to any one of claims 10 to 16, wherein: The first chip is a central processing unit (CPU), and the second chip is a data processing unit (DPU).

18. The computing device according to claim 13, wherein: The clock cycle counter is a performance monitoring unit PMU.

19. A computing device comprising a processor and a memory, wherein the memory stores computer instructions, and when the computer instructions are executed by the processor, the computing device executes the method according to any one of claims 1 to 9. 20 . A computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are capable of implementing the method according to claim 1 when executed by a processor.

21. A computer program product comprising computer executable instructions, wherein the computer executable instructions implement the method according to any one of claims 1 to 9 when executed.

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