Memory management method, device, electronic device and readable storage medium

Abstract

The embodiment of the present invention provides a memory management method, device, electronic device and readable storage medium. The method includes: based on the client virtual address to be accessed, accessing the page table corresponding to the client virtual address; when the current page table entry currently accessed belongs to the large page page table entry, determining the client physical memory large page corresponding to the client virtual address as the target physical memory page based on the current page table entry; when the current page table entry does not belong to the large page page table entry, determining the next-level page table entry pointed to by the current page table entry as the new current page table entry, and performing the operation of determining the client physical memory large page corresponding to the client virtual address as the target physical memory page based on the current page table entry again; obtaining the memory access status of the target physical memory page; if the memory access status indicates that the target physical memory page meets the preset memory access requirements, writing the memory access attributes of the target physical memory page into the preset cache table. Improve the efficiency of the translator in implementing address conversion.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a memory management method, device, electronic device and readable storage medium. Background Art

[0002] In the field of computer technology, binary translation technology is usually used, that is, a translator translates client instructions into host instructions, so that a program compiled for one instruction set architecture (ISA) can also run on a hardware platform of another instruction set architecture.

[0003] Currently, cross-ISA program simulation is typically achieved through a binary translator. Accordingly, the binary translator needs to simulate the client's memory mapping, that is, the conversion of virtual memory addresses to physical memory addresses. In related technologies, translators often achieve this conversion through the client's multi-level page table. However, these multi-level page tables require multiple traversals, resulting in poor efficiency. Summary of the Invention

[0004] The purpose of the embodiments of the present invention is to provide a memory management method, device, electronic device, and readable storage medium to solve the problem of poor address conversion efficiency of a translator. The specific technical solution is as follows:

[0005] In a first aspect of the present invention, a memory management method is provided, which is applied to a system-level translator and includes:

[0006] Accessing a page table corresponding to the client virtual address based on the client virtual address to be accessed;

[0007] In a process of accessing the page table, if a current page table entry currently accessed is a huge page page table entry, determining, based on the current page table entry, a client physical memory huge page corresponding to the client virtual address as a target physical memory page;

[0008] If the current page table entry does not belong to a huge page table entry, determine the next-level page table entry pointed to by the current page table entry as a new current page table entry, and again perform the operation of determining, based on the current page table entry, as the target physical memory page the client physical memory huge page corresponding to the client virtual address when the current page table entry currently being accessed belongs to a huge page page table entry;

[0009] Obtaining a memory access status of the target physical memory page;

[0010] If the memory access status indicates that the target physical memory page meets the preset memory access requirements, the memory access attributes of the target physical memory page are written into the preset cache table; the memory access attributes include at least the address mapping relationship of the target physical memory page and the memory access permissions of the target physical memory page; the address mapping relationship is the mapping relationship between the target physical memory page and the client virtual address and the corresponding host virtual address.

[0011] In a second aspect of the present invention, a memory management device is provided. The device is applied to a system-level translator, and the device includes:

[0012] An access module, configured to access a page table corresponding to a client virtual address based on the client virtual address to be accessed;

[0013] A first determining module is configured to, in a process of accessing the page table, determine, based on the current page table entry, a client physical memory huge page corresponding to the client virtual address as a target physical memory page when the current page table entry currently accessed is a huge page page table entry;

[0014] an execution module, configured to, if the current page table entry does not belong to a huge page table entry, determine the next-level page table entry pointed to by the current page table entry as a new current page table entry, and again perform the operation of determining, if the current page table entry currently being accessed belongs to a huge page page table entry, the client physical memory huge page corresponding to the client virtual address based on the current page table entry as the target physical memory page;

[0015] A first acquisition module, configured to acquire a memory access status of the target physical memory page;

[0016] The first writing module is used to write the memory access attributes of the target physical memory page into a preset cache table if the memory access status indicates that the target physical memory page meets the preset memory access requirements; the memory access attributes include at least the address mapping relationship of the target physical memory page and the memory access permission of the target physical memory page; the address mapping relationship is the mapping relationship between the target physical memory page and the client virtual address and the corresponding host virtual address.

[0017] In a third aspect of the present invention, an electronic device is provided, comprising a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus;

[0018] Memory for storing computer programs;

[0019] The processor is configured to implement the method described in the first aspect above when executing the program stored in the memory.

[0020] In a fourth aspect of the present invention, a computer-readable storage medium is provided, wherein instructions are stored in the computer-readable storage medium. When the computer-readable storage medium is run on a computer, the computer executes the method described in the first aspect.

[0021] In a fifth aspect of the implementation of the present invention, a computer program product comprising instructions is further provided, which, when executed on a computer, enables the computer to execute the method described in the first aspect above.

[0022] The memory management method provided by the embodiment of the present invention can realize support for large pages in a system-level translator by identifying large page page table entries during page table access and determining the client physical memory large page as the target physical memory page based on the large page page table entries. When the large page page table entry is accessed, the target physical memory page can be determined directly using the address mapping relationship of the large page through the large page page table entry, thereby reducing the number of page table traversals and improving the efficiency of the translator in achieving address conversion. At the same time, by writing the memory access attributes of the target physical memory page into a preset cache table when the memory access status of the target physical memory page meets the preset memory access requirements, the number of table entries in the preset cache table can be greatly reduced. Only one table entry is required to record the memory access attributes of the large page. While accelerating memory access through the preset cache table, the space occupied by the preset cache table can be greatly reduced, thereby improving the simulation performance of the translator. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for describing the embodiments or the prior art.

[0024] Figure 1 A flowchart of a memory management method according to an embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of the structure of a preset record table provided by an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of a page table traversal provided by an embodiment of the present invention;

[0027] Figure 4 Schematic diagram of the structure of a memory management device according to an embodiment of the present invention;

[0028] Figure 5 FIG. 4 is a schematic diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0030] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after the association are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0031] Figure 1 FIG is a flow chart of the steps of a memory management method in an embodiment of the present invention, which can be applied to a system-level translator, such as Figure 1 As shown, the method includes:

[0032] Step 101: Based on the client virtual address to be accessed, access the page table corresponding to the client virtual address.

[0033] Step 102: During access to the page table, if the current page table entry being accessed is a large page page table entry, determine the client physical memory page corresponding to the client virtual address as the target physical memory page based on the current page table entry.

[0034] Step 103: When the current page table entry does not belong to a large page page table entry, the next-level page table entry pointed to by the current page table entry is determined as a new current page table entry, and the operation of determining the client physical memory large page corresponding to the client virtual address as the target physical memory page based on the current page table entry is performed again when the current page table entry currently accessed belongs to a large page page table entry.

[0035] Step 104: Obtain the memory access status of the target physical memory page.

[0036] Step 105: If the memory access status indicates that the target physical memory page meets the preset memory access requirements, the memory access attributes of the target physical memory page are written into a preset cache table; the memory access attributes include at least the address mapping relationship of the target physical memory page and the memory access permission of the target physical memory page; the address mapping relationship is the mapping relationship between the target physical memory page and the client virtual address and the corresponding host virtual memory address.

[0037] Regarding steps 101-105 above, the embodiments of the present invention can be applied to any system-level translator (also referred to as a system-level binary translator). Specifically, binary translation technology can enable cross-ISA compatibility for executable files and can be applied in scenarios such as software compatibility, architecture simulation, program analysis, and debugging. It typically involves multiple aspects such as compilation, operating systems, and system architecture, and can migrate the software ecosystem of mature processor (Central Processing Unit) architectures to emerging CPU architectures. The translator is used to translate source program A in a guest (guest) into target program B in a host (host), and then execute target program B in the host, enabling simulated execution of the guest program on the host. For example, the guest in the embodiments of the present invention can adopt a complex instruction set (CISC) architecture, while the host can adopt a reduced instruction set (RSIC) architecture. Specifically, a binary translation system typically includes a user-level binary translation system and a system-level binary translation system. The user-level binary translation system supports running guest applications, while the system-level binary translation system supports running a complete guest operating system, thereby enabling the execution of any guest application. Therefore, in a system-level binary translator, it is often necessary to simulate the guest's virtual memory.

[0038] The guest virtual address mentioned above refers to the guest virtual memory address (GVA). A virtual memory address is a logical address generated when the CPU executes instructions. The operating system provides each process with an independent, continuous address space. It does not directly correspond to a physical memory location, but is dynamically mapped to a physical address through collaboration between the hardware and the operating system. Furthermore, a guest physical memory address refers to a logical abstract address managed internally by the guest. A physical memory page refers to the management unit of physical memory, and a base physical memory page refers to the smallest management unit of physical memory. Specifically, a system-level binary translator can emulate the guest's physical address space, which can include memory areas such as random access memory (RAM), read-only memory (ROM), and memory-mapped input / output (MMIO). Furthermore, the binary translator can simulate the guest program performing corresponding memory access operations on the host machine. This process requires deriving the guest physical address (GPA) based on the GVA, which in turn derives the host virtual address (HVA), and ultimately the host physical address (HPA). Specifically, the binary translator is used to implement address conversion from GVA to GPA and then to HVA, and the host operating system is used to implement address conversion from HVA to HPA. It should be noted that the embodiment of the present invention can be applied to the stage where the system-level binary translator implements GVA to GPA conversion.

[0039] The aforementioned page table (PT) is a client page table, which refers to a mapping table between the client's virtual memory addresses and the client's physical memory addresses. It contains a one-to-one mapping between client virtual memory pages and client physical memory pages. Specifically, to reduce the memory space occupied by the page table, a multi-level page table is often used. The page table in the embodiments of the present invention can be a multi-level page table.

[0040] The client virtual address to be accessed may be a memory address indicated by any client memory access instruction in the client program. The client virtual address to be accessed may be determined based on the actual memory access requirements of the client program, and this is not limited in this embodiment of the present invention. Step 101 may be to access a page table corresponding to the client virtual address based on a query index.

[0041] Specifically, when using a multi-level page table, the virtual memory address can be divided into multiple query indices and page offsets. Based on these multiple query indices, queries are performed sequentially through the page table hierarchy until the base address of the physical memory address corresponding to the virtual memory address is found. The final physical memory address can then be obtained based on this base address and the page offset. Using a multi-level page table can significantly reduce the memory footprint of the page table.

[0042] Among them, the above-mentioned physical memory large page refers to a larger continuous physical memory block, and its size is often much larger than the conventional basic physical memory page. For example, the basic physical memory page size is often 4KB, while the size of the large page is often 2MB or 1GB, etc. Specifically, although the multi-level page table greatly reduces the memory space occupied by the page table, it also increases the traversal time of the page table to a certain extent. In order to further speed up the page table traversal, large pages can be used to reduce the number of page table level queries. The above-mentioned large page page table entry refers to a page table entry that directly points to a large page. The large page page table entry often no longer points to the next level page table, but directly points to the physical memory large page.

[0043] On this basis, the embodiment of the present invention can access the corresponding page table based on the client virtual address to be accessed. Specifically, it can access the page tables of each level in sequence based on multiple query indexes contained in the client virtual address.

[0044] Specifically, in a multi-level page table, each level of the page table can contain multiple page table entries. The different page table entries contained in the non-last-level page table can point to the base address of the next-level page table. The page table entries contained in the last-level page table all point to the corresponding basic physical memory page, and the large page page table entry directly points to the corresponding physical memory large page. On this basis, when accessing the page table based on the client virtual address, the embodiment of the present invention can first determine the page table entry corresponding to the client virtual address in the highest-level page table according to the page table hierarchy order, and accordingly, determine whether the page table entry belongs to the large page page table entry. If it does, the target physical memory page can be directly determined based on the page table entry. If it does not, the page table entry pointed to by the page table entry in the next-level page table can be determined, and the judgment operation of the large page page table entry can be performed again.

[0045] Among them, the client physical memory huge page corresponding to the above-mentioned client virtual address refers to the huge page where the client physical memory address corresponding to the client virtual address is located. Specifically, when the current page table entry currently accessed belongs to the huge page page table entry, it indicates that the huge page where the client physical address corresponding to the client virtual address is located can be obtained through the current page table entry, and there is no need to continue accessing the next level page table. At this time, the embodiment of the present invention can directly use the client physical memory huge page corresponding to the client virtual address as the target physical memory page based on the huge page page table entry. Specifically, in the case that the current page table entry belongs to the huge page page table entry, the embodiment of the present invention can obtain the physical base address of the huge page where the corresponding client physical memory address is located based on the current page table entry, and can obtain the range of the target physical memory page based on the base address and the fixed page offset of the huge page.

[0046] Specifically, when the current page table entry does not belong to the huge page page table entry, it indicates that the physical memory page corresponding to the client virtual address cannot be directly obtained through the current page table entry, and thus the memory access attribute of the huge page cannot be obtained. At this time, the current page table entry often points to the base address of the next-level page table corresponding to the client virtual address. Therefore, based on the current page table entry, it is possible to continue to access downward in the hierarchical order of the page table, and determine the page table entry it points to as the new current page table entry based on the current page table entry. Until the huge page page table entry is found, the client physical memory huge page corresponding to the client virtual address can be determined.

[0047] Optionally, the operation of accessing the page table corresponding to the client virtual address to be accessed in step 101 may include:

[0048] S1011. Divide the client virtual address to be accessed into N levels of index fields and in-page offset fields; N is the number of levels of the client page table.

[0049] S1012: Obtain a base address of a top-level page table of the client page table based on a preset register.

[0050] S1013. Use the top-level page table as the currently accessed page table, and determine the currently accessed current page table entry from the page table entries included in the currently accessed page table based on the base address of the currently accessed page table and the index field corresponding to the currently accessed page table in the N-level index field.

[0051] S1014. After the current page table entry determined in the currently accessed page table is accessed, a base address of a new currently accessed page table is determined based on the current page table entry, and the operation of determining the currently accessed current page table entry in the page table entries contained in the currently accessed page table based on the base address of the currently accessed page table and the index field corresponding to the currently accessed page table in the N-level index field is performed again, until the current page table entry determined in the currently accessed page table is accessed, and the base address of the client physical address corresponding to the client virtual address is obtained.

[0052] The preset register is a register in the client used to store the base address of the top-level page table. The virtual address partitioning operation may be performed according to preset rules corresponding to the client processor architecture. Specifically, the client's page table structure is also generated according to the preset rules, thereby ensuring that any virtual address can be accurately queried through the page table to obtain the corresponding physical address.

[0053] For example, taking a four-level page table structure as an example, PGD (Page Global Directory) is the root node, covering the entire virtual address space (128TB). Different bit segments in the virtual address are determined as four indexes: high-order index PGD of the virtual address → mid-order index PUD → mid-low-order index PMD → low-order index PTE. Accordingly, when accessing a four-level page table based on a virtual address, the corresponding physical base address can be first obtained from the page directory table physical memory base address register (CR3 register). This can be used as the base address of the highest-level page table. Then, based on the high-order index and this base address, the page table entry corresponding to the high-order index can be obtained. Furthermore, the base address of the next-level page table can be obtained from the entry value of the current page table entry, and then the page table entry pointed to by the mid-order index can be obtained from the mid-order index and this base address. This process continues in this way until the base address of the last-level page table is obtained through the low-order index, and the final physical address is obtained through this base address and the offset of the virtual address.

[0054] In this case, the next-level page table entry pointed to by the current page table entry refers to the page table entry obtained by the base address of the next-level page table determined by the current page table entry and the index corresponding to the client virtual address in the next-level page table.

[0055] In an embodiment of the present invention, when the current page table entry does not belong to a large page table entry, the next-level page table entry pointed to by the current page table entry is determined as a new current page table entry, and the operation of determining the client physical memory large page corresponding to the client virtual address as the target physical memory page based on the current page table entry is performed again when the current page table entry currently being accessed belongs to a large page table entry. In this way, the page table structure can be traversed in hierarchical order to ensure that the client physical memory large page corresponding to the large page page table entry and meeting the preset memory access requirements can be found, and then the memory access attributes of the client physical memory large page that meets the preset memory access requirements can be stored in the preset cache table, ensuring that the space occupied by the table entries of the preset cache table is reduced while avoiding memory access exceptions caused by large pages that do not meet the preset memory access requirements.

[0056] The memory access status indicates whether the target physical memory page can be accessed normally, for example, whether it is readable or writable. Specifically, because a large page often contains multiple small pages (basic physical memory pages), the memory access permissions of different small pages may differ. Therefore, the memory access status of a large page can be determined based on the memory access permissions of the small pages it contains. Specifically, the memory access status of the target physical memory page can include the memory access permissions of each small page.

[0057] The preset memory access requirement may be that the memory access permissions of all small pages contained in the target physical memory page are consistent. The preset cache table may be pre-created and may be a Translation Lookaside Buffer (TLB), a hardware TLB, or a software TLB, which is not limited in this embodiment of the present invention. When the memory access status indicates that the target physical memory page meets the preset memory access requirement, the embodiment of the present invention may write the memory access attributes of the target physical memory page into the preset cache table. The memory access attributes include at least an address mapping relationship of the target physical memory page and the memory access permissions of the target physical memory page. The address mapping relationship refers to the mapping relationship between the target physical memory page and the client virtual memory address and the host virtual memory address. The mapping relationship between the GVA and GPA can be directly obtained from the huge page table as the first mapping relationship. The translator may pre-allocate or dynamically allocate the address space required by the GPA and generate a mapping relationship between the GPA and the HVA as the second mapping relationship. Furthermore, the address mapping relationship of the target physical memory page may be a GVA to HVA mapping relationship obtained based on the first and second mapping relationships. The above-mentioned memory access permission refers to whether the target physical memory page is accessible, and can be obtained based on the memory access permission of each small page contained in the target physical memory page.

[0058] The preset cache table can be used for subsequent memory accesses. Specifically, a client memory access request first passes through the TLB cache. If the cache hits, the HVA corresponding to the GVA can be directly obtained to complete the memory access. If the cache fails, the address mapping from GVA to HVA must be re-obtained and filled into the preset cache table. Accordingly, the preset cache table can accelerate the memory access process to a certain extent.

[0059] In summary, the embodiment of the present invention can support large pages in a system-level translator by identifying large page page table entries during page table access and determining the client physical memory large page as the target physical memory page based on the large page page table entries. When the large page page table entry is accessed, the target physical memory page can be determined directly using the address mapping relationship of the large page through the large page page table entry, thereby reducing the number of page table traversals and improving the efficiency of the translator in achieving address conversion. At the same time, by writing the memory access attributes of the target physical memory page into the preset cache table when the memory access status of the target physical memory page meets the preset memory access requirements, the number of table entries in the preset cache table can be greatly reduced. Only one table entry is required to record the memory access attributes of the large page. While accelerating memory access through the preset cache table, the space occupied by the preset cache table can be greatly reduced, thereby improving the simulation performance of the translator.

[0060] Optionally, the embodiment of the present invention may further include:

[0061] S21. For any client physical memory huge page corresponding to any huge page page table entry in the page table, obtain memory access permissions of each basic physical memory page included in the client physical memory huge page.

[0062] S22. When the memory access permissions of the basic physical memory pages in the client physical memory large page are consistent, generate a memory access status of the first state for the client physical memory large page; the first state is used to represent that the client physical memory large page meets the preset memory access requirement.

[0063] S23. Writing the memory access status of each client physical memory huge page into a preset record table.

[0064] The operation of obtaining the memory access status of the target physical memory page may specifically include:

[0065] S1031. Obtain the memory access status of the target physical memory page from the preset record table.

[0066] The basic physical memory pages contained in the huge page refer to the small memory pages contained in the huge page, which are often the smallest memory pages supported by the client. Specifically, the memory access permission of each physical memory page can be obtained based on the flag bits of each physical memory page contained in the huge page page table entry.

[0067] Furthermore, if the memory access permissions of each underlying physical memory page in a large page are consistent, it indicates that the memory access permissions of the client's physical memory large page are unified, and there will be no memory access errors caused by inconsistent memory access permissions. In this case, the embodiment of the present invention can directly generate a memory access status for the large page as the first state, which is used to indicate that the large page meets the preset memory access requirements, and write the memory access status of each large page into a preset record table. Accordingly, when obtaining the memory access status of the target physical memory page, the memory access status of the target physical memory page can be directly obtained from the preset record table.

[0068] In an embodiment of the present invention, for any client physical memory large page corresponding to any large page page table entry in the page table, the memory access permissions of each basic physical memory page contained in the client physical memory large page are obtained; when the memory access permissions of each basic physical memory page in the client physical memory large page are consistent, a memory access status is generated for the client physical memory large page as a first state; the first state is used to represent that the client physical memory large page meets the preset memory access requirement; the memory access status of each client physical memory large page is written into a preset record table; the memory access status of each large page is written into a preset record table; the memory access status of the target physical memory page is obtained from the preset record table. In this way, the memory access status of the large page can be maintained according to the memory access permissions of each basic physical memory page contained in the client physical memory large page, and the accuracy and availability of the memory access status of the large page can be guaranteed. At the same time, by generating a first state representing that the preset memory access requirements are met for each basic physical memory page of the large page when the memory access permissions of the pages are consistent, the memory access permissions of all basic physical memory pages contained in the client physical memory large page can be recorded in a preset record table through one table entry, thereby reducing the number of table entries in the preset record table to a certain extent and improving the simulation performance.

[0069] Optionally, the embodiment of the present invention may further include:

[0070] S31. When the memory access permission of any basic physical memory page in the client physical memory large page is inconsistent with the memory access permission of other basic physical memory pages, a second memory access status is generated for the client physical memory large page; the second status is used to indicate that the client physical memory large page does not meet the preset memory access requirement.

[0071] Among them, the above-mentioned other basic physical memory pages refer to basic physical memory pages in the client physical memory large page that are different from the basic physical memory page. Furthermore, when the memory access permission of any basic physical memory page in the basic physical memory pages included in the client physical memory large page is inconsistent with the memory access permission of other basic physical memory pages, it indicates that the memory access permission in the client physical memory large page is not unified. In order to avoid the memory access anomaly caused by directly writing the memory access attribute of the large page into the preset record table, a second state can be generated for the large page to indicate that the large page does not meet the preset memory access requirement.

[0072] Exemplarily, if the memory access permissions of the basic physical memory pages contained in the large page are all readable and writable, then the memory access status of the large page can also be readable and writable, and a memory access status of the first state can be generated for the large page, which is used to characterize that the memory access permissions of the basic physical memory pages contained in the large page can be recorded in a preset record table as a whole, meeting the preset memory access requirements. As another example, if there are basic physical memory pages contained in a large page whose memory access permissions of some basic physical memory pages are not writable, then the memory access permissions of the large page are inconsistent. If the memory access status of the large page is directly set to not writable, other writable basic physical memory pages in the large page may also be regarded as not writable, resulting in memory access anomalies. In order to avoid this problem, an embodiment of the present invention can generate a memory access status of the second state for the large page, which is used to characterize that the large page does not meet the preset memory access requirements.

[0073] The preset record table may be a pre-created data structure for storing the memory access status of each major page. Specifically, the preset record table may be a tree data structure or a linear data structure, and may be configured according to actual needs, which is not limited in the embodiment of the present invention.

[0074] In an embodiment of the present invention, when the memory access permissions of any underlying physical memory page in the client physical memory large page are inconsistent with the memory access permissions of other underlying physical memory pages, a second memory access status is generated for the client physical memory large page; the second state is used to indicate that the client physical memory large page does not meet the preset memory access requirements. In this way, the memory access status of client physical memory large pages with inconsistent memory access permissions can be maintained, ensuring that the memory access status of all client physical memory large pages can be found through a preset record table, thereby improving translator efficiency.

[0075] Optionally, the preset record table includes multiple entries, each entry corresponding to each basic physical memory page; the embodiment of the present invention may further include:

[0076] S41. Writing the memory access permission of each basic physical memory page into the preset record table respectively into the table entry corresponding to each basic physical memory page.

[0077] The operation of writing the access status of each client physical memory huge page into the preset record table may specifically include:

[0078] S42: Select one basic physical memory page from the basic physical memory pages included in each of the client physical memory huge pages as a target mark page.

[0079] S43. In the preset record table, the memory access status of each client physical memory huge page is written into the table entry corresponding to each target mark page.

[0080] The preset record table may include multiple entries, each of which may correspond to a different underlying physical memory page. Furthermore, embodiments of the present invention may write the memory access permissions of each underlying physical memory page into its respective entry. Accordingly, in step S21, when obtaining the memory access permissions of each underlying physical memory page contained in the client's physical memory huge page, the permissions may be directly obtained from the preset record table.

[0081] Furthermore, the above operation of selecting the target mark page can be arbitrarily selected, and of course it can also be selected according to preset rules. For example, the first basic physical memory page contained in the client physical memory large page can be selected as the target mark page, and of course the last basic physical memory page contained in the client physical memory large page can also be selected as the target mark page. The embodiment of the present invention does not limit this.

[0082] Furthermore, an embodiment of the present invention can divide the table entries corresponding to the target mark page into a first area and a second area. Accordingly, the first area can be used to store the memory access status of the client physical memory large page where the target mark page is located, and the second area can be used to store the memory access permission of the target mark page itself.

[0083] Optionally, the entries in the preset record table are arranged linearly.

[0084] Specifically, to further improve the efficiency of obtaining memory access status from a preset record table, embodiments of the present invention can employ a flat data structure as the preset record table. That is, the entries in the preset record table are arranged linearly. Thus, when obtaining the memory access status of a target physical memory page from the preset record table, the corresponding stored data can be read simply by calculating the offset address. Furthermore, the arrangement order of the entries in the preset record table can be consistent with the arrangement order of their corresponding underlying physical memory pages.

[0085] For example, Figure 2 This is a schematic diagram of the structure of a preset record table provided by an embodiment of the present invention. Figure 2As shown in the figure, the client physical page refers to the client's physical memory page, and the 4KB page is the smallest memory page (that is, the basic physical memory page). Figure 2 The large page shown contains 8 minimum memory pages. On this basis, the embodiment of the present invention can use 8 bits of data to record the memory access permissions for each 4KB page. Accordingly, the embodiment of the present invention can use the 8-bit data corresponding to the first 4KB page of the large page to store the memory access status of the large page. Specifically, for the first 4KB page of the large page, the high 4 bits of the 8-bit data corresponding to the 4KB page can be used to store the memory access status of the large page, and the low 4 bits can be used to store the memory access permissions of the 4KB page. Of course, other storage methods can also be set, and the embodiment of the present invention does not limit this.

[0086] Through the above preset record table, the memory access status of large pages can be quickly obtained, reducing the overhead of page-by-page traversal.

[0087] In the embodiment of the present invention, the entries in the preset record table are arranged linearly. Thus, when obtaining the memory access status of the target physical memory page from the preset record table, the corresponding stored data can be read by simply calculating the offset address, further improving the efficiency of obtaining the memory access status from the preset record table.

[0088] Optionally, the embodiment of the present invention may further include:

[0089] S51. When the current page table entry belongs to a last-level page table entry, determine, based on the current page table entry, a base physical memory page corresponding to the client virtual address and at least one other base physical memory page as memory pages to be processed.

[0090] Or, S52, if the memory access status indicates that the target physical memory page does not meet the preset memory access requirement, determine the basic physical memory page corresponding to the client virtual address and at least one other basic physical memory page from the basic physical memory pages contained in the target physical memory page as the memory page to be processed.

[0091] S53: Write the memory access attribute of the memory page to be processed into the preset cache table.

[0092] The aforementioned last-level page table refers to the smallest level of the page table structure, containing the smallest page table entries. For example, in a four-level page table, both levels 3 and 2 may contain large page table entries. Level 1 entries are often the smallest page table entries and can be referred to as last-level page table entries. For example, in a 48-bit address space, with a last-level page table size of 4KB and a width of 9 per page table level, the large page corresponding to a level 3 page table entry is often 1GB (i.e., 48-9-9 = 30 bits), and the large page corresponding to a level 2 page table entry is often 2MB (i.e., 48-9-9-9 = 21 bits). During the page table traversal process, embodiments of the present invention can sequentially identify and process the large pages corresponding to level 3 and level 2 page table entries. When the large page's memory access status meets preset memory access requirements, it can be directly written to the TLB cache. For last-level page table entries, multiple adjacent pages can be processed simultaneously and written to the TLB cache.

[0093] Among them, the above-mentioned other basic physical memory pages can be basic physical memory pages adjacent to the above-mentioned basic physical memory pages, and of course can also be other basic physical memory pages, which is not limited by the embodiment of the present invention. Specifically, the above-mentioned other basic physical memory pages can be basic physical memory pages adjacent to the above-mentioned basic physical memory pages, so that the GVA corresponding to the other basic physical memory pages can be directly determined by the offset, which facilitates obtaining the mapping relationship of the other basic physical memory pages.

[0094] Alternatively, when the memory access status of the target physical memory page indicates that the target physical memory page does not meet the preset memory access requirements, it indicates that the target physical memory page may have problems such as inconsistent memory access permissions. In order to avoid memory access exceptions caused by directly storing the memory access attributes of the target physical memory page, the target physical memory page can be downgraded at this time, that is, from the various basic physical memory pages contained in the target physical memory page, the basic physical memory page corresponding to the client virtual address and at least one other basic physical memory page are directly determined as the memory pages to be processed.

[0095] Specifically, if the memory access status indicates that the target physical memory page does not meet the preset memory access requirements, it indicates that the memory access permission of any basic physical memory page is inconsistent with the memory access permission of other basic physical memory pages. At this time, the following abnormal situations may occur: For example, the target physical memory page has a basic physical memory page whose memory access permission is not writable. If the memory access attribute of the target physical memory page is directly recorded as not writable in the preset cache table, other writable basic physical memory pages will also be regarded as not writable, resulting in the inability to write data normally to other basic physical memory pages, and a memory access error will occur. Alternatively, the target physical memory page has a basic physical memory page whose memory access permission is not readable. If the memory access attribute of the target physical memory page is directly recorded as not readable in the preset cache table, other readable basic physical memory pages will also be regarded as unreadable, resulting in the inability to read data normally, and a memory access abnormality will occur.

[0096] In order to avoid the above-mentioned abnormal situation, an embodiment of the present invention can downgrade the target physical memory page when the target physical memory page does not meet the preset memory access requirements, and directly determine the basic physical memory page corresponding to the client virtual address and at least one other basic physical memory page from the basic physical memory pages contained in the target physical memory page. In this way, the memory access attributes of the basic physical memory page can be directly recorded in the preset cache table, avoiding the problem of memory access abnormality caused by directly storing the memory access attributes of the target physical memory page that does not meet the memory access requirements.

[0097] In an embodiment of the present invention, when the current page table entry belongs to the last-level page table entry, the underlying physical memory page corresponding to the client virtual address and at least one other underlying physical memory page are determined based on the current page table entry as memory pages to be processed; or, if the memory access status indicates that the target physical memory page does not meet the preset memory access requirement, the underlying physical memory page corresponding to the client virtual address and at least one other underlying physical memory page are determined from the underlying physical memory pages contained in the target physical memory page as memory pages to be processed; and the memory access attributes of the memory page to be processed are written into the preset cache table. In this way, the memory access attributes of multiple underlying physical memory pages can be stored in the TLB cache through a single traversal, which can reduce the number of page table traversals and improve the simulation efficiency of the translator.

[0098] Figure 3 This is a schematic diagram of a page table traversal provided by an embodiment of the present invention, such as Figure 3As shown, when a guest-level huge page entry is identified, the address mapping relationship between GVA and GPA can be obtained from the huge page entry, and the memory access status of the guest physical memory huge page can be further obtained. At this time, if the status of the guest physical memory huge page fails (does not meet the preset memory access requirements), for example, if at least one small page in the guest physical memory huge page has a hardware-encrypted Secure Memory Encryption (SMC) area, making the small page unable to be directly read or written, the status can be reduced to a smaller page size for processing, ultimately reducing it to the minimum page size (the base physical memory page). This achieves downgraded huge page traversal.

[0099] It should be noted that in related technologies, open-source binary translators, such as the Quick Emulator (QEMU), can be used to implement binary translation technology. Binary translators typically have both user-level and system-level modes, supporting a variety of host and guest architectures. For example, for client memory accesses, QEMU uses a software-emulated Memory Management Unit (MMU) module to perform address translation. Specific implementations include emulating the guest physical address space based on memory regions (MRs), software-implemented guest page table walks, and a software-based TLB address translation cache.

[0100] However, the structure of MR is relatively complex. To simulate the client physical address GVA space, QEMU uses a tree structure based on memory regions. Each node contains information about a region, which together realize the simulation of the complete physical address space. This includes the simulation of the address space of the client's physical memory. For access to physical memory, this data structure is mainly responsible for the address conversion from GPA to HVA. At the same time, to meet the memory address conversion requirements of cross-architecture clients, QEMU implements a software traversal process for the client page table structure, and combines it with the memory region data structure to realize the memory address conversion from GVA to HVA. In order to reduce overhead, QEMU uses a software TLB cache to store the address mapping relationship from GVA to HVA for subsequent reuse.

[0101] However, the page table traversal process usually consists of two major steps. First, it is necessary to complete the address conversion from GVA to GPA by reading the client page table. Since the page table is usually a multi-level structure, multiple memory accesses are required, and multiple address conversions from GPA to HVA are required during the traversal process. Second, for a given GVA, after obtaining the corresponding GPA through page table traversal, different processing is required based on the information in the page table structure. The most common cases include MMIO and SMC. The MMIO area cannot be directly accessed, so special tags are required to avoid direct memory access. The SMC area cannot be written, so its write permission needs to be prohibited. This information will be recorded in the software TLB to implement special control of memory access. The final GPA needs to be further converted into HVA before it can be cached by the software TLB.

[0102] However, in the aforementioned related technologies, page table traversals are performed using the smallest page table size as the processing unit, which significantly increases the number of entries in the TLB cache and occupies a large amount of space. Furthermore, page table traversals often process only one page table entry at a time, resulting in a high number of page table traversals.

[0103] In an embodiment of the present invention, by identifying a large page table in a page table and determining a client physical memory large page as a target physical memory page based on the large page table entry, large pages can be supported in a translator, reducing the number of page table traversals and improving the efficiency of the translator in achieving address conversion. At the same time, by writing the memory access attributes of the target physical memory page into a preset cache table when the memory access status of the target physical memory page meets the preset memory access requirements, the number of entries in the preset cache table can be greatly reduced. Only one entry is required to record the memory access attributes of the large page, greatly reducing the space occupied by the preset cache table and improving performance.

[0104] At the same time, in an embodiment of the present invention, when the current page table entry belongs to the last-level page table entry, the basic physical memory page corresponding to the client virtual address and at least one other basic physical memory page are determined based on the current page table entry as the memory page to be processed; or, if the memory access status indicates that the target physical memory page does not meet the preset memory access requirement, the basic physical memory page corresponding to the client virtual address and at least one other basic physical memory page are determined from the various basic physical memory pages contained in the target physical memory page as the memory page to be processed; the memory access attributes of the memory page to be processed are written into the preset cache table. In this way, the memory access attributes of multiple small pages can be stored in the TLB cache through one traversal, which can reduce the number of page table traversals and improve the simulation efficiency of the translator.

[0105] It should be noted that for the sake of simplicity, the method embodiments are described as a series of actions. However, those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0106] Figure 4 FIG is a schematic diagram of the structure of a memory management device according to an embodiment of the present invention, which can be applied to a translator, such as Figure 4 As shown, the device 20 may include:

[0107] An access module 201 is configured to access a page table corresponding to a client virtual address to be accessed based on the client virtual address to be accessed;

[0108] A first determining module 202 is configured to, in a process of accessing the page table, determine, based on the current page table entry, a client physical memory huge page corresponding to the client virtual address as a target physical memory page when the current page table entry currently accessed is a huge page page table entry;

[0109] Execution module 203 is used to determine the next-level page table entry pointed to by the current page table entry as the new current page table entry when the current page table entry does not belong to the large page page table entry, and to re-execute the operation of determining the client physical memory large page corresponding to the client virtual address as the target physical memory page based on the current page table entry when the current page table entry currently accessed belongs to the large page page table entry.

[0110] A first acquisition module 204 is configured to acquire a memory access status of the target physical memory page;

[0111] The first writing module 205 is used to write the memory access attributes of the target physical memory page into the preset cache table if the memory access status indicates that the target physical memory page meets the preset memory access requirements; the memory access attributes include at least the address mapping relationship of the target physical memory page and the memory access permission of the target physical memory page; the address mapping relationship is the mapping relationship between the target physical memory page and the client virtual address and the corresponding host virtual memory address.

[0112] Optionally, the device further comprises:

[0113] A second acquisition module is configured to acquire, for any client physical memory huge page corresponding to any huge page page table entry in the page table, memory access permissions of each basic physical memory page contained in the client physical memory huge page;

[0114] A first generating module is configured to generate a memory access state as a first state for the client physical memory huge page when the memory access permissions of the basic physical memory pages in the client physical memory huge page are consistent; the first state is used to indicate that the client physical memory huge page meets the preset memory access requirement;

[0115] A second writing module is used to write the memory access status of each client physical memory huge page into a preset record table;

[0116] The first acquisition module is specifically configured to acquire the memory access status of the target physical memory page from the preset record table.

[0117] Optionally, the device further comprises:

[0118] The second generation module is used to generate a second memory access state for the client physical memory large page when the memory access permission of any basic physical memory page in the client physical memory large page is inconsistent with the memory access permission of other basic physical memory pages; the second state is used to represent that the client physical memory large page does not meet the preset memory access requirement.

[0119] Optionally, the device further comprises:

[0120] a second determining module, configured to determine, when the current page table entry belongs to a last-level page table entry, a base physical memory page and at least one other base physical memory page corresponding to the client virtual address based on the current page table entry as memory pages to be processed;

[0121] A third determining module is configured to determine, from the respective basic physical memory pages included in the target physical memory page, the basic physical memory page corresponding to the client virtual address and at least one other basic physical memory page as the memory page to be processed if the memory access status indicates that the target physical memory page does not meet the preset memory access requirement;

[0122] The third writing module is used to write the memory access attribute of the memory page to be processed into the preset cache table.

[0123] Optionally, the preset record table includes a plurality of entries, each entry corresponding to each basic physical memory page; the device further includes:

[0124] A fourth writing module is configured to write the memory access permission of each of the basic physical memory pages into the preset record table, respectively, into the table entry corresponding to each of the basic physical memory pages;

[0125] The second writing module includes:

[0126] A selection submodule, configured to select a basic physical memory page from the basic physical memory pages included in each of the client physical memory huge pages as a target marking page;

[0127] The fifth writing submodule is used to write the memory access status of each client physical memory huge page into the table entry corresponding to each target mark page in the preset record table.

[0128] Optionally, the entries in the preset record table are arranged linearly.

[0129] Optionally, the access module 201 includes:

[0130] A division submodule, configured to divide the client virtual address to be accessed into N-level index fields and page offset fields, wherein N is the number of levels of the client page table;

[0131] A third acquisition submodule, configured to acquire a base address of a top-level page table of the client page table based on a preset register;

[0132] a fourth determining submodule, configured to use the top-level page table as the currently accessed page table, and determine a currently accessed current page table entry from page table entries included in the currently accessed page table based on a base address of the currently accessed page table and an index field in the N-level index field corresponding to the currently accessed page table;

[0133] The fifth determination submodule is used to determine the base address of a new currently accessed page table based on the current page table entry after the current page table entry determined in the currently accessed page table is accessed, and to perform again the operation of determining the currently accessed current page table entry in the page table entries contained in the currently accessed page table based on the base address of the currently accessed page table and the index field corresponding to the currently accessed page table in the N-level index field after the current page table entry determined in the currently accessed page table is accessed, until the current page table entry determined in the currently accessed page table is accessed to obtain the base address of the client physical address corresponding to the client virtual address.

[0134] In summary, the memory management device provided by the embodiment of the present invention can support large pages in the system-level translator by identifying large page page table entries in the page table access process and determining the client physical memory large page as the target physical memory page based on the large page page table entries. When the large page page table entry is accessed, the target physical memory page can be determined directly using the address mapping relationship of the large page through the large page page table entry, thereby reducing the number of page table traversals and improving the efficiency of the translator in achieving address conversion. At the same time, by writing the memory access attributes of the target physical memory page into the preset cache table when the memory access status of the target physical memory page meets the preset memory access requirements, the number of table entries in the preset cache table can be greatly reduced. Only one table entry is required to record the memory access attributes of the large page. While accelerating memory access through the preset cache table, the space occupied by the preset cache table can be greatly reduced, thereby improving the simulation performance of the translator.

[0135] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0136] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0137] Regarding the request processing device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0138] An embodiment of the present invention further provides an electronic device, comprising: a processor and a memory for storing processor-executable instructions, wherein the processor is configured to execute the above binary translation method.

[0139] Reference Figure 5 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 5 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the memory management method of the aforementioned embodiment.

[0140] It should be noted that the electronic devices in the embodiments of the present application include mobile electronic devices and non-mobile electronic devices.

[0141] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0142] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 3 The fact that only one line is used does not mean that there is only one bus or one type of bus.

[0143] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable ReadOnly Memory), a CD-ROM (Compact Disc Read Only), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0144] The embodiment of the present invention further provides a non-transitory computer-readable storage medium, which, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), enables the processor to execute Figure 1 The memory management method shown.

[0145] The present invention also provides a computer program product comprising instructions, which, when executed on a computer, causes the computer to execute Figure 1 The memory management method shown.

[0146] An embodiment of the present application also provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned binary translation method embodiment and achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0147] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0148] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0149] Those skilled in the art will appreciate that embodiments of the present invention can be provided as methods, apparatuses, or computer program products. Therefore, embodiments of the present invention can be implemented in whole or in part via software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part as a computer program product. The computer program product comprises one or more computer instructions. When loaded and executed on a computer, the computer program instructions fully or partially perform the processes or functions described in accordance with the embodiments of the present invention. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible by a computer or a data storage device, such as a server or data center, that integrates one or more available media. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0150] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0151] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0152] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0153] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0154] Each embodiment in this specification is described in a related manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiment is generally similar to the method embodiment, so the description is relatively simple. For related parts, refer to the description of the method embodiment.

[0155] It should be noted that the various data-related processes in the embodiments of the present application are all carried out in compliance with the corresponding data protection laws and policies of the country where they are located, and with the authorization given by the owner of the corresponding device.

[0156] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0157] The above is a detailed introduction to a memory management method, device, electronic device and readable storage medium provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A memory management method, characterized in that: The method is applied to a system-level translator, and the method includes: Accessing a page table corresponding to the client virtual address based on the client virtual address to be accessed; In a process of accessing the page table, if a current page table entry currently accessed is a huge page page table entry, determining, based on the current page table entry, a client physical memory huge page corresponding to the client virtual address as a target physical memory page; If the current page table entry does not belong to a huge page table entry, determine the next-level page table entry pointed to by the current page table entry as a new current page table entry, and again perform the operation of determining, based on the current page table entry, as the target physical memory page the client physical memory huge page corresponding to the client virtual address when the current page table entry currently being accessed belongs to a huge page page table entry; Obtaining a memory access status of the target physical memory page; If the memory access status indicates that the target physical memory page meets the preset memory access requirements, the memory access attributes of the target physical memory page are written into the preset cache table; the memory access attributes include at least the address mapping relationship of the target physical memory page and the memory access permissions of the target physical memory page; the address mapping relationship is the mapping relationship between the target physical memory page and the client virtual address and the corresponding host virtual address.

2. The method according to claim 1, characterized in that The method further comprises: For any client physical memory huge page corresponding to any huge page page table entry in the page table, obtaining memory access permissions of each basic physical memory page included in the client physical memory huge page; When the memory access permissions of the basic physical memory pages in the client physical memory huge page are consistent, generating a memory access state for the client physical memory huge page as a first state; the first state is used to indicate that the client physical memory huge page meets the preset memory access requirement; Writing the access status of each client's physical memory huge page into a preset record table; The acquiring the memory access status of the target physical memory page includes: acquiring the memory access status of the target physical memory page from the preset record table.

3. The method according to claim 2, characterized in that The method further comprises: When the memory access permission of any basic physical memory page in the client physical memory large page is inconsistent with the memory access permission of other basic physical memory pages, a second memory access status is generated for the client physical memory large page; the second state is used to represent that the client physical memory large page does not meet the preset memory access requirement.

4. The method according to claim 1, wherein The method further comprises: In a case where the current page table entry belongs to a last-level page table entry, determining, based on the current page table entry, a base physical memory page corresponding to the client virtual address and at least one other base physical memory page as memory pages to be processed; or, if the memory access status indicates that the target physical memory page does not meet the preset memory access requirement, determining, from each basic physical memory page included in the target physical memory page, a basic physical memory page corresponding to the client virtual address and at least one other basic physical memory page as memory pages to be processed; The memory access attribute of the memory page to be processed is written into the preset cache table.

5. The method according to claim 2, characterized in that The preset record table includes a plurality of entries, each entry corresponding to each basic physical memory page; the method further includes: In the preset record table, the memory access permission of each of the basic physical memory pages is written into the table entry corresponding to each of the basic physical memory pages; The step of writing the access status of each client physical memory huge page into a preset record table includes: Selecting one basic physical memory page from the basic physical memory pages included in each of the client physical memory huge pages as a target marking page; In the preset record table, the memory access status of each client physical memory huge page is written into the table entry corresponding to each target mark page.

6. The method according to claim 5, characterized in that The entries in the preset record table are arranged linearly.

7. The method according to any one of claims 1 to 6, characterized in that The step of accessing a page table corresponding to a client virtual address based on the client virtual address to be accessed includes: Divide the client virtual address to be accessed into N-level index fields and page offset fields, where N is the number of levels in the client page table; Obtaining a base address of a top-level page table of the client page table based on a preset register; Taking the top-level page table as the currently accessed page table, and determining a currently accessed current page table entry from the page table entries included in the currently accessed page table based on a base address of the currently accessed page table and an index field corresponding to the currently accessed page table in the N-level index field; After the current page table entry determined in the currently accessed page table is accessed, a base address of a new currently accessed page table is determined based on the current page table entry, and the operation of determining the currently accessed current page table entry in the page table entries contained in the currently accessed page table based on the base address of the currently accessed page table and the index field corresponding to the currently accessed page table in the N-level index field is performed again, until the current page table entry determined in the currently accessed page table is accessed, and the base address of the client physical address corresponding to the client virtual address is obtained.

8. A memory management device, characterized in that: The device is applied to a system-level translator, and includes: An access module, configured to access a page table corresponding to a client virtual address based on the client virtual address to be accessed; A first determining module is configured to, in a process of accessing the page table, determine, based on the current page table entry, a client physical memory huge page corresponding to the client virtual address as a target physical memory page when the current page table entry currently accessed is a huge page page table entry; an execution module, configured to, if the current page table entry does not belong to a huge page table entry, determine the next-level page table entry pointed to by the current page table entry as a new current page table entry, and again perform the operation of determining, if the current page table entry currently being accessed belongs to a huge page page table entry, the client physical memory huge page corresponding to the client virtual address based on the current page table entry as the target physical memory page; A first acquisition module, configured to acquire a memory access status of the target physical memory page; The first writing module is used to write the memory access attributes of the target physical memory page into a preset cache table if the memory access status indicates that the target physical memory page meets the preset memory access requirements; the memory access attributes include at least the address mapping relationship of the target physical memory page and the memory access permission of the target physical memory page; the address mapping relationship is the mapping relationship between the target physical memory page and the client virtual address and the corresponding host virtual address.

9. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory for storing computer programs; A processor, configured to implement the method according to any one of claims 1 to 7 when executing a program stored in a memory.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

11. A computer program, characterized in that When the computer program is executed by a computer, the method according to any one of claims 1 to 7 is implemented.

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