Low-delay tight coupling data communication method for custom function module

Abstract

The invention discloses a low-delay tight-coupling data communication method for a custom function module, and relates to the technical field of processors, in a communication architecture adopted by the method, data communication is carried out between an access memory execution unit LSU and the custom function module by using a special point-to-point low-delay communication interface, and the low-delay tight-coupling data communication method for the custom function module is realized by using the special point-to-point low-delay communication interface. According to the method, interface tight coupling between the custom function module and a processor module core is achieved, and the processor module can achieve data communication with the custom function module through an LSU and a special bus interface by using a memory access instruction. According to the method, the independence of function realization of the user-defined function module is reserved, the realization is flexible and simple, a processor module is slightly changed, the performance is greatly improved, an optimized data path is provided, the low-delay real-time requirement is ensured, and various scenes with high requirements on the performance and delay are met.

Description

Technical Field

[0001] The present application relates to the field of processor technology, and in particular to a low-latency tightly coupled data communication method for a custom functional module. Background Art

[0002] A CFPU (Custom Function Processing Unit) is a specially designed hardware processing unit used to accelerate specific computing tasks or functions. Unlike general-purpose processors (such as CPUs or GPUs), CFPUs focus on performing specific, highly customized operations, often with significant advantages in performance, power consumption, or latency. CFPUs are typically used in scenarios where efficient processing of specific tasks is required. High-speed, low-latency communication between the CFPU and the CPU core enables better performance in scenarios such as artificial intelligence (AI), machine learning (ML), signal processing, encryption and decryption, and image processing.

[0003] There are currently two main ways to implement CFPU:

[0004] (1) Embed it as an execution unit in the CPU micro-architecture pipeline. This implementation method is mainly used for CFPUs with clear functions and high usage frequency, such as ALU (Arithmetic and Logic Unit), MAC (Multiply-Accumulate Unit), Vector FU (Vector Functional Unit), and Gemmini DNN accelerators. Based on modern classic superscalar CPU micro-architecture, such as Figure 1 The CFPU-1 in the

[15] adopts this embedded structure. This embedded method has a great impact on the CPU, affecting the CPU from instruction decoding to execution write-back. In particular, for execution units with complex functions and uncertain execution cycles, it has a great impact on the CPU pipeline and requires custom instructions, compilation tools and software libraries to support their use. This results in a large workload and cost for this implementation method, poor architectural flexibility, complex implementation, and a long design and verification cycle, requiring the support of custom instructions and compilation tool chains.

[0005] (2) Treat it as an independent functional module and use the system interconnect bus (such as AXI bus) to communicate with the CPU core through reading and writing shared memory to achieve loosely coupled interconnection, based on modern classic superscalar CPU microarchitecture, such as Figure 1The CFPU-2 in the

[15] employs this embedded structure, a common approach used in current system-level IP units. Loose coupling is a common approach, but the inclusion of a system bus between the CFPU and the CPU, coupled with multiple master and slave ports on the system bus, introduces significant data latency. The entire data movement path is long, requiring both intra-core and extra-core buses, as well as arbitration, resulting in significant time and latency. For performance-critical applications, this implementation introduces significant latency, and the inflexible data path becomes a performance bottleneck, making optimization difficult and improvement limited, limiting real-time performance and flexibility. Summary of the Invention

[0006] In response to the above-mentioned problems and technical requirements, this application proposes a low-latency tightly coupled data communication method for custom function modules. The technical solution of this application is as follows:

[0007] A low-latency tightly coupled data communication method for a custom function module, wherein the custom function module and a memory access execution unit (LSU) in a processor module are interconnected using a point-to-point low-latency dedicated bus interface. The low-latency tightly coupled data communication method includes:

[0008] During the execution of the processor module instruction pipeline, in the data acquisition phase of the memory access execution unit LSU, the data reading process of the processor module initiates a point-to-point Non-Cacheable read and write request to the custom function module through the point-to-point low-latency dedicated bus interface using the Load instruction based on the custom function module address space calculated in the address generation phase; after receiving the data returned by the custom function module, the memory access execution unit LSU continues to execute subsequent pipeline steps to complete the data reading process for the custom function module.

[0009] A further technical solution is that the low-latency tightly coupled data communication method further includes:

[0010] The processor module pre-configures the custom function module address space and configures the physical memory attribute PMA of the custom function module address space to a non-cacheable non-high cache attribute, and uses a Store instruction to configure the control status register CSR of the custom function module by writing the memory register of the internal space of the custom function module.

[0011] Its further technical solution is that the low-latency tightly coupled data communication method is implemented based on a modern reduced instruction set architecture.

[0012] A further technical solution is that the data reading process uses the standard Load instruction of the modern reduced instruction set architecture to read data from the custom function module and reads back a general register data bit width each time.

[0013] A further technical solution is that the data reading process uses a custom Load instruction of a modern reduced instruction set architecture to read data from a custom function module, and multiple register data are read back each time to implement multi-data prefetching.

[0014] Its further technical solution is that after receiving a point-to-point Non-Cacheable read or write request, the custom function module returns the data temporarily stored in the data storage RAM to the processor module. The data temporarily stored in the data storage RAM comes from the internal operation logic of the custom function module or is obtained from the external data source of the custom function module through the data interface.

[0015] Its further technical solution is that the data returned by the custom function module is temporarily stored in the read buffer of the memory access execution unit LSU and skips the cache to enter the subsequent pipeline steps, and the data to be written into the custom function module by the processor module is temporarily stored in the write buffer of the memory access execution unit LSU and skips the cache to write into the custom function module.

[0016] A further technical solution is that the memory access execution unit LSU and multiple custom function modules are interconnected using point-to-point low-latency dedicated bus interfaces.

[0017] A further technical solution is that the custom function module is a single circuit module, or a system-level integrated module integrating multiple circuit modules.

[0018] Its further technical solution is that the custom function module supports the storage and computing integrated cache type.

[0019] A further technical solution is that the data reading process remains in a dormant state when it does not receive a data reading notification from the custom function module, and is awakened and starts execution after receiving a data reading notification from the custom function module.

[0020] The beneficial technical effects of this application are:

[0021] The present application discloses a low-latency tightly coupled data communication method for a custom function module. The method proposes that the custom function module can be moved inward to the processor module core and the memory access execution unit to achieve tight interface coupling through a point-to-point low-latency dedicated bus interface. The processor module can achieve data communication with the custom function module through the LSU and the dedicated bus interface using only memory access instructions. While reducing the latency of the processor module accessing the custom function module data, the method retains the independence of the function implementation of the custom function module. Compared with traditional embedded methods and loosely coupled methods, the implementation is flexible and simple, with few changes to the processor module, low cost, no impact on the CPU pipeline, no need for instruction-level scheduling, no maintenance of cache consistency, and simple implementation. The method can be implemented by only modifying some interfaces of the hardware microarchitecture, with small changes and limited impact. It is relatively easy to implement and does not require modification of the software tool chain, but it significantly improves performance and can give full play to the role of the CFPU, providing an optimized data path, ensuring low-latency real-time requirements, and meeting various scenarios with high performance and latency requirements.

[0022] This method, based on a modern RISC (Reduced Instruction Set Architecture), provides a third possibility for high-speed, low-latency communication between custom function modules and processor modules. Thanks to the characteristics of a modern RISC, this method enables modularization and customization of instructions, enabling multiple data prefetches by adding custom Load instructions. This requires only adding the corresponding custom Load instruction decoder to the ID decoding module. Backend execution only requires optimization changes to the data buffer at the interface, further improving data movement efficiency and maximizing real-time performance.

[0023] This method can also increase the interconnection network according to needs and performance requirements to expand the number of supported custom functional modules, thereby achieving scalability and flexibility. In addition, this method is compatible with traditional architectures to achieve more flexible functional expansion. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a communication architecture diagram of the CFPU and CPU core using the existing embedded architecture and loosely coupled architecture.

[0025] Figure 2 This is a communication architecture diagram used by the custom function module and processor module in this application.

[0026] Figure 3 It is a flowchart of a low-latency tightly coupled data communication method according to an embodiment of the present application. DETAILED DESCRIPTION

[0027] The specific implementation of this application will be further described below with reference to the accompanying drawings.

[0028] This application discloses a low-latency tightly coupled data communication method for a custom function module. The data communication architecture adopted by the low-latency tightly coupled data communication method is as follows: Figure 2 shown. Figure 2 The subsequent introduction of this embodiment is illustrated using this as an example. Unlike the traditional loosely coupled architecture, the architecture of the present application moves the integration location of the custom function module from the traditional external system bus interface to the processor module. However, unlike the traditional embedded structure that embeds the custom function module as an execution unit into the pipeline, the custom function module moved into the processor module and the memory access execution unit (Load & Store Unit, LSU) in the processor module are interconnected using a point-to-point low-latency dedicated bus interface (represented by the IF interface in the figure), thereby achieving tight coupling of the interface between the custom function module and the memory access execution unit LSU in the processor module.

[0029] based on Figure 2 The data communication architecture shown in FIG. 1 , a low-latency tightly coupled data communication method provided by an embodiment includes the following steps, please refer to Figure 3 The flowchart shown:

[0030] First, the processor module must be configured, which includes two parts: (1) The processor module pre-configures the custom function module address space and configures the physical memory attributes (PMA) of the custom function module address space to non-cacheable, thereby avoiding data consistency maintenance issues. (2) Use the Store instruction to write to the memory register in the custom function module's internal space to configure the control status register (CSR) of the custom function module.

[0031] After completing the above processor module configuration, you can enable the custom function module and use the Load instruction to read data from the custom function module using the data reading process of the processor module. Specifically:

[0032] During the data read process, as the processor module's instruction pipeline executes, the LSU (Memory Access Execution Unit) initiates a point-to-point, non-cacheable read or write request to the custom function module using the Load instruction via a dedicated, low-latency bus interface, based on the custom function module's address space calculated during the address generation phase (AG phase). After receiving the data returned by the custom function module, the LSU continues executing subsequent pipeline steps, completing the data read process.

[0033] After receiving a point-to-point non-cacheable read or write request, the custom function module returns the data temporarily stored in the data storage RAM to the processor module. The data temporarily stored in the data storage RAM comes from the custom function module's internal computing logic or is obtained from an external data source via a data interface. The custom function module's internal computing logic includes at least one of FPGA programmable logic, in-memory computing logic, or near-memory computing logic. The custom function module's external data source includes various sensors or external storage.

[0034] Figure 2 Taking the processor module adopting a typical CPU micro-architecture pipeline as an example, this method has no impact on the instruction fetch (IF), decoding (ID) and instruction issuance (IS) stages when only standard instructions are used. Only Load and Store instructions need to be used, and the impact only involves the internal micro-architecture implementation of the memory access execution unit LSU. Figure 2 Taking the LSU's internal microarchitecture, which uses a typical four-stage pipeline, as an example, the LSU sequentially includes the address generation stage (AG), data acquisition stage (DC), data alignment stage (DA), and data writeback stage (WB). After receiving data returned by the custom function module, the LSU continues with the data alignment stage (DA) and data writeback stage (WB), updating registers. The program then continues executing, and the data read process enters the next custom function module data return phase, waiting.

[0035] Please refer to Figure 2The point-to-point low-latency dedicated bus interface added to the memory access execution unit LSU is connected to the read buffer (RdBuffer) and the write buffer (WrBuffer). The data returned by the custom function module is temporarily stored in the read buffer of the memory access execution unit LSU and skips the cache to enter the subsequent pipeline steps. The data to be written to the custom function module by the processor module is temporarily stored in the write buffer of the memory access execution unit LSU and skips the cache to write to the custom function module. In other words, the memory access execution unit LSU does not need to pass through the cache to read and write data to the custom function module. In modern CPU hardware architecture, in order to solve the gap between the fast CPU processing speed and the slow memory data access speed, a hierarchical cache is often added to fill the gap. Therefore, if the cache is used between multiple CPU cores or multi-level caches, the same memory address will appear, and multiple data backups will appear in the cache. Moreover, since the CPU uses a write-back strategy, data inconsistency between multiple backups may occur before data synchronization is completed. Therefore, this application does not use cache to ensure that data is selected from a unique source, avoiding the problem of data inconsistency caused by the existence of multiple backups in the cache.

[0036] In order to facilitate the modularization and customization of instructions, the low-latency tightly coupled data communication method is implemented based on a modern reduced instruction set architecture, such as a RISC-V architecture. When the data reading process uses the Load instruction to read data from the custom function module, one method is to use the standard Load instruction of the modern reduced instruction set architecture to read data from the custom function module, and read back a general register data bit width each time, such as RV64I can read back 64 bits of data at a time. In order to further improve performance, in another embodiment, the data reading process uses the custom Load instruction of the modern reduced instruction set architecture to read data from the custom function module, and reads back multiple register data each time to implement multi-data prefetching, thereby improving bus utilization. For example, in one instance, a custom Load instruction is implemented using a RISC-V instruction set I-type custom instruction, then the funct3 field in the custom Load instruction records the number of prefetched register data, the opcode field is set to 0001011, and the custom type is selected.

[0037] In addition, to reduce power consumption, the data reading process remains in a dormant state when it does not receive a data reading notification from the custom function module, and is awakened and begins executing the above method after receiving a data reading notification from the custom function module. The custom function module sends a data reading notification to the processor module through an interrupt or other means.

[0038] This method can expand the number of supported custom function modules. The memory access execution unit LSU and multiple custom function modules are interconnected using point-to-point low-latency dedicated bus interfaces, thereby forming an interconnection network between the memory access execution unit LSU and multiple custom function modules, which can have good scalability and flexibility according to needs and performance requirements.

[0039] In one embodiment, the custom function module is a single circuit module. For example, the custom function module is a common custom function processing unit (CFPU).

[0040] In another embodiment, the above-mentioned custom function module is a system-level integrated module that integrates multiple circuit modules. The number, type, and integration method of the circuit modules integrated within the custom function module can be flexibly adjusted. The various forms of custom function modules formed can use the method provided by this application to achieve tight interface coupling with the memory access execution unit LSU of the processor module, which has strong flexibility and universality. In an embodiment in which the custom function module adopts a system-level integrated module structure, the above-mentioned custom function module is a processor with an embedded CFPU, that is, in a multi-core scenario, the CFPU adopts a traditional embedded structure to be embedded in the pipeline of the processor and constitutes a custom function module with the processor, that is, the communication architecture provided by this application is compatible with the traditional embedded architecture.

[0041] Because the method provided in this application achieves a tight interface coupling between the custom function module and the memory access execution unit (LSU) of the processor module, the custom function module can provide data processing results for the processor module to schedule and make decisions. In a typical application, whether a single circuit module or a multi-circuit module integration is used, the custom function module is a custom function module that supports a cache-type storage and computing integration. This type of custom function module demonstrates high potential for tightly coupled, low-latency communication with the processor module.

[0042] In addition, regardless of whether the custom function module adopts the structure of a single circuit module or a system-level integrated module, after the custom function module adopts the method provided in this application to achieve tight interface coupling with the memory access execution unit LSU of the processor module, a variety of communication architectures can be formed between the custom function module and the processor module, including master-slave communication architecture and peer-to-peer communication architecture.

[0043] Compared with the differences in the interconnection and integration positions between the processor module and the custom function module implemented in the embedded and loosely coupled ways, this method proposes a third way: tight coupling of the interface between the custom function module and the processor module core is achieved, and data communication is carried out between the memory access execution unit LSU and the custom function module using a dedicated point-to-point low-latency communication interface, which can greatly reduce data access latency while maintaining the flexibility and independence of the custom function module, without affecting the CPU pipeline, requiring no instruction-level scheduling, and maintaining cache consistency, making it simple to implement. A simple reference comparison is given here: taking the custom function module as CFPU as an example, the data path of the traditional loosely coupled method needs to include CFPU writing to DDR, notifying the CPU to fetch data, and the CPU reading DDR to retrieve data. However, in the method provided in this application, the CFPU result does not need to be written back to DDR, and the CPU can directly read back the result from the CFPU's data storage RAM through a point-to-point low-latency dedicated bus interface. The flexibility of the CFPU implementation can be fully utilized to select the appropriate data path. Traditional embedded methods require instruction support, such as the Gemmini DNN accelerator, which requires several instructions with different functions to complete scheduling. For memory-type instructions, cache consistency needs to be maintained on the Last Level Cache, which is relatively complex to implement. The method of this application only requires modifying some interfaces of the hardware microarchitecture. The changes are small, the impact range is limited, and it is relatively easy to implement without modifying the software tool chain.

[0044] The above description is only a preferred embodiment of the present application, and the present application is not limited to the above embodiments. It is understood that other improvements and variations directly derived or imagined by those skilled in the art without departing from the spirit and concept of the present application should be considered to be included in the scope of protection of the present application.

Claims

1. A low-latency tightly coupled data communication method for a custom function module, characterized in that: The custom function module and the memory access execution unit LSU in the processor module are interconnected using a point-to-point low-latency dedicated bus interface. The low-latency tightly coupled data communication method includes: During the execution of the processor module instruction pipeline, in the data acquisition phase of the memory access execution unit LSU, the data reading process of the processor module initiates a point-to-point Non-Cacheable read and write request to the custom function module through the point-to-point low-latency dedicated bus interface using the Load instruction based on the custom function module address space calculated in the address generation phase; after receiving the data returned by the custom function module, the memory access execution unit LSU continues to execute subsequent pipeline steps to complete the data reading process for the custom function module.

2. The low-latency tightly coupled data communication method according to claim 1, wherein: The low-latency tightly coupled data communication method further includes: The processor module pre-configures the custom function module address space and configures the physical memory attribute PMA of the custom function module address space to a non-cacheable non-high cache attribute, and uses a Store instruction to configure the control status register CSR of the custom function module by writing the memory register of the internal space of the custom function module.

3. The low-latency tightly coupled data communication method according to claim 1, wherein: The low-latency tightly coupled data communication method is implemented based on a modern reduced instruction set architecture. The data reading process uses the standard Load instruction of the modern reduced instruction set architecture to read data from the custom function module and reads back a general register data bit width each time.

4. The low-latency tightly coupled data communication method according to claim 3, wherein: The data reading process uses the custom Load instruction of the modern reduced instruction set architecture to read data from the custom function module, and realizes multi-data prefetching by reading back multiple register data each time.

5. The low-latency tightly coupled data communication method according to claim 1, wherein: After receiving a point-to-point Non-Cacheable read or write request, the custom function module returns the data temporarily stored in the data storage RAM to the processor module. The data temporarily stored in the data storage RAM comes from the internal operation logic of the custom function module or is obtained from the external data source of the custom function module through the data interface.

6. The low-latency tightly coupled data communication method according to claim 2, wherein: The data returned by the custom function module is temporarily stored in the read buffer of the memory access execution unit LSU and skips the cache to enter the subsequent pipeline steps. The data to be written to the custom function module by the processor module is temporarily stored in the write buffer of the memory access execution unit LSU and skips the cache to write to the custom function module.

7. The low-latency tightly coupled data communication method according to claim 1, wherein: The memory access execution unit LSU and multiple custom function modules are interconnected using point-to-point low-latency dedicated bus interfaces.

8. The low-latency tightly coupled data communication method according to claim 1, wherein: The custom function module is a single circuit module, or a system-level integrated module integrating multiple circuit modules.

9. The low-latency tightly coupled data communication method according to claim 1, wherein: Custom function modules support storage and computing integrated cache type.

10. The low-latency tightly coupled data communication method according to claim 1, wherein: The data reading process remains in a dormant state when no data reading notification from the custom function module is received, and is awakened and starts execution after receiving the data reading notification from the custom function module.

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