Data strobe signal processing circuit, controller and data reading system
The preamble of the data strobe signal is filtered through the combination processing circuit of the logic unit and the delay unit, which solves the problems of long initialization time and large hardware overhead in the prior art, and realizes efficient data reading and low overhead data transmission.
Patent Information
- Application Number
- CN202510534631.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-25
- Publication Date
- 2025-08-08
AI Technical Summary
In the prior art, the effective segment of the data strobe signal is selected through training methods, which has problems such as long initialization time, reduced data transmission bandwidth and large hardware overhead, while the timer or counter method has too large hardware overhead.
The processing circuit of the logic unit, the selection unit and the cascade delay unit is adopted to filter the leading segment of the data strobe signal through delay processing and logic operations, and select the valid segment.
It reduces the initialization time, improves the transmission bandwidth and performance of the data reading system, reduces hardware overhead, and improves the competitiveness of the processing circuit.
Smart Images
Figure CN120448304A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of integrated circuit design, and in particular to a data strobe signal processing circuit, a controller, and a data reading system. Background Art
[0002] Central processing units (CPUs), graphics processing units (GPUs), or communication modems (modems) typically use double-bit rate memory (DDR) and its controller to store and read data. The data read process begins with the controller sending a command and address (CA). Upon receiving the command, the DDR returns the data (DQ) at the corresponding address and simultaneously sends a data strobe signal (DQS) to ensure the controller correctly receives, selects, and reads the data. The effective portion of the data strobe signal is a clock signal.
[0003] As double-rate memory speeds increase and communication channel insertion loss increases, intersymbol interference (ISI) can affect the quality of the first or even the first few clock edges of the data strobe signal, hindering correct data reading. The Joint Solid State Technology Association (JEDEC) double-rate memory protocols (JESD79-x and JESD209-x) specify the use of a preamble in the data strobe signal to mitigate ISI and improve its quality.
[0004] The leading segment is composed of a fixed level or one or more logic level flips, and the leading segment cannot be used for data selection. In practical applications, it is necessary to filter out the leading segment of the data selection signal and retain only the valid segment to correctly read the data.
[0005] Traditional methods for filtering preambles and generating valid data selection signals typically use training to select valid segments. This training approach requires a certain amount of initialization time when the data reading system is initially operating. Furthermore, the training effect deteriorates with changes in voltage and temperature, necessitating periodic training to mitigate the effects of voltage and temperature variations. This reduces the data transmission bandwidth of the data reading system. Traditional methods also employ hardware methods such as timers or counters to mitigate preambles. This approach is relatively accurate, but the timing or counting circuits introduced incur a certain amount of hardware overhead. Summary of the Invention
[0006] The technical problem to be solved by the present disclosure is to overcome the defects of the prior art in which a training method is used to select the valid segment of the data selection signal, which has the disadvantages of occupying the initialization time and reducing the data transmission bandwidth, and the hardware method of using a timer or counter to avoid the leading segment of the data selection signal, which has the disadvantages of large hardware overhead, and to provide a data selection signal processing circuit, controller and data reading system.
[0007] The present disclosure solves the above technical problems through the following technical solutions:
[0008] The present disclosure provides a data strobe signal processing circuit, which is applied to a controller and includes a logic unit, a selection unit, and a plurality of cascaded delay units;
[0009] Each of the delay units is electrically connected to the selection unit, and the selection unit is electrically connected to the logic unit;
[0010] The delay unit of the first stage is used to receive an initial data strobe signal and an enable signal, and perform delay processing on the enable signal based on the initial data strobe signal to obtain a corresponding initial delayed signal;
[0011] The delay unit of the subsequent stage is used to receive the initial data strobe signal and the initial delayed signal output by the delay unit of the previous stage, and perform delay processing on the initial delayed signal of the previous stage based on the initial data strobe signal to obtain a corresponding initial delayed signal;
[0012] The delay unit at each stage is further configured to output the corresponding initial delay signal to the selection unit;
[0013] The selection unit is configured to receive the initial delay signal and a control signal, select a target delay signal from the initial delay signal based on the control signal, and output the target delay signal to the logic unit;
[0014] The control signal is used to represent the number of clock edges in the leading segment of the initial data strobe signal, and the clock edge is a rising edge or a falling edge;
[0015] The logic unit is used to receive the target delay signal and the initial data selection signal, and perform logic operations on the target delay signal and the initial data selection signal to filter out the leading segment of the initial data selection signal to obtain the target data selection signal with the valid segment retained.
[0016] Preferably, the delay unit includes a D flip-flop, and the selection unit includes a selector;
[0017] The D flip-flop of the first stage is used to respond to the first clock edge of the initial data strobe signal and obtain the corresponding initial delay signal according to the enable signal;
[0018] The D flip-flop of the next stage is used to respond to the Nth clock edge of the initial data strobe signal and obtain a corresponding initial delay signal according to the initial delay signal output by the D flip-flop of the previous stage;
[0019] Wherein, N is consistent with the number of stages of the D flip-flop;
[0020] The selector is configured to select, based on the control signal, the initial delay signal output by the D flip-flop corresponding to the number of the clock edges from the initial delay signals output by the plurality of D flip-flops as the target delay signal.
[0021] Preferably, the number of the delay units arranged in cascade is greater than or equal to the number of the clock edges.
[0022] Preferably, the processing circuit further comprises a first comparing unit;
[0023] The first comparison unit is electrically connected to the memory and each of the delay units respectively;
[0024] The memory is used to output a differential data strobe signal;
[0025] The first comparison unit is configured to obtain the initial data strobe signal based on a reference voltage and one component signal of the differential data strobe signal, and output the initial data strobe signal to each of the delay units.
[0026] Preferably, the voltage value of the reference voltage is between a preset value and an amplitude value of one of the component signals of the differential data strobe signal;
[0027] and / or,
[0028] The memory includes double data rate memory.
[0029] Preferably, the voltage value is half of the amplitude value.
[0030] Preferably, the processing circuit further includes a second comparing unit;
[0031] The second comparing unit is electrically connected to the memory and the logic unit respectively;
[0032] The second comparison unit is used to receive the differential data strobe signal, compare the two component signals of the differential data strobe signal to obtain an intermediate data strobe signal and output the intermediate data strobe signal to the logic unit;
[0033] The logic unit is further configured to perform a logic operation on the target delay signal and the intermediate data strobe signal to obtain the target data strobe signal.
[0034] Preferably, the first comparison unit comprises a single-ended comparator;
[0035] and / or,
[0036] The second comparing unit includes a differential comparator.
[0037] The present disclosure also provides a controller, which includes the data strobe signal processing circuit as described above.
[0038] The present disclosure also provides a data reading system, which includes a memory and the controller as described above.
[0039] On the basis of conforming to the common sense in this field, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.
[0040] The positive progress of this disclosure is:
[0041] The present invention uses a number of delay units to delay the enable signal based on the data selection signal, thereby completing the filtering of the leading segment of the data selection signal to select the valid segment of the data selection signal. Compared with the traditional method of using training to select the valid segment, the present invention does not require initialization training, thereby reducing the initialization time of the data reading system. The processing circuit is little affected by voltage and temperature changes, and there is no need to use periodic training to track voltage and temperature changes, which is conducive to improving the effective transmission bandwidth and performance of the data reading system. Compared with the traditional method of using hardware to avoid the leading segment, the present invention uses fewer circuits to achieve the filtering of the leading segment, the processing circuit hardware overhead is smaller, and it has better performance, power consumption and area (PPA) advantages, thereby improving the competitiveness of the processing circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] Figure 1 This is a module diagram of a data strobe signal processing circuit according to embodiment 1 of the present disclosure.
[0043] Figure 2 This is a structural diagram of the data selection signal processing circuit of embodiment 2 of the present disclosure.
[0044] Figure 3 Schematic diagram of the waveform of the signal in the data selection signal processing circuit of embodiment 2 of the present disclosure. DETAILED DESCRIPTION
[0045] The present disclosure is further illustrated below by way of examples, but the present disclosure is not limited to the scope of the examples.
[0046] In the embodiments of the present disclosure, prefixes such as "first" and "second" are used only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. In the embodiments of the present disclosure, the use of prefixes such as ordinal numbers to distinguish description objects does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the claims or embodiments, and no unnecessary limitations should be constituted due to the use of such prefixes. In addition, in the description of this embodiment, unless otherwise specified, the meaning of "plurality" is two or more.
[0047] In the embodiments of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved comply with the provisions of relevant laws and regulations and do not violate public order and good morals.
[0048] Example 1
[0049] This embodiment provides a data strobe signal processing circuit, which is applied to a controller, such as Figure 1 As shown, the processing circuit includes a logic unit 1, a selection unit 2 and a plurality of delay units 3 arranged in cascade;
[0050] Each delay unit 3 is electrically connected to the selection unit 2, and the selection unit 2 is electrically connected to the logic unit 1;
[0051] The first-stage delay unit 3 is used to receive the initial data strobe signal and the enable signal, and delay the enable signal based on the initial data strobe signal to obtain a corresponding initial delayed signal;
[0052] The delay unit 3 of the latter stage is used to receive the initial data strobe signal and the initial delay signal output by the delay unit 3 of the previous stage, and perform delay processing on the initial delay signal of the previous stage based on the initial data strobe signal to obtain a corresponding initial delay signal;
[0053] The delay unit 3 of each stage is also used to output the corresponding initial delay signal to the selection unit 2;
[0054] The selection unit 2 is used to receive the initial delay signal and the control signal, select the target delay signal from the initial delay signal based on the control signal, and output the target delay signal to the logic unit 1;
[0055] The control signal is used to represent the number of clock edges in the leading segment of the initial data strobe signal, and the clock edge is a rising edge or a falling edge;
[0056] The logic unit 1 is used to receive the target delay signal and the initial data strobe signal, and perform logic operations on the target delay signal and the initial data strobe signal to filter out the leading segment of the initial data strobe signal to obtain the target data strobe signal with the valid segment retained.
[0057] Specifically, the logical operation may be an AND operation.
[0058] In this embodiment, several delay units are used to delay the enable signal based on the data strobe signal, thereby filtering the leading segment of the data strobe signal and selecting the valid segment of the data strobe signal. Compared with traditional methods that use training to select valid segments, this embodiment does not require initialization training, thereby reducing the initialization time of the data reading system. The processing circuit is minimally affected by voltage and temperature changes, and there is no need to use periodic training to track voltage and temperature changes, which is beneficial for improving the effective transmission bandwidth and performance of the data reading system. Compared with traditional methods that use hardware to avoid leading segments, this embodiment uses fewer circuits to achieve leading segment filtering processing, resulting in lower hardware overhead for the processing circuit, better performance, power consumption, and area advantages, and improving the competitiveness of the processing circuit.
[0059] Example 2
[0060] This embodiment provides a data strobe signal processing circuit, which is a further improvement to the first embodiment.
[0061] In one feasible solution, Figure 2 As shown, the delay unit 3 includes a D flip-flop (DFF) 31, and the selection unit 2 includes a selector (MUX) 21;
[0062] The first-stage D flip-flop 31 is used to respond to the first clock edge of the initial data strobe signal and obtain the corresponding initial delay signal according to the enable signal;
[0063] The D flip-flop 31 of the next stage is used to respond to the Nth clock edge of the initial data strobe signal and obtain a corresponding initial delay signal according to the initial delay signal output by the D flip-flop 31 of the previous stage;
[0064] Wherein, N is consistent with the level number of the D flip-flop 31;
[0065] The selector 21 is configured to select, based on a control signal, an initial delay signal output by a D flip-flop 31 corresponding to the number of clock edges from among the initial delay signals output by a plurality of D flip-flops 31 as a target delay signal.
[0066] Specifically, the initial data strobe signal is used as an input signal of the processing circuit, while the enable signal is used as another input signal. The processing circuit includes a certain number of D flip-flops 31, a selector 21 and a logic unit (Logic) 1.
[0067] Figure 2 Only three D flip-flops are shown, namely a first D flip-flop 311 , a second D flip-flop 312 , and a third D flip-flop 313 , that is, three D flip-flops are used for illustration.
[0068] Among them, the level flip of the initial data selection signal serves as the trigger edge of the D flip-flop 31. The trigger edge of the D flip-flop 31 can be a logic high level to a low level (falling edge trigger) or a logic low level to a high level (rising edge trigger). Here, rising edge trigger is taken as an example. When the corresponding waveform of the initial data selection signal has the first rising edge, the first D flip-flop 311 latches the enable signal and outputs the first delay signal. Similarly, when the corresponding waveform of the initial data selection signal has the second rising edge, the second D flip-flop 312 latches the first delay signal and outputs the second delay signal. By analogy, when the corresponding waveform of the initial data selection signal has the third rising edge, the third D flip-flop 313 latches the second delay signal and outputs the third delay signal. The initial delay signal includes the first delay signal, the second delay signal, and the third delay signal.
[0069] The enable signal and the corresponding outputs of the first D flip-flop 311, the second D flip-flop 312, and the third D flip-flop 313 serve as inputs to the selector 21. The output of the selector 21 is controlled by a control signal. The control signal matches the leading segment of the initial data selection signal and is consistent on the controller side and the double data rate memory side. The control signal is used to characterize the number of clock edges in the leading segment of the initial data selection signal. The control signal specifically includes a control word, which instructs the selector 21 to select the corresponding initial delay signal as the target delay signal. For example, if the leading segment of the initial data selection signal includes two rising edges, the selector 21 uses the second delay signal output by the second D flip-flop 312 as the target delay signal.
[0070] The output signal of selector 21, i.e., the target delay signal, is filtered out of the leading segment of the initial data strobe signal and, together with the initial data strobe signal, serves as the input of logic unit 1. Logic unit 1 performs an AND operation on the target delay signal and the initial data strobe signal, ultimately outputting the valid segment of the initial data strobe signal, i.e., the target data strobe signal.
[0071] In this solution, a number of D flip-flops are used to delay the enable signal based on the initial data selection signal. The selector selects the target delay signal based on the control signal, completing the filtering of the leading segment of the initial data selection signal to select the data selection signal that retains the valid segment. Compared with the traditional method of using training to select the valid segment, this solution does not require initialization training, thereby reducing the initialization time of the data reading system. The processing circuit is only slightly affected by voltage and temperature changes, and there is no need to use periodic training to track voltage and temperature changes, which is beneficial to improving the effective transmission bandwidth and performance of the data reading system. Compared with the traditional method of using hardware to avoid the leading segment, this solution uses fewer circuits to achieve the filtering of the leading segment. The hardware overhead of the processing circuit is smaller, and it has better performance, power consumption and area advantages, which improves the competitiveness of the processing circuit.
[0072] In an implementable solution, the number of cascaded delay units is greater than or equal to the number of clock edges.
[0073] Specifically, the number of delay cells needs to match the number of clock edges in the preamble segment specified by the double data rate memory protocol. In actual applications, the number of delay cells should be greater than or equal to the number of clock edges in the initial data strobe signal.
[0074] In this solution, by setting the number of delay units to be greater than or equal to the number of clock edges in the initial data selection signal, the selection unit can reasonably and accurately output the initial delay signal of the corresponding delay unit as the target delay signal, thereby ensuring the accuracy and reliability of the processing circuit.
[0075] In one practicable solution, the processing circuit further includes a first comparison unit 4;
[0076] The first comparison unit 4 is electrically connected to the memory and each delay unit 3 respectively;
[0077] The memory is used to output a differential data strobe signal;
[0078] The first comparison unit 4 is configured to obtain an initial data strobe signal based on a reference voltage and one component signal of the differential data strobe signal, and output the initial data strobe signal to each delay unit 3 .
[0079] Specifically, during the data reading process, the controller sends an enable signal (IE) 900. The enable signal is a binary signal, which is usually represented by a high level (logic 1) or a low level (logic 0) to indicate an enabled or disabled state. Here, a logic high level is used as an example of effective enable. The controller also sends a command / address signal. After receiving the command / address, the memory, such as a double data rate memory, sends a differential data selection signal, namely a first data selection signal (DQS_T) 901 and a second data selection signal (DQS_C) 902. Compared with a single-ended signal, the differential data selection signal has a stronger anti-interference ability and can suppress the influence of PVT (Process / Voltage / Temperature) on the performance of the data selection signal, such as the duty cycle. The differential data strobe signals DQS_T901 and DQS_C902 are generally divided into three phases, namely, a tri-state phase 903 (Tri-state), a preamble phase 904 (Preamble) and an effective phase 905 (Effective), as shown in FIG. Figure 3 As shown in Figure 1, DQS_T901 and DQS_C902 are sent from the double data rate memory and arrive at the controller through the connection channel. When the double data rate memory is not operating or before the data strobe signal is sent, the data strobe signal appears in a tri-state segment, also known as an indeterminate state or high-impedance state.
[0080] A differential comparator is generally used in the controller to receive and determine the differential data selection signal, and output the corresponding determination results CP906 and CN907. The determination results are in the form of logic high level and logic low level, where CP906 corresponds to DQS_T901 and CN907 corresponds to DQS_C902.
[0081] Typically, the characteristics of a differential comparator cause it to output an erroneous glitch signal 909 when processing the tri-state segment 908 of the differential data strobe signal. In some cases, a flip 910 of the enable signal IE900 sent by the controller may also cause the differential comparator to generate an erroneous glitch signal 909 output.
[0082] The output of glitch signal 909 could be mistaken for the preamble segment 904 or valid segment 905, causing malfunctions in the controller's functionality or logic. To prevent logic misjudgments, a first comparison unit 4 with a reference voltage (VREF) is typically used to receive and determine one of the differential data strobe signal components, such as DQS_C 902. The output of first comparison unit 4 is the initial data strobe signal (CSN) 911. The logic level of initial data strobe signal 911 corresponds to that of DQS_C 902, and there are no erroneous glitch outputs.
[0083] The level flip of the initial data strobe signal 911 serves as the trigger edge of the first D flip-flop 311. When the corresponding waveform of the initial data strobe signal 911 shows the first rising edge, the first D flip-flop 311 latches the enable signal 900 and outputs the first delayed signal (CSN_D1) 912. Similarly, when the corresponding waveform of the initial data strobe signal 911 shows the second rising edge, the second D flip-flop 312 latches the first delayed signal 912 and outputs the second delayed signal (CSN_D2) 913. Similarly, when the corresponding waveform of the initial data strobe signal 911 shows the third rising edge, the third D flip-flop 313 latches the second delayed signal 913 and outputs the third delayed signal (CSN_D3) 914.
[0084] The enable signal 900 and the first delayed signal 912, the second delayed signal 913, and the third delayed signal 914 serve as inputs to the selector 21. The output of the selector 21 is controlled by a control signal (CTRL).
[0085] The output signal of selector 21, namely the target delay signal (CSN_G) 915, filters out the leading segment of the initial data strobe signal and serves as the input of logic unit 1 together with the differential CP906 and CN907. Logic unit 1 performs an AND operation on the target delay signal 915 and the differential CP906 and CN907, and ultimately outputs the valid segment of the initial data strobe signal, namely the target data strobe signals DQS_T_G 916 and DQS_C_G 917.
[0086] In this solution, by using a first comparison unit with a reference voltage to receive and determine one of the component signals of the differential data strobe signal, the glitch signal of the three-state segment in the differential data strobe signal is filtered out, thereby ensuring the accuracy and reliability of the initial data strobe signal.
[0087] In one embodiment, the voltage value of the reference voltage is between a preset value and an amplitude value of a component signal of the differential data strobe signal;
[0088] Specifically, the preset value may be 0, and the voltage value may be half of the amplitude value.
[0089] In this solution, the voltage value of the reference voltage of the first comparison unit is determined by the amplitude value of a component signal of the differential data selection signal, thereby ensuring the correct filtering of the glitch signal of the three-state segment in the differential data selection signal and ensuring the accuracy and reliability of the initial data selection signal.
[0090] In one practicable solution, the processing circuit further includes a second comparison unit 5;
[0091] The second comparison unit 5 is electrically connected to the memory and the logic unit 1 respectively;
[0092] The second comparison unit 5 is used for receiving the differential data strobe signal, comparing the two component signals of the differential data strobe signal to obtain an intermediate data strobe signal and outputting the intermediate data strobe signal to the logic unit 1;
[0093] The logic unit 1 is further configured to perform a logic operation on the target delay signal and the intermediate data strobe signal to obtain a target data strobe signal.
[0094] In this solution, by adopting the second comparison unit to receive and determine the level of the differential data strobe signal, the anti-interference capability and signal integrity of the signal are improved, and the accuracy and reliability of the target data strobe signal are guaranteed.
[0095] In one embodiment, the first comparison unit 4 includes a single-ended comparator.
[0096] In this solution, a single-ended comparator with a reference voltage is used to receive and determine one of the component signals of the differential data strobe signal, thereby filtering out the glitch signal of the three-state segment in the differential data strobe signal and ensuring the accuracy and reliability of the initial data strobe signal.
[0097] In one embodiment, the second comparison unit 5 includes a differential comparator.
[0098] In this solution, a differential comparator is used to receive and determine the level of the differential data strobe signal, thereby improving the signal's anti-interference capability and signal integrity, and ensuring the accuracy and reliability of the target data strobe signal.
[0099] In this embodiment, several delay units are used to delay the enable signal based on the data strobe signal, thereby filtering the leading segment of the data strobe signal and selecting the valid segment of the data strobe signal. Compared with traditional methods that use training to select valid segments, this embodiment does not require initialization training, thereby reducing the initialization time of the data reading system. The processing circuit is minimally affected by voltage and temperature changes, and there is no need to use periodic training to track voltage and temperature changes, which is beneficial for improving the effective transmission bandwidth and performance of the data reading system. Compared with traditional methods that use hardware to avoid leading segments, this embodiment uses fewer circuits to achieve leading segment filtering processing, resulting in lower hardware overhead for the processing circuit, better performance, power consumption, and area advantages, and improving the competitiveness of the processing circuit.
[0100] Example 3
[0101] This embodiment provides a controller, which includes a data strobe signal processing circuit as in the first or second embodiment.
[0102] Specifically, the controller includes a central processing unit, a graphics processing unit, or a communication modem.
[0103] In addition, the data strobe signal processing circuit can also be used in double data rate memory particles and double data rate memory controller components, such as FPGA (Field Programmable Gate Array), SoC (System on Chip), IP core (Intellectual Property Core), etc.
[0104] In this embodiment, the controller integrates the above-mentioned data selection signal processing circuit to filter the leading segment of the initial data selection signal, ensure the accuracy and reliability of the target data selection signal, and improve the accuracy and reliability of the controller's data reading.
[0105] Example 4
[0106] This embodiment provides a data reading system, which includes a memory and the controller of embodiment 3.
[0107] Specifically, the memory includes double data rate memory.
[0108] In this embodiment, the accuracy and reliability of data reading are guaranteed by providing the above-mentioned controller and memory.
[0109] While specific embodiments of the present disclosure have been described above, those skilled in the art will appreciate that these are merely illustrative and that the scope of protection of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, and such changes and modifications are intended to fall within the scope of protection of the present disclosure.
Claims
1. A data strobe signal processing circuit, wherein the processing circuit is applied to a controller, and is characterized in that: The processing circuit includes a logic unit, a selection unit and a plurality of delay units arranged in cascade; Each of the delay units is electrically connected to the selection unit, and the selection unit is electrically connected to the logic unit; The delay unit of the first stage is used to receive an initial data strobe signal and an enable signal, and perform delay processing on the enable signal based on the initial data strobe signal to obtain a corresponding initial delayed signal; The delay unit of the subsequent stage is used to receive the initial data strobe signal and the initial delayed signal output by the delay unit of the previous stage, and perform delay processing on the initial delayed signal of the previous stage based on the initial data strobe signal to obtain a corresponding initial delayed signal; The delay unit at each stage is further configured to output the corresponding initial delay signal to the selection unit; The selection unit is configured to receive the initial delay signal and a control signal, select a target delay signal from the initial delay signal based on the control signal, and output the target delay signal to the logic unit; The control signal is used to represent the number of clock edges in the leading segment of the initial data strobe signal, and the clock edge is a rising edge or a falling edge; The logic unit is used to receive the target delay signal and the initial data selection signal, and perform logic operations on the target delay signal and the initial data selection signal to filter out the leading segment of the initial data selection signal to obtain the target data selection signal with the valid segment retained.
2. The data strobe signal processing circuit according to claim 1, wherein: The delay unit includes a D flip-flop, and the selection unit includes a selector; The D flip-flop of the first stage is used to respond to the first clock edge of the initial data strobe signal and obtain the corresponding initial delay signal according to the enable signal; The D flip-flop of the next stage is used to respond to the Nth clock edge of the initial data strobe signal and obtain a corresponding initial delay signal according to the initial delay signal output by the D flip-flop of the previous stage; Wherein, N is consistent with the number of stages of the D flip-flop; The selector is configured to select, based on the control signal, the initial delay signal output by the D flip-flop corresponding to the number of the clock edges from the initial delay signals output by the plurality of D flip-flops as the target delay signal.
3. The data strobe signal processing circuit according to claim 1, wherein: The number of the delay units arranged in cascade is greater than or equal to the number of the clock edges.
4. The data strobe signal processing circuit according to any one of claims 1 to 3, characterized in that: The processing circuit further includes a first comparison unit; The first comparison unit is electrically connected to the memory and each of the delay units respectively; The memory is used to output a differential data strobe signal; The first comparison unit is configured to obtain the initial data strobe signal based on a reference voltage and one component signal of the differential data strobe signal, and output the initial data strobe signal to each of the delay units.
5. The data strobe signal processing circuit according to claim 4, wherein: The voltage value of the reference voltage is between a preset value and an amplitude value of one of the component signals of the differential data strobe signal; and / or, The memory includes double data rate memory.
6. The data strobe signal processing circuit according to claim 5, wherein: The voltage value is half of the amplitude value.
7. The data strobe signal processing circuit according to claim 4, wherein: The processing circuit further includes a second comparison unit; The second comparing unit is electrically connected to the memory and the logic unit respectively; The second comparison unit is used to receive the differential data strobe signal, compare the two component signals of the differential data strobe signal to obtain an intermediate data strobe signal and output the intermediate data strobe signal to the logic unit; The logic unit is further configured to perform a logic operation on the target delay signal and the intermediate data strobe signal to obtain the target data strobe signal.
8. The data strobe signal processing circuit according to claim 7, wherein: The first comparison unit includes a single-ended comparator; and / or, The second comparing unit includes a differential comparator.
9. A controller, characterized in that: The controller includes a data strobe signal processing circuit according to any one of claims 1 to 8.
10. A data reading system, characterized in that: The data reading system includes a memory and the controller according to claim 9.