Serial port expansion circuit suitable for RS485 and RS232 communication

Abstract

The invention relates to a serial port expansion circuit suitable for RS485 and RS232 communication, and belongs to the field of serial port communication. According to the serial port expansion circuit, a group of SPIs (Serial Peripheral Interface) of a microcontroller are expanded into a plurality of groups of sub-serial ports by using an expansion serial port chip; each group of sub serial ports is correspondingly connected with one RS232 transceiver and one RS485 transceiver; then, the IO interface of the microcontroller is expanded into a plurality of enabling control ends by using a shift register; each enabling control end is connected with a negation circuit and an RS232 transceiver; each negation circuit is correspondingly connected with one RS232 transceiver and one logic control chip; each logic control chip is correspondingly connected with one RS485 transceiver; the extended serial port chip is connected with a plurality of logic control chips; switching of communication modes of the RS232 transceiver and the RS485 transceiver is achieved through the microcontroller, the shifting register, the negation circuit and the logic control chip, an external interface can be shared under the condition that the device is not disassembled, and the flexibility of serial port expansion is effectively improved.

Description

Technical Field

[0001] The invention relates to a serial port expansion circuit suitable for RS485 and RS232 communications, belonging to the field of serial port communications. Background Art

[0002] To enhance autonomy and controllability and ensure supply chain security, the power system is placing greater demands on localized product production. Communication gateways and distribution network terminals must have a sufficient number of RS485 and RS232 ports to facilitate communication with various peripherals.

[0003] Among all the interfaces on the microcontroller unit (MCU) of a communication gateway or distribution terminal, the number of Universal Asynchronous Receiver / Transmitter (UART) interfaces used for communication with RS485 and RS232 is limited, or the UART interfaces are occupied by other functions. Furthermore, because peripheral products may use different interfaces, this further increases the requirements for the MCU. To meet the requirements of using multiple peripherals and different interfaces, the serial port design of current products is mainly implemented through the following four methods:

[0004] 1. Design an equal number of RS485 and RS232 communication interfaces, each corresponding to the MCU's UART interface. Although this approach can meet the needs of peripherals with different interfaces, it doubles the number of UARTs required on the MCU, limiting chip selection and the number of external interfaces.

[0005] Second, add an additional MCU with multiple UART interfaces to expand the serial port and forward the serial port data to the main controller. Although this method can increase the number of UARTs to meet the needs of different interface peripherals, it increases hardware costs. The additional MCU requires a separate program control, which also increases software development costs.

[0006] During product design, the RS485 and RS232 communication interfaces are connected to the same UART port via 0-ohm resistors or jumpers. Although this method uses only one UART port for each external interface, field use requires opening the product casing, unsoldering the 0-ohm resistors, or manually switching jumpers, which is cumbersome and reduces reliability.

[0007] 4. When designing the product, connect the RS485 and RS232 communication interface signal receiving ends to the UART interface's RX (receive port) through pull-up resistors and reverse diodes. Although this approach uses only one UART interface per external interface and is adaptive to both RS485 and RS232 interfaces, the external communication interfaces cannot be combined, resulting in a large terminal space occupation problem.

[0008] From the above analysis, it can be seen that the above four solutions all have the problem of poor flexibility when performing serial port expansion. Summary of the Invention

[0009] The purpose of the present invention is to provide a serial port expansion circuit suitable for RS485 and RS232 communications, so as to solve the problem of poor flexibility when performing serial port expansion in the prior art.

[0010] To achieve the above object, the solution of the present invention includes:

[0011] The present invention discloses a serial port expansion circuit suitable for RS485 and RS232 communications, comprising: a microcontroller, an expansion serial port chip whose output end connected to a group of SPI communication buses of the microcontroller includes a plurality of serial port communication connection ends, and a shift register whose output end connected to an IO interface of the microcontroller includes a plurality of parallel output ends;

[0012] The microcontroller is used to control the shift register to output a high or low level enable signal according to communication requirements;

[0013] Each parallel output terminal of the shift register is connected to a corresponding inversion circuit for inverting the input signal;

[0014] The output end of each negation circuit is correspondingly connected to a logic control chip for mapping the signal of the input end to the output end when the control enable end receives a level signal that is the same as its effective level, and outputting a high-impedance state when receiving a level signal that is opposite to its effective level;

[0015] The data transmission terminal and the data reception terminal in each group of serial communication connection terminals are connected to an RS485 transceiver and an RS232 transceiver. The RS232 transceiver corresponding to each group of serial communication connection terminals is also correspondingly connected to a parallel output terminal of a shift register and an output terminal of an inversion circuit. The request-to-send data terminal in each group of serial communication terminals is correspondingly connected to an input terminal of a logic control chip. The output terminal of each logic control chip is connected to a group of data transmission and reception enable terminals of the RS485 transceiver connected to the same group of serial communication terminals.

[0016] The RS232 transceiver is used to automatically transmit and receive data when the parallel output terminal of the shift register connected thereto and the output terminal of the inverting circuit connected thereto output corresponding set level signals;

[0017] The logic control chip is used to control the RS485 transceiver connected to it to automatically send and receive data when the output terminal of the inversion circuit connected to it outputs a level signal that is the same as the effective level of its control enable terminal.

[0018] Furthermore, the inversion circuit is a triode;

[0019] The base of the transistor is connected to the parallel output end of the shift register; the collector of the transistor is connected to the shutdown control end of the RS232 transceiver and the control enable end of the logic control chip as the output end of the inversion circuit.

[0020] Furthermore, a current limiting resistor for current limiting is provided on the base of the transistor.

[0021] Furthermore, a pull-up resistor for stabilizing the output signal is connected in series to the connection line between the collector of the transistor and the power supply.

[0022] Furthermore, an RC absorption network for filtering is connected in parallel between the emitter and the base of the transistor.

[0023] Furthermore, the serial port expansion circuit also includes a plurality of connection terminals;

[0024] Each wiring terminal is connected to a group of RS232 signal transmission ends and a group of RS485 signal transmission ends.

[0025] Furthermore, the extended serial port chip includes two WK2168 chips connected in parallel on a set of SPI communication buses of the microcontroller;

[0026] The two WK2168 chips are distinguished by the chip select signal.

[0027] Furthermore, the shift register is an AiP74HC595 chip.

[0028] Furthermore, the RS232 transceiver is a UM3221E chip; and the RS485 transceiver is a UM3085E chip.

[0029] Furthermore, the logic control chip is an AiP74LVC2G125 chip.

[0030] The beneficial effects of the present invention are as follows: as a pioneering invention, the present invention provides a serial port expansion circuit suitable for RS485 and RS232 communications, comprising a microcontroller, an extended serial port chip whose output end connected to a group of SPI communication buses of the microcontroller includes several groups of serial port communication connection ends, and a shift register whose output end connected to the IO interface of the microcontroller includes several parallel output ends; the microcontroller is used to control the shift register to output a high-level or low-level enable signal according to communication requirements; each parallel output end of the shift register is correspondingly connected to an inversion circuit for inverting the input signal; the output end of each inversion circuit is correspondingly connected to a logic control chip for mapping the input signal to the output end when the control enable end receives a level signal with the same level as its effective level, and outputting a high-impedance state when receiving a level signal opposite to its effective level; in each group of serial port communication connection ends, the microcontroller is used to control the shift register to output a high-level or low-level enable signal; each parallel output end of the shift register is correspondingly connected to an inversion circuit for inverting the input signal; the output end of each inversion circuit is correspondingly connected to a logic control chip for mapping the input signal to the output end when the control enable end receives a level signal with the same level as its effective level, and outputting a high-impedance state when the control enable end receives a level signal with the opposite level to its effective level; The data sending terminal and the data receiving terminal are commonly connected to an RS485 transceiver and an RS232 transceiver. The RS232 transceiver corresponding to each group of serial port communication connection terminals is also correspondingly connected to a parallel output terminal of the shift register and an output terminal of an inversion circuit; the request to send data terminal in each group of serial port communication terminals is correspondingly connected to the input terminal of a logic control chip; the output terminal of each logic control chip is connected to a group of data transmission and reception enable terminals of the RS485 transceiver connected to the same group of serial port communication terminals; the RS232 transceiver is used to automatically send and receive data when the parallel output terminal of the shift register connected to it and the output terminal of the inversion circuit connected to it output corresponding set level signals; the logic control chip is used to control the RS485 transceiver connected to it to automatically send and receive data when the output terminal of the inversion circuit connected to it outputs a level signal with the same effective level as its control enable terminal. The present invention expands a group of SPI interfaces of a microcontroller into several groups of sub-serial ports by using an extended serial port chip. Each group of sub-serial ports is used to connect to an RS232 transceiver and an RS485 transceiver respectively. Then, a shift register is used to expand the IO interface of the microcontroller into several enable control terminals. Finally, the microcontroller, the shift register, the inversion circuit and the logic control chip are used to realize that when the RS232 transceiver is turned on, the RS485 transceiver is in a high-impedance state; when the RS485 transceiver is turned on, the RS232 transceiver is in a high-impedance state. Therefore, the communication mode of the sub-serial ports can be switched through software configuration without disassembling the device, and the external interface is shared, thereby reducing the number of terminals and the occupied space, and effectively improving the communication capability and flexibility of the MCU serial port. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 1 is a schematic structural diagram of a serial port expansion circuit suitable for RS485 and RS232 communications provided by an embodiment of the present invention;

[0032] Figure 2This embodiment of the present invention provides a Figure 1 A schematic diagram of the specific connection relationship between the microcontroller, the extended serial port chip and the shift register;

[0033] Figure 3 1 is a schematic structural diagram of a negation circuit provided by an embodiment of the present invention;

[0034] Figure 4 This embodiment of the present invention provides a Figure 1 A schematic diagram of the specific connection relationship between a logic control chip, an RS232 transceiver and an RS485 transceiver. DETAILED DESCRIPTION

[0035] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0036] The concept of the present invention is to realize the expansion of an SPI port of a microcontroller by utilizing the functions of an extended serial port chip, a shift register, an inversion circuit, a logic control chip, an RS485 transceiver and an RS232 transceiver.

[0037] Specifically: it includes a microcontroller, an extended serial port chip whose output end connected to a group of SPI communication buses of the microcontroller includes several groups of serial communication connection ends, and a shift register whose output end connected to the IO interface of the microcontroller includes several parallel output ends; the microcontroller is used to control the shift register to output a high-level or low-level enable signal according to communication requirements; each parallel output end of the shift register is correspondingly connected to an inversion circuit for inverting the input signal; the output end of each inversion circuit is correspondingly connected to a logic control chip for mapping the input signal to the output end when the control enable end receives a level signal with the same level as its effective level, and outputting a high-impedance state when receiving a level signal opposite to its effective level; the data sending terminal and the data receiving terminal in each group of serial communication connection ends are connected to an RS4 85 transceiver and an RS232 transceiver, the RS232 transceiver corresponding to each group of serial port communication connection terminals is also correspondingly connected to a parallel output terminal of the shift register and an output terminal of the inverting circuit; the request to send data terminal in each group of serial port communication terminals is correspondingly connected to the input terminal of a logic control chip; the output terminal of each logic control chip is connected to a group of data transmission and reception enable terminals of the RS485 transceiver connected to the same group of serial port communication terminals; the RS232 transceiver is used to automatically transmit and receive data when the parallel output terminal of the shift register connected to it and the output terminal of the inverting circuit connected to it output corresponding set level signals; the logic control chip is used to control the RS485 transceiver connected to it to automatically transmit and receive data when the output terminal of the inverting circuit connected to it outputs a level signal that is the same as the effective level of its control enable terminal.

[0038] An embodiment of a serial port expansion circuit suitable for RS485 and RS232 communications:

[0039] Figure 1 1 is a schematic diagram of the structure of a serial port expansion circuit suitable for RS485 and RS232 communications provided by an embodiment of the present invention. Figure 1As shown, the serial port expansion circuit includes a microcontroller, an extended serial port chip whose output end connected to a group of SPI communication buses of the microcontroller includes several groups of serial port communication connection ends, and a shift register whose output end connected to the IO interface of the microcontroller includes several parallel output ends; the microcontroller is used to control the shift register to output a high-level or low-level enable signal according to communication requirements; each parallel output end of the shift register is correspondingly connected to an inversion circuit for inverting the input signal; the output end of each inversion circuit is correspondingly connected to a circuit for mapping the input end signal to the output end signal when the control enable end receives a level signal with the same level as its effective level. The output terminal of the serial communication terminal is connected to a logic control chip that outputs a high-impedance state when receiving a level signal opposite to its effective level; the data sending terminal and the data receiving terminal in each group of serial communication connection terminals are commonly connected to an RS485 transceiver and an RS232 transceiver, and the RS232 transceiver corresponding to each group of serial communication connection terminals is also correspondingly connected to a parallel output terminal of the shift register and an output terminal of the inversion circuit; the request to send data terminal in each group of serial communication terminals is correspondingly connected to the input terminal of a logic control chip; the output terminal of each logic control chip is connected to a group of data transmission and reception enable terminals of the RS485 transceiver connected to the same group of serial communication terminals.

[0040] The RS232 transceiver is used to automatically send and receive data when the parallel output end of the shift register connected to it and the output end of the inverting circuit connected to it output corresponding set level signals; the logic control chip is used to control the RS485 transceiver connected to it to automatically send and receive data when the output end of the inverting circuit connected to it outputs a level signal that is the same as the effective level of its control enable end.

[0041] Among them, to realize the automatic transmission and reception of data of RS232 transceiver, it is required that the setting level signal outputted by the parallel output terminal of the shift register connected thereto needs to be the same as the effective level of its enable terminal, and the setting level signal outputted by the output terminal of the inverting circuit connected thereto needs to be the same as the effective level of its shutdown control terminal. That is, if the enable terminal of RS232 transceiver is low level effective, the setting level signal outputted by the parallel output terminal of the shift register connected thereto is required to be a low level signal; if the enable terminal of RS232 transceiver is high level effective, the setting level signal outputted by the parallel output terminal of the shift register connected thereto is required to be a high level signal; if the shutdown control terminal of RS232 transceiver is low level effective, the setting level signal outputted by the output terminal of the inverting circuit connected thereto is required to be a low level signal; if the shutdown control terminal of RS232 transceiver is high level effective, the setting level signal outputted by the output terminal of the inverting circuit connected thereto is required to be a high level signal. This embodiment is subsequently explained by taking the enable terminal of RS232 transceiver being low level effective and the shutdown control terminal also being low level effective as an example.

[0042] In order for the logic control chip to control the RS485 transceiver connected to it to automatically transmit and receive data, the output terminal of the connected inverter circuit is required to output a signal at the same level as the active level of its control enable terminal. That is, if the control enable terminal of the logic control chip is active low, the output terminal of the connected inverter circuit is required to output a low-level signal; if the control enable terminal of the logic control chip is active high, the output terminal of the connected inverter circuit is required to output a high-level signal. This embodiment is subsequently described using the case where the control enable terminal of the logic control chip is active low as an example.

[0043] Among them, the number of groups of serial communication connection terminals is related to the number of peripheral devices that need to be connected to the microcontroller, that is, the number of groups of serial communication connection terminals is the same as the number of peripheral devices that need to be connected; and the number of parallel output terminals of the shift register is consistent with the number of groups of serial communication connection terminals. This can not only ensure stable switching between the RS232 transceiver and the RS485 transceiver, but also reduce the waste of pins caused by the emergence of useless pins. The following example takes the serial communication connection terminals including 8 groups as an example for exemplary explanation.

[0044] Among them, several groups of serial port communication connection terminals can be completed by one chip or by two or more chips. The present invention does not specifically limit this. The following will take the example of several groups of serial port communication connection terminals being completed by two chips as an example for illustrative explanation. This can reduce the design requirements for the chip, make it easier to obtain, and also reduce production costs.

[0045] As a preferred embodiment, the chip for extending the serial port includes two WK2168 chips connected in parallel on a set of SPI communication buses of the microcontroller.

[0046] The WK2186 chip is specifically designed for expanding serial ports. It is the first low-power 4-channel Universal Asynchronous Receiver / Transmitter (UART) with a 256-level FIFO and supports UART* / SPITM* / ⅡC* / 8-bit parallel bus interfaces. The chip can be enabled to operate in any of the above main interface modes through mode selection.

[0047] Among them, the shift register is an 8-bit serial-in / serial-out or parallel-out shift register with a storage register and a three-state output; the three-state refers to the high level, low level and high impedance state, which is very suitable for bus systems because it can put its output in a high impedance state when it does not need to drive the bus, thereby avoiding the situation where multiple devices try to drive the same bus at the same time and reducing conflicts in the circuit.

[0048] As a preferred embodiment, the shift register is an AiP74HC595 chip.

[0049] Among them, the AiP74HC595 chip includes an enable input pin Low level is valid, at the enable input of AiP74HC595 chip When it is low, the data in the storage register will appear in the output. When the level is high, the output is in high impedance state, preventing data transmission; it also includes the serial data input pin DS, the shift register clock pin SHCP and the storage register clock input pin STCP, all of which are valid at high level; it also includes the serial data output pin Q7S and the parallel output pins Q0~Q7; it also includes the shift register clear pin Active low, clears the shift register pin When the received signal is low, the existing bit data in the shift register is cleared.

[0050] The following combination Figure 2 , specifically explain the specific connection relationship between the MCU (also known as the microcontroller), the extended serial port chip and the shift register.

[0051] Figure 2 This embodiment of the present invention provides a Figure 1 A schematic diagram of the specific connection relationship between the microcontroller, extended serial port chip and shift register, as shown in Figure 2 As shown in the figure, the extended serial port chip uses two WK2168 chips, and the shift register uses the AiP74HC595 chip. Then, a group of SPI communication buses of the MCU are connected to the two WK2168 chips, and the IO interface of the MCU is connected to the AiP74HC595 chip.

[0052] Specifically, the SPI_CS0 pin of the MCU is connected to the MP3 pin of the first WK2168 chip U2, the SPI_CS1 pin of the MCU is connected to the MP3 pin of the second WK2168 chip U3, the SPI_CLK pin of the MCU is respectively connected to the MP2 pin of the first WK2168 chip U2 and the MP2 pin of the second WK2168 chip U3, the SPI_MOSI pin of the MCU is respectively connected to the MP1 pin of the first WK2168 chip U2 and the MP1 pin of the second WK2168 chip U3, and the SPI_MISO pin of the MCU is respectively connected to the MP0 pin of the first WK2168 chip U2 and the MP0 pin of the second WK2 The MP0 pin of the AiP74HC595 chip U3 and the WK2168_RST pin of the MCU are respectively connected to the RSTN pin of the first WK2168 chip U2 and the RSTN pin of the second WK2168 chip U3. The WK2168_IRQ pin of the MCU are respectively connected to the IRQ pin of the first WK2168 chip U2 and the IRQ pin of the second WK2168 chip U3. The DATA pin of the MCU is connected to the DS pin of the AiP74HC595 chip. The SHCP pin of the MCU is connected to the SHCP pin of the AiP74HC595 chip. The STCP pin of the MCU is connected to the STCP pin of the AiP74HC595 chip.

[0053] Among them, the WK2168_RST pin of the MCU is essentially the GPIO pin of the MCU. In this embodiment, the GPIO pin of the MCU is called the WK2168_RST pin to illustrate that the pin is to be connected to the RSTN pin in the WK2168 chip for reset, rather than to be connected to the AiP74HC595 chip; the WK2168_IRQ pin of the MCU is essentially also the GPIO pin of the MCU. In this embodiment, the GPIO pin of the MCU is called the WK2168_IRQ pin to illustrate that the pin is to be connected to the IRQ pin in the WK2168 chip, rather than to be connected to the AiP74HC595 chip.

[0054] The output end of the first WK2168 chip U2 and the output end of the second WK2168 chip U3 each include four groups of serial communication connection terminals, and each group of serial communication connection terminals includes a data sending terminal TX, a data receiving terminal RX, and a request to send data terminal RTS.

[0055] Among them, serial port 1 includes RTS1 pin, RX1 pin and TX1 pin, which are the first group of serial port communication connection terminals of the first WK2168 chip U2, serial port 2 includes RTS2 pin, RX2 pin and TX2 pin, which are the second group of serial port communication connection terminals of the first WK2168 chip U2, serial port 3 includes RTS3 pin, RX3 pin and TX3 pin, which are the third group of serial port communication connection terminals of the first WK2168 chip U2, and serial port 4 includes RTS4 pin, RX4 pin and TX4 pin, which are the fourth group of serial port communication connection terminals of the first WK2168 chip U2.

[0056] Among them, serial port 5 includes RTS5 pin, RX5 pin and TX5 pin, which is the first group of serial port communication connection terminals of the second WK2168 chip U3, serial port 6 includes RTS6 pin, RX6 pin and TX6 pin, which is the second group of serial port communication connection terminals of the second WK2168 chip U3, serial port 7 includes RTS7 pin, RX7 pin and TX7 pin, which is the third group of serial port communication connection terminals of the second WK2168 chip U3, and serial port 8 includes RTS8 pin, RX8 pin and TX8 pin, which is the fourth group of serial port communication connection terminals of the second WK2168 chip U3.

[0057] The WK2168's SPI interface boasts a maximum speed of 10Mbit / s and supports continuous transmission and reception of up to 256 bytes. The SPI_CS0 and SPI_CS1 signals, corresponding to the MCU's SPI_CS0 and SPI_CS1 pins, are chip select signals. When SPI_CS0 is low, the first WK2168 chip, U2, is enabled, and serial ports 1 through 4 on the first WK2168 chip, transmit data to the MCU via the SPI bus. When SPI_CS1 is low, the second WK2168 chip, U3, is enabled, and serial ports 5 through 8 on the second WK2168 chip, transmit data to the MCU via the SPI bus. Using different chip select signals, the MCU's single SPI interface can be expanded into eight independent sub-serial ports, facilitating the connection of peripherals. The baud rate, word length, and parity format of each sub-serial UART port can be independently configured, providing a maximum communication rate of 2Mbps.

[0058] In this circuit, the MCU's three IOs control the shift register. The MCU outputs 8-bit serial data to the AiP74HC595. The data is shifted on the rising edge of SHCP and transferred to its internal storage register on the rising edge of STCP. The 8-bit parallel data first enable signal EN1 to the eighth enable signal EN8 are output on the eight parallel output terminals Q0-Q7.

[0059] Among them, the data sending terminal in each group of serial ports is respectively connected to the input end of the driver of an RS485 transceiver and the input end of the driver of an RS232 transceiver, the data receiving terminal in each group of serial ports is respectively connected to the output end of the receiver of an RS485 transceiver and the output end of the receiver of an RS232 transceiver, and the request to send data terminal in each group of serial ports is correspondingly connected to the input end of a logic control chip; the 8 parallel output ends of the shift register, each signal enable end is respectively connected to an RS232 enable signal end and an inversion circuit.

[0060] The RS485 transceiver connected to the data transmitting terminal and the RS485 transceiver connected to the data receiving terminal in each group of serial ports are the same RS485 transceiver. The RS232 transceiver connected to the data transmitting terminal, the RS232 transceiver connected to the data receiving terminal and the RS232 transceiver connected to a parallel output end of the shift register in each group of serial ports are the same RS232 transceiver. In order to facilitate the description of the principle, the first RS232 transceiver to the eighth RS232 transceiver and the first RS485 transceiver to the eighth RS485 transceiver are taken as examples for exemplary explanation.

[0061] The inversion circuit may be any existing circuit that can invert an input signal.

[0062] In order to reduce the cost, as a preferred embodiment, the inversion circuit is a transistor.

[0063] The following combination Figure 3 The inversion circuit is introduced in detail.

[0064] Figure 3 FIG. 1 is a schematic diagram of a structure of an inversion circuit provided by an embodiment of the present invention. Figure 3 As shown, since the shift register has 8 parallel output terminals, there are also eight inversion circuits, namely the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7 and the eighth transistor Q8.

[0065] The base of each transistor serves as the input end of the inversion circuit and is correspondingly connected to a parallel output end of the shift register; the collector of each transistor serves as the output end of the inversion circuit and is correspondingly connected to a shutdown control end of an RS232 transceiver and a control enable end of a logic control chip.

[0066] It is understandable that those skilled in the art should know that the collector of the transistor needs to be connected to a power supply and the emitter of the transistor needs to be grounded to ensure that the transistor can work normally.

[0067] To further stabilize the signal outputted by the output terminal of the inverter circuit, as an optional embodiment, a pull-up resistor is connected in series with the connection line between the collector of each transistor and the power supply to stabilize the output signal. That is, the collector of the transistor is connected to the power supply VCC via the pull-up resistor.

[0068] The present invention does not impose any particular limitation on the resistance value of the pull-up resistor. A pull-up resistor of 2 kilo-ohms (KΩ) is used as an example for illustrative description.

[0069] In order to prevent the voltage of the input signal from being too large and causing damage to the transistor, as an optional implementation, a current-limiting resistor is connected in series to the base of each transistor.

[0070] The present invention does not impose any particular limitation on the resistance value of the current-limiting resistor. A current-limiting resistor of 2KΩ is used as an example for illustrative description.

[0071] In order to make the received input signal more accurate and facilitate subsequent precise control, as an optional implementation, an RC absorption network for filtering is connected in parallel between the emitter and base of each transistor.

[0072] The RC absorption network includes a resistor and a capacitor connected in parallel.

[0073] The present invention does not specifically limit the resistance value of the resistor and the capacitance value of the capacitor in the RC absorption network. The following description will be given by taking the resistance value of the resistor in the RC absorption network as 2KΩ as an example.

[0074] As a preferred embodiment, taking the first transistor Q1 as an example: the base of the first transistor Q1 is connected to the first parallel output terminal Q0 of the AiP74HC595 chip via a first current-limiting resistor R2. The collector of the first transistor Q1 is connected to the power supply VCC, the shutdown control terminal of the RS232 transceiver, and the control enable terminal of the first logic control chip via a first pull-up resistor R1. The emitter of the first transistor Q1 is grounded GND, and a first RC snubber network is connected in parallel between the base and emitter of the first transistor Q1. The first RC snubber network includes a third resistor R3 and a first capacitor C1 connected in parallel. The specific structure of the second transistor Q2 to the eighth transistor Q8 is similar to that of the first transistor Q1 and will not be repeated here.

[0075] The following details the inverting principle of transistor Q1 as an inverting circuit, using the first transistor Q1 as an example: In this circuit, the first transistor Q1 and its external resistors and capacitors form an inverter (i.e., an inverting circuit). The first current-limiting resistor R2 provides current limiting, while the third resistor R3 and the first capacitor C1 form a filter circuit to prevent interference. The first pull-up resistor R1 provides a high level for the first inverted signal EN1' when the transistor is off. Specifically, when the first enable signal EN1 is high, the first transistor Q1 is turned on, and the first inverted signal EN1' is grounded through the first transistor Q1, indicating a low level. When the first enable signal EN1 is low, the first transistor Q1 is turned off, and the first inverted signal EN1' is directly derived from VCC, indicating a high level. Therefore, the first transistor Q1 inverts the input first enable signal EN1. The second transistor Q2 through the eighth transistor Q8 operate in a similar manner to the first transistor Q1 and will not be further described here.

[0076] In summary, the MCU controls the AiP74HC595 and the transistor circuit through three IOs to obtain eight pairs of EN1-EN8 and EN1'-EN8' signals with opposite levels, which are used to control the transmission and reception enable of the RS485 transceiver and RS232 transceiver.

[0077] As a preferred embodiment, the logic control chip is an AiP74LVC2G125 chip, the RS232 transceiver is a UM3221E chip, and the RS485 transceiver is a UM3085E chip.

[0078] Among them, the AiP74LVC2G125 chip is a dual-channel non-inverting buffer with three-state outputs, including Pins, pin, 1A pin, 2A pin, 2Y pin, 1Y pin, GND pin, and VCC pin. Pins and The AiP74LVC2G125 chip has two control enable ports, active low. Pins 1A and 2A are the AiP74LVC2G125 chip's two data input ports (also known as the inputs to the logic control chip). Pins 2Y and 1Y are the AiP74LVC2G125 chip's two data output ports (also known as the outputs to the logic control chip). The AiP74LVC2G125 chip operates as follows: when the input signal to the control enable port is low, the input controls the output. When the connected signal is high, the output outputs enter a high-impedance state, interrupting data transmission.

[0079] Among them, the UM3221E chip includes VCC pin, C1+ pin, C1- pin, C2+ pin, C2- pin, T1IN pin, R1OUT pin, pin, GND pin, Pin, R1IN pin, T1OUT pin, V- pin and V+ pin. T1IN pin is the input end of the driver of UM3221E chip (that is, the input end of the RS232 driver), T1OUT pin is the output end of the driver of UM3221E chip (that is, the output end of the RS232 driver), R1OUT pin is the output end of the receiver of UM3221E chip (that is, the output end of the RS232 receiver), R1IN pin is the input end of the receiver of UM3221E chip (that is, the input end of the RS232 receiver), The pin is the enable pin of the UM3221E chip, and the low level is valid. The pin is the shutdown control terminal of the UM3221E chip (that is, the shutdown control terminal of the RS232 receiver), and the low level is valid.

[0080] Among them, the T1IN pin and R1OUT pin of the UM3221E chip are called the communication ends of the RS232 transceiver.

[0081] Among them, the UM3085E chip includes RO pin, DI pin, VCC pin, Pin, DE pin, GND pin, A pin, B pin and VCC pin. RO pin is the output pin of the receiver of UM3085E chip, DI pin is the input pin of the transmitter of UM3085E chip, The DE pin is the enable pin of the UM3085E chip's receiver, and the DE pin is the enable pin of the UM3085E chip's transmitter. The A pin and the DE pin are collectively referred to as the transceiver enable terminal of the UM3085E chip, that is, the data transceiver enable terminal of the RS485 transceiver. The A pin and the B pin are the differential signal terminals for receiving and sending of the UM3085E chip.

[0082] Among them, the RO pin and DI pin of the UM3085E chip are called the communication ends of the RS485 transceiver.

[0083] The following combination Figure 4 Describe the specific connection relationship between the logic control chip, RS232 transceiver and RS485 transceiver.

[0084] Figure 4 This embodiment of the present invention provides a Figure 1 A schematic diagram of the specific connection relationship between a logic control chip, an RS232 transceiver and an RS485 transceiver, as shown in FIG. Figure 4As shown, the AiP74LVC2G125 chip is a logic control chip, the UM3221E chip is an RS232 transceiver, and the UM3085E chip is an RS485 transceiver.

[0085] Figure 4 The following is an example of a serial port communication connection end (serial port 1) of the extended serial port chip to illustrate the specific connection relationship between the logic control chip, RS232 transceiver and RS485 transceiver. Specifically, the AiP74LVC2G125 chip Pins and The pins are connected together and then connected to the collector of the first transistor Q1. The 1A pin and 2A pin of the AiP74LVC2G125 chip are connected together and then connected to the RTS1 pin of the first WK2168 chip U2. The 1Y pin of the AiP74LVC2G125 chip is connected to the Pin connection, 1Y pin of AiP74LVC2G125 chip and 1Y pin of UM30858E chip The connecting line between the pins is also connected to the power supply VCC through the twenty-fifth pull-up resistor R25, the 2Y pin of the AiP74LVC2G125 chip is connected to the DE pin of the UM30858E chip, and the connecting line between the 2Y pin of the AiP74LVC2G125 chip and the DE pin of the UM30858E chip is also connected to the ground GND through the twenty-sixth pull-down resistor R26.

[0086] The RO pin of the UM3085E chip is connected to the RX1 pin of the first WK2168 chip U2, and the DI pin of the UM3085E chip is connected to the TX1 pin of the first WK2168 chip U2. The A pin and B pin of the UM3085E chip are used to connect external devices (referred to as "peripherals"). The T1IN pin of the UM3221E chip is connected to the TX1 pin of the first WK2168 chip U2, and the R1OUT pin of the UM3221E chip is connected to the RX1 pin of the first WK2168 chip U2. The pin is connected to the first parallel output Q0 of the AiP74HC595 chip (that is, the first parallel output Q0 of the AiP74HC595 chip needs to be output to the UM3221E chip Pin), UM3221E chip The pin is connected to the collector of the first transistor Q1 (that is, the first negative signal EN1' output by the collector of the first transistor Q1 needs to be output to the UM3221E chip pin), the T1OUT pin and R1IN pin of the UM3221E chip are used to connect peripherals.

[0087] As an optional implementation, the A pin of the UM3085E chip and the T1OUT pin of the UM3221E chip are connected together and then connected to the first pin of the first terminal J1. The B pin of the UM3085E chip and the R1IN pin of the UM3221E chip are connected together and then connected to the second pin of the first terminal J1. When using the terminals to connect to external devices, the external device does not need to specifically search for the communication interface of the chip corresponding to the communication method, which facilitates the connection of the external device.

[0088] The present invention does not specifically limit the resistance value of the twenty-fifth pull-up resistor R25 , and this embodiment takes 10KΩ as an example for exemplary description; the resistance value of the twenty-sixth pull-down resistor R26 is not specifically limited, and this embodiment takes 10KΩ as an example for exemplary description.

[0089] It's understandable that the AiP74LVC2G125, UM3221E, and UM3085E chips also have peripheral circuits. The combination of these chips and peripheral circuits enhances chip control. Specifically, the AiP74LVC2G125's peripheral circuits include: The AiP74LVC2G125's GND pin is connected to the second end of capacitor C9 and ground GND, and the AiP74LVC2G125's VCC pin is connected to the first end of capacitor C9 and power supply VCC.

[0090] Among them, the peripheral circuit of the UM3221E chip includes: the VCC pin of the UM3221E chip is respectively connected to the power supply VCC and the first end of the tenth capacitor C10, the second end of the tenth capacitor C10 is connected to the ground GND, the eleventh capacitor C11 is connected in parallel between the C1+ pin and the C1- pin of the UM3221E chip, the twelfth capacitor C12 is connected in parallel between the C2+ pin and the C2- pin of the UM3221E chip, the thirteenth capacitor C13 is connected in parallel between the V+ pin of the UM3221E chip and the ground GND, and the fourteenth capacitor C14 is connected in parallel between the V- pin of the UM3221E chip and the ground GND.

[0091] Among them, the peripheral circuit of the UM3085E chip includes: the VCC pin of the UM3085E chip is respectively connected to the power supply VCC and the first end of the fifteenth capacitor C15, the second end of the fifteenth capacitor C15 is grounded GND, the connection line between the A pin of the UM3085E chip and the T1OUT pin of the UM3221E chip is also connected to the power supply VCC through the twenty-seventh pull-up resistor R27, the connection line between the B pin of the UM3085E chip and the R1IN pin of the UM3221E chip is also grounded GND through the twenty-eighth pull-down resistor R28, and the GND pin of the UM3085E chip is grounded GND.

[0092] The specific connection relationship between serial port 2 to serial port 8 and the logic control chip, RS232 transceiver and RS485 transceiver is similar to the specific connection relationship between reference serial port 1 and the logic control chip, RS232 transceiver and RS485 transceiver, and will not be repeated here.

[0093] The following combination Figures 2 to 4 The working principle of the serial port expansion circuit applicable to RS485 and RS232 communications provided by the embodiment of the present invention is introduced in detail.

[0094] Taking the first RS232 transceiver and the first RS485 as an example, an exemplary description is given:

[0095] Specifically, when RS232 communication is required, the MCU controls the first enable signal EN1 output from the first parallel output terminal Q1 of the AiP74HC595 chip to be low level, and the EN1' obtained after the first transistor Q1 inverts to be high level, then the receiver of the first RS232 transceiver U6 (ie, UM3221E chip) Enable, shutdown control terminal of the first RS232 transceiver U6 Failure, the driver is not shut down, at this time the first RS232 transceiver U1 is in a bidirectional conduction state, and can realize RS232 full-duplex communication.

[0096] Since EN1' is high, the AiP74LVC2G125 chip Pins and The pin receives a high level signal. Pins and The pin is low level active, so the two output pins of AiP74LVC2G125 chip (1Y pin and 2Y pin) are in high impedance state. At this time, the two enable pins of the first RS485 transceiver U7 (ie UM3085E chip) are and DE are controlled by the twenty-fifth pull-up resistor R25 and the twenty-sixth pull-down resistor R26 respectively. The 25th pull-up resistor R25 is controlled to be high level, and the 26th pull-down resistor R26 of the UM3085E chip is controlled to be low level. It is active at a low level, and the enable terminal DE of the transmitter is active at a high level. Therefore, the UM3085E chip enters a low-power shutdown mode, and the bidirectional output is in a high-impedance state, which will not affect the communication of the first RS232 transceiver U6.

[0097] When RS485 communication is required, the MCU controls the first parallel output terminal Q1 of the AiP74HC595 chip to output the first enable signal EN1 to be high, and the EN1' obtained after the first transistor Q1 inversion is low. Since EN1 is high and EN1' is low, the receiver of the first RS232 transceiver Disable, the receiver output is high impedance; the shutdown control terminal of the first RS232 transceiver U6 Enable, the driver is turned off, the driver output is in high impedance state, and the bidirectional output of the first RS232 transceiver is in high impedance state, which will not affect the communication of the RS485 transceiver.

[0098] Since EN1' is low, the AiP74LVC2G125 chip Pins and The pin is low, the output is controlled by the input, that is, the receiver output of the first RS485 transceiver is enabled The driver output enable DE of the first RS485 transceiver is controlled by the RTS1 signal. Configure the WK2168 sub-serial port to RS485 automatic transceiver mode. The RTS1 signal is used for the automatic transceiver control of the RS485 transceiver. When receiving data, RTS1 outputs a low level by default. At this time, the two input terminals 1A and 2A of the AiP74LVC2G125 chip receive low-level signals, and the two output terminals 1Y and 2Y of the AiP74LVC2G125 chip output low-level signals, that is, the signal at the input terminal is mapped to the output terminal. At this time, the first RS485 transceiver U7 The pin is enabled and the DE pin is disabled, and the first RS485 transceiver U7 is in the receiving state. When sending data, the RTS1 signal automatically reverses and outputs a high level. At this time, the two input terminals 1A and 2A of the AiP74LVC2G125 chip receive high-level signals, and the two output terminals 1Y and 2Y of the AiP74LVC2G125 chip output high-level signals. The first RS485 transceiver U7 The pin is disabled and the DE pin is valid, and the first RS485 transceiver U7 is in the sending state. After the data is sent, RTS1 returns to the default low level and the RS485 receiver is in the receiving state.

[0099] About the working principle of the second RS232 transceiver and the second RS485 transceiver, the working principle of the 3rd RS232 transceiver and the 3rd RS485 transceiver, the working principle of the 4th RS232 transceiver and the 4th RS485 transceiver, the working principle of the 5th RS232 transceiver and the 5th RS485 transceiver, the working principle of the 6th RS232 transceiver and the 6th RS485 transceiver, the working principle of the 7th RS232 transceiver and the 7th RS485 transceiver and the working principle of the 8th RS232 transceiver and the 8th RS485 transceiver are similar to the working principle of the first RS232 transceiver and the first RS485 transceiver, and will not repeat them here.

[0100] An embodiment of the present invention provides a serial port expansion circuit suitable for RS485 and RS232 communications, comprising a microcontroller, an expansion serial port chip whose output end connected to a group of SPI communication buses of the microcontroller includes several groups of serial port communication connection ends, and a shift register whose output end connected to an IO interface of the microcontroller includes several parallel output ends; the microcontroller is used to control the shift register to output a high-level or low-level enable signal according to communication requirements; each parallel output end of the shift register is correspondingly connected to an inversion circuit for inverting an input signal; the output end of each inversion circuit is correspondingly connected to a logic control chip for mapping the input signal to the output end when the control enable end receives a level signal with the same level as its effective level, and outputting a high-impedance state when receiving a level signal opposite to its effective level; the data sending terminal and The data receiving terminal is commonly connected to an RS485 transceiver and an RS232 transceiver. The RS232 transceiver corresponding to each group of serial port communication connection terminals is also correspondingly connected to a parallel output terminal of a shift register and an output terminal of an inverting circuit. The request-to-send data terminal in each group of serial port communication terminals is correspondingly connected to an input terminal of a logic control chip. The output terminal of each logic control chip is connected to a group of data transmit and receive enable terminals of the RS485 transceiver connected to the same group of serial port communication terminals. The RS232 transceiver is used to automatically transmit and receive data when the parallel output terminal of the shift register connected to it and the output terminal of the inverting circuit connected to it output corresponding set level signals. The logic control chip is used to control the RS485 transceiver connected to it to automatically transmit and receive data when the output terminal of the inverting circuit connected to it outputs a level signal that is the same as the effective level of its control enable terminal. The present invention expands a group of SPI interfaces of a microcontroller into several groups of sub-serial ports by using an extended serial port chip. Each group of sub-serial ports is used to connect to an RS232 transceiver and an RS485 transceiver respectively. Then, a shift register is used to expand the IO interface of the microcontroller into several enable control terminals. Finally, the microcontroller, the shift register, the inversion circuit and the logic control chip are used to realize that when the RS232 transceiver is turned on, the RS485 transceiver is in a high-impedance state; when the RS485 transceiver is turned on, the RS232 transceiver is in a high-impedance state. Therefore, the communication mode of the sub-serial ports can be switched through software configuration without disassembling the device, and the external interface is shared, thereby reducing the number of terminals and the occupied space, and effectively improving the communication capability and flexibility of the MCU serial port.

Claims

1. A serial port expansion circuit suitable for RS485 and RS232 communications, characterized in that: include: A microcontroller, an extended serial port chip having an output end connected to a group of SPI communication buses of the microcontroller and including a plurality of serial communication connection ends, and a shift register having an output end connected to an IO interface of the microcontroller and including a plurality of parallel output ends; The microcontroller is used to control the shift register to output a high or low level enable signal according to communication requirements; Each parallel output terminal of the shift register is connected to a corresponding inversion circuit for inverting the input signal; The output end of each negation circuit is correspondingly connected to a logic control chip for mapping the signal of the input end to the output end when the control enable end receives a level signal that is the same as its effective level, and outputting a high-impedance state when receiving a level signal that is opposite to its effective level; The data sending terminal and the data receiving terminal in each group of serial communication connection terminals are commonly connected to an RS485 transceiver and an RS232 transceiver, and the RS232 transceiver corresponding to each group of serial communication connection terminals is also correspondingly connected to a parallel output terminal of the shift register and an output terminal of an inversion circuit; the request to send data terminal in each group of serial communication terminals is correspondingly connected to an input terminal of a logic control chip; the output terminal of each logic control chip is connected to a group of data transmission and reception enable terminals of the RS485 transceiver connected to the same group of serial communication terminals; The RS232 transceiver is used to automatically transmit and receive data when the parallel output terminal of the shift register connected thereto and the output terminal of the inverting circuit connected thereto output corresponding set level signals; The logic control chip is used to control the RS485 transceiver connected to it to automatically send and receive data when the output terminal of the inversion circuit connected to it outputs a level signal that is the same as the effective level of its control enable terminal.

2. The serial port expansion circuit for applicable RS485 and RS232 communications according to claim 1, wherein The inversion circuit is a triode; The base of the transistor is connected to the parallel output end of the shift register; the collector of the transistor serves as the output end of the inversion circuit and is respectively connected to the shutdown control end of the RS232 transceiver and the control enable end of the logic control chip.

3. The serial port expansion circuit for applicable RS485 and RS232 communications according to claim 2, wherein A current limiting resistor for current limiting is provided on the base of the transistor.

4. The serial port expansion circuit for applicable RS485 and RS232 communications according to claim 2, wherein A pull-up resistor for stabilizing the output signal is connected in series on the connection line between the collector of the transistor and the power supply.

5. The serial port expansion circuit for applicable RS485 and RS232 communications according to claim 2, wherein An RC absorption network for filtering is connected in parallel between the emitter and the base of the triode.

6. The serial port expansion circuit according to any one of claims 1 to 5, wherein the serial port expansion circuit is adapted for RS485 and RS232 communications. The serial port expansion circuit also includes a plurality of connection terminals; Each wiring terminal is connected to a group of RS232 signal transmission ends and a group of RS485 signal transmission ends.

7. The serial port expansion circuit for applicable RS485 and RS232 communications according to claim 1, wherein The extended serial port chip includes two WK2168 chips connected in parallel on a set of SPI communication buses of the microcontroller; The two WK2168 chips are distinguished by the chip select signal.

8. The serial port expansion circuit for applicable RS485 and RS232 communications according to claim 1, wherein The shift register is an AiP74HC595 chip.

9. The serial port expansion circuit for applicable RS485 and RS232 communications according to claim 1, wherein The RS232 transceiver is a UM3221E chip; the RS485 transceiver is a UM3085E chip.

10. The serial port expansion circuit suitable for RS485 and RS232 communications according to claim 1, wherein: The logic control chip is an AiP74LVC2G125 chip.

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