Method and device for realizing high-speed communication between FPGA (Field Programmable Gate Array) and superconducting chip, and electronic equipment

Abstract

The invention provides a method and a device for realizing high-speed communication between an FPGA (Field Programmable Gate Array) and a superconducting chip and electronic equipment, and relates to the technical field of integrated circuit chip design and the technical field of digital communication. The method is applied to an FPGA, and comprises the following steps: in response to a received pseudo-random number sent by a superconducting chip, carrying out parallel conversion processing on the pseudo-random number to obtain a pseudo-random sequence; the pseudo-random sequence of the kth period and the pseudo-random sequence of the (k-1) th period are detected, a first detection result is obtained, and k is a positive integer larger than 1; in response to the fact that the first detection result is the same, sending target data to the superconducting chip for operation; the pseudo-random sequence of the (k + n) th period and the pseudo-random sequence of the (k + n-1) th period are detected, a second detection result is obtained, and n is a positive integer larger than 1; and in response to the same second detection result, storing an operation result returned by the superconducting chip.

Description

Technical Field

[0001] The present invention relates to the technical fields of integrated circuit chip design and digital communication, and in particular to a method, device and electronic equipment for realizing high-speed communication between FPGA and superconducting chip. Background Art

[0002] With the development of the internet, faster network transmission speeds and increased local storage capacity have led to explosive growth in data volumes. At the same time, faced with this vast amount of data, people's demand for data retrieval has also increased. However, as the size of MOS transistors (metal-oxide semiconductor field-effect transistors) continues to shrink, their gate widths are approaching their physical limits. This has limited the power consumption density of current CMOS (complementary metal oxide semiconductor)-based processors, leading to a slowdown in their development. Therefore, in the face of growing data processing demands, CMOS-based processors are unable to provide the corresponding processing speeds. This imbalance in development is forcing the emergence of faster, lower-power processors.

[0003] The existing communication architecture for superconducting processors has two main problems:

[0004] (1) Low off-chip communication speed of superconducting chips: Due to the small integration scale of current superconducting chips and the small capacity of low-temperature storage units, complex applications cannot be deployed solely relying on superconducting chips. Therefore, processing systems based on superconducting chips often require the use of external room-temperature storage units. In the past, the off-chip communication speed of superconducting chips was too low, which seriously blocked the operation of the entire system pipeline.

[0005] (2) Superconducting chips are susceptible to noise interference and poor channel quality: The output level of superconducting chips is only at the millivolt level, so the communication channel is susceptible to noise interference. Secondly, the control current of the superconducting chip is very weak, and the SFQ (superconducting single flux quantum circuit) circuit determines the digital logic based on the presence or absence of Josephson junction flux quanta. Therefore, the working state of the superconducting chip is susceptible to noise and magnetic field interference. The unstable communication channel in time and space limits the reliability of high-speed communication outside the superconducting chip. Summary of the Invention

[0006] In view of the above problems, the present invention provides a method, device and electronic equipment for realizing high-speed communication between FPGA and superconducting chip.

[0007] According to a first aspect of an embodiment of the present invention, a method for implementing high-speed communication between an FPGA and a superconducting chip is provided, which is applied to the FPGA and includes: in response to receiving a pseudo-random number transmitted from the superconducting chip, performing parallel conversion processing on the pseudo-random number to obtain a pseudo-random sequence; detecting the pseudo-random sequence of the kth period and the pseudo-random sequence of the k-1th period to obtain a first detection result, where k is a positive integer greater than 1; in response to the first detection results being the same, sending target data to the superconducting chip for calculation; detecting the pseudo-random sequence of the k+nth period and the pseudo-random sequence of the k+n-1th period to obtain a second detection result, where n is a positive integer greater than 1; and in response to the second detection results being the same, storing the calculation result returned by the superconducting chip.

[0008] According to an embodiment of the present invention, the method for implementing high-speed communication between an FPGA and a superconducting chip further includes: adaptively adjusting the load of the target data according to the second detection result.

[0009] According to an embodiment of the present invention, adaptively adjusting the load of target data according to the second detection result includes: adaptively increasing the load of target data in response to the same second detection result; and adaptively reducing the load of target data in response to different second detection results.

[0010] According to an embodiment of the present invention, before sending target data to a superconducting chip for operation, the process includes: packaging the target data; and performing serial conversion on the packaged target data.

[0011] According to an embodiment of the present invention, in response to the second detection result being the same, before storing the operation result returned by the superconducting chip, the method includes: performing descrambling and alignment processing on the operation result returned by the superconducting chip and the target data.

[0012] According to an embodiment of the present invention, in response to the second detection results being the same, before storing the operation result returned by the superconducting chip, the method further includes: unpacking the operation result and the target data after descrambling and alignment.

[0013] According to a second aspect of an embodiment of the present invention, a method for implementing high-speed communication between an FPGA and a superconducting chip is provided, which is applied to a superconducting chip and includes: generating and sending a pseudo-random number to the FPGA, wherein the pseudo-random number is used to receive target data sent by the FPGA based on a detection result of the FPGA; performing an operation on the target data in response to receiving the target data; and returning the operation result to the FPGA.

[0014] According to an embodiment of the present invention, performing operations on the target data includes: performing scrambling processing on the target data.

[0015] According to a third aspect of an embodiment of the present invention, a device for implementing high-speed communication between an FPGA and a superconducting chip is provided, characterized in that the device includes: a conversion module for, in response to receiving a pseudo-random number sent from the superconducting chip, performing parallel conversion processing on the pseudo-random number to obtain a pseudo-random sequence; a first detection module for detecting the pseudo-random sequence of the kth period and the pseudo-random sequence of the k-1th period to obtain a first detection result, wherein k is a positive integer greater than 1; a sending module for, in response to the first detection results being the same, sending target data to the superconducting chip for calculation; a second detection module for detecting the pseudo-random sequence of the k+nth period and the pseudo-random sequence of the k+n-1th period to obtain a second detection result, wherein n is a positive integer greater than 1; and a storage module for storing the calculation result returned by the superconducting chip in response to the second detection results being the same.

[0016] According to a fourth aspect of an embodiment of the present invention, an electronic device is provided, comprising: one or more processors; a storage device for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the above method.

[0017] The method for realizing high-speed communication between an FPGA and a superconducting chip provided by the present invention has at least the following beneficial effects:

[0018] (1) The present invention provides a method for realizing high-speed communication between FPGA and superconducting chip. To address the problem of low communication rate of superconducting chip, a high-speed communication protocol based on pseudo-random sequence (PRS) is designed. When applied to the control circuit inside the FPGA, it can effectively solve the problem of low communication rate outside the current superconducting chip and effectively reduce the hardware overhead caused by the communication outside the superconducting chip.

[0019] (2) The method for realizing high-speed communication between FPGA and superconducting chip provided by the present invention is equipped with an adaptive load algorithm to effectively avoid unstable channel transmission and unstable working state of superconducting chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above contents and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0021] Figure 1 The structure diagram of the Josephson junction and its circuit symbol according to an embodiment of the present invention is schematically shown.

[0022] Figure 2 The structure of a conventional superconducting processor operation pipeline according to an embodiment of the present invention is schematically shown.

[0023] Figure 3 The flowchart of the method for realizing high-speed communication between FPGA and superconducting chip according to an embodiment of the present invention is schematically shown.

[0024] Figure 4 The principle diagram of a method for implementing high-speed communication between an FPGA and a superconducting chip according to an embodiment of the present invention is schematically shown.

[0025] Figure 5 The structure block diagram of the apparatus for realizing high-speed communication between FPGA and superconducting chip according to an embodiment of the present invention is schematically shown.

[0026] Figure 6 The block diagram schematically shows an electronic device suitable for implementing a high-speed communication method between an FPGA and a superconducting chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. Obviously, the embodiments described are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "including", "comprising", etc. used herein indicate the existence of features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0028] In the present invention, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood broadly. For example, they may refer to fixed or detachable connections, or integration; mechanical or electrical connections, or communication; direct or indirect connections through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0029] In the description of the present invention, it should be understood that the terms "longitudinal", "length", "circumferential", "front", "rear", "left", "right", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the subsystem or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0030] Throughout the drawings, identical elements are represented by identical or similar reference numerals. Conventional structures or configurations may be omitted when they may obscure the understanding of the present invention. Furthermore, the shapes, sizes, and positional relationships of components in the drawings do not reflect actual size, proportion, or actual positional relationships.

[0031] Similarly, in order to streamline the present invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. Descriptions with reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" and the like mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in an appropriate manner.

[0032] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the technical features being referred to. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means at least two, such as two or three, unless otherwise specifically defined.

[0033] When expressions such as "at least one of A, B and C, etc." are used, they should generally be interpreted in accordance with the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0034] In the technical solution of the present invention, the collection, storage, use, processing, transmission, provision, disclosure and application of the data involved (including but not limited to user personal information) comply with the provisions of relevant laws and regulations, take necessary confidentiality measures, and do not violate public order and good morals.

[0035] With the development of the internet, faster network transmission speeds and increased local storage capacity have led to explosive growth in data volumes. Simultaneously, with this vast amount of data, people's demand for data retrieval is also increasing. However, as MOS transistors continue to shrink in size, their gate widths are approaching their physical limits. This has limited the power consumption density of current CMOS-based processors, leading to a slowdown in their speed. Consequently, CMOS-based processors are unable to meet the growing demand for data processing speeds. This imbalance in development is forcing the development of faster, lower-power processors.

[0036] Superconducting chips based on Josephson junctions rely on the presence or absence of internal magnetic flux to represent "0" and "1" in digital logic. Because the internal magnetic flux of the Josephson junction responds at picosecond speeds, superconducting digital circuits not only have higher operating clock speeds than CMOS circuits that rely on current transmission, but also have extremely low power consumption. Therefore, data retrieval processors based on superconducting chips can provide higher computing power and lower power consumption.

[0037] Figure 1 The structure diagram of the Josephson junction and its circuit symbol according to an embodiment of the present invention is schematically shown.

[0038] like Figure 1 As shown, normally, when voltage is applied across a Josephson junction structure, no current will flow because the series connection is a short circuit. However, when the non-superconducting layer is thin enough, electrons (Cooper pairs) can tunnel between the two superconducting layers, flowing from one end to the other, generating current. When the current across the Josephson junction exceeds the critical current of the device, it switches to a voltage-applied state and releases a flux quantum. The presence or absence of a flux quantum in a Josephson junction-based single flux quantum (SFQ) circuit represents the "1" and "0" of digital logic.

[0039] Figure 2 The structure of a conventional superconducting processor operation pipeline according to an embodiment of the present invention is schematically shown.

[0040] like Figure 2As shown, with the advancement of superconducting technology, a variety of customized, specialized task accelerators based on superconducting devices have been proposed. Although these specialized task accelerators can achieve extremely high processing speeds and extremely low power consumption at high clock speeds, processors that rely solely on superconducting devices struggle to achieve high efficiency for end-to-end task processing. The key reason is that current superconducting chips face the problem of small memory cells at low temperatures. Hybrid SRAM (static random access memory) based on Josephson junctions and CMOS can only store 64Kb. While it offers extremely high access speeds, its bit width and storage capacity are insufficient to meet the needs of complex tasks. Limited by interference resistance and high-speed interface design, the development of low-temperature SRAM has been slow. On the other hand, as the scale of superconducting integrated circuits increases, the computing bandwidth of computing units based on superconducting devices has doubled, reaching over 100Gbps. This imbalance in development makes it difficult for processors that rely solely on superconducting devices to efficiently process large amounts of data. Therefore, when deploying real-world tasks, it is necessary to divide subtasks based on memory capacity. However, overly detailed task division will lead to frequent and low-speed data interaction between SRAM and the host computer, resulting in low efficiency of the overall processing system when deploying end-to-end tasks. In addition, in the past, data communication between the host computer and the superconducting chip was often low-frequency communication, with a communication speed of only 100Kbps, while the on-chip computing bandwidth can reach more than 12Gbps. The mismatch between the two causes the overall processor to have such problems. Figure 2 The pipeline shown is blocked.

[0041] Because SFQ-based superconducting chips use the presence or absence of magnetic flux to represent "0" and "1" in digital logic, and require only a weak current for control, the output level of superconducting chips is often in the millivolt range. Consequently, the transmission channel is extremely susceptible to noise interference during signal transmission. Furthermore, superconducting chips are extremely sensitive to changes in magnetic fields, and their operating current is extremely weak, making their operating state equally susceptible to noise interference.

[0042] In summary, the existing communication architecture for superconducting processors has two main problems:

[0043] (1) Low off-chip communication speed of superconducting chips: Due to the small integration scale of current superconducting chips and the small capacity of low-temperature storage units, complex applications cannot be deployed solely relying on superconducting chips. Therefore, processing systems based on superconducting chips often require the use of external room-temperature storage units. In the past, the off-chip communication speed of superconducting chips was too low, which seriously blocked the operation of the entire system pipeline.

[0044] (2) Superconducting chips are susceptible to noise interference, resulting in poor channel quality: The output level of superconducting chips is only at the millivolt level, making the communication channel susceptible to noise interference. Furthermore, the control current of superconducting chips is very weak, and the SFQ circuit determines digital logic based on the presence or absence of Josephson junction flux quanta. Therefore, the operating state of superconducting chips is susceptible to noise and magnetic field interference. The unstable communication channel in time and space limits the reliability of high-speed communication outside the superconducting chip.

[0045] Based on this, an embodiment of the present invention provides a method for realizing high-speed communication between FPGA and superconducting chip.

[0046] Figure 3 The flowchart of the method for realizing high-speed communication between FPGA and superconducting chip according to an embodiment of the present invention is schematically shown.

[0047] like Figure 3 As shown, the method for implementing high-speed communication between an FPGA and a superconducting chip according to an embodiment of the present invention includes:

[0048] S1. In response to receiving a pseudo-random number sent from a superconducting chip, performing parallel conversion processing on the pseudo-random number to obtain a pseudo-random sequence.

[0049] In this embodiment, a pseudo-random number is generated by a PRNG (pseudo-random number generator) and periodically sent to an FPGA (field programmable gate array). After receiving the pseudo-random number, the FPGA converts it into a pseudo-random sequence.

[0050] S2. Detect the pseudo-random sequence of the kth period and the pseudo-random sequence of the k-1th period to obtain a first detection result, where k is a positive integer greater than 1.

[0051] In this embodiment, whether the working state of the superconducting chip is stable is detected by detecting whether the pseudo-random sequences of the previous and next cycles are consistent.

[0052] S3. In response to the first detection result being the same, sending the target data to the superconducting chip for calculation.

[0053] In this embodiment, when it is detected that the pseudo-random sequences of the previous and next cycles are consistent, it indicates that the working state of the superconducting chip is stable, and the target data is sent to the superconducting chip for calculation.

[0054] S4. Detect the pseudo-random sequence of the k+nth period and the pseudo-random sequence of the k+n-1th period to obtain a second detection result, where n is a positive integer greater than 1.

[0055] In this embodiment, since the superconducting chip may become unstable in working state after the operation, it is necessary to detect for the second time whether the pseudo-random sequences of the previous and next cycles are consistent.

[0056] S5. In response to the second detection result being the same, store the operation result returned by the superconducting chip.

[0057] In this embodiment, when the second detection shows that the pseudo-random sequences of the previous and next cycles are consistent, it indicates that the working state of the superconducting chip after the calculation is also in a stable state, and the calculation result is saved.

[0058] Based on the above embodiment, since the working state of the superconducting chip is easily interfered by noise when sending multiple packets of target data, data transmission is extremely prone to unstable transmission during the process of sending and receiving multiple data packets. In order to avoid unstable channel conditions, this embodiment adopts an adaptive dynamic load algorithm, that is, adaptively adjusting the load of the target data according to the second detection result.

[0059] Specifically, in response to the second detection results being the same, the load of the target data is adaptively increased; in response to the second detection results being different, the load of the target data is adaptively reduced.

[0060] The adaptive dynamic load algorithm uses the success of each transmission to determine whether the load of the next transmission needs to be increased or decreased. If the previous transmission can be stable, the load of the next transmission can be appropriately increased. If the previous transmission fails, the load of the next transmission can be appropriately reduced. In this way, bandwidth utilization can be improved when sending multiple packets, while avoiding unstable working conditions.

[0061] The pseudo code of the adaptive load algorithm can be shown in Table 1 below. Packet refers to the data packet to be sent, State refers to whether a single transmission is successful, RC represents the reward coefficient, and PC represents the penalty coefficient.

[0062]

[0063] Table 1: Pseudocode of the adaptive load algorithm

[0064] The present invention provides a method for realizing high-speed communication between FPGA and superconducting chip, which is equipped with an adaptive load algorithm and can effectively avoid unstable channel transmission and unstable working state of superconducting chip.

[0065] Based on the above embodiment, before sending the target data to the superconducting chip for calculation, the FPGA further includes packaging the target data and performing serial conversion on the packaged target data.

[0066] Based on the above embodiment, in response to the second detection results being the same, before storing the operation result returned by the superconducting chip, the method includes: performing descrambling and alignment processing on the operation result returned by the superconducting chip and the target data.

[0067] Since the target data is scrambled in the superconducting chip, when the superconducting chip returns the calculation result to the FPGA, the returned calculation result and the target data need to be descrambled and aligned.

[0068] Based on the above embodiment, in response to the second detection results being the same, before storing the operation result returned by the superconducting chip, the method further includes: unpacking the operation result and the pseudo-random sequence after descrambling and alignment.

[0069] Before storing the calculation results, the calculation results need to be unpacked.

[0070] The present invention provides a method for realizing high-speed communication between FPGA and superconducting chip. To address the problem of low communication rate of superconducting chip, a high-speed communication protocol based on pseudo-random sequence is designed. When applied to the control circuit inside the FPGA, it can effectively solve the problem of low communication rate outside the superconducting chip and effectively reduce the hardware overhead caused by the communication outside the superconducting chip.

[0071] Figure 4 The principle diagram of a method for implementing high-speed communication between an FPGA and a superconducting chip according to an embodiment of the present invention is schematically shown.

[0072] like Figure 4 As shown, in the method for implementing high-speed communication between an FPGA and a superconducting chip according to an embodiment of the present invention, the superconducting chip is mainly used for:

[0073] A pseudo-random number is generated according to the PRNG and sent to the FPGA, wherein the pseudo-random number is used to receive target data sent by the FPGA according to the detection result of the FPGA, and in response to receiving the target data, the target data is operated, and finally the operation result after the operation is returned to the FPGA.

[0074] The transceiver is mainly used for serial and parallel conversion processing, including parallel conversion of serial data sent by the superconducting chip and serial conversion of target data sent by the FPGA.

[0075] PRS-checking means checking the pseudo-random sequences of the previous and next cycles to measure whether the working state of the superconducting chip is stable.

[0076] Figure 5 The structure block diagram of the apparatus for realizing high-speed communication between FPGA and superconducting chip according to an embodiment of the present invention is schematically shown.

[0077] like Figure 5As shown, the device for implementing high-speed communication between FPGA and superconducting chip in this embodiment includes: a conversion module 501 , a first detection module 502 , a sending module 503 , a second detection module 504 and a storage module 505 .

[0078] The conversion module 501 is used for performing parallel conversion in response to receiving serial data sent from the superconducting chip, including performing parallel conversion on pseudo-random numbers output by the superconducting chip to obtain a pseudo-random sequence.

[0079] The first detection module 502 is used to detect the pseudo-random sequence of the kth period and the pseudo-random sequence of the k-1th period to obtain a first detection result, where k is a positive integer greater than 1.

[0080] The sending module 503 is configured to send the target data to the superconducting chip for calculation in response to the first detection result being the same.

[0081] The second detection module 504 is used to detect the pseudo-random sequence of the k+nth period and the pseudo-random sequence of the k+n-1th period to obtain a second detection result, where n is a positive integer greater than 1.

[0082] In response to the second detection result being the same, the storage module 505 stores the operation result returned by the superconducting chip.

[0083] Figure 6 The block diagram schematically shows an electronic device suitable for implementing a high-speed communication method between an FPGA and a superconducting chip according to an embodiment of the present invention.

[0084] like Figure 6 As shown, the electronic device 600 according to an embodiment of the present invention includes a processor 601, which can perform various appropriate actions and processes according to a program stored in a dynamic random access memory (DRAM) 602 or a program loaded from a storage portion 408 into a static random access memory (SRAM) 603. The processor 601 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or a related chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 601 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present invention.

[0085] SRAM 603 stores various programs and data required for the operation of electronic device 600. Processor 601, DRAM 602, and SRAM 603 are interconnected via bus 604. Processor 601 executes the programs stored in DRAM 602 and / or SRAM 603 to perform various operations according to the method flow of the embodiment of the present invention. It should be noted that the programs may also be stored in one or more memories other than DRAM 602 and SRAM 603. Processor 601 may also execute the programs stored in one or more memories to perform various operations according to the method flow of the embodiment of the present invention.

[0086] According to an embodiment of the present invention, electronic device 600 may further include an input / output (I / O) interface 605, which is also connected to bus 604. Electronic device 600 may also include one or more of the following components connected to I / O interface 605: an input section 606 including a keyboard, mouse, etc.; an output section 607 including components such as a high-speed communication interface, a cathode ray tube (CRT), a liquid crystal display (LCD), and speakers; a storage section 608 including a hard disk; and a communication section 604 including a network interface card such as a LAN card or a modem. Communication section 604 performs communication processing via a network such as the Internet. A drive 610 is also connected to I / O interface 605 as needed. Removable media 611, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed in drive 610 as needed, so that computer programs read from the removable media can be installed into storage section 608 as needed.

[0087] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functions and operations that may be implemented according to the systems and methods of various embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0088] Those skilled in the art will appreciate that the features described in the various embodiments of the present invention may be combined and / or coupled in various ways, even if such combinations and / or couplings are not explicitly described in the present invention. In particular, the features described in the various embodiments of the present invention may be combined and / or coupled in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or couplings fall within the scope of the present invention.

[0089] The above describes embodiments of the present invention. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A method for realizing high-speed communication between FPGA and superconducting chip, applied to FPGA, characterized in that: The method comprises: In response to receiving a pseudo-random number sent from a superconducting chip, performing parallel conversion processing on the pseudo-random number to obtain a pseudo-random sequence; Detecting the pseudo-random sequence of the kth period and the pseudo-random sequence of the k-1th period to obtain a first detection result, where k is a positive integer greater than 1; In response to the first detection results being the same, sending target data to the superconducting chip for calculation; Detecting the pseudo-random sequence of the k+nth period and the pseudo-random sequence of the k+n-1th period to obtain a second detection result, where n is a positive integer greater than 1; In response to the second detection result being the same, the operation result returned by the superconducting chip is stored.

2. The method for realizing high-speed communication between FPGA and superconducting chip according to claim 1, characterized in that: Also includes: The load of the target data is adaptively adjusted according to the second detection result.

3. The method for realizing high-speed communication between FPGA and superconducting chip according to claim 2, characterized in that: Adaptively adjusting the load of the target data according to the second detection result includes: In response to the second detection result being the same, adaptively increasing the load of the target data; In response to the second detection result being different, the load of the target data is adaptively reduced.

4. The method for realizing high-speed communication between FPGA and superconducting chip according to claim 1, characterized in that: Before sending the target data to the superconducting chip for calculation, the method includes: Packaging the target data; The packaged target data is serially converted.

5. The method for realizing high-speed communication between FPGA and superconducting chip according to claim 1, characterized in that: Before storing the operation result returned by the superconducting chip in response to the second detection result being the same, the method includes: The calculation result returned by the superconducting chip and the target data are descrambled and aligned.

6. The method for realizing high-speed communication between FPGA and superconducting chip according to claim 5, characterized in that: Before storing the operation result returned by the superconducting chip in response to the second detection result being the same, the method further includes: Unpack the operation results and target data after descrambling and alignment processing.

7. A method for realizing high-speed communication between FPGA and superconducting chip, applied to superconducting chip, characterized in that: The method comprises: Generate and send a pseudo-random number to the FPGA, wherein the pseudo-random number is used to receive target data sent by the FPGA according to a detection result of the FPGA; In response to receiving the target data, performing an operation on the target data; The calculated result is returned to the FPGA.

8. The method for realizing high-speed communication between FPGA and superconducting chip according to claim 7, characterized in that: The performing operation on the target data includes: The target data and the calculation result are scrambled.

9. A high-speed communication device for implementing FPGA and superconducting chip, characterized in that: The device comprises: a conversion module, configured to, in response to receiving a pseudo-random number sent from the superconducting chip, perform parallel conversion processing on the pseudo-random number to obtain a pseudo-random sequence; A first detection module is configured to detect the pseudo-random sequence of the kth period and the pseudo-random sequence of the k-1th period to obtain a first detection result, where k is a positive integer greater than 1; a sending module, configured to send target data to the superconducting chip for calculation in response to the first detection results being the same; A second detection module is used to detect the pseudo-random sequence of the k+nth period and the pseudo-random sequence of the k+n-1th period to obtain a second detection result, where n is a positive integer greater than 1; The storage module stores the operation result returned by the superconducting chip in response to the user that the second detection result is the same.

10. An electronic device comprising: one or more processors; a storage device for storing one or more computer programs, The method is characterized in that the one or more processors execute the one or more computer programs to implement the steps of the method according to any one of claims 1 to 8.

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