Storage and calculation integrated circuit and device based on FPGA

Abstract

The invention discloses a storage and calculation integrated circuit and device based on an FPGA, and relates to the field of calculation circuits. The circuit comprises a bit serial processing unit and a BRAM; the bit serial processing unit is connected with a storage column of the BRAM, and the BRAM is used for reading data and transmitting the read data to the bit serial processing unit; and the bit serial processing unit is used for carrying out operation on the read data, starting a write enable signal of the BRAM and activating a corresponding row, and transmitting a final result to the BRAM. According to the invention, the computing throughput can be improved, and efficient utilization of resources and low delay and low power consumption of data transmission can be realized.

Description

Technical Field

[0001] The present application relates to the field of computing circuits, and in particular to an FPGA-based storage and computing integrated circuit and device. Background Art

[0002] With the rapid development of artificial intelligence (AI), facing the ever-increasing scale of data and the demand for ultra-high computing power, traditional computing architectures are gradually showing their limitations. Traditional computer architectures utilize a "computation-storage" separation. When processing data, instructions are first fetched from memory. After decoding, the control unit retrieves data from memory, transfers it via a bus to the computer for computation, and finally writes the results back to memory. Throughout this process, sequential instruction execution is computationally inefficient. Furthermore, computing units and processors are rapidly advancing in line with Moore's Law, with performance far exceeding that of memory. This results in memory speeds being far lower than CPU speeds, creating a "memory wall" problem. Therefore, in traditional computer architectures, the frequent data transfer between memory and the computer results in significant latency and power consumption, limiting computational efficiency.

[0003] To address these issues, integrated memory and computing hardware architectures have emerged and developed. By embedding computing units within or near memory, this architecture significantly reduces data transfer between memory and computing units, thereby significantly reducing computational latency and power consumption. In this context, field programmable gate arrays (FPGAs), as highly flexible and parallel programmable logic devices, offer users flexible programmability and reconfigurability by integrating programmable logic modules, configurable routing, input / output modules, memory, and digital signal processing units. Furthermore, modern FPGAs, particularly those used for complex applications and high-performance computing, incorporate built-in block random access memory (BRAM), which consists of static random access memory (SRAM). This distributed architecture, combined with reconfigurable logic, increases on-chip bandwidth, supports high-speed data transmission, and effectively overcomes the performance bottlenecks of traditional computer architectures. Furthermore, a large number of independent BRAMs can be configured as parallel processing units, enabling highly parallel computing capabilities.

[0004] In existing FPGAs, however, the computing unit (Digital Signal Processing, DSP) and the storage unit composed of BRAM are independent of each other. Even if they are physically close, data still needs to be transferred from the storage unit to the computing unit or from the computing unit back to the storage unit, thus limiting the FPGA's acceleration potential. In existing FPGAs, BRAM is only used as a traditional storage unit with a single function. For FPGA-based hardware design, its scale is usually limited by the number of lookup tables (LUTs), resulting in low resource utilization and high power consumption.

[0005] Therefore, in order to solve the above problems, there is an urgent need for an FPGA-based storage and computing integrated circuit and device to improve computing throughput, achieve efficient resource utilization, and achieve low latency and low power consumption in data transmission. Summary of the Invention

[0006] The purpose of this application is to provide an FPGA-based storage and computing integrated circuit and device to improve computing throughput, achieve efficient resource utilization, and achieve low latency and low power consumption for data transmission.

[0007] To achieve the above objectives, this application provides the following solutions:

[0008] In a first aspect, the present application provides a storage-computation integrated circuit based on FPGA, comprising: a bit-serial processing unit and a BRAM; the bit-serial processing unit is connected to a storage column of the BRAM;

[0009] The BRAM is used to read data and transmit the read data to the bit serial processing unit;

[0010] The bit serial processing unit is used to perform operations on the read data and transmit the final result to the BRAM by turning on the write enable signal of the BRAM and activating the corresponding row.

[0011] Optionally, the number of bit serial processing units is greater than or equal to 1.

[0012] Optionally, the bit serial processing unit includes: a full adder, a carry trigger, a 3-to-1 data selector, a 2-to-1 data selector, and a tag trigger;

[0013] The full adder is used to receive the read data and perform addition operation; transmit the carry data to the carry trigger, and transmit the sum bit data to the 3-to-1 data selector;

[0014] The carry trigger is used to store carry data and transmit the carry data to the full adder and the 3-to-1 data selector;

[0015] The tag trigger is used to perform a multiplication operation according to the low-order part of the read data and store the binary bit data of the multiplier;

[0016] The 3-to-1 data selector is used to select different data sources of operation results and output the operation results to the 2-to-1 data selector; the different data sources of the operation results include: input data, sum bit data and carry data; the operation results include: addition operation results and multiplication operation results;

[0017] The 2-to-1 data selector is used to select different data sources of the final result, output the final result, and write it back to the BRAM; the different data sources of the final result include: the operation result and binary bit data output by the 3-to-1 data selector.

[0018] Optionally, the full adder uses a gate circuit to perform addition operations.

[0019] Optionally, the process of the bit serial processing unit performing the addition operation is:

[0020] Get two n-bit source operands from the read port of the same column of the BRAM; take n as the total number of binary bits;

[0021] Calculate the least significant bit of the two n-bit source operands bit by bit to get the position i of the current traversal binary bit;

[0022] Determine the position of the currently traversed binary digit and the total number of binary digits;

[0023] If the position of the currently traversed binary bit is less than the total number of binary bits, the two n-bit source operands are transferred to the bit serial processing unit for addition, and the sum bit of the addition result is written back to the BRAM; if the addition result generates carry data, it is transferred to the carry flip-flop for use in the next clock cycle;

[0024] If the position of the currently traversed binary digit is greater than or equal to the total number of binary digits, the carry of the most significant bit is written back to the BRAM.

[0025] Optionally, the process of the bit serial processing unit performing the multiplication operation is:

[0026] Store two n-bit source operands in the same column of BRAM; add 2n rows to store the product R; initialize 2n rows to 0; and set n as the total number of binary bits.

[0027] Load the multiplier into the tag flip-flop bit by bit from the least significant bit to obtain the position i of the binary bit that currently activates the multipliers corresponding to the two storage rows;

[0028] Determine the position of the binary bits of the multipliers corresponding to the two storage rows currently activated and the size of the total number of binary bits;

[0029] If the positions of the binary bits of the multipliers corresponding to the two storage rows currently activated are less than the total number of binary bits, it is determined whether the input signal of the tag trigger is 1; if the input signal of the tag trigger is equal to 1, the most significant bit of the multiplicand and the binary bit corresponding to the multiplication result are added; if the addition result generates carry data, it is transferred to the carry trigger; if the input signal of the tag trigger is not equal to 1, the corresponding bit of the multiplication result is written back to the BRAM; the input signal is the binary bit of the multiplier;

[0030] If the positions of the binary bits of the multipliers corresponding to the two storage rows currently activated are greater than or equal to the total number of binary bits, the data in the carry trigger is written back to the most significant bit of the multiplication result; the most significant bit of the multiplicand is added to the binary bit corresponding to the multiplication result to generate carry data, which is written back to the BRAM.

[0031] In a second aspect, the present application provides an FPGA-based storage and computing integrated device, comprising: a microinstruction memory, a first enhanced BRAM structure, a second enhanced BRAM structure, and two interface circuits; the first enhanced BRAM structure and the second enhanced BRAM structure are the FPGA-based storage and computing integrated circuit;

[0032] The microinstruction memory is used to store microinstructions; each microinstruction is a combination of all control signals required to be executed by the first enhanced BRAM structure and the second enhanced BRAM structure and the interface circuit within one clock cycle; the microinstructions include: addition microinstructions and multiplication microinstructions;

[0033] The first enhanced BRAM structure and the second enhanced BRAM structure are correspondingly connected to the interface circuit; the two interface circuits are used to transmit data between the first enhanced BRAM structure and the second enhanced BRAM structure.

[0034] Optionally, the first enhanced BRAM structure and the second enhanced BRAM structure both include a storage mode and a computing mode;

[0035] When the first enhanced BRAM structure and the second enhanced BRAM structure are in a storage mode, the first enhanced BRAM structure and the second enhanced BRAM structure perform read and write operations;

[0036] When the first enhanced BRAM structure and the second enhanced BRAM structure are in a calculation mode, the first enhanced BRAM structure and the second enhanced BRAM structure are used to control the bit-serial processing unit to perform bit-serial addition or multiplication operations according to microinstructions.

[0037] Optionally, the interface circuit is used to extract odd-numbered and even-numbered data from the first enhanced BRAM structure and the second enhanced BRAM structure, and control the clock cycle through a clock signal to alternately output the odd-numbered and even-numbered data.

[0038] Optionally, the FPGA-based storage and computing integrated device is used to perform a convolution operation, specifically including:

[0039] Obtaining a weight vector and an input vector; and quantizing and transposing the weight vector and the input vector;

[0040] Align the weight vector and the input vector and store them in the first enhanced BRAM structure;

[0041] Using the multiplication microinstruction called by the first enhanced BRAM structure, multiplying the weight vector and the input vector, and aligning and storing the multiplication result in the first enhanced BRAM structure;

[0042] Reading a row of data from the first enhanced BRAM structure using an interface circuit connected to the first enhanced BRAM structure, and writing the data back to the second enhanced BRAM structure alternately in odd and even positions;

[0043] Using the second enhanced BRAM structure to call an addition microinstruction, perform an addition operation, and store the addition operation result in the second enhanced BRAM structure;

[0044] Reading a row of data from the second enhanced BRAM structure using an interface circuit connected to the second enhanced BRAM structure, and writing the data back to the first enhanced BRAM structure in alternating odd and even positions;

[0045] The addition microinstructions are called in sequence using the first enhanced BRAM structure and the second enhanced BRAM structure, and data is transmitted through the interface circuit connected thereto until the result is stored in the same column of the corresponding enhanced BRAM structure.

[0046] According to the specific embodiments provided in this application, this application has the following technical effects:

[0047] The present application provides an FPGA-based storage and computing integrated circuit and device, which reads data through BRAM and transmits the read data to the bit-serial processing element (PE); the bit-serial processing element performs addition or multiplication on the read data and transmits the final result to the BRAM by turning on the write enable signal of the BRAM and activating the corresponding row. The present application directly connects the storage column of the BRAM to the bit-serial processing element, without going through a complex cache hierarchy and processor pipeline, and can support arithmetic operations of fixed-point numbers of any precision, reducing data movement between the storage unit and the computing unit, reducing the pressure on internal routing resources, improving computing throughput, and achieving low latency in data transmission. The FPGA-based storage and computing integrated device provided in the present application enables its BRAM to have dual functions of computing and storage. On the one hand, the FPGA contains multiple independent BRAMs that can be configured as parallel processing units. Cooperate with other computing units to improve computing throughput. On the other hand, when the BRAM is not used for computing, it can still be used as a traditional storage unit, providing standard storage functions. It not only supports highly parallel computing, but also serves as a memory when idle, reflecting the flexibility and efficiency of computing and storage. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0049] Figure 1 This is a structural diagram of a storage and computing integrated circuit based on FPGA in one embodiment of the present application;

[0050] Figure 2 This is a structural diagram of a mid-bit serial processing unit of a storage and computing integrated circuit based on an FPGA in one embodiment of the present application;

[0051] Figure 3 A schematic diagram of a flow chart showing an addition operation performed by a bit-serial processing unit in an FPGA-based storage and computation integrated circuit;

[0052] Figure 4 A schematic diagram of a multiplication process performed by a bit-serial processing unit in an FPGA-based storage and computing circuit;

[0053] Figure 5 This is a structural diagram of a storage and computing integrated device based on FPGA in one embodiment of the present application;

[0054] Figure 6This is a schematic diagram of the structure of the interface circuit in an FPGA-based storage and computing device;

[0055] Figure 7 A schematic diagram of the flow of convolution operation in an FPGA-based storage and computing device;

[0056] Figure 8 This is a timing diagram of the enhanced BRAM structure in computing mode in an FPGA-based storage and computing device.

[0057] Reference numerals:

[0058] 101-bit serial processing unit, 102-full adder, 103-carry trigger, 104-tag trigger, 105-3-to-1 data selector, 106-2-to-1 data selector, 107-BRAM, 108-microinstruction memory, 109-first enhanced BRAM structure, 110-second enhanced BRAM structure, 111-interface circuit. DETAILED DESCRIPTION

[0059] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0060] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0061] In an exemplary embodiment, Figure 1 As shown, an embodiment of the present application provides an FPGA-based storage and computing integrated circuit, which includes a bit serial processing unit 101 and a BRAM 107. The bit serial processing unit is connected to the storage column of the BRAM.

[0062] Specifically, the number of the bit serial processing units 101 is greater than or equal to one.

[0063] The BRAM 107 is used to read data and transmit the read data to the bit serial processing unit 101 .

[0064] The bit serial processing unit 101 is used to perform operations on the read data and transmit the final result to the BRAM 107 by turning on the write enable signal of the BRAM 107 and activating the corresponding row.

[0065] Specifically, port A of BRAM 107 reads data by activating two storage rows at the same time, and respectively constitutes the high-order part and the low-order part of the read data. Assume that the total bit width of the read data is 20 bits, wherein the high-order part refers to the high 10 bits of the data ([19:10]), and the low-order part refers to the low 10 bits of the data ([9:0]). In addition, the width of the data read can be any width. In this application, the high-order part of the data is transmitted to the input port A of the bit serial processing unit 101, and the low-order part is transmitted to the input port B of the bit serial processing unit 101. After the calculation is completed, the processing result is written back to BRAM 107 from port B of BRAM 107.

[0066] like Figure 2 As shown, the bit serial processing unit 101 includes: a full adder 102 , a carry flip-flop 103 , a 3-to-1 data selector 105 , a 2-to-1 data selector 106 and a tag flip-flop 104 .

[0067] The full adder 102 is used to receive the read data, perform addition operation, transmit the carry data to the carry flip-flop 103, and transmit the sum bit data to the 3-to-1 data selector 105. The full adder 102 uses a gate circuit to perform addition operation.

[0068] The carry flip-flop 103 is used to store carry data and transmit the carry data to the full adder 102 and the 3-to-1 data selector 105 .

[0069] The tag trigger 104 is used to perform a multiplication operation according to the low-order portion of the read data and store the binary bit data of the multiplier.

[0070] The 3-to-1 data selector 105 is used to select different data sources of operation results and output the operation results to the 2-to-1 data selector 106; the different data sources of the operation results include: input data, sum bit data and carry data; the operation results include: addition operation results and multiplication operation results.

[0071] The 2-to-1 data selector 106 is used to select different data sources of the final result, output the final result, and write it back to the BRAM 107; the different data sources of the final result include: the operation result output by the 3-to-1 data selector and the binary bit data.

[0072] In an exemplary embodiment, the present application provides a bit-serial processing unit 101 (Processing Element, PE) for supporting basic arithmetic operations such as addition and multiplication, including: a full adder 102 using gate circuits to implement the addition of two binary bits while considering the carry data; a carry trigger 103 is used to save the carry signal so as to participate in the calculation of the next clock cycle; a tag trigger 104 is used for multiplication operations to save the binary bits of the multiplier; a 3-to-1 data selector 105 is used to select different data sources for the operation results: input data (Din), sum bit (Sum) and carry (Cin); a 2-to-1 data selector 106 is used to judge the operation steps in the multiplication operation and select different data sources: the operation result output by the 3-to-1 data selector and the binary bit of a certain operand.

[0073] like Figure 3 As shown, the process of performing the addition operation by the bit serial processing unit 101 includes the following steps S11-S15:

[0074] S11: Get two n-bit source operands from the read port of the same column of the BRAM 107; n is the total number of binary bits. The two n-bit source operands are stored in the same column of the dual-port BRAM 107; where n represents the number of binary bits of the source operands.

[0075] S12: Calculate the least significant bits of the two n-bit source operands bit by bit to obtain the position i of the currently traversed binary bit. Simultaneously, calculate the least significant bits (i=0) of the two source operands bit by bit. Where i represents the position of the currently traversed binary bit. Specifically, two memory rows are simultaneously activated through port A of BRAM 107. At this time, the two memory rows respectively store the least significant bits of the two source operands.

[0076] S13: Determine the position of the currently traversed binary digit and the total number of binary digits.

[0077] S14: If the position of the currently traversed binary bit is less than the total number of binary bits, the two n-bit source operands are transferred to the bit-serial processing unit 101 for addition, and the sum bit of the addition result is written back to the BRAM 107; if the addition result generates a carry data, it is transferred to the carry flip-flop 103 for use in the next clock cycle. The two source operands are read simultaneously from port A of the BRAM 107 and transferred to the PE connected to the storage column for addition. After each two-bit binary addition operation, the current sum bit is written back to the BRAM 107 through port B of the BRAM 107. If a carry is generated, it is transferred to the carry flip-flop 103, and the value of the carry flip-flop 103 is updated for use in the next clock cycle, and the addition operation of the next binary bit i++ in the two source operands is performed.

[0078] S15: If the position of the currently traversed binary bit is greater than or equal to the total number of binary bits, the carry of the most significant bit is written back to BRAM 107. At this point, all binary bits of the source operands have been traversed, and the carry generated by the addition of the most significant bits of the two source operands is written back to BRAM 107.

[0079] During addition, tag flip-flop 104 does not participate. During each clock cycle, operands A and B are first read simultaneously from BRAM 107 and transmitted to full adder 102. The carry bit is then transmitted to carry flip-flop 103 for use in the next clock cycle. The sum bit, Sum, is then transmitted to 1-of-3 data selector 105. In the circuit, the Predication signal controls whether the value in tag flip-flop 104 is used as a decision signal. Bit-serial addition does not require the Predication signal and can be set to 0. The WPS signal serves as the write enable signal for BRAM 107.

[0080] like Figure 4 As shown, the process of the multiplication operation performed by the bit serial processing unit 101 is S21-S25:

[0081] S21: Store two n-bit source operands into the same column of the BRAM 107; add 2n rows for storing the multiplication result R; initialize the 2n rows to 0; and take n as the total number of binary bits.

[0082] S22: Load the multiplier from the least significant bit i into the tag flip-flop 104 bit by bit to obtain the position i of the binary bit of the multiplier corresponding to the two storage rows currently activated simultaneously.

[0083] S23: Determine the positions of the binary bits of the multipliers corresponding to the two storage rows currently activated simultaneously and the size of the total number of binary bits.

[0084] S24: If the positions of the binary bits of the multipliers corresponding to the two storage rows currently activated are less than the total number of binary bits, it is determined whether the input signal (Tag) of the tag trigger 104 is 1; the input signal is the binary bit of the multiplier. If the input signal of the tag trigger 104 is equal to 1, the most significant bit of the multiplicand and the binary bits corresponding to the multiplication result are transmitted to the bit serial processing unit 101 for addition. In the following n cycles, the addition operation of the multiplicand and the multiplication result R is performed bit by bit, where the least significant bit of the multiplication result R is consistent with the position of the multiplier. Specifically, each time the binary bit of the multiplier is loaded into the tag trigger 104, the binary bits corresponding to the multiplicand and the multiplication result R are read from port A of the BRAM 107 at the same time and transmitted to the PE for addition. Among them, the method of simultaneously reading the multiplicand and the multiplication result R is as follows: each time a bit of the multiplier is loaded into the tag trigger 104, the position of reading the multiplicand still starts from the least significant bit, and the position of reading the multiplication result R remains consistent with the position of the currently loaded multiplier.

[0085] If the addition operation results in a carry, it is transferred to the carry flip-flop 103. If the input signal of the tag flip-flop 104 is not equal to 1, the corresponding bit of the multiplication result is written back to the BRAM 107. In the following n cycles, the corresponding bit of the multiplication result R is retained and written back to the BRAM 107. Specifically, if a bit of the multiplier is 0, the addition operation is not performed, that is, the corresponding bit of the multiplication result R is retained and written back to the BRAM 107.

[0086] S25: If the positions of the binary bits of the multipliers corresponding to the two storage rows currently activated are greater than or equal to the total number of binary bits, the data in the carry trigger 103 is written back to the most significant bit of the multiplication result; the most significant bit of the multiplicand is added to the binary bit corresponding to the multiplication result to generate carry data, which is written back to the BRAM 107.

[0087] During a multiplication operation, a tag flip-flop 104 is involved, and its value determines whether the multiplication result R is updated and written back. A binary bit of the multiplier serves as the input signal to the tag flip-flop 104. If the input signal is 1, the multiplicand and the multiplication result are added, and the updated multiplication result is written back to the BRAM 107. If the input signal is 0, the multiplication result is directly written back to the BRAM 107.

[0088] This application proposes an FPGA-based storage and computing integrated circuit, which improves the existing BRAM 107 device in the FPGA and adds logic circuits to the BRAM 107 in the FPGA, so that the BRAM 107 has computing capabilities and can support arithmetic operations of fixed-point numbers of any precision, reduce data movement between storage units and computing units, reduce internal routing resource pressure, and utilize its high parallelism and distributed characteristics to enhance the performance of the existing FPGA logic resources while maintaining them, thereby improving computing throughput and achieving acceleration.

[0089] In another exemplary embodiment, Figure 5 As shown, the present application provides an FPGA-based storage and computing integrated device including: a microinstruction memory 108, a first enhanced BRAM structure 109, a second enhanced BRAM structure 110 and two interface circuits 111. The first enhanced BRAM structure 109 and the second enhanced BRAM structure 110 are the FPGA-based storage and computing integrated circuit;

[0090] The microinstruction memory 108 is used to store microinstructions; each microinstruction is a combination of all control signals that the first enhanced BRAM structure 109 and the second enhanced BRAM structure 110 need to execute with the interface circuit 111 within one clock cycle; the microinstructions include: addition microinstructions and multiplication microinstructions.

[0091] The first enhanced BRAM structure 109 and the second enhanced BRAM structure 110 are connected to the interface circuit 111 respectively; the two interface circuits 111 are used to transmit data between the first enhanced BRAM structure 109 and the second enhanced BRAM structure 110. The read port of the first enhanced BRAM structure 109 is connected to the input end of the interface circuit 111, and the output end of the interface circuit 111 is connected to the input end Din of the bit serial processing unit 101 in the second enhanced BRAM structure 110.

[0092] In one embodiment, the present application provides an FPGA-based storage and computing integrated device, wherein the FPGA-based storage and computing integrated device is a storage and computing integrated architecture that supports convolution operations, wherein the microinstruction memory 108 is used to store microinstructions, and each microinstruction defines all control signal combinations that need to be executed by the functional components within its architecture within one clock cycle; the first enhanced BRAM structure 109 and the second enhanced BRAM structure 110 are both coordinated by BRAM 107 and PE, wherein a PE is set for each storage column of BRAM 107 to directly process the data read on the column; the interface circuit 111 allows data transmission between the first enhanced BRAM structure 109 and the second enhanced BRAM structure 110, and each BRAM 107 is connected to the interface circuit 111, thereby realizing reduction operations.

[0093] Specifically, the first enhanced BRAM structure 109 and the second enhanced BRAM structure 110 both include a storage mode and a calculation mode;

[0094] When the first enhanced BRAM structure 109 and the second enhanced BRAM structure 110 are in storage mode, the first enhanced BRAM structure 109 and the second enhanced BRAM structure 110 remain consistent and perform read and write operations.

[0095] When the first enhanced BRAM structure 109 and the second enhanced BRAM structure 110 are in computing mode, the first enhanced BRAM structure 109 and the second enhanced BRAM structure 110 are used to control the bit-serial processing unit 101 to perform bit-serial addition or multiplication operations according to microinstructions, that is, the BRAM and PE work together to perform bit-serial addition and multiplication operations.

[0096] like Figure 6 As shown, the interface circuit is used to extract odd-bit and even-bit data from the first enhanced BRAM structure 109 and the second enhanced BRAM structure 110, and control the clock cycle through the clock signal to alternately output the odd-bit and even-bit data.

[0097] The present application adopts a smaller-scale interface circuit and implements data flow control through a simple logic structure (such as a selector), which simplifies the signal transmission path. The scale of the interface circuit will not increase exponentially with the increase of the BRAM 107 port width, reducing the utilization rate of LUT resources in the FPGA, improving resource utilization, reducing resource occupation, simplifying the signal transmission path, and achieving low power consumption of data transmission.

[0098] like Figure 7 As shown, the FPGA-based storage and computing integrated device is used to perform convolution operations, specifically including S31-S37:

[0099] S31: Obtain a weight vector and an input vector; and quantize and transpose the weight vector and the input vector.

[0100] Specifically, data preprocessing is performed on the weight vector and the input vector, and each vector is quantized into n-bit binary and transposed for storage.

[0101] S32: Align the weight vector and the input vector and store them in the first enhanced BRAM structure 109. In storage mode, the transposed weight vector and the input vector are stored in the BRAM 107 array of the first enhanced BRAM structure 109, where each n-bit weight and its corresponding input vector element are stored in the same column.

[0102] S33: Using the multiplication microinstruction called by the first enhanced BRAM structure 109, the weight vector and the input vector are multiplied, and the multiplication result is aligned and stored in the first enhanced BRAM structure 109. The multiplication microroutine is called from the microinstruction memory 108 to perform n-bit binary multiplication, and the multiplication result is written back to the first enhanced BRAM structure 109.

[0103] S34: Using the interface circuit 111 connected to the first enhanced BRAM structure 109, read a row of data from the first enhanced BRAM structure 109 and write it back to the second enhanced BRAM structure 110 in alternating odd and even positions. The interface circuit 111 connected to the first enhanced BRAM structure 109 is responsible for data transmission on its bit lines.

[0104] S35: Perform an addition operation using the addition microinstruction called by the second enhanced BRAM structure 110, and store the addition operation result in the second enhanced BRAM structure 110. The addition microinstruction is called from the microinstruction memory 108 to perform n-bit binary addition, and the addition operation result is written back to the dual-port second enhanced BRAM structure 110.

[0105] S36: using the interface circuit 111 connected to the second enhanced BRAM structure 110 to read a row of data from the second enhanced BRAM structure 110, and writing the data back to the first enhanced BRAM structure 109 alternately in odd and even positions.

[0106] S37: Using the first enhanced BRAM structure 109 and the second enhanced BRAM structure 110 to sequentially call addition microinstructions, and transmit data through the interface circuit 111 connected thereto, until the result is stored in the same column of the corresponding enhanced BRAM structure.

[0107] like Figure 8As shown, data is read from the first enhanced BRAM structure 109 and port A of the BRAM 107 in the first enhanced BRAM structure 109. Then, the PE obtains the read data and writes the final result to the BRAM 107 by turning on the write enable signal of port B of the BRAM 107 and activating the corresponding row. A timing diagram of the first enhanced BRAM structure 109 in the computing mode is obtained.

[0108] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0109] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above examples is only intended to help understand the method and core concept of this application. At the same time, for those skilled in the art, based on the concept of this application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A storage and computing integrated circuit based on FPGA, characterized in that: The storage and computing integrated circuit includes: a bit serial processing unit and a BRAM; the bit serial processing unit is connected to the storage column of the BRAM; The BRAM is used to read data and transmit the read data to the bit serial processing unit; The bit serial processing unit is used to perform operations on the read data and transmit the final result to the BRAM by turning on the write enable signal of the BRAM and activating the corresponding row.

2. The FPGA-based storage and computing integrated circuit according to claim 1, characterized in that: The number of bit serial processing units is greater than or equal to one.

3. The FPGA-based storage and computing integrated circuit according to claim 1, characterized in that: The bit serial processing unit includes: a full adder, a carry trigger, a 3-to-1 data selector, a 2-to-1 data selector, and a tag trigger; The full adder is used to receive the read data and perform addition operation; transmit the carry data to the carry trigger, and transmit the sum bit data to the 3-to-1 data selector; The carry trigger is used to store carry data and transmit the carry data to the full adder and the 3-to-1 data selector; The tag trigger is used to perform a multiplication operation according to the low-order part of the read data and save the binary bit data of the multiplier; The 3-to-1 data selector is used to select different data sources of operation results and output the operation results to the 2-to-1 data selector; the different data sources of the operation results include: input data, sum bit data and carry data; the operation results include: addition operation results and multiplication operation results; The 2-to-1 data selector is used to select different data sources of the final result, output the final result, and write it back to the BRAM; the different data sources of the final result include: the operation result and binary bit data output by the 3-to-1 data selector.

4. The FPGA-based storage and computing integrated circuit according to claim 3, characterized in that: The full adder uses gate circuits to perform addition operations.

5. The FPGA-based storage and computing integrated circuit according to claim 3, characterized in that: The process of the bit serial processing unit performing the addition operation is as follows: Get two n-bit source operands from the read port of the same column of the BRAM; take n as the total number of binary bits; Calculate the least significant bit of the two n-bit source operands bit by bit to get the position i of the current traversal binary bit; Determine the position of the currently traversed binary digit and the total number of binary digits; If the position of the currently traversed binary bit is less than the total number of binary bits, the two n-bit source operands are transferred to the bit serial processing unit for addition, and the sum bit of the addition result is written back to the BRAM; if the addition result generates carry data, it is transferred to the carry flip-flop for use in the next clock cycle; If the position of the currently traversed binary digit is greater than or equal to the total number of binary digits, the carry of the most significant bit is written back to the BRAM.

6. The FPGA-based storage and computing integrated circuit according to claim 3, characterized in that: The process of the bit serial processing unit performing multiplication operation is as follows: Store two n-bit source operands in the same column of BRAM; add 2n rows to store the product R; initialize 2n rows to 0; and set n as the total number of binary bits. Load the multiplier into the tag flip-flop bit by bit from the least significant bit to obtain the position i of the binary bit that currently activates the multipliers corresponding to the two storage rows; Determine the position of the binary bits corresponding to the multipliers of the two storage rows currently activated simultaneously and the size of the total number of binary bits; If the positions of the binary bits of the multipliers corresponding to the two storage rows currently activated are less than the total number of binary bits, then determine whether the input signal of the tag trigger is 1; if the input signal of the tag trigger is equal to 1, then perform an addition operation on the most significant bit of the multiplicand and the binary bit corresponding to the multiplication result; If the addition operation results in a carry data, it is transferred to the carry flip-flop; if the input signal of the tag flip-flop is not equal to 1, the corresponding bit of the multiplication operation result is written back to the BRAM; The input signal is the binary bit of the multiplier; If the positions of the binary bits of the multipliers corresponding to the two storage rows currently activated are greater than or equal to the total number of binary bits, the data in the carry trigger is written back to the most significant bit of the multiplication result; the most significant bit of the multiplicand is added to the binary bit corresponding to the multiplication result to generate carry data, which is written back to the BRAM.

7. A storage and computing integrated device based on FPGA, characterized in that: The FPGA-based storage and computing integrated device includes: a microinstruction memory, a first enhanced BRAM structure, a second enhanced BRAM structure, and two interface circuits; the first enhanced BRAM structure and the second enhanced BRAM structure are the FPGA-based storage and computing integrated circuit according to any one of claims 1 to 6; The microinstruction memory is used to store microinstructions; each microinstruction is a combination of all control signals required to be executed by the first enhanced BRAM structure and the second enhanced BRAM structure and the interface circuit within one clock cycle; the microinstructions include: addition microinstructions and multiplication microinstructions; The first enhanced BRAM structure and the second enhanced BRAM structure are correspondingly connected to the interface circuit; the two interface circuits are used to transmit data between the first enhanced BRAM structure and the second enhanced BRAM structure.

8. The FPGA-based storage and computing integrated device according to claim 7, characterized in that: The first enhanced BRAM structure and the second enhanced BRAM structure both include a storage mode and a calculation mode; When the first enhanced BRAM structure and the second enhanced BRAM structure are in a storage mode, the first enhanced BRAM structure and the second enhanced BRAM structure perform read and write operations; When the first enhanced BRAM structure and the second enhanced BRAM structure are in a calculation mode, the first enhanced BRAM structure and the second enhanced BRAM structure are used to control the bit-serial processing unit to perform bit-serial addition or multiplication operations according to microinstructions.

9. The FPGA-based storage and computing integrated device according to claim 7, characterized in that: The interface circuit is used to extract odd-numbered and even-numbered data from the first enhanced BRAM structure and the second enhanced BRAM structure, and control the clock cycle through a clock signal to alternately output the odd-numbered and even-numbered data.

10. The FPGA-based storage and computing integrated device according to claim 7, characterized in that: The FPGA-based storage and computing integrated device is used to perform convolution operations, specifically including: Obtaining a weight vector and an input vector; and quantizing and transposing the weight vector and the input vector; Align the weight vector and the input vector and store them in the first enhanced BRAM structure; Using the multiplication microinstruction called by the first enhanced BRAM structure, multiplying the weight vector and the input vector, and aligning and storing the multiplication result in the first enhanced BRAM structure; Reading a row of data from the first enhanced BRAM structure using an interface circuit connected to the first enhanced BRAM structure, and writing the data back to the second enhanced BRAM structure alternately in odd and even positions; Using the second enhanced BRAM structure to call an addition microinstruction, perform an addition operation, and store the addition operation result in the second enhanced BRAM structure; Reading a row of data from the second enhanced BRAM structure using an interface circuit connected to the second enhanced BRAM structure, and writing the data back to the first enhanced BRAM structure in alternating odd and even positions; The addition microinstructions are called in sequence using the first enhanced BRAM structure and the second enhanced BRAM structure, and data is transmitted through the interface circuit connected thereto until the result is stored in the same column of the corresponding enhanced BRAM structure.

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