Electrothermal simulation and vertical interconnection planning system, method and device for integrated core particles

Abstract

The invention relates to the technical field of integrated circuits, discloses an electrothermal simulation and vertical interconnection planning system, method and device for integrated core particles, and solves the problems of low thermal simulation efficiency, incomplete electrothermal coupling modeling and VIC redundancy. The temperature simulation module is used for performing temperature simulation on core particle packaging based on an effective thermal conductivity model and a thermal resistance and thermal capacity network solver, and the effective thermal conductivity model determines thermal conductivity of different packaging layers through a predefined lookup table; a core particle architecture emulator for performing temperature dependent power consumption analysis in which the temperature dependencies of dynamic power consumption and leakage power consumption are modeled by a temperature scaling function; a vertical interconnect planning module to optimize the number of vertical interconnects (VICs) under signal connectivity, power routing constraints, and thermal integrity constraints; according to the system, through iteration of electrothermal coupling simulation and adjustment of power consumption distribution and VIC planning, the temperature of the core particles is lower than a preset threshold value, and the number of VICs is minimized.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design and provides an electrothermal simulation and vertical interconnection planning system, method and device for integrated core particles. Background Art

[0002] In recent years, as the evolution of Moore's Law has slowed, traditional monolithic integrated circuits have faced significant bottlenecks in performance improvement and manufacturing costs. In this context, chiplet technology has become an important solution for high-performance computing (such as artificial intelligence processors) by decomposing complex functional modules into multiple heterogeneous chips and integrating them using advanced packaging technology. Chiplet technology achieves high-density interconnection through 2.5D interconnect substrates or 3D stacked packaging. The vertical interconnect structures (VICs), including microbumps (μbumps), through-silicon vias (TSVs) and C4 bumps, not only undertake signal transmission and power distribution functions, but also serve as key heat conduction paths that affect overall heat dissipation efficiency.

[0003] However, existing technologies for electrothermal simulation and vertical interconnect planning of chiplets have the following limitations:

[0004] 1. The contradiction between thermal simulation accuracy and efficiency

[0005] The microscopic size of VICs in the core particles (such as μbumps with a diameter of about 20-50μm) requires thermal simulation tools to have refined modeling capabilities. Although traditional finite element method (FEM) tools (such as COMSOL) can accurately capture the thermal conduction effects of VICs, their high meshing complexity causes calculations to take up to several hours, making it difficult to meet the iteration requirements of the early design stage. Rapid thermal analysis tools (such as HotSpot) use coarse-grained modeling and ignore the local thermal conduction characteristics of VICs, resulting in significant temperature prediction errors (for example, errors exceeding 50°C in 3D stacking). Although existing literature has proposed a simplified TSV thermal resistance model, it has not solved the modeling problem of the synergistic effect of multiple types of VICs (μbumps, TSV, C4), which limits its application in heterogeneous packaging.

[0006] 2. One-sidedness of electrothermal coupling analysis

[0007] Existing architecture simulators (such as GEM5[1] and OPU[2]) often use a fixed temperature assumption in their power estimation, without considering the impact of temperature on dynamic power consumption. Studies have shown that when the temperature rises from 25°C to 100°C, short-circuit power consumption increases by 10%-15% due to the extended transistor switching time, resulting in an underestimate of the overall power consumption by approximately 10% (see references [3][4]). In addition, although existing methods (such as reference [5]) introduce a temperature-dependent model for leakage power consumption, they do not establish a nonlinear relationship between dynamic power consumption and temperature, resulting in deviations from power integrity analysis and thermal management strategies.

[0008] 3. Local Optimization and Overdesign of VIC Planning

[0009] Current vertical interconnect planning methods mostly focus on a single constraint (such as signal integrity or thermal integrity) and lack comprehensive optimization of electrical and thermal coupling. For example, references [6][7] proposed improving heat dissipation by adding thermal VICs (Thermal VICs), but did not take into account power transmission requirements, resulting in redundant interconnects (for example, the number of VICs in reference [5] exceeded the actual demand by 21.7%). In addition, although existing EDA tools (such as Floorplet [8]) support chip layout planning, their physical implementation layer does not integrate thermal-electrical synergy analysis, making it difficult to evaluate the coupling effect of VICs on temperature distribution and current density at an early stage, resulting in design iterations and increased costs.

[0010] References:

[0011] [1] N.Binkert et al., "The gem5 simulator," SIGARCH Computer Architecture News, vol.39, p.1-7, Aug.2011.

[0012] [2] Y.Yu et al., "OPU: An FPGA-Based Overlay Processor for Convo lutioualNeural Networks," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.28, no.1, pp.35-47, 2020.

[0013] [3]W.Liao et al.,“Temperature and Supply Voltage Aware Performanceand Power Modeling at Microarchitecture Level,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,Vol.24,no.7,pp.1042-1053,2005.

[0014] [4]K.Wang et al.,“Rethinking Thermal Via Planning with Timing-PowerTemperature Dependence for 3D ICs,”in Proceedings of the 16th Asia and SouthPacific Design Automation Conference,ASPDAC’11,p.261-266,IEEE Press,2011.

[0015] [5]H.Yu et al.,“Thermal Via Allocation for 3D ICs Considering Temporally and Spatially Variant Thermal Power,”in ISLPED’06 Proceedings of the2006 Internatioual Symposium on Low Power Electronics and Design,pp.156-161,2006.

[0016] [6]J.Cong et al.,“Thermal Via Planning for 3-D ICs,”in Proceedings ofthe 2005 IEEE / ACM International Conference on Computer-Aided Design,ICCAD’05,(USA),p.745-752,IEEE Computer Society,2005.

[0017] [7] B.Goplen et al., "Thermal Via Placement in 3D ICs," in Proceedings of the 2005 International Symposium on Physical Design, ISPD'05, (New York, NY, USA), p.167-174, Association for Computing Machinery, 2005.

[0018] [8] S.Chen et al., "Floorplet: Performance-Aware Floorplan Framework for Chiplet Integration," Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.43, p.1638-1649, June 2024. Summary of the Invention

[0019] This technology aims to address the technical issues in existing chiplet design, such as low thermal simulation efficiency and large errors, electro-thermal coupling analysis that does not consider the temperature dependence of dynamic power consumption, and the lack of multi-constraint collaborative optimization in vertical interconnect planning.

[0020] In order to achieve the above-mentioned purpose, the present invention adopts the following technical means:

[0021] The present invention provides an electrothermal simulation and vertical interconnection planning system for integrated chips, comprising:

[0022] The thermal analysis module uses the effective thermal conductivity (ETC) model to model the vertical interconnect structures (VICs) in the chip package, including microbumps, through-silicon vias (TSVs), and C4 bumps. The module divides the package layer into the chip layer, TSV layer, bump layer, and redistribution layer by establishing a thermal macro model based on uniform thermal conductivity, and uses a thermal resistance and capacitance network solver for temperature calculation.

[0023] a core-grain architecture simulator for performing temperature-dependent power analysis, the power analysis including temperature scaling functions for dynamic power and leakage power, wherein the temperature dependence of dynamic power is modeled based on the temperature-dependent characteristics of short-circuit current;

[0024] The vertical interconnect planning module uses mathematical programming to optimize and minimize the number of VICs based on the results of electrothermal coupling analysis while satisfying signal connectivity, power integrity, and maximum temperature constraints.

[0025] The electrothermal iteration module iteratively executes the thermal analysis module and the core grain architecture simulation module until the temperature change converges to a set threshold.

[0026] In the above solution, the implementation method of the thermal analysis module includes the following steps:

[0027] Step (a1): Packaging layer division: the core package structure is divided into a chip layer, a TSV layer, a bump layer, and a redistribution layer according to its physical composition, wherein the TSV layer includes through silicon vias (TSVs), the bump layer includes microbumps and C4 bumps, and the RDL layer includes a grid structure formed by copper wires and copper pillars;

[0028] Step (a2): Effective Thermal Conductivity (ETC) Modeling: Determine the ETC value for each layer based on experimental measurements. The ETC calculation formula is:

[0029]

[0030] Calculated, where h1 is the upper surface heat transfer coefficient, l is the layer height, T1 is the top temperature, T2 is the bottom temperature, T ∞ is the ambient temperature;

[0031] Step (a3): Parameterized ETC lookup table construction: Generate an ETC lookup table (LUT) through experimental measurement for the geometric parameter ranges of μbumps, TSVs, and RDLs. The geometric parameters include the radius and spacing of μbumps, the radius and spacing of TSVs, and the line width and spacing of RDLs.

[0032] Step (a4) constructing a three-dimensional grid thermal resistance and heat capacitance network: mapping the ETC lookup table to a three-dimensional grid model, and calculating the thermal resistance value of each grid cell based on the layer height, grid cell size, and ETC value;

[0033] Step (a5) temperature field solution: solve the thermal resistance and heat capacitance network model through a circuit simulator, and output the three-dimensional temperature field distribution of the chip package.

[0034] In the above solution, the temperature-dependent power consumption analysis of the core-grain architecture simulator includes the following steps:

[0035] Step (b1) Circuit classification and parameterization: divide the circuits in the chiplet architecture into analog circuits, digital functional units, and memories, and define independent temperature scaling functions f for each type of circuit. a 、f FU 、f mem :

[0036] P a (T)=P a (T0)·f a (T, T0)

[0037] P FU (T)=P FU (T0)·f FU (T,T0)

[0038] P mem (T)=P mem (T0)·f mem (T,T0)

[0039] Among them, P a (T), P a (T0) is the temperature of the analog circuit at temperature T and temperature T0, P FU (T), P FU (T0) is the temperature of the digital logic circuit at temperature T and temperature T0, P mem (T), P mem (T0) is the temperature of the memory module at temperature T and temperature T0.

[0040] The leakage power temperature scaling function of the digital functional unit is based on a cubic polynomial model:

[0041]

[0042] Where T0 is the reference temperature, T is the current temperature, α1, α2, α3 are process correlation coefficients,

[0043] The dynamic power consumption temperature scaling function of the digital functional unit is based on the temperature dependence of the short-circuit current and is expressed as:

[0044]

[0045] I peak is the short-circuit current peak, t r and t f They are rise time and fall time respectively. As the temperature increases, t r and t f increases, leading to P sc increases, which in turn increases dynamic power consumption, where V DD is the power supply voltage, f is the circuit operating frequency;

[0046] Step (b2): Basic unit library construction and weighting, select the core unit set C from the process design library basic , including inverters, logic gates and triggers, for each cell j ∈C basic Perform multi-temperature characterization and extract its temperature scaling function

[0047]

[0048] in is the temperature of digital unit j at temperature T and temperature T0, and the weight of each unit in the functional unit is determined by logic synthesis Synthesize the functional unit-level scaling function in the form of a weighted sum:

[0049]

[0050] Step (b3): Global scaling function integration, based on the frequency of occurrence of functional units in the processor and power consumption ratio, calculate the global digital circuit scaling function f FU (T, T0):

[0051]

[0052] Step (b4): Lookup table and interpolation implementation, f FU 、f mem and f a Discretized into a temperature lookup table LUT,

[0053] And in the simulation, the power consumption value at the actual temperature is calculated by linear interpolation;

[0054] In step (b3), during the electrothermal coupling iteration, the power consumption value of each core functional module is dynamically adjusted according to the current temperature field until the temperature distribution converges.

[0055] In the above solution, the implementation method of the vertical interconnection planning module includes the following steps:

[0056] Step (c1) defines the vertical interconnection layer structure: divide the interconnection layer in the package into micro-bump layer L μb , C4 bump layer L C4b and TSV layer L TSV , and determine the maximum current density constraint I of each layer max and manufacturing cost coefficients α, β, and γ;

[0057] Step (c2) Construct a mathematical programming model: Minimizing the total number of interconnections is the objective function

[0058] min αN μb +βN C4b +γN TSV

[0059] Constraints include:

[0060] Signal connectivity constraints: in is the number of vertical interconnections at layer i, is the required number of signal channels, in represents the collection of micro-bump layers, Represents the set of C4 bump layers, represents a collection of through silicon via layers;

[0061] Current density constraint: The current of all bumps and through-silicon vias I≤I max , determined by calculating the current distribution of the power supply network;

[0062] Thermal integrity constraint: Based on the temperature distribution output by the thermal analysis module, ensure the maximum temperature T of all core particles max ≤T t , where T t is the preset threshold;

[0063] Step (c3) solving the objective function and the constraints using a mathematical programming solver to generate a vertical interconnection allocation plan for each layer;

[0064] Step (c4) divides the packaging layer into multiple evenly distributed blocks, and distributes vertical interconnections within each block according to the solution results to ensure that the spatial distribution density of microbumps, C4 bumps and through-silicon vias meets the process requirements;

[0065] Step (c5) Verify thermal integrity constraints: Call the thermal analysis module to calculate the core temperature T under the current VIC plan max If it exceeds T t , then increase the number of thermal VIC and solve again until T is satisfied max ≤T t ;

[0066] Step (c6) outputs the final VIC planning scheme.

[0067] In the above solution, the temperature scaling function includes:

[0068] Scaling function for dynamic power consumption based on the effect of temperature on short-circuit current rise / fall times;

[0069] The scaling function of leakage power consumption adopts a cubic polynomial model;

[0070] The scaling functions are divided into three categories according to circuit types: functional units, storage modules and analog circuits, and interpolation calculations are implemented through a lookup table.

[0071] In the above solution, the scaling function of the functional unit is obtained by weighted summation of the temperature dependencies of the basic logic units, and the weight is determined based on the number of logic units in the functional unit and the power consumption ratio.

[0072] In the above scheme, the vertical interconnect planning module models VIC allocation as a mathematical programming problem. The objective function is to minimize the total number of μbumps, C4 bumps, and TSVs. The constraints include:

[0073] The number of signal VICs meets the interconnection protocol requirements;

[0074] The current density of the power supply VIC is lower than the electromigration threshold;

[0075] The number of thermal VICs ensures that the die temperature does not exceed a preset threshold.

[0076] In the above scheme, the solution of the mathematical programming problem includes hierarchical optimization:

[0077] The first round distributes signal and power VIC;

[0078] If the temperature exceeds the threshold, iteratively increase the thermal VIC and recalculate the temperature until the constraint is met.

[0079] The present invention also provides an electrothermal simulation method for an integrated core particle, comprising the following steps:

[0080] a. Generate the equivalent thermal conductivity of the package layer based on the effective thermal conductivity model and calculate the initial temperature distribution using the thermal resistance and heat capacitance network solver;

[0081] b. Use the chiplet architecture simulator to analyze the temperature-dependent power consumption, where dynamic power and leakage power are adjusted by the temperature scaling function;

[0082] c. Iteratively update the temperature and power consumption until convergence, and feed the final temperature back to the vertical interconnect planning module;

[0083] d. Optimize the number of vertical interconnects based on temperature constraints to generate a die layout that meets the electro-thermal performance.

[0084] The present invention also provides a vertical interconnection planning device, comprising:

[0085] Signal VIC allocation unit, which determines the minimum number of signal channels according to the interconnection protocol;

[0086] Power VIC allocation unit, which allocates power and ground VICs based on current density constraints;

[0087] Thermal VIC optimization unit, which increases thermal VIC and recalculates temperature distribution when temperature exceeds the limit;

[0088] The device outputs a VIC layout that meets signal, power, and thermal constraints and minimizes the total number of VICs.

[0089] The integrated chip electrothermal simulation and vertical interconnect planning framework (SYSgen) proposed in this invention has the following significant benefits:

[0090] 1. Efficient and accurate thermal analysis capabilities

[0091] The present invention adopts a thermal macro model combined with a thermal resistance and heat capacitance network solver to significantly improve the efficiency of thermal simulation. By mapping the packaging layer into a heat block with uniform effective thermal conductivity (ETC) and constructing an equivalent thermal network in the vertical direction, compared with the finite element method tool COMSOL, when the core temperature is about 100°C, the simulation speed is increased by 97.77 times, and the maximum temperature error is less than 1.2°C (as shown in Table III). The model supports 2.5D and 3D packaging structures, and can accurately capture the thermal conduction effects of vertical interconnects (VICs) such as microbumps and through-silicon vias (TSVs). For example, by introducing thermal VICs, the temperature of the underlying core can be reduced from 379.23K to 337.97K (Table V), effectively alleviating the thermal bottleneck of 3D stacking.

[0092] 2. Temperature-dependent dynamic power consumption modeling and optimization

[0093] This invention is the first to simultaneously consider the impact of temperature on dynamic power consumption and leakage power consumption in core architecture simulation. Experiments show that when the temperature rises from 25°C to 100°C, the dynamic power consumption increases by 10% to 15% due to the increase in short-circuit current, resulting in an increase of about 10% in total power consumption. By establishing a temperature scaling function based on the basic cell library (such as Formula 6) and combining it with the composition weights of functional units (FUs) (Table IV), accurate modeling of power consumption estimation is achieved. This innovation avoids the over-design of VICs caused by traditional methods that ignore the temperature dependence of dynamic power consumption.

[0094] 3. Comprehensive Optimization of Vertical Interconnection (VIC) Planning

[0095] The present invention minimizes the number of VICs under the constraints of signal integrity, power transmission, and thermal integrity through a mathematical programming model (Formula 7). Compared with the existing technologies [4] and [5], under the same signal routing and maximum temperature constraints, the total number of VICs is reduced by 21.7% and 12.4%, respectively (Table VI). Its advantages stem from a comprehensive analysis of the electrothermal coupling effect and non-uniform power distribution. For example, by optimizing the distribution density of the μbump layer and TSV layer, combined with the built-in I / O protocol library (such as UCIe and HBM), interconnect redundancy is significantly reduced.

[0096] 4Support modular simulation of core particle characteristics

[0097] This invention integrates a dedicated coregrain function library, supports protocol-based interconnects (such as PCIe and UCIe) and high-bandwidth memory (HBM) modeling, and is compatible with multiple process parameters such as TSMC28 and SMIC40. Through iterative coupling of event-driven simulation and thermal analysis (with a temperature difference convergence threshold of 0.1K), a steady-state power consumption-temperature solution is achieved within 10 iterations, providing rapid layout evaluation in the early design stages.

[0098] In summary, the present invention significantly improves the efficiency and reliability of chip design through thermal model acceleration, precise electrothermal coupling modeling, and VIC planning optimization, providing a low-power, high-thermal integrity solution for high-performance AI computing processors. BRIEF DESCRIPTION OF THE DRAWINGS

[0099] Figure 1 Package structure diagram, where (a) is a 2.5D package structure and (b) is a 3D package structure. The VICs are aligned for reference only; they may be misaligned during the manufacturing process.

[0100] Figure 2 Temperature distribution comparison diagram, where (a) is the vertical temperature distribution of the 3D integrated circuit with VICs, (b) is the vertical temperature distribution of the 3D integrated circuit without VICs, (c) is the bottom surface temperature distribution of Die3 (the third chip from top to bottom) with VICs, and (d) is the bottom surface temperature distribution of Die3 without VICs;

[0101] Figure 3 This is an overview of the framework of the present invention;

[0102] Figure 4 Thermal macro model and its application in 3D integration;

[0103] Figure 5 The temperature scaling curve of the functional unit is shown in Figure 1, where (a) is the dynamic power consumption temperature scaling of the functional unit in the TSMC28 process, and (b) is the leakage power consumption temperature scaling of the functional unit in the TSMC28 process.

[0104] Figure 6 Table I shows the structural parameters of the 2.5D and 3D integration cases;

[0105] Figure 7 Table II shows the execution time comparison of the macro model + thermal resistance and thermal capacitance network with the gold standard;

[0106] Figure 8 Table III shows the accuracy comparison of the macromodel + thermal resistance and thermal capacitance network with the gold standard;

[0107] Figure 9 Table IV shows the configuration of the basic functional unit (FU) and the leakage power consumption and dynamic power consumption. Approximation error;

[0108] Figure 10 Table V shows the VIC planning results for 2.5D and 3D packages;

[0109] Figure 11 Table VI shows the comparison of VIC planning with previous works. DETAILED DESCRIPTION

[0110] The following is a detailed description of the embodiments of the present invention. Although the present invention will be described and illustrated in conjunction with certain specific embodiments, it should be noted that the present invention is not limited to these embodiments. On the contrary, modifications or equivalent substitutions of the present invention are intended to fall within the scope of the claims of the present invention.

[0111] In addition, in order to better illustrate the present invention, numerous specific details are given in the following detailed description. It will be understood by those skilled in the art that the present invention can also be implemented without these specific details.

[0112] The present invention provides an electrothermal simulation and vertical interconnection planning system for integrated chips, comprising:

[0113] The thermal analysis module uses the effective thermal conductivity (ETC) model to model the vertical interconnect structures (VICs) in the chip package, including microbumps, through-silicon vias (TSVs), and C4 bumps. The module divides the package layer into the chip layer, TSV layer, bump layer, and redistribution layer by establishing a thermal macro model based on uniform thermal conductivity, and uses a thermal resistance and capacitance network solver for temperature calculation.

[0114] a core-grain architecture simulator for performing temperature-dependent power analysis, the power analysis including temperature scaling functions for dynamic power and leakage power, wherein the temperature dependence of dynamic power is modeled based on the temperature-dependent characteristics of short-circuit current;

[0115] The vertical interconnect planning module uses mathematical programming to optimize and minimize the number of VICs based on the results of electrothermal coupling analysis while satisfying signal connectivity, power integrity, and maximum temperature constraints.

[0116] The electrothermal iteration module iteratively executes the thermal analysis module and the core grain architecture simulation module until the temperature change converges to a set threshold.

[0117] In the above solution, the implementation method of the thermal analysis module includes the following steps:

[0118] Step (a1): Packaging layer division: the core package structure is divided into a chip layer, a TSV layer, a bump layer, and a redistribution layer according to its physical composition, wherein the TSV layer includes through silicon vias (TSVs), the bump layer includes microbumps and C4 bumps, and the RDL layer includes a grid structure formed by copper wires and copper pillars;

[0119] Step (a2): Effective Thermal Conductivity (ETC) Modeling: Determine the ETC value for each layer based on experimental measurements. The ETC calculation formula is:

[0120]

[0121] Calculated, where h1 is the upper surface heat transfer coefficient, l is the layer height, T1 is the top temperature, T2 is the bottom temperature, T ∞ is the ambient temperature;

[0122] Step (a3): Parameterized ETC lookup table construction: Generate an ETC lookup table (LUT) through experimental measurement for the geometric parameter ranges of μbumps, TSVs, and RDLs. The geometric parameters include the radius and spacing of μbumps, the radius and spacing of TSVs, and the line width and spacing of RDLs.

[0123] Step (a4) constructing a three-dimensional grid thermal resistance and heat capacitance network: mapping the ETC lookup table to a three-dimensional grid model, and calculating the thermal resistance value of each grid cell based on the layer height, grid cell size, and ETC value;

[0124] Step (a5) temperature field solution: solve the thermal resistance and heat capacitance network model through a circuit simulator, and output the three-dimensional temperature field distribution of the chip package.

[0125] In the above solution, the temperature-dependent power consumption analysis of the core-grain architecture simulator includes the following steps:

[0126] Step (b1) Circuit classification and parameterization: divide the circuits in the chiplet architecture into analog circuits, digital functional units, and memories, and define independent temperature scaling functions f for each type of circuit. a 、f FU 、f mem :

[0127] P a (T)=P a (T0)·f a (T,T0)

[0128] P FU (T)=P FU (T0)·f FU (T,T0)

[0129] P mem (T)=Pmem (T0)·f mem (T,T0)

[0130] Among them, P a (T), P a (T0) is the temperature of the analog circuit at temperature T and temperature T0, P FU (T), P FU (T0) is the temperature of the digital logic circuit at temperature T and temperature T0, P mem (T), P mem (T0) is the temperature of the memory module at temperature T and temperature T0.

[0131] The leakage power temperature scaling function of the digital functional unit is based on a cubic polynomial model:

[0132]

[0133] Where T0 is the reference temperature, T is the current temperature, α1, α2, α3 are process correlation coefficients,

[0134] The dynamic power consumption temperature scaling function of the digital functional unit is based on the temperature dependence of the short-circuit current and is expressed as:

[0135]

[0136] I peak is the short-circuit current peak, t r and t f They are rise time and fall time respectively. As the temperature increases, t r and t f increases, leading to P sc increases, which in turn increases dynamic power consumption, where V DD is the power supply voltage, f is the circuit operating frequency;

[0137] Step (b2): Basic unit library construction and weighting, select the core unit set C from the process design library basic , including inverters, logic gates and triggers, for each cell j ∈C basic Perform multi-temperature characterization and extract its temperature scaling function

[0138]

[0139] in is the temperature of digital unit j at temperature T and temperature T0, and the weight of each unit in the functional unit is determined by logic synthesis Synthesize the functional unit-level scaling function in the form of a weighted sum:

[0140]

[0141] Step (b3): Global scaling function integration, based on the frequency of occurrence of functional units in the processor and power consumption ratio, calculate the global digital circuit scaling function f FU (T, T0):

[0142]

[0143] Step (b4): Lookup table and interpolation implementation, f FU 、f mem and f a Discretized into a temperature lookup table LUT,

[0144] And in the simulation, the power consumption value at the actual temperature is calculated by linear interpolation;

[0145] In step (b3), during the electrothermal coupling iteration, the power consumption value of each core functional module is dynamically adjusted according to the current temperature field until the temperature distribution converges.

[0146] In the above solution, the implementation method of the vertical interconnection planning module includes the following steps:

[0147] Step (c1) defines the vertical interconnection layer structure: divide the interconnection layer in the package into micro-bump layer L μb , C4 bump layer L C4b and TSV layer L TSV , and determine the maximum current density constraint I of each layer max and manufacturing cost coefficients α, β, and γ;

[0148] Step (c2) Construct a mathematical programming model: Minimizing the total number of interconnections is the objective function

[0149] min αN μb +βN C4b +γN TSV

[0150] Constraints include:

[0151] Signal connectivity constraints: in is the number of vertical interconnections at layer i, is the required number of signal channels, in represents the collection of micro-bump layers, Represents the set of C4 bump layers, represents a collection of through silicon via layers;

[0152] Current density constraint: The current of all bumps and through-silicon vias I≤Imax , determined by calculating the current distribution of the power supply network;

[0153] Thermal integrity constraint: Based on the temperature distribution output by the thermal analysis module, ensure the maximum temperature T of all core particles max ≤T t , where T t is the preset threshold;

[0154] Step (c3) solving the objective function and the constraints using a mathematical programming solver to generate a vertical interconnection allocation plan for each layer;

[0155] Step (c4) divides the packaging layer into multiple evenly distributed blocks, and distributes vertical interconnections within each block according to the solution results to ensure that the spatial distribution density of microbumps, C4 bumps and through-silicon vias meets the process requirements;

[0156] Step (c5) Verify thermal integrity constraints: Call the thermal analysis module to calculate the core temperature T under the current VIC plan max If it exceeds T t , then increase the number of thermal VIC and solve again until T is satisfied max ≤T t ;

[0157] Step (c6) outputs the final VIC planning scheme.

[0158] In the above solution, the temperature scaling function includes:

[0159] Scaling function for dynamic power consumption based on the effect of temperature on short-circuit current rise / fall times;

[0160] The scaling function of leakage power consumption adopts a cubic polynomial model;

[0161] The scaling functions are divided into three categories according to circuit types: functional units, storage modules and analog circuits, and interpolation calculations are implemented through a lookup table.

[0162] In the above solution, the scaling function of the functional unit is obtained by weighted summation of the temperature dependencies of the basic logic units, and the weight is determined based on the number of logic units in the functional unit and the power consumption ratio.

[0163] In the above scheme, the vertical interconnect planning module models VIC allocation as a mathematical programming problem. The objective function is to minimize the total number of μbumps, C4 bumps, and TSVs. The constraints include:

[0164] The number of signal VICs meets the interconnection protocol requirements;

[0165] The current density of the power supply VIC is lower than the electromigration threshold;

[0166] The number of thermal VICs ensures that the die temperature does not exceed a preset threshold.

[0167] In the above scheme, the solution of the mathematical programming problem includes hierarchical optimization:

[0168] The first round distributes signal and power VIC;

[0169] If the temperature exceeds the threshold, iteratively increase the thermal VIC and recalculate the temperature until the constraint is met.

[0170] The present invention also provides an electrothermal simulation method for an integrated core particle, comprising the following steps:

[0171] a. Generate the equivalent thermal conductivity of the package layer based on the effective thermal conductivity model and calculate the initial temperature distribution using the thermal resistance and heat capacitance network solver;

[0172] b. Use the chiplet architecture simulator to analyze the temperature-dependent power consumption, where dynamic power and leakage power are adjusted by the temperature scaling function;

[0173] c. Iteratively update the temperature and power consumption until convergence, and feed the final temperature back to the vertical interconnect planning module;

[0174] d. Optimize the number of vertical interconnects based on temperature constraints to generate a die layout that meets the electro-thermal performance.

[0175] The present invention also provides a vertical interconnection planning device, comprising:

[0176] Signal VIC allocation unit, which determines the minimum number of signal channels according to the interconnection protocol;

[0177] Power VIC allocation unit, which allocates power and ground VICs based on current density constraints;

[0178] Thermal VIC optimization unit, which increases thermal VIC and recalculates temperature distribution when temperature exceeds the limit;

[0179] The device outputs a VIC layout that meets signal, power, and thermal constraints and minimizes the total number of VICs.

[0180] Example

[0181] To facilitate those skilled in the art to better understand the technical solution of the present invention, the relevant knowledge of the present invention is further explained:

[0182] 1. Prerequisite Knowledge

[0183] A. Advanced Packaging and Vertical Interconnect

[0184] Packaging plays a crucial role in chip-based designs, affecting system performance, area efficiency, thermal dissipation, and overall cost. Figure 1As shown in Figure 1, advanced packaging technologies are generally divided into two categories: 2.5D packaging, in which die are placed on a silicon interconnect layer (interposer) to achieve high-bandwidth interconnection; and 3D packaging, in which die are stacked vertically and higher area utilization and integration density are achieved through bumps and redistribution layers (RDLs). However, 3D stacking also creates obstacles to vertical heat dissipation, making thermal management a key issue. Fortunately, μbumps, TSVs, and RDLs form heat dissipation channels that promote heat conduction from the lower die to the upper layer. Therefore, an effective strategy to alleviate thermal issues is to introduce additional VICs dedicated to thermal management, called thermal VICs. In addition to thermal considerations, VICs must also meet signal and power routing requirements

[19] . These challenges require the development of a comprehensive VIC planning strategy.

[0185] B. Electrothermal coupling

[0186] Existing studies on electrothermal coupling have mainly focused on leakage power consumption. The study in

[20] describes the dependence of leakage power consumption on temperature using a cubic polynomial:

[0187]

[0188] Among them, the coefficients α1, α2, and α3 will vary with different manufacturing processes. However, ignoring the effect of temperature on dynamic power consumption leads to incomplete electrothermal coupling analysis. Dynamic power consumption consists of switching power consumption and internal power consumption (also known as short-circuit power consumption), among which switching power consumption is independent of temperature. However, short-circuit power consumption P sc Affected by temperature, the specific formula is:

[0189]

[0190] Among them, I sc is the short-circuit current, I peak is the short-circuit current peak, t r and t f and fall time respectively. As the temperature increases, t r and t f increases, leading to P sc In the present invention, the dual effects of temperature on dynamic power consumption and leakage power consumption are taken into consideration.

[0191] C. Thermal Macro Model

[0192] The present invention divides the various layers in 2.5D and 3D packaging into four categories based on the physical structure: chip layer, TSV layer, bump layer and RDL layer. It is particularly important to note that the TSV layer refers to the silicon layer containing TSV, including the base chip and the chip embedded with TSV in the 3D package, as well as the interconnect layer in the 2.5D package. These layers can be mapped into effective heat blocks with uniform effective thermal conductivity (ETC) and calculated in the vertical direction. These effective heat blocks can be stacked and used for temperature calculations in 2.5D and 3D integration, such as Figure 4 Experiments show that for this package, when the die temperature is 100°C, the maximum error of the macro model of the present invention is less than 1.2°C.

[0193] 2. The solution proposed in this invention is referred to as the SYSgen framework

[0194] A. SYSgen Framework Overview

[0195] Figure 3 This paper presents an overview of the proposed SYSgen framework. Based on architectural, partition, and chiplet-level floor plans, the tool performs electrothermal analysis and VIC planning, generates early layouts, and reports on chiplet power consumption and temperature. The framework integrates innovative tools for chiplet architectural simulation, thermal analysis, and VIC planning, which are described in detail in the following sections.

[0196] B. Thermal Analysis

[0197] In this section, we first introduce the implementation of the thermal macromodel. Next, we provide a thermal resistance and capacitance network solver for thermal calculations based on equivalent thermal impedance and capacitance networks, serving as a faster alternative to finite element analysis (FEA) tools such as COMSOL. Finally, we present validation results for the proposed macromodel plus thermal resistance and capacitance network approach.

[0198] 1. Implementation: The effectiveness of the macro model is highly dependent on accurate effective thermal conductivity (ETC). The key to the macro model is to determine ETC, which is affected by different parameters in different packaging layers:

[0199]

[0200] In order to obtain h ubump 、h TSV and h RDL , we conducted experimental measurements with the following assumptions:

[0201] Bumps are made of copper pillars and Sn-Pb solder, with epoxy as the filler material. TSVs are copper pillars encapsulated in a silicon dioxide layer and embedded in the silicon. RDLs are represented by copper lines and copper pillars, forming a uniform grid structure.

[0202] Assuming that bumps and TSVs are evenly distributed within the block, each TSV is directly under a bump. In RDL, there is a TSV at each intersection of copper lines.

[0203] The present invention experiments on a block consisting of a bump / TSV / RDL structure to determine ETCs, using the following geometric parameters and boundary conditions: For the bump layer, the radius of the μbump ranges from 20μm to 50μm, and the pitch ranges from 50μm to 330μm. The radius of the C4 bump ranges from 50μm to 80μm, and the pitch ranges from 100μm to 330μm. The radius of the TSV ranges from 10μm to 40μm, and the pitch ranges from 50μm to 220μm. The width of the RDL ranges from 20μm to 60μm, and the pitch ranges from 20μm to 180μm. The ambient temperature is set to 293.15K, the side surfaces are adiabatic, the top surface is maintained at a fixed temperature of 373.15K, and the bottom surface has a 20W / (m 2 ·K) thermal conductivity.

[0204] ETC is calculated using the following formula:

[0205]

[0206] Where T1 is the top temperature, T2 is the bottom temperature, and T ∞ is the ambient temperature. h1 and l are parameters representing the thermal conductivity of the upper surface and the height of the layer, respectively. The ETC is stored in lookup tables (LUTs) for easy access.

[0207] To solve the thermal macromodel, we developed a thermal resistance and capacitance network solver based on a cube mesh. The modeling here has been simplified to a macromodel with uniform ETC, and the thermal resistance and capacitance of each cube can be directly calculated using the following formula:

[0208] R th =h / (k×A),

[0209] Where h is the height, A is the cross-sectional area, and k is the thermal conductivity of the material. The resulting thermal resistance and capacitance network circuit is then solved using HSPICE.

[0210] 2. Verification: We validate our macromodel + thermal resistance and capacitance network approach on four cases, two of which are 2.5D integration and the other two are 3D integration. The structural parameters of these cases are summarized in Table I. The power density of the core particles ranges from 0.1 to 0.4 W / mm 2. The gold standard is to combine detailed modeling of advanced packaging with COMSOL simulation. The errors of maximum and minimum temperatures, as well as the root mean square error (RMSE) values, are reported in Table III for all four cases. The running time and speedup of our method relative to the gold standard are shown in Table II. Our macro model + thermal resistance and heat capacitance network method achieves an average speedup of 97.77 times relative to the gold standard while keeping the maximum RMSE error below 1.2℃.

[0211] C. Chipgrain Architecture Simulation

[0212] The simulator is based on the OPU, originally developed within the TVM (Tensor Virtual Machine) framework. This invention expands its functionality to support chiplets. Regarding interconnects, it supports protocol-based connections such as UCIe and PCIe, as well as direct connections via wires and VICs. We have also integrated HBM, a technology commonly used in AI computing chips. These features are supported in our simulator as built-in libraries.

[0213] A key feature of the simulator is the temperature-dependent power consumption estimation, which is given by:

[0214] P(T)=P(T0)·f s (T,T0) (5)

[0215] Among them, f s represents the temperature scaling function. Circuits with different structures exhibit different temperature-dependent behaviors

[10] . Therefore, circuits are divided into analog circuits and digital circuits, and digital circuits are further divided into functional units (FUs) and memory blocks. Accordingly, the present invention defines f for analog circuits. a , defines f for the functional unit FU , defines f for the storage component mem .

[0216] Since functional units (FUs) account for most of the power consumption, we explain f in detail. FU The following method is applicable to leakage power consumption and dynamic power consumption. For each functional unit (denoted as FU i ) Develop independent scaling functions It is impractical and unnecessary because it is not feasible to define a unique scaling function for all structural changes, and it is not realistic to determine a new rule for each newly introduced functional unit.

[0217] like Figure 5 As shown, functional units generally exhibit similar temperature-dependent behavior, so f FU It is derived as the weighted sum of a set of basic functional units:

[0218]

[0219] in, Indicates FU i The weight of the processor and its frequency of occurrence and power consumption Since the functional unit is composed of standard units (referred to as units), we use the unit-level scaling function to approximate the combination of Instead of simulating functional units directly. This approach enhances scalability and allows new functional units to be supported as long as their cell composition is known. Instead of using the cell library from the entire process design kit (PDK), we focus on a core subset (C basic ), this subset is sufficient to build any functional unit and is universally included in the PDK. Therefore, we will Approximately:

[0220]

[0221] in, It's a cell j ∈C basic The frequency of each unit in the functional unit Determined by logic synthesis, and This can be achieved by characterizing the cell library at different temperatures.

[0222] As an embodiment, the method of the present invention is implemented on two PDKs (TSMC28 and SMIC40) to demonstrate its feasibility and versatility. The temperature range is set to 273K to 393K. basic Contains combinational circuits from the EPFL benchmark

[25] and manually designed sequential circuits with equivalent functionality. basic Includes 24 cells including inverters, buffers, NAND, NOR, AND, OR, XOR, XNOR gates, D flip-flops, and latches, with two drive strengths for each cell type.

[0223] To determine The library was characterized for the basic cells at different temperatures, assuming a fan-out of 4 (FO4) load capacitance. This process used BTDcell and BTDsim, commercial tools from BTD Tech that are functionally equivalent to SiliconSmart and HSPICE. The leakage power and dynamic power values were extracted from the characterization results (.lib files). To obtain We use Cadence Design Compiler to perform logic synthesis on each functional unit described by Verilog, with a clock frequency of 300MHz and a temperature of 338K. Table IV shows the RMSE and R of our approximation and the true value. 2 These real values are obtained by simulating the synthesized circuit at different temperatures.

[0224] Finally, the general scaling function f is derived according to formula (6): FU Refer to the statistics in OPU, set the frequency of adder and multiplier to 1024, and other functional units to 16. Users can modify n as needed. FU For memory and analog circuits, only the effect of temperature on leakage power consumption is considered because their overall power consumption contribution is relatively low. Cacti 7.0 is integrated to determine the f mem At the same time, f is measured by building a typical analog circuit and performing HPICE simulation a . Scaling function f FU 、f mem and f a Stored as lookup tables (LUTs) in SYSgen.

[0225] D.Electrothermal coupling

[0226] The electrical and thermal coupling is performed through iterative simulations of our core architecture simulator and thermal analyzer, e.g. Figure 3 As shown in Figure 2. Iterations continue until the temperature difference between two consecutive iterations is less than 0.1K. Specifically, the core-grain architecture simulator performs event-driven simulation and reports the power consumption, which is then passed to the thermal analyzer for temperature calculation. The thermal analyzer calculates the temperature based on the structural parameters of the package and then feeds the result back to the core-grain architecture simulator. The power consumption of the architecture components is scaled according to the scaling function f FU 、f mem and f a Adjustments are made and Lagrange interpolation is used when referencing lookup tables (LUTs). In most cases, the iterations converge within ten rounds.

[0227] E. Vertical Interconnection (VIC) Planning

[0228] Furthermore, this paper proposes a comprehensive VIC planning strategy that takes into account power delivery, signal integrity, and thermal management. Our approach aims to minimize the number of VICs while ensuring the following constraints:

[0229] Signal Connectivity: Chips typically connect to other chiplets or external memory. These connections are established via microbumps (μbumps) and RDLs in the silicon interconnect layer (2.5D packaging) or the substrate die (3D packaging). Notably, signals do not pass through TSVs in the silicon interconnect layer / substrate die or the underlying C4 bumps. To ensure reliable interconnection, sufficient VICs must be allocated. These VICs used for signal transmission are called signal VICs.

[0230] Power routing: Power is provided through the C4 bumps and delivered to the die through TSVs and μbumps. Due to electromigration (EM) constraints, each bump and TSV has an upper limit current, represented by I max Power delivery is particularly critical in 3D integration, as the bottom-layer bumps and TSVs must withstand the cumulative current from all upper-layer die. To prevent excessive current density, sufficient VICs must be allocated. We refer to the VICs used for the power / ground network as power VICs.

[0231] Thermal integrity: Thermal integrity issues often arise in 3D packages where die are stacked vertically, making heat dissipation from the bottom die inefficient. As shown in Section 2, μbumps and TSVs can form thermal pathways that transfer heat from the lower layer to the upper layer. Although signal VICs and power VICs inherently contribute to heat dissipation, thermal VICs—that is, VICs used only for thermal management—should be added when necessary to enhance heat dissipation efficiency. Sufficient VICs must be allocated to ensure that the maximum die temperature remains at a predetermined threshold, T t Below, thereby ensuring the functionality of the core particle.

[0232] The present invention represents the μbump layer, C4 bump layer and TSV layer as L ub 、L C4b and L TSV , then the bump and TSV allocation problem can be expressed as the following mathematical programming (MP) problem:

[0233] min αN μb +βN C4b +γN TSV

[0234]

[0235] I≤I max , for all bumps and TSVs

[0236] T max ≤T t , for all chiplets

[0237] Here, the objective function is a combination of the number of μbumps, C4 bumps, and TSVs. α, β, and γ are determined based on the manufacturing cost. is the number of vertical connections (μbumps, C4 bumps, or TSVs) in layer i. is the required number of signal channels. T t is the target temperature. MP is solved by the existing MP solver, and T max The calculations are performed using our thermal model.

[0238] To enhance usability, SYSgen includes pinouts for commonly used I / O ports, including PCIe, UCIe, HBM, and Ethernet, as a built-in library. Signal connection requirements can be determined accordingly.

[0239] 3. Experiments and Case Studies

[0240] We evaluate the performance of the proposed VIC planning strategy in two scenarios: one for 3D integration and the other for 2.5D integration. We report the number of VICs and their corresponding die temperatures. Furthermore, we compare the total number of VICs with existing methods to demonstrate the advantages of SYSgen.

[0241] A. VIC Planning for 2.5D and 3D Packages

[0242] The VIC planning strategy of the present invention was tested on the MCore-OPU architecture, which consists of four logic cores. These four cores are divided into four cores. In the case of 3D packaging, these cores are stacked vertically, while in 2.5D packaging, the core-level floor plan is generated using Floorplet to form a 2×2 array. The cores are interconnected using the UCIe protocol through a ring structure. For memory access, the four cores share a common HBM. The average power density of the four cores is about 0.2W / mm 2 The precise power trace is analyzed by the chiplet architecture simulator of the present invention. The area of each chiplet is 70.76mm 2 .

[0243] The heights of the μbumps, C4 bumps, TSVs, and RDLs were set to 40μm, 100μm, 200μm, and 20μm, respectively. The radii of the μbumps, C4 bumps, and TSVs were defined as 20μm, 50μm, and 20μm, respectively. The maximum current density of the μbumps, TSVs, and C4 bumps was set to 50mA, 20mA, and 200mA, respectively. The RDL line width was 20μm, and the VIC pitch was optimized in SYSgen. The target temperature TtT_tTt was set to 338K.

[0244] When planning VICs, we divide the entire package layer into multiple blocks and assume that VICs are evenly distributed within each block, which means that VICs are evenly distributed within each block, while the density between different blocks may be different.

[0245] The results of the VIC planning of this invention are summarized in Table V. In the case of 3D packaging, Die 1 is the top die, and Die 4 is the bottom die. μbump-Die 1 refers to the μbump layer located just below Die 1. The corresponding die temperatures are shown in Table V. In the case of 3D packaging, the addition of thermal VICs reduced the temperature of Die 4 from 379.23 K to 337.97 K, demonstrating their effectiveness in improving heat dissipation.

[0246] B. Comparison with Previous Work

[0247] We also compare our VIC planning with previous work [5] and [6]. Although the spatial and temporal variations of power are considered, the electro-thermal analysis is not included. In contrast, [4] only considers the effect of temperature on leakage power consumption. Since both studies focus on thermal management in 3D packaging, we restrict our experiments to the 3D packaging case for a fair comparison. For the test case, we scale the die in Section IV-A to a smaller version (32mm 2 ) and a larger version (147mm 2 ), maintain about 0.2W / mm 2 The experiments are conducted in 2-stack and 4-stack configurations, and all other settings remain the same as Section IV-A.

[0248] The experimental results and comparisons are shown in Table VI. For simplicity, we count the total number of μbumps, TSVs, and C4 bumps for comparison. Across the six cases, our VIC planning achieves an average reduction of 21.7% and 12.4% in the number of VICs compared to [5] and [4], respectively. This advantage comes from SYSgen's consideration of the effects of non-uniform power distribution and temperature on leakage and dynamic power consumption.

[0249] Summarize

[0250] In this paper, we propose SYSgen, a framework for VIC planning under electro-thermal constraints. We provide a core architecture simulator that enables accurate location-based temperature-dependent power consumption analysis and supports core-specific features such as UCIe and HBM. In addition, we build an efficient thermal tool that simplifies the complex modeling of VICs. The proposed thermal solver achieves a 97.77x speedup compared to COMSOL with a maximum error of less than 1.2°C at a core temperature of approximately 100°C. Compared to [5] and [4], our VIC planning reduces the number of VICs by 21.7% and 12.4%, respectively.

Claims

1. An integrated chip electrothermal simulation and vertical interconnection planning system, characterized in that: include: The thermal analysis module uses the effective thermal conductivity (ETC) model to model the vertical interconnect structures (VICs) in the chip package, including microbumps, through-silicon vias (TSVs), and C4 bumps. The module divides the package layer into the chip layer, TSV layer, bump layer, and redistribution layer by establishing a thermal macro model based on uniform thermal conductivity, and uses a thermal resistance and capacitance network solver for temperature calculation. a core-grain architecture simulator for performing temperature-dependent power analysis, the power analysis including temperature scaling functions for dynamic power and leakage power, wherein the temperature dependence of dynamic power is modeled based on the temperature-dependent characteristics of short-circuit current; The vertical interconnect planning module uses mathematical programming to optimize and minimize the number of VICs based on the results of electrothermal coupling analysis while satisfying signal connectivity, power integrity, and maximum temperature constraints. The electrothermal iteration module iteratively executes the thermal analysis module and the core grain architecture simulation module until the temperature change converges to a set threshold.

2. The system according to claim 1, wherein: The implementation method of the thermal analysis module includes the following steps: Step (a1): Packaging layer division: the core package structure is divided into a chip layer, a TSV layer, a bump layer, and a redistribution layer according to its physical composition, wherein the TSV layer includes through silicon vias (TSVs), the bump layer includes microbumps and C4 bumps, and the RDL layer includes a grid structure formed by copper wires and copper pillars; Step (a2): Effective Thermal Conductivity (ETC) Modeling: Determine the ETC value for each layer based on experimental measurements. The ETC calculation formula is: Calculated, where h1 is the upper surface heat transfer coefficient, l is the layer height, T1 is the top temperature, T2 is the bottom temperature, T ∞ is the ambient temperature; Step (a3): Parameterized ETC lookup table construction: Generate an ETC lookup table (LUT) through experimental measurement for the geometric parameter ranges of μbumps, TSVs, and RDLs. The geometric parameters include the radius and spacing of μbumps, the radius and spacing of TSVs, and the line width and spacing of RDLs. Step (a4) constructing a three-dimensional grid thermal resistance and heat capacitance network: mapping the ETC lookup table to a three-dimensional grid model, and calculating the thermal resistance value of each grid cell based on the layer height, grid cell size, and ETC value; Step (a5) temperature field solution: solve the thermal resistance and heat capacitance network model through a circuit simulator, and output the three-dimensional temperature field distribution of the chip package.

3. The system according to claim 1, wherein: The temperature-dependent power consumption analysis of the core-grain architecture simulator comprises the following steps: Step (b1) Circuit classification and parameterization: divide the circuits in the chiplet architecture into analog circuits, digital functional units, and memories, and define independent temperature scaling functions f for each type of circuit. a 、f FU 、f mem : P a (T)=P a (T0)·f a (T,T0) P FU (T)=P FU (T0)·f FU (T,T0) P mem (T)=P mem (T0)·f mem (T,T0) Among them, P a (T), P a (T0) is the temperature of the analog circuit at temperature T and temperature T0, P FU (T), P FU (T0) is the temperature of the digital logic circuit at temperature T and temperature T0, P mem (T), P mem (T0) is the temperature of the memory module at temperature T and temperature T0; The leakage power temperature scaling function of the digital functional unit is based on a cubic polynomial model: Where T0 is the reference temperature, T is the current temperature, α1, α2, α3 are process correlation coefficients, The dynamic power consumption temperature scaling function of the digital functional unit is based on the temperature dependence of the short-circuit current and is expressed as: I peak is the short-circuit current peak, t r and t f They are rise time and fall time respectively. As the temperature increases, t r and t f increases, leading to P sc increases, which in turn increases dynamic power consumption, where V DD is the power supply voltage, f is the circuit operating frequency; Step (b2): Basic unit library construction and weighting, select the core unit set C from the process design library basic , including inverters, logic gates and triggers, for each cell j ∈C basic Perform multi-temperature characterization and extract its temperature scaling function in is the temperature of digital unit j at temperature T and temperature T0, and the weight of each unit in the functional unit is determined by logic synthesis Synthesize the functional unit-level scaling function in the form of a weighted sum: Step (b3): Global scaling function integration, based on the frequency of occurrence of functional units in the processor and power consumption ratio, calculate the global digital circuit scaling function f FU (T, T0): Step (b4): Lookup table and interpolation implementation, f FU 、f mem and f a Discretized into a temperature lookup table LUT, And in the simulation, the power consumption value at the actual temperature is calculated by linear interpolation; In step (b3), during the electrothermal coupling iteration, the power consumption value of each core functional module is dynamically adjusted according to the current temperature field until the temperature distribution converges.

4. The system according to claim 1, wherein: The implementation method of the vertical interconnection planning module includes the following steps: Step (c1) defines the vertical interconnection layer structure: divide the interconnection layer in the package into micro-bump layer L μb , C4 bump layer L C4b and TSV layer L TSV , and determine the maximum current density constraint I of each layer max and manufacturing cost coefficients α, β, and γ; Step (c2) Construct a mathematical programming model: Minimizing the total number of interconnections is the objective function min αN μb +βN C4b +γN TSV Constraints include: Signal connectivity constraints: in is the number of vertical interconnections at layer i, is the required number of signal channels, in represents the collection of micro-bump layers, Represents the set of C4 bump layers, represents a collection of through silicon via layers; Current density constraint: The current of all bumps and through-silicon vias I≤I max , determined by calculating the current distribution of the power supply network; Thermal integrity constraint: Based on the temperature distribution output by the thermal analysis module, ensure the maximum temperature T of all core particles max ≤T t , where T t is the preset threshold; Step (c3) solving the objective function and the constraints using a mathematical programming solver to generate a vertical interconnection allocation plan for each layer; Step (c4) divides the packaging layer into multiple evenly distributed blocks, and distributes vertical interconnections within each block according to the solution results to ensure that the spatial distribution density of microbumps, C4 bumps and through-silicon vias meets the process requirements; Step (c5) Verify thermal integrity constraints: Call the thermal analysis module to calculate the core temperature T under the current VIC plan max If it exceeds T t , then increase the number of thermal VIC and solve again until T is satisfied max ≤T t ; Step (c6) outputs the final VIC planning scheme.

5. The system according to claim 1, wherein: The temperature scaling function includes: Scaling function for dynamic power consumption based on the effect of temperature on short-circuit current rise / fall times; The scaling function of leakage power consumption adopts a cubic polynomial model; The scaling functions are divided into three categories according to circuit types: functional units, storage modules and analog circuits, and interpolation calculations are implemented through a lookup table.

6. The system according to claim 4, characterized in that The scaling function of the functional unit is obtained by weighted summation of the temperature dependencies of the basic logic units, and the weight is determined based on the number of logic units in the functional unit and the proportion of power consumption.

7. The system according to claim 1, wherein: The vertical interconnect planning module models VIC allocation as a mathematical programming problem. The objective function is to minimize the total number of μbumps, C4 bumps, and TSVs. The constraints include: The number of signal VICs meets the interconnection protocol requirements; The current density of the power supply VIC is lower than the electromigration threshold; The number of thermal VICs ensures that the die temperature does not exceed a preset threshold.

8. The system according to claim 7, characterized in that The solution to the mathematical programming problem involves hierarchical optimization: The first round distributes signal and power VIC; If the temperature exceeds the threshold, iteratively increase the thermal VIC and recalculate the temperature until the constraint is met.

9. An electrothermal simulation method for an integrated chip, characterized in that: The following steps are involved: a. Generate the equivalent thermal conductivity of the package layer based on the effective thermal conductivity model and calculate the initial temperature distribution using the thermal resistance and heat capacitance network solver; b. Use the chiplet architecture simulator to analyze the temperature-dependent power consumption, where dynamic power and leakage power are adjusted by the temperature scaling function; c. Iteratively update the temperature and power consumption until convergence, and feed the final temperature back to the vertical interconnect planning module; d. Optimize the number of vertical interconnects based on temperature constraints to generate a die layout that meets the electro-thermal performance.

10. A vertical interconnection planning device, characterized in that: include: Signal VIC allocation unit, which determines the minimum number of signal channels according to the interconnection protocol; Power VIC allocation unit, which allocates power and ground VICs based on current density constraints; Thermal VIC optimization unit, which increases thermal VIC and recalculates temperature distribution when temperature exceeds the limit; The device outputs a VIC layout that meets signal, power, and thermal constraints and minimizes the total number of VICs.

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