Display device, electronic device including the same, and power voltage generator

Abstract

The invention relates to a display device, an electronic device having the same, and a power voltage generator. The display device includes a display panel including sub-pixels, a data driver, a gate driver, and a power voltage generator. The data driver supplies a data voltage to the sub-pixels. The gate driver receives a first input voltage as a first gate low voltage, and provides a gate signal to the sub-pixel. The power voltage generator receives a first input voltage and a second input voltage, generates a second gate low voltage based on the first input voltage and the second input voltage, and supplies the second gate low voltage to the gate driver. The display device may also include a driving controller for controlling the data driver, the gate driver, and the power voltage generator.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0018437, filed on February 6, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to a display device, an electronic device having the display device, and a power voltage generator. Background Art

[0004] Various display devices have been developed. Examples include liquid crystal display devices and organic light emitting display devices. Various studies have been conducted to reduce the power consumption of display devices. Summary of the Invention

[0005] According to one aspect of the present invention, a display device is provided, comprising: a display panel including sub-pixels; a gate driver; and a driver integrated circuit including a power voltage generator and a data driver configured to provide a data voltage to the sub-pixels, the power voltage generator being configured to receive a first input voltage and a second input voltage, generate a second gate low voltage based on the first input voltage and the second input voltage, and provide the second gate low voltage to the gate driver, wherein the gate driver is configured to receive the first input voltage as the first gate low voltage and provide a gate signal to the sub-pixels.

[0006] The second gate low voltage may have a value obtained by subtracting the second input voltage from the first input voltage.

[0007] The power voltage generator may include a charge pump circuit configured to generate the second gate low voltage based on the first input voltage and the second input voltage.

[0008] The charge pump circuit may include: a first switch including a first terminal coupled to a first reference potential and a second terminal connected to a first node; a second switch including a first terminal connected to the first node and a second terminal connected to the second node; a third switch including a first terminal receiving a second input voltage and a second terminal connected to the second node; a fourth switch including a first terminal coupled to a second reference potential and a second terminal connected to a third node; a fifth switch including a first terminal receiving the first input voltage and a second terminal connected to the third node; a sixth switch including a first terminal coupled to a third reference potential and a second terminal connected to a fourth node; a seventh switch including a first terminal connected to the fourth node and a second terminal connected to a fifth node; a first capacitor including a first electrode connected to the first node and a second electrode connected to the third node; a second capacitor including a first electrode connected to the second node and a second electrode connected to the fourth node; and a third capacitor including a first electrode connected to the fifth node and a second electrode connected to the fourth reference potential. The second gate low voltage may be generated using a voltage stored in the third capacitor.

[0009] The voltage generation period for generating the second gate low voltage may include a first period, a second period after the first period, and a third period after the second period. The first switch, the third switch, the fifth switch, and the sixth switch may be turned on in the first period, the fourth switch may be turned on in the second period, and the second switch, the fourth switch, and the seventh switch may be turned on in the third period.

[0010] The gate driver may output a first gate low voltage as a low logic level of the gate signal.

[0011] The gate driver may include a stage configured to output at least one of the gate signals. The stage may include: an input-stage transistor including a control electrode receiving a first clock signal, a first electrode receiving an input signal, and a second electrode connected to a first-stage node; a control unit (or controller) configured to control a signal of a second-stage node and a signal of a third-stage node based on a signal of the first-stage node; a first output-stage transistor including a control electrode connected to the second-stage node, a first electrode receiving a gate-high voltage, and a second electrode connected to an output terminal; and a second output-stage transistor including a control electrode connected to the third-stage node, a first electrode receiving a first gate-low voltage, and a second electrode connected to the output terminal. The stage may output a gate-high voltage or a first gate-low voltage.

[0012] The second gate low voltage may be applied to at least one of a back gate electrode of a transistor included in the controller and a back gate electrode of an input stage transistor.

[0013] An absolute value of the second gate low voltage may be greater than an absolute value of the first gate low voltage.

[0014] Each of the first gate low voltage and the second gate low voltage may have a negative value.

[0015] The second input voltage may be greater than the first input voltage.

[0016] The first input voltage may have a negative value, and the second input voltage may have a positive value.

[0017] The second input voltage may be greater than the second gate low voltage.

[0018] The display device may further include an emission driver configured to receive the first input voltage as the first gate low voltage, receive the second gate low voltage from the power voltage generator, and provide an emission signal to the sub-pixel.

[0019] The emission driver may output the first gate low voltage as a low logic level of the emission signal.

[0020] The emission driver may include a stage configured to output at least one of the emission signals. The stage may include an input-stage transistor including a control electrode receiving a first clock signal, a first electrode receiving an input signal, and a second electrode connected to a first-stage node; a control unit (or controller) configured to control signals at a second-stage node and a third-stage node based on the signal at the first-stage node; a first output-stage transistor including a control electrode connected to the second-stage node, a first electrode receiving a gate-high voltage, and a second electrode connected to an output terminal; and a second output-stage transistor including a control electrode connected to the third-stage node, a first electrode receiving a first gate-low voltage, and a second electrode connected to the output terminal. The stage may output either a gate-high voltage or a first gate-low voltage.

[0021] The second gate low voltage may be applied to at least one of a back gate electrode of a transistor included in the controller and a back gate electrode of an input stage transistor.

[0022] At least one of the sub-pixels may receive an initialization voltage.The power voltage generator may generate the initialization voltage based on the first input voltage.

[0023] The power voltage generator may further include: a regulator configured to receive the first input voltage to generate the initialization voltage.

[0024] According to another aspect of the present disclosure, an electronic device is provided, comprising: a processor configured to provide input image data to a display device; a display device configured to receive the input image data to display an image; and a voltage supply configured to provide a first input voltage and a second input voltage to the display device, wherein the display device comprises: a display panel comprising sub-pixels; a gate driver; and a driver integrated circuit comprising a power voltage generator and a data driver configured to provide a data voltage to the sub-pixels, the power voltage generator being configured to receive the first input voltage and the second input voltage, generate a second gate low voltage based on the first input voltage and the second input voltage, and provide the second gate low voltage to the gate driver, wherein the gate driver is configured to receive the first input voltage as the first gate low voltage and provide a gate signal to the sub-pixels.

[0025] According to one or more embodiments, a power voltage generator includes: a regulator configured to generate a first voltage based on a first signal; and a voltage generator configured to generate a second voltage based on a first input voltage and a second input voltage, wherein: each of the regulator and the voltage generator is electrically connected to a driver of a display device, the first voltage corresponds to a logic high voltage for the driver, the first input voltage corresponds to a logic low voltage for the driver, and the second voltage is a voltage used to initialize a backgate bias of at least one transistor in the driver. The first signal is a third input voltage. The second input voltage is greater than the first input voltage. The second input voltage is greater than the second voltage. The second voltage is equal to the first input voltage minus the second input voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0027] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0028] Figure 2 It is an icon Figure 1 is a circuit diagram of an example of a sub-pixel of a display device shown in .

[0029] Figure 3 and Figure 4 The graphic is input to Figure 2 Graph of examples of wavelengths of gate signals and emission signals of sub-pixels shown in FIG.

[0030] Figure 5 is a diagram illustrating a method according to an embodiment Figure 1, which is a diagram of an example of a gate driver and an emission driver of a display device shown in FIG.

[0031] Figure 6 It is an icon Figure 5 An example circuit diagram of the first stage of the transmit driver is shown in .

[0032] Figure 7 It is an icon Figure 1 is a block diagram of an example of a power voltage generator for a display device shown in .

[0033] Figure 8 It is an icon Figure 7 A circuit diagram of an example of a second gate low voltage generator is shown in FIG.

[0034] Figure 9 is a diagram showing that in the first period of the voltage generation period Figure 8 is a circuit diagram of an example in which the second gate low voltage generator shown in FIG.

[0035] Figure 10 is a diagram showing that in the second period of the voltage generation period Figure 8 is a circuit diagram of an example in which the second gate low voltage generator shown in FIG.

[0036] Figure 11 is a diagram showing that in the third period of the voltage generation period Figure 8 is a circuit diagram of an example in which the second gate low voltage generator shown in FIG.

[0037] Figure 12 is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0038] Figure 13 It is shown in the figure Figure 12 1 is a diagram of an example in which the electronic device shown in is implemented as a smart phone. DETAILED DESCRIPTION

[0039] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The present disclosure is not limited to the exemplary embodiments described herein, but may be embodied in a variety of different forms. Rather, the exemplary embodiments described herein are provided to thoroughly and completely describe the disclosed content and to fully convey the ideas of the present disclosure to those of ordinary skill in the art.

[0040] Throughout the specification, when an element is referred to as "connected" or "coupled" to another element, the element can be directly connected or directly coupled to the other element, or can be indirectly connected or indirectly coupled to the other element, and one or more intervening elements are between the element and the other element. The technical terms used herein are only used to illustrate the purpose of a specific embodiment and are not intended to limit the embodiment. It will be understood that when a component "includes" an element, the component does not exclude another element, but can further include another element unless there is another opposite description thereof. It will be understood that for the purposes of this disclosure, "at least one of X, Y and Z" can be interpreted as only X, only Y, only Z or any combination of two or more of X, Y and Z (for example, XYZ, XYY, YZ, ZZ). Similarly, for the purposes of this disclosure, "at least one of the group consisting of X, Y and Z" can be interpreted as only X, only Y, only Z or any combination of two or more of X, Y and Z (for example, XYZ, XYY, YZ, ZZ).

[0041] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, the "first" element discussed below may also be referred to as the "second" element without departing from the teachings of the present disclosure.

[0042] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0043] refer to Figure 1 , the display device may include a display panel 100 , a driving controller 200 , a gate driver 300 , a data driver 400 , an emission driver 500 , and a power voltage generator 600 .

[0044] Two or more components among the driving controller 200, the data driver 400, and the power voltage generator 600 may be mounted in one integrated circuit. Figure 1 As shown in FIG, the driving controller 200, the data driver 400, and the power voltage generator 600 may be included in the driver integrated circuit DIC. The driving controller 200, the data driver 400, and the power voltage generator 600 may be a plurality of components functionally divided in one driver integrated circuit DIC. In other embodiments, at least one of the driving controller 200, the data driver 400, and the power voltage generator 600 may be provided as a component different from the driver integrated circuit DIC.

[0045] The display panel 100 may include a display area DA in which an image is displayed, and a non-display area NDA disposed adjacent to the display area DA. In some embodiments, the non-display area NDA may completely surround the display area DA. In other embodiments, the non-display area NDA may only partially surround the display area DA. In some embodiments, the gate driver 300 and the emission driver 500 may be mounted in the non-display area NDA. The gate driver 300 and the emission driver 500 may be located on different sides of the display area DA, or may be located on the same side of the display area DA. The display panel 100 may include a plurality of gate lines GL, a plurality of data lines DL, a plurality of emission lines EL, and a plurality of sub-pixels SP electrically connected to the gate lines GL, the data lines DL, and the emission lines EL. The gate lines GL and the emission lines EL may extend in a first direction DR1, and the data lines DL may extend in a second direction DR2 that intersects (or is disposed perpendicular to) the first direction DR1. In one embodiment, each pixel of the display panel 100 may include a plurality of sub-pixels SP that each emits light of a different color (e.g., red, blue, and green). In another embodiment, the sub-pixels SP of each pixel may emit light of a combination of different colors.

[0046] The drive controller 200 may receive input image data IMG and an input control signal CONT from a host. The host may be an electronic device including a display device, or the host may communicate with the drive controller 200 via at least one communication line. In one embodiment, the host may include a main processor (e.g., a graphics processing unit (GPU)). For example, the input image data IMG may include color image data, such as red image data, green image data, and blue image data. In an embodiment, the input image data IMG may further include white image data. In another example, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0047] The driving controller 200 may generate a plurality of signals. For example, the driving controller 200 may generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0048] The driving controller 200 may generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT and output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include, for example, a vertical start signal and a gate clock signal.

[0049] The driving controller 200 may generate a second control signal CONT2 for controlling the operation of the data driver 400 based on the input control signal CONT and output the second control signal CONT2 to the data driver 400. The second control signal CONT2 may include, for example, a horizontal start signal and a load signal.

[0050] The driving controller 200 may generate a data signal DATA based on input image data IMG and an input control signal CONT. The driving controller 200 may output the data signal DATA to the data driver 400.

[0051] The driving controller 200 may generate a third control signal CONT3 for controlling the operation of the emission driver 500 based on the input control signal CONT and output the third control signal CONT3 to the emission driver 500. The third control signal CONT3 may include, for example, a vertical start signal and an emission clock signal.

[0052] The driving controller 200 may generate a fourth control signal CONT4 for controlling the operation of the power voltage generator 600 based on the input control signal CONT, and output the fourth control signal CONT4 to the power voltage generator 600 .

[0053] The gate driver 300 may generate a gate signal for driving the gate line GL in response to the first control signal CONT1 input from the driving controller 200. The gate driver 300 may output the gate signal to the gate line GL. For example, the gate driver 300 may sequentially output the gate signal to the gate line GL.

[0054] The data driver 400 may receive a second control signal CONT2 and a data signal DATA input from the drive controller 200. The data driver 400 may receive a gamma reference voltage VGREF input from the power voltage generator 600. The data driver 400 may generate data voltages by converting the data signal DATA into a voltage in analog form. The gamma reference voltage VGREF is used to perform gamma correction on the data signal of the data driver 400. For example, the data driver 400 may generate a data voltage for each grayscale value using the gamma reference voltage VGREF including the data voltage for each grayscale value. The data driver 400 may output the data voltages to corresponding data lines among the data lines DL.

[0055] The emission driver 500 may generate emission signals for driving the emission lines EL in response to the third control signal CONT3 input from the driving controller 200. The emission driver 500 may output the emission signals to the emission lines EL. For example, the emission driver 500 may sequentially output the emission signals to the emission lines EL.

[0056] The power voltage generator 600 can generate power voltages VGH, VGL2, VINT, VAINT, and VGREF in response to the fourth control signal CONT4 input from the drive controller 200. The power voltage generator 600 can receive a first input voltage VLOUT3, a second input voltage VCI, and a third input voltage VLIN. These input voltages VLOUT3, VCI, and VLIN can be received, for example, from a host. The power voltage generator 600 can generate initialization voltages VINT and VAINT based on the first input voltage VLOUT3. The power voltage generator 600 can generate a second gate low voltage VGL2 based on the first input voltage VLOUT3 and the second input voltage VCI. The power voltage generator 600 can generate a gate high voltage VGH and a gamma reference voltage VGREF based on the third input voltage VLIN.

[0057] The power voltage generator 600 may provide the gate high voltage VGH and the second gate low voltage VGL2 to the gate driver 300 and the emission driver 500. The power voltage generator 600 may provide the initialization voltages VINT and VAINT to the display panel 100.

[0058] The gate driver 300 and the emission driver 500 may receive the first input voltage VLOUT3 as the first gate low voltage VGL1, such as the reference voltage VGL1. Figure 6 The gate driver 300 and the emission driver 500 may use the gate high voltage VGH as a high logic level and the first gate low voltage VGL1 as a low logic level. This will be described in detail later.

[0059] Figure 2 is a circuit diagram illustrating an example of a sub-pixel SP, which may represent Figure 1 Each of the sub-pixels SP of the display device shown in .

[0060] refer to Figure 2 , each of the sub-pixels SP may include a first pixel transistor TP1 (e.g., a driving transistor), a second pixel transistor TP2, a third pixel transistor TP3, a fourth pixel transistor TP4, a fifth pixel transistor TP5, a sixth pixel transistor TP6, a seventh pixel transistor TP7, and an eighth pixel transistor TP8.

[0061] The first pixel transistor TP1 includes a control electrode connected to the first pixel node NP1, a first electrode connected to the second pixel node NP2, and a second electrode connected to the third pixel node NP3. The second pixel transistor TP2 includes a control electrode that receives the write gate signal GW, a first electrode that receives the data voltage VDATA, and a second electrode connected to the second pixel node NP2. The third pixel transistor TP3 includes a control electrode that receives the compensation gate signal GC, a first electrode connected to the third pixel node NP3, and a second electrode connected to the first pixel node NP1. The fourth pixel transistor TP4 includes a control electrode that receives the initialization gate signal GI, a first electrode that receives the first initialization voltage VINT, and a second electrode connected to the first pixel node NP1. The fifth pixel transistor TP5 includes a control electrode that receives the emission signal EM, a first electrode that receives the first power voltage ELVDD (e.g., a high power voltage), and a second electrode connected to the second pixel node NP2. The sixth pixel transistor TP6 includes a control electrode that receives the emission signal EM, a first electrode connected to the third pixel node NP3, and a second electrode connected to the fourth pixel node NP4. The seventh pixel transistor TP7 includes a control electrode that receives the bias gate signal GB, a first electrode that receives the second initialization voltage VAINT, and a second electrode connected to the fourth pixel node NP4. The eighth pixel transistor TP8 includes a control electrode receiving the bias gate signal GB, a first electrode receiving the bias voltage VBIAS, and a second electrode connected to the second pixel node NP2.

[0062] The sub-pixel SP may further include a storage capacitor CST and a light-emitting element EE. The storage capacitor CST includes a first electrode receiving a first power voltage ELVDD and a second electrode connected to the first pixel node NP1. The light-emitting element EE includes a first electrode (e.g., an anode electrode) connected to the fourth pixel node NP4 and a second electrode (e.g., a cathode electrode) receiving a second power voltage ELVSS (e.g., a low power voltage). However, the present disclosure is not limited thereto. For example, each of the sub-pixels SP may have a 3T1C structure configured with three transistors and one capacitor, a 5T2C structure configured with five transistors and two capacitors, a 7T1C structure configured with seven transistors and one capacitor, or a 9T1C structure configured with nine transistors and one capacitor, etc.

[0063] The first pixel transistor TP1, the second pixel transistor TP2, and the fifth to eighth pixel transistors TP5, TP6, TP7, and TP8 can be implemented with P-channel metal oxide semiconductor (PMOS) transistors. A low logic level can be an activation (or on-state) level, and a high logic level can be a deactivation (or off-state) level. For example, when a signal applied to a control electrode of a PMOS transistor has a low logic level, the PMOS transistor can be turned on. For example, when a signal applied to a control electrode of a PMOS transistor has a high logic level, the PMOS transistor can be turned off.

[0064] The third pixel transistor TP3 and the fourth pixel transistor TP4 can be implemented with N-channel metal oxide semiconductor (NMOS) transistors. The low logic level can be a deactivation (or cut-off state) level, and the high logic level can be an activation (or on-state) level. For example, when the signal applied to the control electrode of the NMOS transistor has a low logic level, the NMOS transistor can be cut off. For example, when the signal applied to the control electrode of the NMOS transistor has a high logic level, the NMOS transistor can be turned on. Therefore, the activation level and the deactivation level can be determined according to the type of transistor.

[0065] However, the present disclosure is not limited to the above-mentioned conductivity. For example, the first pixel transistor TP1, the second pixel transistor TP2, and the fifth to eighth pixel transistors TP5, TP6, TP7, and TP8 can be implemented using NMOS transistors. For example, the third pixel transistor TP3 and the fourth pixel transistor TP4 can be implemented using PMOS transistors.

[0066] For example, during the initialization period, the initialization gate signal GI may have an activation level, and thus the fourth pixel transistor TP4 may be turned on. Accordingly, the first initialization voltage VINT may be applied to the first pixel node NP1 (e.g., performing a gate initialization operation). Thus, the control electrode of the first pixel transistor TP1 (and the node NP1 coupled to the storage capacitor CST) may be initialized.

[0067] For example, in the data writing period, the write gate signal GW and the compensation gate signal GC may have an activation level, and thus the second pixel transistor TP2 and the third pixel transistor TP3 may be turned on. Accordingly, the data voltage VDATA may be written into the storage capacitor CST.

[0068] For example, in the anode initialization period, the bias gate signal GB may have an activation level, and thus the seventh pixel transistor TP7 and the eighth pixel transistor TP8 may be turned on. Accordingly, the second initialization voltage VAINT (e.g., the anode initialization voltage) may be applied to the first electrode (e.g., the anode electrode) of the light emitting element EE, and the bias voltage VBIAS may be applied to the first electrode of the first pixel transistor TP1.

[0069] For example, during the emission period, the emission signal EM may have an activation level, and thus the fifth pixel transistor TP5 and the sixth pixel transistor TP6 may be turned on. Accordingly, since the first power voltage ELVDD is applied to the first pixel transistor TP1, a drive current may be generated in proportion to the data voltage VDATA stored in the storage capacitor CST. This drive current may be applied to the light-emitting element EE. As a result, the light-emitting element EE may emit light having a brightness (or grayscale value) corresponding to the drive current.

[0070] Figure 3 and Figure 4 The graphic is input to Figure 2 Graphs showing examples of wavelengths of gate signals GW, GC, GI, and GB and emission signals EM of sub-pixels SP shown in FIG.

[0071] refer to Figure 3 and Figure 4 The gate signals GW, GC, GI, and GB and the emission signal EM may have a high logic level or a low logic level. The gate high voltage VGH may have a high logic level, and the first gate low voltage VGL1 may have a low logic level.

[0072] refer to Figure 3 For a PMOS transistor, a low logic level may be an activation level, and a high logic level may be a deactivation level. For example, the activation level of the write gate signal GW, the bias gate signal GB, and the emission signal EM may be a low logic level (e.g., corresponding to the first gate low voltage VGL1), and the deactivation level of the write gate signal GW, the bias gate signal GB, and the emission signal EM may be a high logic level (e.g., corresponding to the gate high voltage VGH).

[0073] refer to Figure 4 For an NMOS transistor, a high logic level may be an activation level, and a low logic level may be a deactivation level. For example, the activation level of the compensation gate signal GC and the initialization gate signal GI may be a high logic level (e.g., corresponding to the gate high voltage VGH). The deactivation level of the compensation gate signal GC and the initialization gate signal GI may be a low logic level (e.g., corresponding to the first gate low voltage VGL1).

[0074] Figure 5 It is an icon Figure 1 , which is a diagram of an example of a gate driver 300 and an emission driver 500 of a display device shown in FIG.

[0075] refer to Figure 1 and Figure 5 , the gate driver 300 may include a plurality of stages STG[1], STG[2], STG[3], ... for sequentially generating outputs. The stages STG[1], STG[2], STG[3], ... may sequentially output output signals OUT[1], OUT[2], OUT[3], ... to corresponding gate lines connected thereto among the gate lines GL. The output signals OUT[1], OUT[2], OUT[3], ... of the gate driver 300 may be gate signals.

[0076] For example, the first stage STG[1] of the gate driver 300 may output a first output signal OUT[1] to the gate line GL of the first pixel row. For example, the second stage STG[2] of the gate driver 300 may output a second output signal OUT[2] to the gate line GL of the second pixel row. For example, the third stage STG[3] of the gate driver 300 may output a third output signal OUT[3] to the gate line GL of the third pixel row, and so on.

[0077] The emission driver 500 may include a plurality of stages STG[1], STG[2], STG[3], ... for sequentially generating output voltages. The stages STG[1], STG[2], STG[3], ... may sequentially output output signals OUT[1], OUT[2], OUT[3], ... to corresponding emission lines EL connected thereto. The output signals OUT[1], OUT[2], OUT[3], ... of the emission driver 500 may be emission signals.

[0078] For example, the first stage STG[1] of the emission driver 500 may output a first output signal OUT[1] to the emission line EL of the first pixel row. For example, the second stage STG[2] of the emission driver 500 may output a second output signal OUT[2] to the emission line EL of the second pixel row. For example, the third stage STG[3] of the emission driver 500 may output a third output signal OUT[3] to the emission line EL of the third pixel row, and so on.

[0079] In an embodiment, the stages STG[2], STG[3], ... except the first stage STG[1] may receive the carry signals CR[1], CR[2], CR[3], ... generated by the previous stage to respectively generate the output signals OUT[2], OUT[3], .... In an embodiment, the first stage STG[1] may receive the start signal FLM instead of one of the carry signals CR[1], CR[2], CR[3], ... to generate the first output signal OUT[1].

[0080] However, the present disclosure is not limited to Figure 5 , and the gate driver 300 and the emission driver 500 may have different structures in other embodiments.

[0081] Figure 6 It is an icon Figure 5 ] is a circuit diagram of an example of a first stage STG[1] of the emission driver 500 shown in FIG. The stages STG[2] other than the first stage STG[1] (e.g., STG[2], STG[3], ...) may be substantially the same as the first stage STG[1], except that these stages receive carry signals CR[1], CR[2], CR[3], ... instead of the start signal FLM. In an embodiment, the first clock signal CLK1 and the second clock signal CLK2 may be interchanged with each other according to each of the stages STG[1], STG[2], STG[3], ...

[0082] refer to Figure 5 and Figure 6 , the emission driver 500 may output the first gate low voltage VGL1 as a low logic level of the emission signal. The emission driver 500 may output the gate high voltage VGH as a high logic level of the emission signal.

[0083] The second gate low voltage VGL2 may be applied to back gate electrodes of transistors (e.g., second-stage transistor TS2, fifth-stage transistor TS5, and seventh-stage transistor TS7) included in the emission driver 500. For example, the second gate low voltage VGL2 may be used to initialize back gate biases of the transistors included in the emission driver 500.

[0084] In an embodiment, each of the stages STG[1], STG[2], STG[3], ... may include an input stage transistor, a control unit (or controller), a first output stage transistor, and a second output stage transistor. The input stage transistor (e.g., the second stage transistor TS2) includes a control electrode receiving a first clock signal CLK1, a first electrode receiving an input signal (e.g., a start signal FLM or a carry signal CR[1], CR[2], CR[3], ...), and a second electrode connected to the first stage node NS1. The control unit controls the signal of the second stage node NS2 and the signal of the third stage node NS3 based on the signal of the first stage node NS1. The first output stage transistor (e.g., the eighth stage transistor TS8) includes a control electrode connected to the second stage node NS2, a first electrode receiving a gate high voltage VGH, and a second electrode connected to the output terminal. The second output stage transistor (e.g., the ninth stage transistor TS9) includes a control electrode connected to the third stage node NS3, a first electrode receiving a first gate low voltage VGL1, and a second electrode connected to the output terminal. In one embodiment, the control unit may include third to seventh stage transistors TS3 to TS7 and a first stage capacitor CS1 and a second stage capacitor CS2.

[0085] For example, the first-stage STG[1] may include a first-stage transistor TS1, which includes a control electrode receiving the second clock signal CLK2, a first electrode receiving the start signal FLM, and a second electrode connected to the first-stage node NS1. The first-stage STG[1] may also include second-stage transistors TS2 to ninth-stage transistors TS9. The second-stage transistor TS2 includes a control electrode receiving the first clock signal CLK1, a first electrode receiving the start signal FLM, a second electrode connected to the first-stage node NS1, and a back-gate electrode receiving the second gate low voltage VGL2. The third-stage transistor TS3 includes a control electrode receiving the cutoff control signal ESR, a first electrode receiving the gate high voltage VGH, and a second electrode connected to the first-stage node NS1. The fourth-stage transistor TS4 includes a control electrode connected to the first-stage node NS1, a first electrode receiving the gate high voltage VGH, and a second electrode connected to the second-stage node NS2. The fifth-stage transistor TS5 includes a control electrode connected to the first-stage node NS1, a first electrode receiving the first gate low voltage VGL1, a second electrode connected to the second-stage node NS2, and a back-gate electrode receiving the second gate low voltage VGL2. The sixth-stage transistor TS6 includes a gate electrode connected to the second-stage node NS2, a first electrode receiving a gate high voltage VGH, and a second electrode connected to the first output terminal through which the first carry signal CR[1] is output. The seventh-stage transistor TS7 includes a control electrode connected to the second-stage node NS2, a first electrode receiving a first gate low voltage VGL1, a second electrode connected to the first output terminal, and a back-gate electrode receiving a second gate low voltage VGL2. The eighth-stage transistor TS8 includes a control electrode connected to the second-stage node NS2, a first electrode receiving a gate high voltage VGH, and a second electrode connected to the second output terminal through which the first output signal OUT[1] is output. The ninth-stage transistor TS9 includes a control electrode connected to the third-stage node NS3, a first electrode receiving the first gate low voltage VGL1, and a second electrode connected to the second output terminal. The tenth-stage transistor TS10 includes a control electrode receiving the first gate low voltage VGL1, a first electrode connected to the first-stage node NS1, and a second electrode connected to the third-stage node NS3.

[0086] The first stage STG[1] may further include a first-stage capacitor CS1 and a second-stage capacitor CS2. The first-stage capacitor CS1 includes a first electrode receiving a gate high voltage VGH and a second electrode connected to the first-stage node NS1. The second-stage capacitor CS2 includes a first electrode connected to the third-stage node NS3 and a second electrode connected to the first output terminal.

[0087] The gate driver 300 may output the first gate low voltage VGL1 as a low logic level of the gate signal. The gate driver 300 may output the gate high voltage VGH as a high logic level of the gate signal.

[0088] The second gate low voltage VGL2 may be applied to a back gate electrode of a transistor included in the gate driver 300. For example, the second gate low voltage VGL2 may be used to initialize a back gate bias of the transistor included in the gate driver 300.

[0089] The stages STG[1], STG[2], STG[3], ... of the gate driver 300 may be configured substantially the same as the stages STG[1], STG[2], STG[3], ... of the emission driver 500, except that the output signals OUT[1], OUT[2], OUT[3], ... are gate signals. However, the present disclosure is not limited thereto. For example, except that the first gate low voltage VGL1 is output as a low logic level and except that the second gate low voltage VGL2 initializes the back gate bias of the corresponding transistor in the transistor, at least a portion of the stages STG[1], STG[2], STG[3], ... of the gate driver 300 may be configured differently from the stages STG[1], STG[2], STG[3], ... of the emission driver 500.

[0090] Figure 7 It is an icon Figure 1 8 is a block diagram of an example of a power voltage generator 600 of a display device shown in FIG.

[0091] refer to Figure 7 , the power voltage generator 600 may include a second gate low voltage ( VGL2 ) generator 610 , a first regulator 620 , a second regulator 630 , and a third regulator 650 .

[0092] The second gate low voltage generator 610 may generate a second gate low voltage VGL2 based on the first input voltage VLOUT3 and the second input voltage VCI.

[0093] The absolute value of the second gate low voltage VGL2 may be greater than the absolute value of the first gate low voltage VGL1 (eg, the first input voltage VLOUT3 ). In one embodiment, each of the first gate low voltage VGL1 (eg, the first input voltage VLOUT3 ) and the second gate low voltage VGL2 may have a negative value.

[0094] In one embodiment, the second input voltage VCI may be greater than the first input voltage VLOUT3. For example, the first input voltage VLOUT3 may have a negative value and the second input voltage VCI may have a positive value. The second input voltage VCI may be greater than the second gate low voltage VGL2. For example, the first input voltage VLOUT3 may be -8V, the second input voltage VCI may be 3V, and the second gate low voltage VGL2 may be -11V. However, in other embodiments, the first input voltage VLOUT3, the second input voltage VCI, and / or the second gate low voltage VGL2 may have different values.

[0095] In an embodiment, the second gate low voltage VGL2 may have a value obtained by subtracting the second input voltage VCI from the first input voltage VLOUT3. For example, when the first input voltage VLOUT3 is -8V and the second input voltage VCI is 3V, the second gate low voltage VGL2 may be -11V.

[0096] like Figure 6 As shown in FIG, since the second gate low voltage VGL2 can be a voltage for initializing the back gate bias and the first gate low voltage VGL1 is a voltage used as a low logic level, the current generated by the first gate low voltage VGL1 can be greater than the current generated by the second gate low voltage VGL2. Therefore, in the display device, the second gate low voltage VGL2 (by which a relatively small current is generated) can be generated by the power voltage generator 600, and the first gate low voltage VGL1 (by which a relatively large current is generated) can be supplied as an input voltage to the gate driver 300. Accordingly, the power consumption of the power voltage generator 600 can be reduced.

[0097] The first regulator 620 may generate initialization voltages VINT and VAINT based on the first input voltage VLOUT3. The first regulator 620 may convert the first input voltage VLOUT3 into voltage values set as the initialization voltages VINT and VAINT, and then output the voltage values.

[0098] The second regulator 630 may generate a grayscale display voltage VREG based on the third input voltage VLIN. The gamma reference voltage generator 640 may generate a gamma reference voltage VGREF based on the grayscale display voltage VREG. For example, the grayscale display voltage VREG may be used as a top voltage or a bottom voltage for generating the gamma reference voltage VGREF.

[0099] The third regulator 650 may generate a gate high voltage VGH based on the third input voltage VLIN. The third regulator 650 may output the gate high voltage VGH to the gate driver 300 and the emission driver 500 (eg, see Figure 1 ).

[0100] Figure 8 It is an icon Figure 7 , which is a circuit diagram of an example of the second gate low voltage generator 610 . Figure 9 is a diagram showing that in the first period of the voltage generation period Figure 8 , which is a circuit diagram of an example in which the second gate low voltage generator 610 is driven. Figure 10 is a diagram showing that in the second period of the voltage generation period Figure 8 , which is a circuit diagram of an example in which the second gate low voltage generator 610 is driven. Figure 11 is a diagram showing that in the third period of the voltage generation period Figure 8 , which is a circuit diagram of an example in which the second gate low voltage generator 610 is driven.

[0101] refer to Figure 8 , the second gate low voltage generator 610 may output a second gate low voltage VGL2 having a value obtained by subtracting the second input voltage VCI from the first input voltage VLOUT3. For example, the second gate low voltage generator 610 may be a charge pump circuit.

[0102] For example, the second gate low voltage generator 610 may include a first switch S1 to a seventh switch S7. The first switch S1 includes a first terminal connected to ground (e.g., a first terminal connected to a reference voltage such as ground GND) and a second terminal connected to the first node N1. The second switch S2 includes a first terminal connected to the first node N1 and a second terminal connected to the second node N2. The third switch S3 includes a first terminal receiving the second input voltage VCI and a second terminal connected to the second node N2. The fourth switch S4 includes a first terminal connected to ground and a second terminal connected to the third node N3. The fifth switch S5 includes a first terminal receiving the first input voltage VLOUT3 and a second terminal connected to the third node N3. The sixth switch S6 includes a first terminal connected to ground and a second terminal connected to the fourth node N4. The seventh switch S7 includes a first terminal connected to the fourth node N4 and a second terminal connected to the fifth node N5.

[0103] The second gate low voltage generator 610 may further include first to third capacitors C1 to C3. The first capacitor C1 includes a first electrode connected to the first node N1 and a second electrode connected to the third node N3. The second capacitor C2 includes a first electrode connected to the second node N2 and a second electrode connected to the fourth node N4. The third capacitor C3 includes a first electrode connected to the fifth node N5 and a second electrode grounded. In addition, the second gate low voltage VGL2 may be generated using the voltage stored in the third capacitor C3.

[0104] refer to Figure 8 and Figure 9During the first period of the voltage generation period, in which the second gate low voltage VGL2 is generated, the first switch S1, the third switch S3, the fifth switch S5, and the sixth switch S6 may be turned on. Accordingly, the first electrode of the first capacitor C1 may be grounded, the first input voltage VLOUT3 may be applied to the second electrode of the first capacitor C1, the second input voltage VCI may be applied to the first electrode of the second capacitor C2, and the second electrode of the second capacitor C2 may be grounded. For example, the voltage of the first node N1 may be 0V, the voltage of the third node N3 may be VLOUT3, the voltage of the second node N2 may be VCI, and the voltage of the fourth node N4 may be 0V. VLOUT3 may correspond to the voltage value of the first input voltage VLOUT3, and VCI may correspond to the voltage value of the second input voltage VCI. This will be applied equally hereinafter.

[0105] refer to Figure 8 and Figure 10 In a second period following the first period of the voltage generation period, the first switch S1, the third switch S3, the fifth switch S5, and the sixth switch S6 may be turned off, and the fourth switch S4 and the seventh switch S7 may be turned on. Accordingly, the second electrode of the first capacitor C1 may be grounded, and the voltage of the first electrode of the first capacitor C1 may change due to a change in the voltage of the second electrode of the first capacitor C1. For example, the voltage of the first node N1 may be -VLOUT3, the voltage of the third node N3 may be 0V, the voltage of the second node N2 may be VCI, and the voltage of the fourth node N4 may be 0V.

[0106] refer to Figure 8 and Figure 11 , in a third period after the second period of the voltage generation period, the second switch S2, the fourth switch S4, and the seventh switch S7 may be turned on. Accordingly, the voltage of the second electrode of the second capacitor C2 may change based on the change in the voltage of the first electrode of the second capacitor C2. In an embodiment, the capacitances of the first capacitor C1 and the second capacitor C2 may be the same. For example, the voltages of the first node N1 and the second node N2 may be VCI+(-VLOUT3), the voltage of the third node N3 may be 0V, and the voltages of the fourth node N4 and the fifth node N5 may be –(VCI+(-VLOUT3)) (e.g., VLOUT3-VCI). Therefore, the voltage obtained by subtracting the second input voltage VCI from the first input voltage VLOUT3 (e.g., VLOUT3-VCI) may be stored in the third capacitor C3 and correspond to the second gate low voltage VGL2.

[0107] Figure 12 is a block diagram illustrating an electronic device 1000 according to an embodiment of the present disclosure. Figure 13 It is shown in the figure Figure 12 The electronic device 1000 shown in FIG. 1 is a diagram of an example in which the electronic device 1000 is implemented as a smart phone.

[0108] refer to Figure 12 and Figure 13 , the electronic device 1000 can output various types of information through the display module 1400. For example, when the processor 1100 executes an application stored in the memory 1200, the display module 1400 can provide the user with information generated by the application through the display panel 1410. The display panel 1410 can be Figure 1 The display panel 100 shown in FIG.

[0109] In an embodiment, Figure 13 As shown in FIG, the electronic device 1000 may be implemented as a smartphone. However, this is merely an example, and the electronic device 1000 is not limited thereto. For example, the electronic device 1000 may be implemented as a cellular phone, a video phone, a smart pad, a smart watch, a tablet PC, a car navigation system, a computer monitor, a laptop computer, a head-mounted display device, a television, a media player, a game system, or an appliance control panel.

[0110] The processor 1100 can receive external input through the input module 1300 or the sensor module 1610 and execute an application corresponding to the external input. In an embodiment, when a user selects a camera icon displayed on the display panel 1410, the processor 1100 can receive user input through the input sensor 1610-2 and activate the camera module 1710. The processor 111100 can transmit a data signal corresponding to a captured image acquired by the camera module 1710 to the display module 1400. The display module 1400 can display an image corresponding to the captured image through the display panel 1410.

[0111] In one embodiment, when personal information authentication is performed in display module 1400, fingerprint sensor 1610-1 may obtain input fingerprint information as input data. Processor 1100 may compare the input data received by fingerprint sensor 1610-1 with the authentication data stored in memory 1200 and execute an application based on the comparison result. Display module 1400 may display information executed according to the logic of the application through display panel 1410.

[0112] In one embodiment, when the music streaming icon displayed on the display module 1400 is selected, the processor 1100 may obtain user input through the input sensor 1610-2 and activate the music streaming application stored in the memory 1200. When a music playback command is input in the music streaming application, the processor 1100 may activate the sound output module 1630 to provide the user with sound information corresponding to the music playback command.

[0113] In the above, the operation of the electronic device 1000 is briefly described. Hereinafter, the components of the electronic device 1000 will be described in detail. Some components (to be described later) of the components of the electronic device 1000 can be integrated to be provided as one component. In one embodiment, one component can be divided into two or more components.

[0114] The electronic device 1000 can communicate with the external electronic device 2000 through a network (for example, a short-range wireless communication network (for example, Bluetooth, WiFi, etc.) or a long-range wireless communication network (for example, a mobile communication network)). According to an embodiment, the electronic device 1000 may include a processor 1100, a memory 1200, an input module 1300, a display module 1400, a power module 1500, an internal module 1600, and an external module 1700. According to an embodiment, in the electronic device 1000, at least one of the components described above may be omitted, or one or more other components may be added. According to an embodiment, some components (for example, the sensor module 1610, the antenna module 1620, and / or the sound output module 1630) may be integrated into another component (for example, the display module 1400).

[0115] The processor 1100 can control at least one other component (e.g., a hardware component or a software component) of the electronic device 1000 connected to the processor 1100 by executing software and performing various processes or calculations. According to an embodiment, as an example of data processing and calculation, the processor 1100 can store commands or data received from another component (e.g., the input module 1300, the sensor module 1610, the communication module 1730, etc.) in the volatile memory 1210. The processor 1100 can process the commands or data stored in the volatile memory 1210 and store the resulting data in the non-volatile memory 1220.

[0116] The processor 1100 may include a main processor 1110 and an auxiliary processor 1120. The main processor 1110 may include at least one of a central processing unit (CPU) 1110-1 and an application processor (AP). The main processor 1110 may further include at least one of a graphics processing unit (GPU) 1110-2, a communication processor (CP), and an image signal processor (ISP). The main processor 1110 may further include a neural processing unit (NPU) 1110-3. The NPU 1110-3 is a processor specifically for processing artificial intelligence (AI) models, and the AI models may be generated through machine learning.

[0117] The AI model may include multiple artificial neural network layers. The artificial neural network may be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q network, or one of two or more combinations thereof, but the present disclosure is not limited to the examples described above. In addition to the hardware structure, the AI model may also additionally or alternatively include a software structure. The processing unit described above and at least two of the processors described above may be implemented in one integrated component (e.g., a single chip), or may be implemented as components independent of each other (e.g., multiple chips).

[0118] The auxiliary processor 1120 may include a controller 1120-1. The controller 1120-1 may include, for example, an interface conversion circuit and a timing control circuit. The controller 1120-1 may receive input image data from the main processor 1110, convert the data format of the input image data into a format suitable for the interface specification with the display module 1400, and output a data signal. The controller 1120-1 may also output various control signals for driving the display module 1400.

[0119] In one embodiment, the auxiliary processor 1120 may include a data conversion circuit 1120-2, a gamma correction circuit 1120-3, a rendering circuit 1120-4, etc. The data conversion circuit 1120-2 may receive a data signal from the controller 1120-1 and compensate the data signal to display an image with desired brightness according to characteristics of the electronic device 1000 or user settings, or may convert the data signal for purposes such as reducing power consumption or compensating for afterimages.

[0120] The gamma correction circuit 1120 - 3 may convert a data signal or a gamma reference voltage, etc. to perform a gamma correction scheme so that an image displayed in the electronic device 1000 has a desired gamma characteristic.

[0121] The rendering circuit 1120-4 may receive a data signal from the controller 1120-1 and render the data signal by taking into account pixel arrangement, etc., of the display panel 1410 applied to the electronic device 1000. At least one of the data conversion circuit 1120-2, the gamma correction circuit 1120-3, and the rendering circuit 1120-4 may be integrated into another component (e.g., the main processor 1110 or the controller 1120-1).

[0122] At least one of the controller 1120-1, the data conversion circuit 1120-2, the gamma correction circuit 1120-3, and the rendering circuit 1120-4 may be integrated into a data driver 1430 to be described later. In one embodiment, the auxiliary processor 1120 may be Figure 1 The drive controller 200 shown in FIG.

[0123] The memory 1200 may store various types of data used by at least one component of the electronic device 1000 (e.g., the processor 1100 or the sensor module 1610), and may input or output data related to commands associated with the data. The memory 1200 may include at least one of a volatile memory 1210 and a non-volatile memory 1220.

[0124] The input module 1300 may receive commands or data to be used in components of the electronic device 1000 (e.g., the processor 1100, the sensor module 1610, or the sound output module 1630) from the host of the electronic device 1000 or an external source (e.g., a user or an external electronic device 2000).

[0125] The input module 1300 may include a first input module 1310 to which a command or data is input from a user and a second input module 1320 to which a command or data is input from an external electronic device 2000. The first input module 1310 may include a microphone, a mouse, a keyboard, a key (e.g., a button) or a pen (e.g., a passive pen or an active pen). The second input module 1320 may support a specified protocol that can connect the electronic device 1000 to the external electronic device 2000 via wired or wireless communication. According to an embodiment, the second input module 1320 may include a high-definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface and / or an audio interface. The second input module 1320 may include a connector that can physically connect the electronic device 1000 to the external electronic device 2000 (e.g., an HDMI connector, a USB connector, an SD card connector and / or an audio connector (e.g., a headphone connector)).

[0126] The display module 1400 can provide information visually to the user. The display module 1400 may include a display panel 1410, a gate driver 1420, and a data driver 1430. The display module 1400 may further include a window, a chassis, and a bracket for protecting the display panel 1410. The gate driver 1420 and the data driver 1430 may be Figure 1 The gate driver 300 and the data driver 400 are shown in FIG.

[0127] The display panel 1410 may be one of various display panels. For example, the display panel 1410 may be a liquid crystal display panel, an organic light emitting display panel, or an inorganic light emitting display panel. The type of the display panel 1410 is not specifically limited. The display panel 1410 may be a rigid type or a flexible type in which the display panel 1410 is rollable, bendable, or foldable. The display module 1400 may further include a support member, a bracket, a heat dissipation member, etc. for supporting the display panel 1410.

[0128] The gate driver 1420 may be a driver chip and may be mounted in the display panel 1410. In addition, the gate driver 1420 may be integrated in the display panel 1410. For example, the gate driver 1420 may include an amorphous silicon TFT gate (ASG) driver circuit, a low-temperature polysilicon (LTPS) TFT gate driver circuit, or an oxide semiconductor TFT gate (OSG) driver circuit embedded in the display panel 1410. The gate driver 1420 may receive a control signal from the controller 1120-1 and output a gate signal to the display panel 1410 in response to the control signal.

[0129] The display module 1400 may further include an emission driver. The emission driver may output an emission control signal to the display panel 1410 in response to a control signal received from the controller 1120-1. The emission driver may be formed separately from the gate driver 1420 or may be integrated into the gate driver 1420. The emission driver may be Figure 1 The transmit driver 500 shown in FIG.

[0130] The data driver 1430 may receive a control signal from the controller 1120-1, convert the data signal into an analog voltage (eg, one or more data voltages), and then output the data voltage to the display panel 1410 in response to the control signal. The data driver 1430 may be Figure 1 The data driver 400 in FIG.

[0131] The data driver 1430 may be integrated into another component (eg, the controller 1120 - 1 ). The functions of the interface conversion circuit and the timing control circuit of the controller 1120 - 1 described above may be integrated into the data driver 1430 .

[0132] The display module 1400 may further include a power voltage generator 1440. The power voltage generator 1440 may output various voltages for driving the display panel 1410. The power voltage generator 1440 may be Figure 1 As described above, two or more components among the auxiliary processor 1120, the data driver 1430, and the power voltage generator 1440 may be mounted in one integrated circuit.

[0133] The power module 1500 (e.g., voltage supply) can supply power to at least one component of the electronic device 1000. The power module 1500 may include a battery for charging the power voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. In one embodiment, the power module 1500 may include a power management integrated circuit (PMIC). The PMIC can supply optimized or appropriate power to each of the modules described above and the modules to be described later. For example, the PMIC can supply the first to third input voltages to the power voltage generator 1440, and supply the first input voltage as the first gate low voltage to the gate driver 1420 and the transmit driver (e.g., transmit driver 500). The power module 1500 may include a wireless power transmission / reception circuit electrically connected to the battery. The wireless power transmission / reception circuit may include a plurality of coil-shaped antenna radiators.

[0134] The electronic device 1000 may further include an internal module 1600 and an external module 1700. The internal module 1600 may include a sensor module 1610, an antenna module 1620, and a sound output module 1630. The external module 1700 may include a camera module 1710, an optical module 1720, and a communication module 1730.

[0135] The sensor module 1610 can sense input made by a part of the user's body (e.g., a finger) or input initiated by the pen in the first input module 1310. The sensor module 1610 can generate an electrical signal or data value corresponding to the input. The sensor module 1610 can include at least one of a fingerprint sensor 1610-1, an input sensor 1610-2, and a digitizer 1610-3.

[0136] The fingerprint sensor 1610-1 may generate a data value corresponding to the user's fingerprint. The fingerprint sensor 1610-1 may include any one of an optical fingerprint sensor and a capacitive fingerprint sensor.

[0137] Input sensor 1610-2 may generate data values corresponding to coordinate information of input performed by a user's body part or input initiated by a pen. Input sensor 1610-2 may generate data values corresponding to a change in capacitance caused by the input. Input sensor 1610-2 may sense input performed by a passive pen or may transmit data to / receive data from an active pen.

[0138] Input sensor 1610-2 can measure biometric signals such as, but not limited to, pressure, moisture, or body fat. For example, when a body part of the user is in contact with the sensor layer or sensing panel and the user does not move for a certain period of time, input sensor 1610-2 can sense the biometric signal based on changes in the electric field caused by the body part and output the user's desired information to display module 1400.

[0139] The digitizer 1610-3 may generate a data value corresponding to the coordinate information of the input performed by the pen. The digitizer 1610-3 may generate a data value corresponding to the electromagnetic change caused by the input. The digitizer 1610-3 may sense the input performed by the passive pen or transmit / receive data to / from the active pen.

[0140] At least one of the fingerprint sensor 1610-1, the input sensor 1610-2, and the digitizer 1610-3 may be implemented as a sensor layer formed on the display panel 1410 through a continuous process, for example. At least one of the fingerprint sensor 1610-1, the input sensor 1610-2, and the digitizer 1610-3 may be provided on a predetermined side (e.g., an upper side) of the display panel 1410, and another one of the fingerprint sensor 1610-1, the input sensor 1610-2, and the digitizer 1610-3 (e.g., the digitizer 1610-3) may be provided on the other side (e.g., a lower side) of the display panel 1410.

[0141] At least two of the fingerprint sensor 1610-1, the input sensor 1610-2, and the digitizer 1610-3 can be formed using the same process and integrated into a single sensing panel. When at least two of the fingerprint sensor 1610-1, the input sensor 1610-2, and the digitizer 1610-3 are integrated into a single sensing panel, the sensing panel can be disposed between the display panel 1410 and a window disposed on one side (e.g., the upper side) of the display panel 1410. Depending on the embodiment, the sensing panel can be disposed on the window, and in another embodiment, the sensing panel can be located at another location.

[0142] At least one of the fingerprint sensor 1610-1, the input sensor 1610-2, and the digitizer 1610-3 may be built in or integrated in the display panel 1410. For example, at least one of the fingerprint sensor 1610-1, the input sensor 1610-2, and the digitizer 1610-3 may be simultaneously formed by a process of forming elements (e.g., a light emitting element and a transistor, etc.) included in the display panel 1410.

[0143] The sensor module 1610 may generate an electrical signal or data value corresponding to an internal state or an external state of the electronic device 1000. The sensor module 1610 may further include one or more sensors. For example, the sensor module 1610 may include a gesture sensor, a gyroscope sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, and / or an illumination sensor.

[0144] The antenna module 1620 may include one or more antennas for transmitting signals or power to an external device or receiving signals or power from an external device or source. Depending on the embodiment, the communication module 1730 may transmit signals to or receive signals from the external electronic device 2000 via an antenna suitable for any of a variety of communication protocols. The antenna pattern of the antenna module 1620 may be integrated into a component of the display module 1400 (e.g., the display panel 1410) or the input sensor 1610-2, etc.

[0145] The sound output module 1630 outputs sound signals to the outside of the electronic device 1000 and may include, for example, a speaker for general purposes such as multimedia playback or transcription playback and a receiver for call reception. Depending on the embodiment, the receiver may be integrally formed with the speaker or may be formed separately from the speaker. The sound output mode of the sound output module 1630 may be integrated into the display module 1400.

[0146] The camera module 1710 can capture still images or moving images. Depending on the embodiment, the camera module 1710 may include a flash, one or more lenses, an image sensor, or an image signal processor. The camera module 1710 may further include an infrared camera capable of sensing the user's presence, the user's position, or the user's eyes, etc.

[0147] The light module 1720 may provide light. For example, the light module 1720 may include a light source, such as a light emitting diode or a xenon lamp. The light module 1720 may operate in conjunction with the camera module 1710 or may operate independently of the camera module 1710.

[0148] The communication module 1730 can establish a wired or wireless communication channel between the electronic device 1000 and the external electronic device 2000, and support communication performance through the established communication channel. The communication module 1730 may include any one or all of a wireless communication module and a wired communication module. Examples of wireless communication modules include a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module. Examples of wired communication modules include a local area network (LAN) communication module or a power line communication (PLC) module. The communication module 1730 can communicate with the external electronic device 2000 via a short-range communication network (such as Bluetooth, Wireless Fidelity (WiFi) Direct, or Infrared Data Association (IrDA)) or a long-range communication network (such as a cellular network, the Internet, or a computer network (e.g., a LAN or a wide area network (WAN)). The several types of communication modules described above can be implemented in one chip or can be implemented as separate chips.

[0149] The input module 1300 , the sensor module 1610 , the camera module 1710 , and the like may be used to control the operation of the display module 1400 in cooperation with the processor 1100 .

[0150] The processor 1100 may output commands and / or data to the display module 1400, the sound output module 1630, the camera module 1710, or the optical module 1720 based on the input data received from the input module 1300. For example, the processor 1100 may generate a data signal corresponding to input data applied, for example, via a mouse or an active pen. The processor 1100 may output the data signal to the display module 1400. In one embodiment, the processor 1100 may generate command data corresponding to the input data and may output the command data to the camera module 1710 or the optical module 1720. When no input data is received from the input module 1300 for a certain period of time, the processor 1100 may change the operating mode of the electronic device 1000 to a low power consumption mode or a sleep mode, thereby reducing power consumption in the electronic device 1000.

[0151] The processor 1100 may output commands or data to the display module 1400, the sound output module 1630, the camera module 1710, or the optical module 1720 based on the sensing data received from the sensor module 1610. For example, the processor 1100 may compare the authentication data applied by the fingerprint sensor 1610-1 with the authentication data stored in the memory 1200, and then execute an application or security function based on the comparison result. The processor 1100 may execute a command based on the sensing data sensed by the input sensor 1610-2 or the digitizer 1610-3, or output a corresponding data signal to the display module 1400. When the sensor module 1610 includes a temperature sensor, the processor 1100 may receive temperature data indicating the temperature measured from the sensor module 1610, and may perform brightness correction on the data signal based on the temperature data.

[0152] The processor 1100 may receive measurement data corresponding to the user's presence, the user's position, or the user's eyes from the camera module 1710. The processor 1100 may perform brightness correction on the data signal based on the measurement data. For example, the processor 1100 may determine the user's presence through input from the camera module 1710 and output a data signal with corrected brightness to the display module 1400 through the data conversion circuit 1120-2 or the gamma correction circuit 1120-3.

[0153] At least some of the components described above can be connected to each other, and can pass signals (such as commands or data) between them by the communication scheme between peripheral devices. The example of the communication scheme between peripheral devices includes, but is not limited to, bus, general purpose input / output (GPIO), serial peripheral interface (SPI), mobile industry processor interface (MIPI) or ultra path interconnect (UPI) link. Processor 1100 can communicate with display module 1400 through a specified interface, and can use any of the communication scheme or protocol described above. However, the present disclosure is not limited to the communication scheme described above.

[0154] The present disclosure can be applied to display devices and electronic devices including the display devices. For example, the present disclosure can be applied to digital televisions, 3D televisions, computer monitors, mobile phones, smart phones, tablet computers, VR devices, PCs, home appliances, notebook computers, PDAs, PMPs, digital cameras, music players, portable game consoles, and navigation systems.

[0155] According to the present disclosure, the display device generates a second gate low voltage generated by a relatively small current through the power voltage generator, and can supply the first gate low voltage generated by a relatively large current through the power voltage generator as an input voltage to the gate driver, thereby reducing the power consumption of the power voltage generator.

[0156] Method described herein, technology and / or operation can be performed by the code or instruction executed by a computer, processor, controller or other signal processing device.Computer, processor, controller or other signal processing device can be a computer, processor, controller or other signal processing device described herein, or one except the element described herein.Because the algorithm forming the basis of method (or the operation of computer, processor, controller or other signal processing device) is described in detail, the code or instruction for realizing the operation of method embodiment can convert computer, processor, controller or other signal processing device into a special-purpose processor for performing the method herein.

[0157] In addition, another embodiment may include a computer-readable medium (e.g., a non-transitory computer-readable medium) for storing the codes or instructions described above. The computer-readable medium may be a volatile memory or a non-volatile memory or other storage device, which may be removably or fixedly coupled to a computer, processor, controller, or other signal processing device that executes the codes or instructions for performing the operations of the method embodiments or apparatus embodiments described herein.

[0158] The controllers, processors, devices, modules, drivers, units, generators, regulators, interfaces, and other signal generation and signal processing functions of the embodiments disclosed herein may be implemented, for example, in non-transitory logic that may include hardware, software, or both. When implemented at least partially in hardware, the controllers, processors, devices, modules, drivers, units, generators, regulators, interfaces, and other signal generation and signal processing functions may be, for example, any of a variety of integrated circuits, including, but not limited to, application specific integrated circuits, field programmable gate arrays, combinations of logic gates, systems on chips, microprocessors, or another type of processing or control circuitry. In some embodiments, these functions may be implemented using neural networks, machine learning logic, or other forms of artificial intelligence.

[0159] When implemented at least in part in software, the controller, processor, device, module, driver, unit, generator, regulator, interface and other signal generation and signal processing functions may include, for example, a memory or other storage device for storing code or instructions to be executed by a computer, processor, microprocessor, controller or other signal processing device. The computer, processor, microprocessor, controller or other signal processing device may be a computer, processor, microprocessor, controller or other signal processing device described herein, or one other than the elements described herein. Because the algorithms that form the basis of the method (or the operation of the computer, processor, microprocessor, controller or other signal processing device) are described in detail, the code or instructions for implementing the operation of the method embodiments can convert the computer, processor, controller or other signal processing device into a dedicated processor for performing the method described herein.

[0160] Example embodiments are disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some instances, as will be apparent to one of ordinary skill in the art as of the time of filing this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless specifically indicated otherwise. Accordingly, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the claims. The embodiments may be combined to form additional embodiments.

Claims

1. A display device comprising: a display panel, including sub-pixels; Gate driver; as well as A driver integrated circuit includes a power voltage generator and a data driver configured to provide a data voltage to the sub-pixel, the power voltage generator being configured to receive a first input voltage and a second input voltage, generate a second gate low voltage based on the first input voltage and the second input voltage, and provide the second gate low voltage to the gate driver, wherein the gate driver is configured to receive the first input voltage as a first gate low voltage and provide a gate signal to the sub-pixel.

2. The display device according to claim 1, wherein The second gate low voltage has a value obtained by subtracting the second input voltage from the first input voltage.

3. The display device according to claim 1, wherein The power voltage generator comprises: The charge pump circuit is configured to generate the second gate low voltage based on the first input voltage and the second input voltage.

4. The display device according to claim 3, wherein The charge pump circuit comprises: a first switch including a first terminal coupled to a first reference potential and a second terminal connected to a first node; a second switch including a first terminal connected to the first node and a second terminal connected to a second node; a third switch comprising a first terminal receiving the second input voltage and a second terminal connected to the second node; a fourth switch comprising a first terminal coupled to the second reference potential and a second terminal connected to the third node; a fifth switch comprising a first terminal receiving the first input voltage and a second terminal connected to the third node; a sixth switch comprising a first terminal coupled to the third reference potential and a second terminal connected to the fourth node; a seventh switch comprising a first terminal connected to the fourth node and a second terminal connected to the fifth node; a first capacitor including a first electrode connected to the first node and a second electrode connected to the third node; a second capacitor including a first electrode connected to the second node and a second electrode connected to the fourth node; and A third capacitor includes a first electrode connected to the fifth node and a second electrode connected to a fourth reference potential, wherein the second gate low voltage is generated using a voltage stored in the third capacitor.

5. The display device according to claim 4, wherein A voltage generation period for generating the second gate low voltage includes a first period, a second period after the first period, and a third period after the second period, and The first switch, the third switch, the fifth switch, and the sixth switch are configured to be turned on during the first period. The fourth switch is configured to be turned on during the second period, and The second switch, the fourth switch, and the seventh switch are configured to be turned on during the third period. The display device according to claim 1 , wherein: The gate driver is configured to output the first gate low voltage as a low logic level of the gate signal, and wherein the gate driver includes a stage configured to output at least one of the gate signals, The levels include: an input stage transistor comprising a control electrode configured to receive a first clock signal, a first electrode configured to receive an input signal, and a second electrode connected to a first stage node; a controller configured to control signals of second-stage nodes and third-stage nodes based on signals of the first-stage nodes; a first output-stage transistor including a control electrode connected to the second-stage node, a first electrode configured to receive a gate-high voltage, and a second electrode connected to an output terminal; and A second output stage transistor includes a control electrode connected to the third stage node, a first electrode configured to receive the first gate low voltage, and a second electrode connected to the output terminal, wherein the stage is configured to output the gate high voltage or the first gate low voltage.

7. The display device according to claim 1, wherein The second gate low voltage is applied to at least one of a back gate electrode of a transistor included in the controller and a back gate electrode of the input stage transistor, The absolute value of the second gate low voltage is greater than the absolute value of the first gate low voltage.

8. The display device according to claim 1, wherein Each of the first gate low voltage and the second gate low voltage has a negative value, The second input voltage is greater than the first input voltage.

9. The display device according to claim 1, wherein The first input voltage has a negative value, The second input voltage has a positive value, The second input voltage is greater than the second gate low voltage.

10. The display device according to claim 1, further comprising: an emission driver configured to receive the first input voltage as the first gate low voltage, receive the second gate low voltage from the power voltage generator, and provide an emission signal to the sub-pixel, The emission driver is configured to output the first gate low voltage as a low logic level of the emission signal.

11. The display device according to claim 10, wherein: The transmit driver includes: stage, configured to output at least one of the transmit signals, and The levels include: an input stage transistor comprising a control electrode configured to receive a first clock signal, a first electrode configured to receive an input signal, and a second electrode connected to a first stage node; a controller configured to control signals of second-stage nodes and third-stage nodes based on signals of the first-stage nodes; a first output-stage transistor including a control electrode connected to the second-stage node, a first electrode configured to receive a gate-high voltage, and a second electrode connected to an output terminal; and A second output stage transistor includes a control electrode connected to the third stage node, a first electrode configured to receive the first gate low voltage, and a second electrode connected to the output terminal, wherein the stage is configured to output the gate high voltage or the first gate low voltage.

12. The display device according to claim 10, wherein: The second gate low voltage is applied to at least one of a back gate electrode of a transistor included in the controller and a back gate electrode of the input stage transistor.

13. The display device according to claim 1, wherein At least one of the sub-pixels is configured to receive an initialization voltage, The power voltage generator is configured to generate an initialization voltage based on the first input voltage, The power voltage generator includes a regulator configured to receive the first input voltage to generate the initialization voltage.

14. A power voltage generator comprising: a regulator configured to generate a first voltage based on a first signal; as well as A voltage generator is configured to configure a second voltage based on a first input voltage and a second input voltage, wherein: Each of the regulator and the voltage generator is electrically connected to a driver of a display device, The first voltage corresponds to a logic high voltage for the driver, and the first input voltage corresponds to a logic low voltage for the driver, and The second voltage is a voltage for initializing a back gate bias of at least one transistor in the driver.

15. An electronic device comprising: display device; a processor for providing input image data to the display device, the display device being configured to receive the input image data to display an image; and a voltage supply configured to provide a first input voltage and a second input voltage to the display device, wherein the display device comprises: a display panel, including sub-pixels; gate driver; and A driver integrated circuit includes a power voltage generator and a data driver configured to provide a data voltage to the sub-pixel, the power voltage generator being configured to receive the first input voltage and the second input voltage, generate a second gate low voltage based on the first input voltage and the second input voltage, and provide the second gate low voltage to the gate driver, wherein the gate driver is configured to receive the first input voltage as a first gate low voltage and provide a gate signal to the sub-pixel.

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