Memory, operating method thereof, memory system, and electronic device

Abstract

The embodiment of the invention discloses a memory and an operation method thereof, a memory system and electronic equipment, the memory comprises a memory cell array, and the memory cell array comprises a plurality of memory cells; a peripheral circuit coupled to the memory cell array, the peripheral circuit configured to discharge the selected word line from a first voltage to a second voltage before program verification; wherein the selected word line is coupled to a selected memory cell in the plurality of memory cells; during programming verification, the selected word line is charged from the second voltage to a third voltage, and the third voltage is smaller than the first voltage; wherein at different temperatures, the discharge duration of the selected word line from the first voltage to the second voltage is increased along with the rise of the temperature.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and relate to, but are not limited to, a memory and an operating method thereof, a memory system, and an electronic device. Background Art

[0002] Semiconductor memories are classified into volatile memories and non-volatile memories according to whether they retain stored data when power is off. Non-volatile memories that retain data when power is off may include read-only memories (ROMs) and flash memories.

[0003] Programming can write one or more bits of data into a memory cell. However, temperature changes can affect memory programming, reducing memory reliability. Summary of the Invention

[0004] According to a first aspect of an embodiment of the present disclosure, there is provided a memory, including:

[0005] a memory cell array, the memory cell array comprising a plurality of memory cells;

[0006] A peripheral circuit is coupled to the memory cell array, wherein the peripheral circuit is configured to:

[0007] Before program verification, discharging a selected word line from a first voltage to a second voltage; wherein the selected word line is coupled to a selected memory cell among the plurality of memory cells;

[0008] During the programming verification, the selected word line is charged from the second voltage to a third voltage, where the third voltage is less than the first voltage; wherein, at different temperatures, the discharge time of the selected word line from the first voltage to the second voltage increases with increasing temperature.

[0009] In some embodiments, the peripheral circuit is further configured to:

[0010] determining a temperature of the memory;

[0011] Based on the temperature of the memory, a discharge duration corresponding to the temperature is determined.

[0012] In some embodiments, the peripheral circuit is specifically configured as follows:

[0013] The selected word line is discharged based on the word line driving inhibition signal and the discharge time corresponding to the temperature until the selected word line is discharged to the second voltage.

[0014] In some embodiments, the selected word line includes a first end coupled to the peripheral circuit and a second end coupled to the memory cell; the second voltage includes a first sub-voltage and a second sub-voltage; and the peripheral circuit is specifically configured as follows:

[0015] At a first moment, starting to discharge the selected word line;

[0016] At a second moment after the first moment, discharging the selected word line ends; wherein, at the end of the discharge, the first end and the second end are discharged to the first sub-voltage and the second sub-voltage, respectively, and the second sub-voltage is greater than or equal to the first sub-voltage; and the difference between the second moment and the first moment is the discharge time corresponding to the temperature.

[0017] In some embodiments, the first end is discharged to the first sub-voltage at a third time after the first time, and the third time is earlier than the second time; and the peripheral circuit is specifically configured as follows:

[0018] From the third moment to the second moment, the selected word line continues to be discharged until the second end is discharged to the second sub-voltage.

[0019] In some embodiments, the peripheral circuit is specifically configured as follows:

[0020] determining a temperature difference between a temperature of the memory and a reference temperature;

[0021] Based on the temperature difference and the reference discharge duration, a discharge duration corresponding to the temperature of 0000000 is determined; wherein the reference discharge duration is the discharge duration corresponding to the reference temperature.

[0022] In some embodiments, the first voltage comprises a programming voltage; and the peripheral circuit is further configured to:

[0023] During programming, the program voltage is applied to the selected word line.

[0024] In some embodiments, the first voltage includes a precharge voltage; and the peripheral circuit is further configured to:

[0025] After programming and before the program verification, the precharge voltage is applied to the selected word line.

[0026] In some embodiments, the second voltage includes: -3V.

[0027] In some embodiments, the memory includes: NAND memory.

[0028] According to a second aspect of an embodiment of the present disclosure, a method for operating a memory is provided, including:

[0029] Before program verification, discharging a selected word line from a first voltage to a second voltage; wherein the selected word line is coupled to a selected memory cell among a plurality of memory cells;

[0030] During the program verification, charging the selected word line from the second voltage to a third voltage; wherein the third voltage is lower than the first voltage;

[0031] Wherein, at different temperatures, the discharge time of the selected word line from the first voltage to the second voltage increases with increasing temperature.

[0032] In some embodiments, the operating method further comprises: determining a temperature of the memory;

[0033] In some embodiments, discharging the selected word line from the first voltage to the second voltage includes:

[0034] The selected word line is discharged based on the word line driving inhibition signal and the discharge time corresponding to the temperature until the selected word line is discharged to the second voltage.

[0035] Based on the temperature of the memory, a discharge duration corresponding to the temperature is determined.

[0036] In some embodiments, the selected word line includes a first end coupled to a peripheral circuit and a second end coupled to the memory cell; the second voltage includes a first sub-voltage and a second sub-voltage; and discharging the selected word line includes:

[0037] At a first moment, starting to discharge the selected word line;

[0038] At a second moment after the first moment, discharging the selected word line ends; wherein, at the end of the discharge, the first end and the second end are discharged to the first sub-voltage and the second sub-voltage, respectively, and the second sub-voltage is greater than or equal to the first sub-voltage; and the difference between the second moment and the first moment is the discharge time corresponding to the temperature.

[0039] In some embodiments, the first end portion is discharged to the first sub-voltage at a third time after the first time, and the third time is earlier than the second time; and the discharging of the selected word line further includes:

[0040] From the third moment to the second moment, the selected word line continues to be discharged until the second end is discharged to the second sub-voltage.

[0041] In some embodiments, determining the discharge duration corresponding to the temperature based on the temperature of the memory includes:

[0042] determining a temperature difference between a temperature of the memory and a reference temperature;

[0043] Based on the temperature difference and a reference discharge duration, a discharge duration corresponding to the temperature is determined; wherein the reference discharge duration is the discharge duration corresponding to the reference temperature.

[0044] In some embodiments, the first voltage includes a programming voltage; and the operating method further includes:

[0045] During programming, the program voltage is applied to the selected word line.

[0046] In some embodiments, the first voltage includes a pre-charge voltage; and the operating method further includes:

[0047] After programming and before the program verification, the precharge voltage is applied to the selected word line.

[0048] According to a third aspect of an embodiment of the present disclosure, there is provided a memory system, including:

[0049] One or more memories as described in any one of the embodiments of the first aspect of the present disclosure;

[0050] A memory controller is coupled to the memory and configured to control the memory.

[0051] According to a fourth aspect of an embodiment of the present disclosure, an electronic device is provided, comprising: the memory system as described in the third aspect of the embodiment of the present disclosure.

[0052] In the disclosed embodiment, a selected word line is discharged from a first voltage to a second voltage before programming verification; during programming verification, the selected word line is charged from the second voltage to a third voltage, where the third voltage is less than the first voltage; and at different temperatures, the discharge time of the selected word line from the first voltage to the second voltage increases with increasing temperature. Thus, firstly, both the proximal and distal ends of the word line can be discharged to sufficiently low levels before programming verification, ensuring the accuracy of the programming verification voltage, avoiding sensing errors during programming verification, and improving the reliability of the memory. Secondly, the discharge time of the selected word line from the first voltage to the second voltage increases with increasing temperature, meeting the requirements of programming operations at different temperatures. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0054] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0055] Figure 2a is a schematic diagram of a memory card according to an embodiment of the present disclosure;

[0056] Figure 2b is a schematic diagram of a solid-state hard disk according to an embodiment of the present disclosure;

[0057] Figure 3a 1 is a schematic diagram showing the distribution of storage cells of a three-dimensional NAND memory according to an embodiment of the present disclosure;

[0058] Figure 3b is a schematic block diagram of a three-dimensional NAND memory according to an embodiment of the present disclosure;

[0059] Figure 4 is a cross-sectional schematic diagram of a memory according to an embodiment of the present disclosure;

[0060] Figure 5 is a schematic diagram of a memory including a memory cell array and a peripheral circuit according to an embodiment of the present disclosure;

[0061] Figure 6a and Figure 6b is a schematic diagram showing two timing sequences of programming operations according to an embodiment of the present disclosure;

[0062] Figure 7a and Figure 7b 1 is a schematic diagram showing two timing sequences of a proximal end and a distal end of a word line in a programming operation according to an embodiment of the present disclosure;

[0063] Figure 8 is a schematic diagram showing threshold voltage distributions of two memory cells according to an embodiment of the present disclosure;

[0064] Figure 9 is a schematic block diagram of a memory according to an embodiment of the present disclosure;

[0065] Figure 10 is a schematic diagram illustrating a first timing sequence of a programming operation according to an embodiment of the present disclosure;

[0066] Figure 11 is a schematic diagram of a second timing sequence of a programming operation according to an embodiment of the present disclosure;

[0067] Figure 12 The flowchart of a memory operation method according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0068] To facilitate understanding of the present disclosure, exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0069] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of an actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0070] Generally, terms can be understood, at least in part, from their use in context. For example, depending, at least in part, on the context, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "the" can likewise be understood to convey singular usage or to convey plural usage, depending, at least in part, on the context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending, at least in part, on the context.

[0071] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0072] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0073] The memory in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is used as an example for description.

[0074] Figure 1 1 is a schematic diagram of an electronic device 100 according to an embodiment of the present disclosure. The electronic device 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1 As shown, the electronic device 100 may include a host 108 and a memory system 102, wherein the memory system 102 has one or more memories 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of the electronic device. The host 108 may be configured to send data to the memory 104 or receive data from the memory 104.

[0075] According to some embodiments, the memory controller 106 is coupled to the memory 104 and the host 108 and is configured to control the memory 104. The memory controller 106 can manage data stored in the memory 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as a Solid State Disk (SSD) or an embedded Multi-Media Card (eMMC), and the SSD or eMMC is used as data storage for mobile devices such as smartphones, tablet computers, laptops, etc., as well as enterprise storage arrays.

[0076] The memory controller 106 may be configured to control operations of the memory 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is further configured to process error checking and correction (ECC) on data read from or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with external devices (e.g., Figure 1For example, the memory controller 106 may communicate with the external device through at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI-E (Peripheral Component Interconnect Express) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Development Equipment (IDE) protocol, the Firewire protocol, and the like.

[0077] The memory controller 106 and the one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. Figure 2a In one example shown in FIG, the memory controller 106 and the single memory 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (Personal Computer Memory Card), a CF card, a SmartMedia (SM) card, a memory stick, a multimedia card (MMC (Multi-Media Card), RS-MMC (Reduced-Size MMC), MMCmicro), an SD card (SD, miniSD, microSD, SDHC (Reduced-Size MMC)), UFS, etc. The memory card 202 may also include a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in FIG. Figure 2b In another example shown in , the memory controller 106 and the plurality of memories 104 can be integrated into the SSD 206. The SSD 206 can also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0078] Figure 3a FIG. 1 is a schematic diagram showing the distribution of storage cells of a three-dimensional NAND memory according to an embodiment of the present disclosure. Figure 3a As shown, the memory cell array of a three-dimensional NAND memory device consists of several parallel, staggered rows of memory cell rows parallel to the gate isolation structure. Every two rows of memory cell rows are separated by a gate isolation structure and an upper select gate isolation structure, and each memory cell row includes multiple memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory cell array into multiple memory blocks ("blocks" in English). The multiple second gate isolation structures can divide the memory blocks into multiple finger storage areas ("finger" in English). The upper select gate isolation structure disposed in the middle of each finger storage area can divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices ("strings" in English). Figure 3a The memory block shown in FIG includes 6 memory slices. In practical applications, the number of memory slices in a memory block is not limited thereto. The memory cells in a memory block coupled to a certain word line can be called a memory page.

[0079] It should be noted that Figure 3a The number of memory cell rows between the gate isolation structure and the upper select gate isolation structure is provided for illustrative purposes only and is not intended to limit the number of memory cell rows within a finger storage region of the 3D NAND memory disclosed herein. In practical applications, the number of memory cell rows within a finger storage region can be adjusted to meet specific requirements, such as 2, 4, 8, or 16.

[0080] Figure 3b FIG. 3 is a schematic block diagram of a three-dimensional NAND memory 300 according to an embodiment of the present disclosure. The memory 300 may be Figure 13. An example of a memory 104 in FIG. Memory 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 is described as a three-dimensional NAND memory cell array, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the area of the memory cell 306. Each memory cell 306 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0081] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible storage states and can therefore store one bit of data. For example, the first storage state "0" can correspond to a first voltage range, and the second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four storage states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple level cell (TLC)), or four bits per cell (also known as a quad level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed by writing one of three possible nominal storage values to the cell, and a fourth nominal storage value other than the three nominal storage values can be used to represent an erased state.

[0082] like Figure 3bAs shown in FIG, each NAND memory string 308 may include a bottom select gate (BSG) 310 at its source terminal and a top select gate (TSG) 312 at its drain terminal. BSG 310 and TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselect voltage (e.g., 0V) to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselect voltage (e.g., 0V) to a corresponding BSG 310 via one or more BSG lines 315.

[0083] like Figure 3bAs shown in FIG, a NAND memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block, the source lines coupled to the selected memory block and unselected memory blocks in the same plane as the selected memory block can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, erase operations can be performed at the half-memory block level, at the quarter-memory block level, or at any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent NAND memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, which is a basic data unit for programming operations. The size of a page 320 in bits can be related to the number of NAND memory strings 308 coupled by word lines 318 in a memory block 304. Each word line 318 can include a plurality of control gates (gate electrodes) at each memory cell 306 in a corresponding page 320 and a gate line coupling the control gates. In combination with the previous Figure 3a A page 320 includes multiple memory cells 306. The memory cells are isolated from each other by an upper select gate isolation structure and a gate isolation structure. The memory cells between the upper select gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows. Each memory cell row is parallel to the gate isolation structure and the upper select gate isolation structure. Memory cells in a memory slice that share the same word line form a programmable (read / write) page.

[0084] Figure 4 1 is a cross-sectional schematic diagram of a memory according to an embodiment of the present disclosure. Figure 4 As shown, NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 alternately stacked in sequence, and a memory string 308 vertically extending through the gate layers 411 and insulating layers 412. Gate layers 411 and insulating layers 412 may be alternately stacked, with two adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in stacked structure 410 may determine the number of memory cells included in memory cell array 301.

[0085] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0086] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0087] In some embodiments, NAND memory string 308 includes a channel structure extending vertically through stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with one or more semiconductor materials (e.g., serving as a semiconductor channel) and one or more dielectric materials (e.g., serving as a memory film). In some embodiments, the semiconductor channel comprises silicon, such as polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer comprising a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar). In some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may comprise silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may comprise silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0088] Return Reference Figure 3b, the peripheral circuit 302 may be coupled to the memory cell array 301 via the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, the peripheral circuit 302 may also include Figure 5 Additional peripheral circuits not shown.

[0089] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 can store a page of program data (write data) to be programmed into one page 320 of the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0090] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 using word line voltages generated from a voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the BSG lines 315 and the TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0091] The control logic 512 can be coupled to each peripheral circuit described above and is configured to control the operation of each peripheral circuit. The register 514 can be coupled to the control logic 512 and includes a status register, a command register, and an address register for storing status information, command operation code (OP code), and command address for controlling the operation of each peripheral circuit. The interface 516 can be coupled to the control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, as well as buffer status information received from the control logic 512 and relay it to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay it to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0092] The programming operation of the memory may include multiple programming loops, each programming loop may include multiple stages, and in each stage, voltages may be applied to the bit line 316, word line 318, source line 314, BSG line 315 and TSG line to perform operations of the corresponding stage. Figure 6a and Figure 6b Schematic diagram of two timings of programming operations according to an embodiment of the present disclosure. For ease of understanding, Figure 6a and Figure 6b The timing of applying voltage to the selected word line at different stages in a programming cycle is only shown in FIG. Figure 6a and Figure 6b Each phase of a programming cycle is exemplarily described.

[0093] In one example, referring to Figure 6aAs shown, each programming loop may include a programming phase ① and a program verification phase ③. In the programming phase ①, the voltage generator may generate voltages required for programming, such as the program voltage Vpgm applied to the selected word line; in the program verification phase ③, the voltage generator may generate voltages required for program verification, such as the program verification voltage Vvrf applied to the selected word line.

[0094] In another example, referring to Figure 6b As shown, each programming cycle can include a programming phase ①, a precharge phase ④, and a program verification phase ③. During the precharge phase ④, a voltage generator can generate the voltage required for precharging, such as the precharge voltage applied to the word line. In this example, the precharge phase ④ is provided between the programming phase ① and the program verification phase ③ to reduce the impact of residual electrons in the channel after programming on the program verification results. For details about the programming phase ① and the program verification phase ③, please refer to the description of the above example and will not be repeated for the sake of brevity.

[0095] It should be noted that the programming voltage Vpgm and the precharge voltage are usually greater than the programming verification voltage Vvrf. Figure 6a The programming stage ① or Figure 6b After the precharge phase ④ shown in FIG. 4 , if the selected word line is discharged directly from the programming voltage Vpgm or the precharge voltage to the programming verification voltage Vvrf, the accuracy of the programming verification voltage Vvrf may be affected. Therefore, in order to ensure the accuracy of the programming verification voltage Vvrf, a recovery phase (also known as word-line underdrive) ② is usually required before applying the programming verification voltage Vvrf to the selected word line. Figure 6a or Figure 6b In the word line drive inhibition phase ②, the selected word line may be underdriven to the word line drive inhibition voltage, such as by discharging, and then the programming verification phase ③ is performed.

[0096] Figure 6a and Figure 6b The following also illustrates the programming operation of the memory at different temperatures, where RT, LT, and HT represent regular temperature, low temperature, and high temperature, respectively. Figure 6a and Figure 6b The programming operation of the memory at different temperatures is exemplified.

[0097] During layout design, circuits are usually set with specified design limits to meet the Electrical Design Rule (EDR). As the temperature rises, during programming operations, the first programming verification voltage will approach the design limit allowed by the word line driver suppression circuit. For example, Figure 6a or Figure 6b As shown in (HT), the first programming verification voltage Vvrf is close to the Design limit. For example, the difference between the first programming verification voltage Vvrf and the Design limit is less than 1V. This means that before the programming verification stage at high temperature, the selected word line needs to be underdriven even lower. However, because the word line drive suppression circuit has reached the allowable design limit, the far end of the word line is prone to insufficient underdrive at this time, resulting in inaccurate sensing during subsequent programming verification.

[0098] Figure 7a and Figure 7b This is a schematic diagram of two timings of the near side and far side of the word line in the programming operation according to an embodiment of the present disclosure. It should be noted that the word line includes a near side coupled to the peripheral circuit and a far side coupled to the memory cell. Since the word line is made of conductive material, there is a certain RC delay in the word line itself, which makes the charge / discharge rate of the far side of the word line smaller than the charge / discharge rate of the near side of the word line. Figure 7a and Figure 7b The word line driving inhibition phase ② at the proximal and distal ends of the word line at high temperature is exemplarily described.

[0099] At high temperatures, the programming verification voltage Vvrf approaches the Design limit. To ensure the accuracy of the programming verification voltage Vvrf, the far end of the selected word line needs to be sufficiently underdriven during the word line drive suppression phase ②, that is, the selected word line needs to be underdriven even lower, which may even exceed the Design limit. Figure 7a Or as shown in (HT) on the left in Figure 7b, which would violate electrical design rules.

[0100] In order to comply with the electrical design rules, the selected word line is underdriven to the design limit. Due to the RC delay, the far end of the word line may be underdriven insufficiently. For example, at the end of the word line drive suppression phase ②, the voltage at the far end of the word line is much greater than the voltage at the near end of the word line, such as Figure 7a As shown in (HT) on the right of FIG7b, this will affect the accuracy of the subsequent programming verification voltage Vvrf, causing inaccurate sensing during programming verification.

[0101] In addition, in order to reduce the programming voltage and improve the retention time of the memory cell, the threshold voltage distribution of multiple memory cells can be reduced as a whole. Taking TLC memory as an example, Figure 8 In (a), the threshold voltage distribution of the erased state P0 and the programmed states P1 to P7 is reduced to Figure 8 (b) Threshold voltage distribution of erased state P0' and programmed states P1' to P7'. However, the overall reduction in the threshold voltage distribution of multiple memory cells means that the first programming verification voltage needs to be lower, for example, Figure 8 In (a), PV1′ is reduced to PV1′, which is closer to the design limit. This makes the far-end underdrive of the word line seriously insufficient, and the sensing accuracy during programming verification is further reduced.

[0102] Based on one or more of the above technical problems, an embodiment of the present disclosure provides a memory 600 , which includes but is not limited to a NAND memory. Figure 9 is a schematic block diagram of a memory 600 according to an embodiment of the present disclosure. Figure 10 is a schematic diagram of a first timing sequence of a programming operation according to an embodiment of the present disclosure, Figure 11 This is a schematic diagram of the second timing of the programming operation according to the embodiment of the present disclosure. Figure 9 、 Figure 10 and Figure 11 The memory 600 and programming operation thereof provided by the embodiment of the present disclosure are exemplarily described.

[0103] Reference Figure 9 As shown, the memory 600 includes a memory cell array 610 and a peripheral circuit 620 coupled to the memory cell array 610. The memory cell array 610 includes a plurality of memory cells. The peripheral circuit 620 can apply a voltage signal and / or a current signal to a selected memory cell via a bit line, a word line, a source line, a lower selection gate line, and an upper selection gate line, and sense a voltage signal and / or a current signal from the selected memory cell to facilitate the operation of the memory cell array 610. For details about the structures of the memory 600, the memory cell array 610, and the peripheral circuit 620, please refer to the above-mentioned Figure 3a 、 Figure 3b 、 Figure 4 and Figure 5 The relevant descriptions of the memory 300, the memory cell array 301 and the peripheral circuit 302 are not repeated here.

[0104] The peripheral circuit 620 is configured to: discharge the selected word line from a first voltage to a second voltage before programming verification; wherein the selected word line is coupled to a selected memory cell among a plurality of memory cells; during programming verification, charge the selected word line from the second voltage to a third voltage, the third voltage being less than the first voltage; wherein, at different temperatures, the discharge time of the selected word line from the first voltage to the second voltage increases with increasing temperature.

[0105] It can be understood that in this embodiment, the selected word line is discharged from the first voltage to the second voltage before programming verification, and at different temperatures, the discharge time of the selected word line from the first voltage to the second voltage increases with the increase of temperature. That is, by compensating the discharge time, it can be ensured that the word line is sufficiently underdriven before programming verification, thereby ensuring the accuracy of the subsequent programming verification voltage and avoiding sensing errors during programming verification.

[0106] In some embodiments, the second voltage includes: -3 V or -2.8 V. Of course, the value of the second voltage is not limited thereto, and the value of the second voltage can be reasonably set according to the actual design limit of the circuit, and the present disclosure has no special limitation on this.

[0107] In one embodiment, the first voltage is a programming voltage Vpgm or a precharge voltage Vpre, the second voltage is a word line driver inhibit voltage Vwlud, and the third voltage is a program verification voltage Vvrf. Here, the word line driver inhibit voltage Vwlud is lower than the programming voltage Vpgm and the precharge voltage Vpre.

[0108] For example, combined Figure 10 As shown, at the end of programming phase ①, the proximal end of the word line has discharged from the programming voltage Vpgm to the word line drive inhibit voltage Vwlud. Due to RC delay, the voltage at the distal end of the word line is now much greater than the voltage at the proximal end of the word line. Continuing to discharge the word line, by extending the word line drive inhibit time T (equivalent to extending the discharge time), the voltage at the distal end of the word line can be restored to substantially equal to the word line drive inhibit voltage Vwlud. The word line is then charged to the programming verification voltage Vvrf, thereby ensuring the accuracy of the programming verification voltage Vvrf. In this example, the first voltage is the programming voltage Vpgm.

[0109] For example, combined Figure 11As shown, at the end of precharge phase ④, the proximal end of the word line has discharged from the precharge voltage Vpre to the word line drive inhibition voltage Vwlud. Due to RC delay, the voltage at the distal end of the word line is much greater than the voltage at the proximal end of the word line. Continuing to discharge the word line, by extending the word line drive inhibition time T (equivalent to extending the discharge time), the voltage at the distal end of the word line can be restored to substantially equal to the word line drive inhibition voltage Vwlud. The word line is then charged to the program verification voltage Vvrf, thereby ensuring the accuracy of the program verification voltage Vvrf. In this example, the first voltage is the precharge voltage Vpre.

[0110] It should be noted that Figure 10 and Figure 11 The figure only illustrates the timing of applying voltage to the selected word line at different stages in a programming loop. The programming operation of the memory may include multiple programming loops. Before the programming verification stage of each programming loop, an operation similar to compensating for the discharge time in the above embodiment may be performed to ensure the accuracy of the programming verification voltage of each programming loop, which is beneficial to improving the reliability of the memory.

[0111] In an embodiment of the present disclosure, a selected word line is discharged from a first voltage to a second voltage before programming verification; during programming verification, the selected word line is charged from the second voltage to a third voltage, the third voltage being less than the first voltage; and at different temperatures, the discharge time of the selected word line from the first voltage to the second voltage increases with increasing temperature. Thus, firstly, both the proximal and distal ends of the word line can be discharged to sufficiently low levels before programming verification, thereby ensuring the accuracy of the programming verification voltage and avoiding sensing errors during programming verification, thereby improving the reliability of the memory. Secondly, the discharge time of the selected word line from the first voltage to the second voltage increases with increasing temperature, thereby meeting the requirements of programming operations at different temperatures. Thirdly, by compensating for the discharge time, the distal end of the word line can also be sufficiently underdriven, which allows the first programming verification voltage to be lowered, that is, allows the threshold voltage distribution of multiple memory cells to be reduced as a whole, thereby reducing the programming voltage and improving the retention time of the memory cells.

[0112] In some embodiments, the peripheral circuit 620 is further configured to: determine the temperature of the memory; and determine the discharge time corresponding to the temperature based on the temperature of the memory. It is understandable that the programming verification voltage may change when the memory performs programming operations at different temperatures. Figure 6a or Figure 6bAs shown in the figure, the program verification voltages corresponding to LT, RT, and HT decrease in sequence. That is, as the temperature increases, the program verification voltage of the memory approaches the design limit. Therefore, different discharge times can be compensated for different temperatures. When performing a programming operation, the current temperature of the memory is determined, and the corresponding discharge time is determined based on the current temperature. This can avoid wasting programming time and improve programming efficiency. Here, the range of HT includes 85°C to 125°C.

[0113] In some embodiments, the peripheral circuit 620 includes a temperature sensing circuit and a control logic circuit. The temperature sensing circuit is configured to determine the temperature of the memory, and the control logic circuit is configured to determine the discharge duration corresponding to the temperature. Exemplarily, the temperature sensing circuit includes a temperature sensor that converts an analog temperature signal into a digital temperature signal and transmits the digital temperature signal to the control logic circuit. The control logic circuit can search a mapping table based on the received digital temperature signal to determine the discharge duration corresponding to the digital temperature signal. In this embodiment, the mapping table can be stored in a register of the peripheral circuit 620 or in the memory cell array 610.

[0114] It should be noted that the temperature signal output by the temperature sensor may be a voltage signal corresponding to the sensed temperature, and the number of temperature sensors may be one or more. Although this embodiment describes a case where the temperature sensing circuit is located in the memory, the temperature sensing circuit may be external to the memory and sense the temperature of the memory.

[0115] In one specific embodiment, the peripheral circuit 620 is further configured to: determine a first temperature of the memory; based on the first temperature, determine a first discharge duration corresponding to the first temperature; determine a second temperature of the memory; based on the second temperature, determine a second discharge duration corresponding to the second temperature; wherein if the second temperature is greater than the first temperature, the second discharge duration is greater than the first discharge duration. In this embodiment, when programming operations are performed at different temperatures, the discharge duration of the word line increases as the temperature increases, i.e., the discharge duration of the word line is positively correlated with the change in temperature, where the positive correlation includes a proportional relationship or a nonlinear relationship.

[0116] In some embodiments, the peripheral circuit 620 is specifically configured to discharge the selected word line based on the word line driving inhibition signal and the discharge time corresponding to the temperature, until the selected word line is discharged to the second voltage.

[0117] In some embodiments, reference Figure 9 As shown, the peripheral circuit 620 further includes a word line drive suppression circuit 622 . The word line drive suppression circuit 622 is coupled to the control logic circuit. The word line drive suppression circuit 622 can start discharging the word line or stop discharging the word line under the control of the control logic circuit.

[0118] For example, refer to Figure 9 and Figure 10 As shown, at the end of programming stage ①, the control logic circuit generates a word line drive inhibition signal and sends it to the word line drive inhibition circuit 622. The word line drive inhibition circuit 622 discharges the selected word line based on the word line drive inhibition signal. After the discharge time of the word line reaches the discharge time corresponding to the current temperature, the control logic circuit controls the word line drive inhibition circuit 622 to end the discharge, thereby discharging the selected word line to the second voltage.

[0119] For example, refer to Figure 9 and Figure 11 As shown, at the end of the pre-charging stage ④, the control logic circuit generates a word line drive inhibition signal and sends it to the word line drive inhibition circuit 622. The word line drive inhibition circuit 622 discharges the selected word line based on the word line drive inhibition signal. After the discharge time of the word line reaches the discharge time corresponding to the current temperature, the control logic circuit controls the word line drive inhibition circuit 622 to end the discharge, thereby discharging the selected word line to the second voltage.

[0120] In some embodiments, a selected word line includes a first end coupled to the peripheral circuit 620 and a second end coupled to the memory cell; the second voltage includes a first sub-voltage and a second sub-voltage; the peripheral circuit 620 is specifically configured to: begin discharging the selected word line at a first moment; and end discharging the selected word line at a second moment after the first moment; wherein, at the end of discharge, the first end and the second end are discharged to the first sub-voltage and the second sub-voltage, respectively, and the second sub-voltage is greater than or equal to the first sub-voltage; and the difference between the second moment and the first moment is the discharge duration corresponding to the temperature. In this embodiment, the first end may be the proximal end of the word line, and the second end may be the distal end of the word line; the first moment may be the moment discharge begins in programming phase ① or the moment discharge begins in the precharge phase.

[0121] For example, refer to Figure 10 As shown, after programming is completed, the charging of the word line is stopped and the word line starts to discharge. At time t1, the proximal end of the word line is discharged to the first sub-voltage, and the programming phase ① ends at this time; the word line continues to be discharged, and at time t2, the distal end of the word line is discharged to the second sub-voltage, and the word line drive inhibition phase ② ends at this time. The proximal and distal ends of the word line are restored to a level equal to or close to the word line drive inhibition voltage Vwlud.

[0122] For example, refer to Figure 11As shown, after the pre-charging is completed, the charging of the word line is stopped and the word line starts to discharge. At time t4, the proximal end of the word line is discharged to the first sub-voltage, and the pre-charging stage ④ ends at this time; the word line continues to be discharged, and at time t2, the distal end of the word line is discharged to the second sub-voltage, and the word line drive inhibition stage ② ends at this time. The proximal and distal ends of the word line are restored to a level equal to or close to the word line drive inhibition voltage Vwlud.

[0123] It should be noted that due to the inherent resistance of the word line, at the end of word line drive inhibition phase ②, the voltage at the far end of the word line may be equal to or slightly greater than the voltage at the near end of the word line, but this voltage difference is small and can be essentially ignored. The discharge time for the word line to fully discharge from the first voltage to the second voltage can be the sum of the discharge time during the programming phase and the discharge time during the word line drive inhibition phase, or the sum of the discharge time during the precharge phase and the discharge time during the word line drive inhibition phase.

[0124] In some embodiments, the first end is discharged to the first sub-voltage at a third time after the first time, and the third time is earlier than the second time; the peripheral circuit 620 is specifically configured to: continue to discharge the selected word line from the third time to the second time until the second end is discharged to the second sub-voltage. The third time may be Figure 10 Any time between t1 and t2 shown in the figure may also be any time between t4 and t2, and the present disclosure has no special limitation on this. It is understandable that in this embodiment, by delaying the time when the word line discharge ends from the third time to the second time, it is possible to ensure that the far end of the word line is fully discharged to a level equal to or close to the word line drive inhibition voltage Vwlud, as shown in FIG. Figure 10 Or as shown in 11.

[0125] In some embodiments, the peripheral circuit 620 is specifically configured to: determine the temperature difference between the memory temperature and the reference temperature; determine the discharge time corresponding to the temperature based on the temperature difference and the reference discharge time; wherein the reference discharge time is the discharge time corresponding to the reference temperature.

[0126] In a specific embodiment, multiple temperature increments can be determined based on a reference temperature, and the multiple temperature increments correspond to multiple discharge time increments respectively. Multiple mapping entries are established to show the correspondence between the multiple temperature increments and the multiple discharge time increments. A mapping table is generated based on the multiple mapping entries, and the mapping table is stored in a register of the peripheral circuit 620 or in the memory cell array 610.

[0127] For example, a temperature difference between the current temperature and a reference temperature is determined, where the temperature difference is a target temperature increment among multiple temperature increments. A target discharge duration increment is determined by searching a mapping table based on the target temperature increment. The sum of the target discharge duration increment and the discharge duration corresponding to the reference temperature is the discharge duration corresponding to the current temperature. In this example, the current temperature is greater than the reference temperature. The reference temperature can be the aforementioned LT or RT, and the current temperature can be the aforementioned HT.

[0128] In some embodiments, the first voltage includes a programming voltage Vpgm; the peripheral circuit 620 is further configured to apply the programming voltage to the selected word line during programming. Figure 10 or Figure 11 As shown, the word line starts to be charged at time t0 until the word line is charged to the programming voltage Vpgm.

[0129] In some embodiments, the first voltage includes a precharge voltage; the peripheral circuit 620 is further configured to apply the precharge voltage to the selected word line after programming and before program verification. Figure 11 As shown, the word line starts to be charged at time t3 until the word line is charged to the precharge voltage Vpre.

[0130] In some embodiments, the peripheral circuit 620 is specifically configured to charge the selected word line based on a word line drive signal until the selected word line is charged to a programming voltage Vpgm or a precharge voltage Vpre. The word line drive signal includes a programming drive signal or a precharge drive signal.

[0131] In some embodiments, reference Figure 9 As shown, the peripheral circuit 620 further includes a word line driving circuit 621 . The word line driving circuit 621 is coupled to the control logic circuit. The word line driving circuit 621 can start charging the word line or stop charging the word line under the control of the control logic circuit.

[0132] An embodiment of the present disclosure provides a memory, which includes a memory cell array and a peripheral circuit coupled to the memory cell array, wherein the memory cell array includes multiple memory cells; the peripheral circuit is configured to discharge a selected word line from a first voltage to a second voltage before programming verification; wherein the selected word line is coupled to a selected memory cell among the multiple memory cells; during programming verification, the selected word line is charged from the second voltage to a third voltage, and the third voltage is less than the first voltage; wherein, at different temperatures, the discharge time of the selected word line from the first voltage to the second voltage increases with increasing temperature. In this way, on the one hand, both the proximal and distal ends of the word line can be discharged to a sufficiently low level before programming verification, which can ensure the accuracy of the programming verification voltage, avoid sensing errors during programming verification, and help improve the reliability of the memory; on the other hand, the discharge time of the selected word line from the first voltage to the second voltage increases with the increase of temperature, which can meet the needs of programming operations at different temperatures; on the third hand, by compensating for the discharge time, the distal end of the word line can also be sufficiently underdrive, which will allow the first programming verification voltage to be lowered, that is, allowing the threshold voltage distribution of multiple memory cells to be reduced as a whole, which is conducive to reducing the programming voltage and improving the retention time of the memory cells.

[0133] Based on the above memory, an embodiment of the present disclosure provides a memory operating method, which can be applied to the memory in any of the above embodiments. Figure 12 is a flowchart of a memory operation method according to an embodiment of the present disclosure, referring to Figure 12 As shown, the operation method includes:

[0134] Step S710: Discharging a selected word line from a first voltage to a second voltage before program verification; wherein the selected word line is coupled to a selected memory cell among a plurality of memory cells;

[0135] Step S720: During programming verification, the selected word line is charged from the second voltage to a third voltage; wherein the third voltage is less than the first voltage; wherein, at different temperatures, the discharge time of the selected word line from the first voltage to the second voltage increases with increasing temperature.

[0136] It should be noted that Figure 12 The steps shown in the operation are not exclusive, and other steps may be performed before, after, or between any steps in the operation shown; Figure 12 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0137] In some embodiments, the operating method further includes: determining a temperature of the memory; and determining a discharge duration corresponding to the temperature based on the temperature of the memory.

[0138] In some embodiments, discharging the selected word line from the first voltage to the second voltage includes: discharging the selected word line based on the word line drive inhibition signal and a discharge time corresponding to the temperature until the selected word line is discharged to the second voltage.

[0139] In some embodiments, the selected word line includes a first end coupled to a peripheral circuit and a second end coupled to a memory cell; the second voltage includes a first sub-voltage and a second sub-voltage; and discharging the selected word line includes:

[0140] At the first moment, the selected word line begins to be discharged;

[0141] At a second moment after the first moment, discharging the selected word line is terminated; wherein, at the end of the discharge, the first end and the second end are discharged to a first sub-voltage and a second sub-voltage, respectively, and the second sub-voltage is greater than or equal to the first sub-voltage; and the difference between the second moment and the first moment is the discharge time corresponding to the temperature.

[0142] In some embodiments, the first end is discharged to the first sub-voltage at a third time after the first time, and the third time is earlier than the second time; and the discharging of the selected word line further includes:

[0143] From the third moment to the second moment, the selected word line continues to be discharged until the second end is discharged to the second sub-voltage.

[0144] In some embodiments, determining the discharge duration corresponding to the temperature based on the temperature of the memory includes:

[0145] determining a temperature difference between a temperature of the memory and a reference temperature;

[0146] Based on the temperature difference and the reference discharge duration, the discharge duration corresponding to the temperature is determined; wherein the reference discharge duration is the discharge duration corresponding to the reference temperature.

[0147] In some embodiments, the first voltage includes a programming voltage; and the operating method further includes:

[0148] During programming, a programming voltage is applied to the selected word line.

[0149] In some embodiments, the first voltage includes a pre-charge voltage; and the operating method further includes:

[0150] After programming and before program verification, a precharge voltage is applied to the selected word line.

[0151] Regarding the above method embodiment, reference may be made to the relevant description of the above device embodiment, which will not be repeated for the sake of brevity.

[0152] Based on the above memory, an embodiment of the present disclosure provides a memory system, including:

[0153] One or more memories 600 according to any one of the embodiments of the present disclosure;

[0154] A memory controller is coupled to the memory 600 and is configured to control the memory.

[0155] The memory controller can correspond to the reference Figure 1 Regarding the memory controller 106 in the illustrated embodiment, the functions, applications, and interactions between the memory 600 and the memory controller 106 are not described in detail here.

[0156] Based on the above memory, an embodiment of the present disclosure provides an electronic device, including: a memory system as in the embodiment of the present disclosure.

[0157] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0158] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0159] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0160] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0161] The above description is merely an embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory, characterized in that: include: a memory cell array, the memory cell array comprising a plurality of memory cells; A peripheral circuit is coupled to the memory cell array, wherein the peripheral circuit is configured to: Before program verification, discharging a selected word line from a first voltage to a second voltage; wherein the selected word line is coupled to a selected memory cell among the plurality of memory cells; During the programming verification, the selected word line is charged from the second voltage to a third voltage, where the third voltage is less than the first voltage; wherein, at different temperatures, the discharge time of the selected word line from the first voltage to the second voltage increases with increasing temperature.

2. The memory according to claim 1, wherein The peripheral circuit is further configured to: determining a temperature of the memory; Based on the temperature of the memory, a discharge duration corresponding to the temperature is determined.

3. The memory according to claim 2, wherein: The peripheral circuit is specifically configured as follows: The selected word line is discharged based on the word line driving inhibition signal and the discharge time corresponding to the temperature until the selected word line is discharged to the second voltage.

4. The memory according to claim 3, wherein: The selected word line includes a first end coupled to the peripheral circuit and a second end coupled to the memory cell; the second voltage includes a first sub-voltage and a second sub-voltage; and the peripheral circuit is specifically configured as follows: At a first moment, starting to discharge the selected word line; At a second moment after the first moment, discharging the selected word line ends; wherein, at the end of the discharge, the first end and the second end are discharged to the first sub-voltage and the second sub-voltage, respectively, and the second sub-voltage is greater than or equal to the first sub-voltage; and the difference between the second moment and the first moment is the discharge time corresponding to the temperature.

5. The memory according to claim 4, wherein: The first end is discharged to the first sub-voltage at a third time after the first time, and the third time is earlier than the second time; the peripheral circuit is specifically configured as follows: From the third moment to the second moment, the selected word line continues to be discharged until the second end is discharged to the second sub-voltage.

6. The memory according to claim 2, wherein: The peripheral circuit is specifically configured as follows: determining a temperature difference between a temperature of the memory and a reference temperature; Based on the temperature difference and a reference discharge duration, a discharge duration corresponding to the temperature is determined; wherein the reference discharge duration is the discharge duration corresponding to the reference temperature.

7. The memory according to claim 1, wherein: The first voltage includes a programming voltage; the peripheral circuit is further configured to: During programming, the program voltage is applied to the selected word line.

8. The memory according to claim 1, wherein: The first voltage includes a precharge voltage; the peripheral circuit is further configured to: After programming and before the program verification, the precharge voltage is applied to the selected word line.

9. The memory according to claim 1, wherein: The second voltage includes: -3V.

10. The memory according to claim 1, wherein: The memory includes: a NAND memory.

11. A method for operating a memory, characterized in that: The operation method includes: Before program verification, discharging a selected word line from a first voltage to a second voltage; wherein the selected word line is coupled to a selected memory cell among a plurality of memory cells; During the program verification, charging the selected word line from the second voltage to a third voltage; wherein the third voltage is lower than the first voltage; Wherein, at different temperatures, the discharge time of the selected word line from the first voltage to the second voltage increases with increasing temperature.

12. The operating method according to claim 11, characterized in that: The operation method further includes: determining a temperature of the memory; Based on the temperature of the memory, a discharge duration corresponding to the temperature is determined.

13. The operating method according to claim 12, characterized in that: Discharging the selected word line from a first voltage to a second voltage includes: The selected word line is discharged based on the word line driving inhibition signal and the discharge time corresponding to the temperature until the selected word line is discharged to the second voltage.

14. The operating method according to claim 13, characterized in that: The selected word line includes a first end coupled to a peripheral circuit and a second end coupled to the memory cell; The second voltage includes a first sub-voltage and a second sub-voltage; The discharging the selected word line comprises: At a first moment, starting to discharge the selected word line; At a second moment after the first moment, discharging the selected word line ends; wherein, at the end of the discharge, the first end and the second end are discharged to the first sub-voltage and the second sub-voltage, respectively, and the second sub-voltage is greater than or equal to the first sub-voltage; and the difference between the second moment and the first moment is the discharge time corresponding to the temperature.

15. The operating method according to claim 14, characterized in that: The first end portion is discharged to the first sub-voltage at a third time after the first time, and the third time is earlier than the second time; and the discharging of the selected word line further includes: From the third moment to the second moment, the selected word line continues to be discharged until the second end is discharged to the second sub-voltage.

16. The operating method according to claim 12, characterized in that: The determining, based on the temperature of the memory, a discharge duration corresponding to the temperature, includes: determining a temperature difference between a temperature of the memory and a reference temperature; Based on the temperature difference and a reference discharge duration, a discharge duration corresponding to the temperature is determined; wherein the reference discharge duration is the discharge duration corresponding to the reference temperature.

17. The operating method according to claim 11, characterized in that: The first voltage includes a programming voltage; the operating method further includes: During programming, the program voltage is applied to the selected word line.

18. The operating method according to claim 11, characterized in that: The first voltage includes a pre-charge voltage; and the operating method further includes: After programming and before the program verification, the precharge voltage is applied to the selected word line.

19. A memory system, characterized in that: include: One or more memories according to any one of claims 1 to 9; A memory controller is coupled to the memory and configured to control the memory.

20. An electronic device, characterized in that: include: The memory system of claim 19.

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