Memory device and operation method thereof

Abstract

The present disclosure provides a memory device and an operating method thereof. The operating method includes: charging the bit line to a read voltage level; coupling the bit line to the memory component; and adjusting the voltage level of the bit line from the read voltage level according to the data bit stored in the memory component. The read voltage level is less than a coercive voltage level of the memory component.

Description

Technical Field

[0001] This disclosure relates to a memory device and a method of operating the memory device. Background Art

[0002] The memory device performs a read operation. However, the memory state of the memory device is destroyed after the read operation, and a write-back operation is required after the read operation. During compute-in-memory (CiM) operations, the memory state of each memory cell cannot be identified after charge sharing. In other words, the memory state corresponding to the CiM weight is lost after the CiM operation. Summary of the Invention

[0003] This disclosure provides a method for operating a memory device, comprising the steps of: charging a bit line to a read voltage level; coupling the bit line to a memory component; and adjusting the voltage level of the bit line from the read voltage level based on a data bit stored in the memory component. The read voltage level is less than a coercive voltage level of the memory component.

[0004] This disclosure provides a memory device comprising a first memory cell, a converter, and a first bit line. The first memory cell is configured to store data bits. The converter is configured to read the data bits. The first bit line is coupled between the first memory cell and the converter. The first memory cell comprises a first switch and a first memory component. During a read operation, the first bit line is charged to a read voltage level. The read voltage level is less than a coercive voltage level of the first memory component.

[0005] This disclosure provides a method for operating a memory device, comprising the steps of storing a data bit in a memory component, charging a bit line to a read voltage level, closing a switch coupled between the memory component and the bit line, and sensing the bit line via a converter after the switch is closed. The read voltage level is less than a voltage level at which the polarization of the memory component is zero when the voltage difference between two terminals of the memory component is equal to the voltage level. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the embodiments of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a schematic diagram of a memory device according to some embodiments of the present disclosure;

[0008] Figure 2During a read operation according to some embodiments of the present disclosure, Figure 1 A timing diagram of the voltage levels of the word lines, bit lines, and plate lines shown in FIG;

[0009] Figure 3 is a schematic diagram illustrating the relationship between a voltage difference between two terminals of a memory component and polarization of the memory component according to some embodiments of the present disclosure;

[0010] Figure 4A is a schematic diagram of an equivalent capacitor of a bit line and a corresponding memory cell during a destructive read according to some embodiments of the present disclosure;

[0011] Figure 4B is a schematic diagram of an equivalent capacitor of a bit line and a corresponding memory cell during non-destructive read according to some embodiments of the present disclosure;

[0012] Figure 5A During a write operation according to some embodiments of the present disclosure, Figure 1 A timing diagram of the voltage levels of the word lines, bit lines, and plate lines shown in FIG;

[0013] Figure 5B is a diagram illustrating a relationship between a voltage difference between two terminals of a memory component and polarization of the memory component during a write operation for writing a first logic value according to some embodiments of the present disclosure;

[0014] Figure 5C is a diagram illustrating a relationship between a voltage difference between two terminals of a memory component and polarization of the memory component during a write operation for writing a first logic value according to some embodiments of the present disclosure;

[0015] Figure 5D is a diagram illustrating a relationship between a voltage difference between two terminals of a memory component and polarization of the memory component during a write operation for writing a second logic value according to some embodiments of the present disclosure;

[0016] Figure 5E is a diagram illustrating a relationship between a voltage difference between two terminals of a memory component and polarization of the memory component during a write operation for writing a second logic value according to some embodiments of the present disclosure;

[0017] Figure 6A According to some embodiments of the present disclosure Figure 1 a cross-sectional view of a memory device corresponding to the memory device shown in ;

[0018] Figure 6B For a memory device according to some embodiments of the present disclosure along Figure 6A A cross-sectional view of the line shown in ;

[0019] Figure 6C According to some embodiments of the present disclosure Figure 6A The layout diagram of the memory device shown in ;

[0020] Figure 7A For operations according to some embodiments of the present disclosure Figure 1 and Figure 6A A flowchart of a method of at least one of the semiconductor devices shown in;

[0021] Figure 7B For operations according to some embodiments of the present disclosure Figure 1 and Figure 6A A flowchart of a method of at least one of the semiconductor devices shown in;

[0022] Figure 8 For designing and manufacturing according to some embodiments of the present disclosure Figure 1 and Figure 6A A schematic diagram of a system including at least one of the semiconductor devices shown in ; and

[0023] Figure 9 FIG. 1 is a block diagram of an integrated circuit (IC) / semiconductor device manufacturing system and an associated IC manufacturing process according to some embodiments of the present disclosure.

[0024]

Explanation of symbols

[0025] 100:Memory device

[0026] 200: Timing diagram

[0027] 300: Schematic diagram

[0028] 500A: Timing Diagram

[0029] 500B, 500C, 500D, 500E: Schematic diagram

[0030] 600: Memory device

[0031] 700A, 700B: Method

[0032] 800: System

[0033] 802: Hardware processor

[0034] 804: Computer readable storage medium

[0035] 806: Computer Program Code

[0036] 808: Bus

[0037] 810: I / O interface

[0038] 812: Network interface

[0039] 814: Network

[0040] 816: Layout Design

[0041] 818: User Interface

[0042] 820: Manufacturing unit

[0043] 822: Manufacturing Tools

[0044] 900:IC manufacturing system

[0045] 920: Design Factory

[0046] 922:IC Design Layout

[0047] 930:Mask Factory

[0048] 932:Mask Data Preparation

[0049] 934:Mask Manufacturing

[0050] 940:IC wafer fab

[0051] 942:Semiconductor wafer

[0052] 960:IC device

[0053] A51~A56: Arrow

[0054] ADC0~ADC2: Converter

[0055] BL0~BL2: bit lines

[0056] BLC0, BLC1: curve

[0057] BLS: Bit Line Signal

[0058] CBL, CDR41~CDR43: capacitors

[0059] CG41~CG43: Capacitor Bank

[0060] CV30,CV31: Curve

[0061] DP30, DP31: Polarization difference

[0062] FP61, FP62, FP63, FP64: memory part

[0063] FR61: Memory Structure

[0064] GWL1,GWL2: Gate structure

[0065] ILD6: Dielectric Structure

[0066] L6: Line

[0067] MBL1, MBL2, MBL3: conductive structure

[0068] MC00~MC03: memory unit

[0069] MC10~MC13: memory unit

[0070] MC20~MC23: memory unit

[0071] ME00~ME23: memory components

[0072] ME61, ME62, ME63, ME64: Memory components

[0073] MPL: Conductive structure

[0074] P21~P26,P51~P54: Time period

[0075] P31, P32, P33, P34: Polarization

[0076] PL: Plate Line

[0077] PLC: Curve

[0078] PLS: Plate Line Signal

[0079] PR30, PR31, PS30, PS31: points

[0080] SA71~SA73: Operation

[0081] SB6:Substrate

[0082] SB71~SB74: Operation

[0083] SD61~SD65: Source / drain structure

[0084] SWLS: Selected word line signal

[0085] T00~T23: switch

[0086] TN61~TN65: Electrode

[0087] TP61,TP62,TP63,TP64:Electrode part

[0088] USWLS: Unselected word line signal

[0089] V61~V69,V610:Through hole structure

[0090] VC,-VC: coercive voltage level

[0091] VGND: Ground voltage level

[0092] VH,-VH: voltage level

[0093] VREAD0, VREAD1: Read voltage level

[0094] VWL: Write voltage level

[0095] WL0~WL3: word line

[0096] WLC: Curve DETAILED DESCRIPTION

[0097] The following disclosure provides many different embodiments or examples to implement the different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the embodiments of this disclosure may repeat element symbols and / or letters in each example. This repetition is for simplicity and clarity purposes and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0098] In addition, for ease of description, spatially relative terms (such as "below," "beneath," "lower," "above," "upper," and the like) may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features) shown in the figures. Spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientations depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted similarly. As used herein, "approximately," "about," "approximately," or "substantially" may generally mean within 20%, within 10%, or within 5% of a given value or range. Numerical quantities given herein are approximate, meaning that the terms "approximately," "about," "approximately," or "substantially" may be inferred unless expressly specified. However, those skilled in the art will understand that the values or ranges listed in the specification are merely examples and may decrease or change as integrated circuits shrink.

[0099] The terms used throughout the following description and claims generally have their ordinary meanings as established in the art or in the specific context in which each term is used. One of ordinary skill in the art will understand that a component or process may be referred to by different names. The many different embodiments detailed in this specification are illustrative only and do not in any way limit the scope and spirit of this disclosure or any exemplified term.

[0100] It is worth noting that the terms "first" and "second" used herein to describe various components or procedures are intended to distinguish one component or procedure from another. However, the components, procedures, and their sequences should not be limited by these terms. For example, a first component may be referred to as a second component, and a second component may similarly be referred to as a first component without departing from the scope of this disclosure.

[0101] In the following description and claims, the terms "include," "comprising," "containing," "having," "involving," and the like should be understood as open ended, that is, interpreted as including but not limited to. As used herein, the term "and / or" includes any one of the associated listed items and all combinations of one or more of the associated listed items, and is not mutually exclusive.

[0102] Figure 1 FIG. 1 is a schematic diagram of a memory device 100 according to some embodiments of the present disclosure. Figure 1 Memory device 100 is illustratively shown as including memory cells MC00-MC03, MC10-MC13, MC20-MC23, converters ADC0-ADC2, word lines WL0-WL3, bit lines BL0-BL2, and plate line PL. The present disclosure is not limited thereto. In various embodiments, memory device 100 includes various numbers of memory cells, converters, word lines, and bit lines.

[0103] In some embodiments, each of the memory cells MC00-MC03, MC10-MC13, and MC20-MC23 is used to store a corresponding data bit. Converters ADC0-ADC2 are used to convert signals associated with the data bit to read the data bit. In some embodiments, converters ADC0-ADC2 are implemented by analog-to-digital converters.

[0104] like Figure 1illustratively shown in FIG, each of memory cells MC00-MC03, MC10-MC13, and MC20-MC23 includes a corresponding switch and a corresponding memory element. Specifically, memory cell MC00 includes switch T00 and memory element ME00. Memory cell MC01 includes switch T01 and memory element ME01. Memory cell MC11 includes switch T11 and memory element ME11, and so on. Memory cell MC23 includes switch T23 and memory element ME23. In some embodiments, switches T00-T23 are implemented by transistors, and memory elements ME00-ME23 are implemented by variable capacitors (such as ferroelectric capacitors) that store logic values through polarization.

[0105] like Figure 1 As illustratively shown in FIG, first terminals of switches T00-T03 are coupled to bit line BL0, first terminals of switches T10-T13 are coupled to bit line BL1, and first terminals of switches T20-T23 are coupled to bit line BL2. Second terminals of switches T00-T23 are coupled to first terminals of memory units ME00-ME23, respectively. Second terminals of memory units ME00-ME23 are each coupled to plate line PL. Control terminals of switches T00, T10, and T20 are coupled to word line WL0, control terminals of switches T01, T11, and T21 are coupled to word line WL1, control terminals of switches T02, T12, and T22 are coupled to word line WL2, and control terminals of switches T03, T13, and T23 are coupled to word line WL3.

[0106] In some embodiments, during a read operation, converter ADC0 is used to convert the bit line signal of bit line BL0 into a digital signal. Converter ADC1 is used to convert the bit line signal of bit line BL1 into a digital signal. Converter ADC2 is used to convert the bit line signal of bit line BL2 into a digital signal.

[0107] like Figure 1 As illustratively shown in FIG, each of the bit lines BL0-BL2 has an equivalent capacitor CBL. During a read operation, the memory elements ME00-ME23 share charge with the capacitor CBL to adjust the voltage level of the bit line signal of the bit lines BL0-BL2 according to the logic value stored by the memory elements ME00-ME23. Figure 2 Further details of the read operation are described in the associated embodiments.

[0108] Figure 2 During a read operation according to some embodiments of the present disclosure, Figure 12. A timing diagram 200 of the voltage levels of the word lines, bit lines, and plate lines is shown in FIG. The horizontal axis of the timing diagram 200 corresponds to time, while the vertical axis of the timing diagram 200 corresponds to voltage. Figure 2 As illustratively shown in FIG. 2 , the timing diagram 200 includes time periods P21 to P26 that are sequentially arranged.

[0109] In some embodiments, during a read operation, multiple word lines are activated to turn on switches in corresponding memory cells. Figure 1 and Figure 2 ,exist Figure 2 In the embodiment shown in FIG, during a read operation, word lines WL0-WL3 are activated to turn on switches T00-T23. However, the embodiments of the present disclosure are not limited thereto. In various embodiments, various numbers of word lines are activated.

[0110] like Figure 2 illustratively shown in FIG. , timing diagram 200 includes curves WLC, BLC0, BLC1, and PLC. For illustrative purposes, curve WLC corresponds to the voltage level of word lines WL0-WL3, curves BLC0 and BLC1 correspond to the voltage level of bit line BL1, and curve PLC corresponds to the voltage level of plate line PL. However, the embodiments of the present disclosure are not limited thereto. For example, in other embodiments, curves BLC0 and BLC1 correspond to the voltage level of bit line BL0 or bit line BL2.

[0111] Reference Figure 1 and Figure 2 , the curve BLC0 corresponds to the case where each of the memory elements ME10 ˜ ME13 stores a logic value of 0, and the curve BLC1 corresponds to the case where each of the memory elements ME10 ˜ ME13 stores a logic value of 1.

[0112] During period P21 , the memory device 100 is in a standby state. Therefore, each of the word lines WL0 - WL3 , the bit line BL1 , and the plate line PL has a ground voltage level VGND, so that the switches T10 - T13 are turned off.

[0113] During period P22, bit line BL1 is precharged to read voltage level VREAD1, and word lines WL0-WL3 are kept at ground voltage level VGND, so that switches T10-T13 are turned off. It should be noted that read voltage level VREAD1 is less than coercive voltage level VC. Figure 3 Further details of the coercive voltage level VC are described in the related embodiments. In some embodiments, during period P22, bit lines BL0 and BL2 are also precharged to a read voltage level VREAD1.

[0114] During period P23, word lines WL0-WL3 are raised to the enable voltage level VWL, turning on switches T00-T23. Specifically, switches T10-T13 are turned on, allowing bit line BL1 to share charge with memory elements ME10-ME13. Therefore, the voltage level of bit line BL1 is adjusted based on the logic values stored in memory elements ME10-ME13.

[0115] Referring to curve BLC1, in response to each of memory elements ME10-ME13 storing a logic value of 1, bit line BL1 is maintained at read voltage level VREAD1. Referring to curve BLC0, in response to each of memory elements ME10-ME13 storing a logic value of 0, bit line BL1 is adjusted to read voltage level VREAD0. In some embodiments, read voltage level VREAD0 is lower than read voltage level VREAD1.

[0116] In some embodiments, memory elements ME10-ME13 store at least one logic value 0 and at least one logic value 1. In such embodiments, bit line BL1 is adjusted to a voltage level between voltage levels VREAD0 and VREAD1. In response to a higher number of logic values 1, the voltage level is closer to voltage level VREAD1. In response to a higher number of logic values 0, the voltage level is closer to voltage level VREAD0.

[0117] During period P24, converters ADC0-ADC2 are enabled to sense corresponding bit lines BL0-BL2. Specifically, converter ADC1 senses bit line BL1. In the case corresponding to curve BLC0, bit line BL1 is maintained at read voltage level VREAD0. In the case corresponding to curve BLC1, bit line BL1 is maintained at read voltage level VREAD1.

[0118] During period P25 , word lines WL0 - WL3 are adjusted to the ground voltage level VGND to turn off switches T00 - T23 . Specifically, switches T10 - T13 are turned off, so that bit line BL1 stops sharing charges with memory elements ME10 - ME13 .

[0119] During period P26, the memory device 100 returns to the standby state. Therefore, the bit line BL1 is adjusted to the ground voltage level VGND. In some embodiments, after period P26, the operations of periods P22 to P25 are performed again to perform another read operation.

[0120] In some embodiments, during a read operation, the voltage level of bit line BL0 corresponds to the sum of the logic values stored in memory elements ME00-ME03, the voltage level of bit line BL1 corresponds to the sum of the logic values stored in memory elements ME10-ME13, and the voltage level of bit line BL2 corresponds to the sum of the logic values stored in memory elements ME20-ME23. Therefore, the read operation is referred to as a compute-in-memory (CiM) operation.

[0121] Figure 3 Graph 300 illustrates the relationship between the voltage difference between two terminals of a memory device and the polarization of the memory device according to some embodiments of the present disclosure. The horizontal axis of graph 300 corresponds to voltage level, while the vertical axis of graph 300 corresponds to polarization. In some embodiments, the voltage level is expressed in volts, while the polarization is expressed in microcoulombs per square centimeter (μC / cm2). 2 ).

[0122] Reference Figure 1 and Figure 3 For illustrative purposes, the voltage difference and polarization of the memory element ME11 are described below as an example of the schematic diagram 300. However, the present disclosure is not limited thereto. The features described by the schematic diagram 300 are also applicable to other memory elements.

[0123] like Figure 3 As illustratively shown in FIG. 3 , diagram 300 includes curves CV31 and CV30. As the voltage difference between the two terminals of memory element ME11 changes, the state of memory element ME11 changes along curves CV31 and CV30. The polarization of memory element ME11 increases in response to the increase in the voltage difference. When the absolute value of the voltage difference between the two terminals of memory element ME11 equals the coercive voltage level VC, the polarization of memory element ME11 equals the zero voltage level.

[0124] In some embodiments, during a read operation, the plate line PL coupled to the memory element ME11 is maintained at the ground voltage level VGND. Therefore, the voltage difference between the two terminals of the memory element ME11 corresponds to the voltage level of the bit line BL1.

[0125] like Figure 3 As illustratively shown in FIG. , curve CV30 includes points PS30 and PR30, while curve CV31 includes points PS31 and PR31. At point PS30, plate line PL has a ground voltage level VGND, and switch T11 is turned off, resulting in a zero voltage difference between the two terminals of memory element ME11. Consequently, memory element ME11 has a polarization P31 to store a logic value of 0.

[0126] During a read operation, switch T11 is turned on, and bit line BL1 has a read voltage level VREAD1. This causes the voltage difference between the two terminals of memory element ME11 to be the read voltage level VREAD1. Consequently, the state of memory element ME11 changes from point PS30 to point PR30, causing memory element ME11 to have a polarization P32. In some embodiments, polarization P32 is less than zero and greater than polarization P31.

[0127] After the read operation, the switch T11 is turned off, so that the voltage difference between the two terminals of the memory unit ME11 returns to zero. Therefore, the state of the memory unit ME11 changes from point PR30 to point PS30. Figure 2 and Figure 3 , point PS30 corresponds to the time periods P21 and P26, and point PR30 corresponds to the time period P23.

[0128] Similarly, at point PS31, the plate line PL has the ground voltage level VGND and the switch T11 is turned off, so that the voltage difference between the two terminals of the memory element ME11 is zero. The memory element ME11 has a polarization P33 to store a logic value of 1.

[0129] During a read operation, switch T11 is turned on, and bit line BL1 has a read voltage level VREAD1. This causes the voltage difference between the two terminals of memory element ME11 to be the read voltage level VREAD1. Consequently, the state of memory element ME11 changes from point PS31 to point PR31, causing memory element ME11 to have a polarization P34. In some embodiments, polarization P33 is less than polarization P34 and greater than zero.

[0130] After the read operation, the switch T11 is turned off, so that the voltage difference between the two terminals of the memory element ME11 returns to zero. Therefore, the state of the memory element ME11 changes from point PR31 to point PS31. Figure 2 and Figure 3 , point PS31 corresponds to the time periods P21 and P26, and point PR31 corresponds to the time period P23.

[0131] In some approaches, during a read operation, a bit line coupled to a memory device has a read voltage level greater than a coercive voltage level, causing the memory device to switch from a logic value of 0 to a logic value of 1. In other words, a destructive read is performed. Consequently, a logic value of 0 cannot be recovered during a CiM operation.

[0132] Compared to the above method, in some embodiments of the present disclosure, during a read operation, the bit line BL1 coupled to the memory element ME11 has a read voltage level VREAD1 that is less than the coercive voltage level VC, so that the logic value stored in the memory element ME11 is not lost after the CiM operation and can be reused for the next CiM operation.

[0133] In some embodiments, the read voltage level VREAD1 is within a range of 0.3 to 0.8 times the coercive voltage level VC. The read voltage level VREAD1 depends on the sensing resolution of the converters ADC0-ADC2, the polarization-voltage (PV) curves of the memory elements ME00-ME23 (such as curves CV30 and CV31), and the number of cells per bit line.

[0134] Reference Figure 1 and Figure 3 For illustrative purposes, the following describes features of converter ADC1, bit line BL1, and memory elements ME10-ME13 (particularly memory element ME11) as an example of read voltage level VREAD1. However, the present disclosure is not limited thereto. Features associated with read voltage level VREAD1 are also applicable to other converters, other bit lines, and other memory elements.

[0135] In some embodiments, the sensing resolution of the converter is used to distinguish different sums of logic values stored in memory elements ME10-ME13. Each of memory elements ME10-ME13 stores a logic value of 0 or 1. The sum is one of logic values 0, 1, 2, 3, and 4.

[0136] Reference Figure 2 , voltage levels VREAD0 and VREAD1 correspond to sum values 0 and 4, respectively. The three voltage levels between voltage levels VREAD0 and VREAD1 correspond to sum values 1, 2, and 3, respectively.

[0137] To distinguish the sum values 0-4 from each other, converter ADC1 has a sensing resolution capable of distinguishing the five voltage levels. If the sensing resolution of converter ADC1 is too low to distinguish the five voltage levels, voltage level VREAD1 is increased to widen the differences between the five voltage levels. In other words, when the sensing resolution of converter ADC1 is higher, a lower voltage level VREAD1 can be used. In some embodiments, as the sensing resolution of converter ADC1 increases, voltage level VREAD1 decreases. When the sensing resolution of converter ADC1 decreases, voltage level VREAD1 increases.

[0138] For example, when the converter ADC1 has a first sensing resolution, the read voltage level VREAD1 has a first value. When the converter ADC1 has a second sensing resolution higher than the first sensing resolution, the read voltage level VREAD1 has a second value lower than the first value.

[0139] Regarding the relationship between PV curves CV30 and CV31 and read voltage level VREAD1, a processor can calculate signal difference SD3 associated with curves CV30 and CV31 to determine read voltage level VREAD1. Specifically, polarization difference DP30 is equal to the difference between polarizations P31 and P32, while polarization difference DP31 is equal to the difference between polarizations P33 and P34. Signal difference SD3 is equal to polarization difference DP30 minus polarization difference DP31, i.e., SD3 = DP30 - DP31.

[0140] In some embodiments, for different structures of the memory unit ME11, the curves CV30 and CV31 have different shapes. When the difference between the curves CV30 and CV31 is small, the signal difference SD3 is small. When the difference between the curves CV30 and CV31 is large, the signal difference SD3 is large. Figure 6A The associated embodiments describe further details of the structure of the memory unit ME11.

[0141] For example, when the polarization difference between polarizations P31 and P34 has a first polarization difference value (i.e., the difference between curves CV30 and CV31 is small), signal difference SD3 has a first difference value. When the polarization difference between polarizations P31 and P34 has a second polarization difference value greater than the first difference value (i.e., the difference between curves CV30 and CV31 is large), signal difference SD3 has a second difference value greater than the first difference value. In some embodiments, a larger signal difference SD3 favors a lower read voltage level VREAD1. In other words, a lower read voltage level VREAD1 corresponds to a larger signal difference SD3. In some embodiments, as signal difference SD3 increases, voltage level VREAD1 decreases. As signal difference SD3 decreases, voltage level VREAD1 increases.

[0142] Therefore, in some embodiments, in response to signal difference SD3 having a first difference value, read voltage level VREAD1 has a first value. In response to signal difference SD3 having a second difference value greater than the first difference value, read voltage level VREAD1 has a second value less than the first value. In some embodiments, read voltage level VREAD1 is determined after curves CV30 and CV31 are obtained by measuring memory device ME11.

[0143] Regarding the relationship between the number of cells per bit line and the read voltage level VREAD1, as the number of cells per bit line increases, more cells can be used to store the same data bit. Consequently, memory device 100 has a larger sensing window (i.e., the difference between voltage levels VREAD1 and VREAD0) relative to the sensing resolution of converter ADC1, and the read voltage level VREAD1 can be reduced. In some embodiments, the number of cells per bit line refers to the number of memory cells coupled to the bit line during a read operation.

[0144] For example, if bit line BL1 has two cells, that is, only memory cells MC10 and MC11 are coupled to bit line BL1, with each memory cell storing one data bit. During a read operation, both memory elements ME10 and ME11 share charge with bit line BL1. Therefore, the difference between voltage levels VREAD1 and VREAD0 is small, and the larger read voltage level VREAD1 is used to meet the sensing resolution of converter ADC1.

[0145] Compared to the above case, when bit line BL1 has four cells, that is, memory cells MC10-MC13 are coupled to bit line BL1, two memory cells are used to store one data bit. During a read operation, the four memory cells ME10-MC13 share charge with bit line BL1. Therefore, the difference between voltage levels VREAD1 and VREAD0 is larger, and the read voltage level VREAD1 can be lower.

[0146] In some embodiments, in response to bit line BL1 having a first number of cells, read voltage level VREAD1 has a first value. In response to bit line BL1 having a second number of cells greater than the first number of cells, read voltage level VREAD1 has a second value less than the first value. In some embodiments, as the number of cells on bit line BL1 increases, read voltage level VREAD1 decreases. As the number of cells on bit line BL1 decreases, read voltage level VREAD1 increases.

[0147] Figure 4A Schematic diagram of a bit line and an equivalent capacitor of a corresponding memory cell during a destructive read according to some embodiments of the present disclosure. Figure 4A illustratively shown in FIG, a schematic diagram includes capacitors CDR41-CDR43 and CBL. Capacitor CBL corresponds to the equivalent capacitor of the bit line, and capacitors CDR41-CDR43 correspond to the equivalent capacitors of the memory cells coupled to the bit line. In various embodiments, various numbers of memory cells are coupled to the bit line.

[0148] For example, refer to Figure 4A and Figure 1 , capacitor CBL corresponds to the equivalent capacitor of bit line BL1, and capacitors CDR41-CDR43 correspond to the equivalent capacitors of memory elements ME10, ME11 and ME13, respectively.

[0149] like Figure 4A illustratively shown in FIG, before the CiM read operation, the capacitor CBL stores charges and does not share charges with the capacitors CDR41 ˜ CDR43 . After the CiM read operation is performed, the capacitor CBL shares charges with the capacitors CDR41 ˜ CDR43 .

[0150] Figure 4B Schematic diagram of a bit line and an equivalent capacitor of a corresponding memory cell during non-destructive read according to some embodiments of the present disclosure. Figure 4B , the schematic diagram includes capacitor groups CG41-CG43 and capacitor CBL. Capacitor CBL corresponds to an equivalent capacitor of a bit line, and capacitor groups CG41-CG43 correspond to an equivalent capacitor of a memory cell coupled to the bit line.

[0151] like Figure 4B As illustratively shown in FIG, each of capacitor groups CG41-CG43 includes multiple capacitors, such as four capacitors. Each capacitor corresponds to a memory cell. Before a CiM read operation, capacitor CBL stores charge and does not share charge with capacitor groups CG41-CG43. After a CiM read operation, capacitor CBL shares charge with capacitor groups CG41-CG43.

[0152] Reference Figure 4A and Figure 4B The per-cell sensing window corresponding to the signal difference SD3 for non-destructive reading is approximately 0.2 to 0.25 times that of destructive reading. To balance the per-cell sensing window loss in non-destructive reading, 4 to 5 memory cells per bit line (i.e., the number of cells per bit line) are used.

[0153] exist Figure 4A and Figure 4B In the embodiment shown in , capacitor group CG41 stores the charge of capacitor CDR41, capacitor group CG42 stores the charge of capacitor CDR42, and capacitor group CG43 stores the charge of capacitor CDR43. Therefore, by increasing the number of cells, the sensing window is increased.

[0154] Figure 5A During a write operation according to some embodiments of the present disclosure, Figure 15. A timing diagram 500A is shown showing the voltage levels of the word lines, bit lines, and plate lines shown in FIG. The horizontal axis of the timing diagram 500A corresponds to time, while the vertical axis of the timing diagram 500A corresponds to voltage. Figure 5A As illustratively shown in FIG. 5 , timing diagram 500A includes voltage levels of the bit line signal BLS, the selected word line signal SWLS, the unselected word line signal USWLS, and the plate line signal PLS during time periods P51 - P54 that are sequentially arranged.

[0155] Reference Figure 5A and Figure 1 Bit line signal BLS corresponds to the voltage level of one of bit lines BL0-BL2. Selected word line signal SWLS corresponds to the voltage level of a selected one of word lines WL0-WL3, while unselected word line signal USWLS corresponds to the voltage levels of the other word lines WL0-WL3. Plate line signal PLS corresponds to the voltage level of plate line PL.

[0156] For the purpose of explanation, the bit line BL1, the word line WL1, and the memory element ME11 are described below as an example for explaining the bit line signal BLS and the selected word line signal SWLS. Figure 5A In the embodiment shown in FIG, bit line signal BLS and selected word line signal SWLS are located on bit line BL1 and word line WL1, respectively. However, the present disclosure is not limited thereto. Features associated with bit line signal BLS and selected word line signal SWLS are also applicable to other bit lines, other word lines, and other memory components.

[0157] During period P51, each of the bit line signal BLS, the selected word line signal SWLS, the unselected word line signal USWLS, and the plate line signal PLS has the ground voltage level VGND. Therefore, the switches T00-T23 are turned off.

[0158] During period P52, the selected word line signal SWLS rises to the write voltage level VWL, turning on switches T01, T11, and T21. In response to bit line BL1 carrying a logic value of 1, bit line signal BLS rises to a voltage level VH. At this time, plate line signal PLS is held at ground voltage level VGND, causing the voltage difference between the two terminals of memory element ME11 to be voltage level VH. Consequently, a logic value of 1 is written into memory element ME11. In some embodiments, voltage level VH is greater than coercive voltage level VC.

[0159] During period P53, the selected word line signal SWLS is maintained at the write voltage level VWL, causing switches T01, T11, and T21 to remain turned on. In response to bit line BL1 carrying a logic value of 0, bit line signal BLS is maintained at ground voltage level VGND. At this time, plate line signal PLS rises to voltage level VH, causing the voltage difference between the two terminals of memory element ME11 to become voltage level -VH (i.e., the negative of voltage level VH). Consequently, a logic value of 0 is written into memory element ME11. At the end of period P53, plate line signal PLS is adjusted to ground voltage level VGND.

[0160] During period P54, each of the bit line signal BLS and the selected word line signal SWLS is adjusted to the ground voltage level VGND. Therefore, the switches T00-T23 are turned off, and the write operation is completed.

[0161] Figure 5B Schematic diagram 500B illustrates the relationship between the voltage difference between two terminals of memory element ME11 and the polarization of memory element ME11 during a write operation for writing a logic value 1 according to some embodiments of the present disclosure. The horizontal axis of schematic diagram 500B corresponds to voltage level, while the vertical axis of schematic diagram 500B corresponds to polarization. Schematic diagram 500B corresponds to a case where memory element ME11 stores a logic value of 0 before the write operation and is written with a logic value of 1 after the write operation.

[0162] Reference Figure 3 and Figure 5B , schematic diagram 500B is a specific embodiment of schematic diagram 300. Figure 5B Follow and Figure 3 Similar marking rules. Figure 5B illustratively shown in FIG, before a write operation, the memory element ME11 is at point PS30 to store a logic value of 0. During the write operation, in response to the voltage difference between the two terminals of the memory element ME11 being adjusted to a voltage level VH, the state of the memory element ME11 moves along arrow A51 to point P51 corresponding to the voltage level VH, and then moves along arrow A52 to point PS31 to store a logic value of 1.

[0163] Figure 5C Schematic diagram 500C illustrates the relationship between the voltage difference between two terminals of memory element ME11 and the polarization of memory element ME11 during a write operation for writing a logic value 1 according to some embodiments of the present disclosure. The horizontal axis of schematic diagram 500C corresponds to voltage level, while the vertical axis of schematic diagram 500C corresponds to polarization. Schematic diagram 500C corresponds to a case where memory element ME11 stores a logic value 1 before the write operation and is written with the logic value 1 after the write operation.

[0164] Reference Figure 3 and Figure 5C , schematic diagram 500C is a specific embodiment of schematic diagram 300. Figure 5C Follow and Figure 3 Similar marking rules. Figure 5C illustratively shown in FIG, before a write operation, the memory element ME11 is at point PS31 to store a logic value of 1. During the write operation, in response to the voltage difference between the two terminals of the memory element ME11 being adjusted to a voltage level VH, the state of the memory element ME11 moves along arrow A53 to point P51 corresponding to the voltage level VH, and then moves along arrow A52 to point PS31 to store a logic value of 1.

[0165] Figure 5D Schematic diagram 500D illustrates the relationship between the voltage difference between two terminals of memory element ME11 and the polarization of memory element ME11 during a write operation for writing a logic value 0 according to some embodiments of the present disclosure. The horizontal axis of schematic diagram 500D corresponds to voltage level, while the vertical axis of schematic diagram 500D corresponds to polarization. Schematic diagram 500D corresponds to a case where memory element ME11 stores a logic value 0 before the write operation and is written with a logic value 0 after the write operation.

[0166] Reference Figure 3 and Figure 5D , schematic diagram 500D is a specific embodiment of schematic diagram 300. Figure 5D Follow and Figure 3 Similar marking rules. Figure 5D illustratively shown in FIG, before a write operation, the memory element ME11 is at point PS30 to store a logic value of 0. During the write operation, in response to the voltage difference between the two terminals of the memory element ME11 being adjusted to a voltage level of -VH, the state of the memory element ME11 moves along arrow A54 to point P52 corresponding to the voltage level of -VH, and then moves along arrow A55 to point PS30 to store a logic value of 0.

[0167] Figure 5E Schematic diagram 500E illustrates the relationship between the voltage difference between two terminals of memory element ME11 and the polarization of memory element ME11 during a write operation for writing a logic value 0 according to some embodiments of the present disclosure. The horizontal axis of schematic diagram 500E corresponds to voltage level, while the vertical axis of schematic diagram 500E corresponds to polarization. Schematic diagram 500E corresponds to a case where memory element ME11 stores a logic value 1 before the write operation and is written with a logic value 0 after the write operation.

[0168] Reference Figure 3 and Figure 5E , schematic diagram 500E is a specific embodiment of schematic diagram 300. Figure 5E Follow and Figure 3 Similar marking rules. Figure 5E illustratively shown in FIG, before a write operation, the memory element ME11 is at point PS31 to store a logic value of 1. During the write operation, in response to the voltage difference between the two terminals of the memory element ME11 being adjusted to a voltage level of -VH, the state of the memory element ME11 moves along arrow A56 to point P52 corresponding to the voltage level of -VH, and then moves along arrow A55 to point PS30 to store a logic value of 0.

[0169] Figure 6A According to some embodiments of the present disclosure Figure 1 The memory device 100 shown in FIG. 1 is a cross-sectional view of the memory device 600 corresponding to the memory device 100. Figure 6A illustratively shown in FIG, the memory device 600 includes a substrate SB6, source / drain structures SD61-SD63, via structures V61-V66, gate structures GWL1, GWL2, conductive structures MBL1, MPL, electrodes TN61-TN63, a memory structure FR61 and a dielectric structure ILD6.

[0170] like Figure 6A illustratively shown in FIG, source / drain structures SD61-SD63 are formed in substrate SB6 and separated from each other along the X-direction. Gate structures GWL1 and GWL2 are formed above substrate SB6 and separated from substrate SB6. Along the Z-direction, portions of dielectric structure ILD6 are formed above substrate SB6 and below gate structures GWL1 and GWL2. Conductive structure MBL1 is formed above gate structures GWL1 and GWL2 and below electrode TN62. In some embodiments, the X-direction and the Z-direction are perpendicular to each other.

[0171] In some embodiments, the source / drain structure SD61 is coupled to the electrode TN61 via the via structure V61 , the source / drain structure SD63 is coupled to the electrode TN62 via the via structure V62 , and the source / drain structure SD62 is coupled to the conductive structure MBL1 via the via structure V63 .

[0172] like Figure 6AAs illustratively shown in FIG6 , electrode TN63 includes electrode portions TP61 and TP62. Memory structure FR61 includes memory portions FP61 and FP62. Memory portions FP61, FP62, and electrodes TN61, TN62 each have a U-shape. Memory portion FP61 is interposed between electrode TN61 and electrode portion TP61. Memory portion FP62 is interposed between electrode TN62 and electrode portion TP62.

[0173] In some embodiments, the memory portion FP61, the electrode TN61, and the electrode portion TP61 are configured to operate as the memory element ME61. The memory portion FP62, the electrode TN62, and the electrode portion TP62 are configured to operate as the memory element ME62.

[0174] like Figure 6A As illustratively shown in FIG, electrode TN63 is coupled to conductive structure MPL via via structures V64-V66. Via structure V64 is formed directly above electrode portion TP61. Via structure V66 is formed directly above electrode portion TP62. Via structure V65 is formed along the X direction between via structures V64 and V66. Dielectric structure ILD6 is formed between these components.

[0175] In some embodiments, substrate SB6 is implemented using silicon. Via structures V61-V66 and conductive structures MBL1 and MPL are implemented using metal. Gate structures GWL1 and GWL2 are implemented using a gate material such as polysilicon. Electrodes TN61-TN63 are implemented using titanium nitride (TiN). Memory structure FR61 is implemented using a ferroelectric material such as hafnium zirconium oxide (HfZrOx) or hafnium silicon oxide (HfSiOx). Dielectric structure ILD6 is also known as an interlayer dielectric or intermetallic dielectric and is implemented using silicon oxide (SiOx) or other low-k dielectric materials.

[0176] Reference Figure 1 and Figure 6A Memory device 600 is an embodiment of memory device 100. In some embodiments, bit line BL1, word lines WL1 and WL2, plate line PL, and memory elements ME11 and ME12 are implemented by conductive structure MBL1, gate structures GWL1 and GWL2, conductive structure MPL, and memory elements ME61 and ME62. Source / drain structures SD61 and SD62 and gate structure GWL1 operate as a transistor corresponding to switch T11. Source / drain structures SD63 and SD62 and gate structure GWL2 operate as a transistor corresponding to switch T12.

[0177] In alternative embodiments, switches T11 and T12 (as well as other switches in the memory device 100 ) are implemented by back-end-of-line (BEOL) compatible polysilicon thin film transistors (TFTs) or indium gallium zinc oxide (IGZO) TFTs used in three-dimensional (3D) stacked ferroelectric random-access memory (FeRAM).

[0178] Reference Figure 3 and Figure 6A The shapes of curves CV30 and CV31 are associated with the configuration of memory structure FR61. In some embodiments, curves CV30 and CV31 vary depending on the thickness of memory structure FR61, the composition of memory structure FR61, and the interface between memory structure FR61 and electrodes (such as electrodes TN61-TN63). In other words, signal difference SD3 varies depending on the thickness of memory structure FR61, the composition of memory structure FR61, and the interface between memory structure FR61 and electrodes.

[0179] Figure 6B The memory device 600 according to some embodiments of the present disclosure is Figure 6A The cross-sectional view of line L6 shown in FIG. Figure 6B Memory device 600 illustratively shows that it further includes source / drain structures SD64-SD65, isolation structures IS61 and IS62, via structures V67-V69 and V610, conductive structures MBL2 and MBL3, and electrodes TN64-TN65. Electrode TN63 further includes electrode portions TP63 and TP64. Memory structure FR61 further includes memory portions FP63 and FP64.

[0180] like Figure 6B illustratively shown in FIG, source / drain structures SD63-SD65 are formed in substrate SB6 and separated from each other along the Y direction. Isolation structure IS61 is formed in substrate SB6 and serves to isolate source / drain structures SD63 and SD64. Isolation structure IS62 is formed in substrate SB6 and serves to isolate source / drain structures SD65 and SD64. In some embodiments, the Y direction, X direction, and Z direction are perpendicular to each other.

[0181] In some embodiments, source / drain structure SD64 is coupled to electrode TN64 via via structure V67. Source / drain structure SD65 is coupled to electrode TN65 via via structure V68. Along the Y direction, via structure V62, conductive structure MBL1, via structure V67, conductive structure MBL2, via structure V68, and conductive structure MBL3 are sequentially arranged and separated from each other.

[0182] like Figure 6B illustratively shown in FIG, each of the memory portions FP63, FP64 and the electrodes TN64, TN65 has a U-shape. The memory portion FP63 is interposed between the electrode TN64 and the electrode portion TP63. The memory portion FP64 is interposed between the electrode TN65 and the electrode portion TP64.

[0183] In some embodiments, memory portion FP63, electrode TN64, and electrode portion TP63 are configured to operate as memory element ME63. Memory portion FP64, electrode TN65, and electrode portion TP64 are configured to operate as memory element ME64.

[0184] like Figure 6B As illustratively shown in FIG, electrode TN63 is coupled to conductive structure MPL via via structures V69 and V610. Via structure V69 is formed directly above electrode portion TP63. Via structure V610 is formed directly above electrode portion TP64.

[0185] Reference Figure 1 and Figure 6A In some embodiments, the bit line BL2 and the memory element ME12 are implemented by the conductive structure MBL2 and the memory element ME63. The source / drain structures SD63 and SD64 are used to operate as two terminals of the switch T21.

[0186] Figure 6C According to some embodiments of the present disclosure Figure 6A The layout diagram of the memory device 600 is shown in FIG. Figure 6C In the figure, the Z direction points out from the paper. Figure 6C As illustratively shown in FIG, each of the gate structures GWL1 and GWL2 is elongated along the Y direction. Each of the conductive structures MBL1 and MBL2 is elongated along the X direction. The conductive structure MPL extends along the XY plane.

[0187] In some embodiments, the conductive structure MPL is implemented by a sheet metal layer that covers all memory cells in the same array, such as Figure 1 The memory cells MC00 to MC23 shown in FIG.

[0188] Figure 7AFor operations according to some embodiments of the present disclosure Figure 1 and Figure 6A Flowchart of method 700A of at least one of memory devices 100 and 600 shown in FIG. Figure 7A As illustratively shown in FIG. 7 , method 700A includes operations SA71 - SA73 .

[0189] During operation SA71, the bit line is charged to a read voltage level VREAD1. For example, Figure 1 The bit line BL1 or Figure 6A The conductive structure MBL1 shown in FIG. 1 is charged to a read voltage level VREAD1 .

[0190] During operation SA72 , bit lines are coupled to memory devices. For example, bit line BL1 is coupled to memory device ME11 via switch T11 . For another example, memory device ME61 is coupled to conductive structure MBL1 via transistors corresponding to source / drain structures SD61 , SD62 and gate structure GWL1 .

[0191] During operation SA73, the voltage level of the bit line is adjusted from read voltage level VREAD1 based on the data bits stored in the memory elements. For example, when each of the data bits stored in the memory elements ME10-ME13 has a logic value of 0, the voltage level of bit line BL1 is adjusted from read voltage level VREAD1 to voltage level VREAD0. When each of the data bits stored in the memory elements ME10-ME13 has a logic value of 1, the voltage level of bit line BL1 is maintained at read voltage level VREAD1.

[0192] Figure 7B For operations according to some embodiments of the present disclosure Figure 1 and Figure 6A Flowchart of method 700B of at least one of memory devices 100 and 600 shown in FIG. Figure 7B As illustratively shown in FIG. 7 , method 700B includes operations SB71 - SB74 .

[0193] During operation SB71, the memory component stores data bits. For example, Figure 1 The memory unit shown in ME11 or Figure 6A The memory element ME61 shown in FIG stores data bits.

[0194] During operation SB72, the bit line is charged to a read voltage level VREAD1. Figure 2 During the period P22 shown in Figure 1 The bit line BL1 or Figure 6A The conductive structure MBL1 shown in FIG. 1 is charged to a read voltage level VREAD1 .

[0195] During operation SB73, switches coupled between memory elements and bit lines are turned on. For example, during period P23, switch T11 coupled between memory element ME11 and bit line BL1 is turned on. For another example, during period P23, transistors corresponding to source / drain structures SD61 and SD62 and gate structure GWL1 are turned on, where the transistors are coupled to memory element ME61 and conductive structure MBL1.

[0196] During operation SB74 , after the switch is turned on, the converter senses the bit line. For example, after the switch T11 is turned on, the converter ADC1 senses the bit line BL1 .

[0197] Figure 8 For designing and manufacturing according to some embodiments of the present disclosure Figure 1 and Figure 6A 600 . As described herein, system 800 generates or places one or more integrated circuit (IC) layout designs. In some embodiments, as described herein, system 800 manufactures one or more semiconductor devices based on the one or more IC layout designs. System 800 includes a hardware processor 802 and a non-transitory computer-readable storage medium 804, which is encoded with (e.g., stores) computer program code 806, such as an executable instruction set. Computer-readable storage medium 804 is configured to interface with a manufacturing machine for producing semiconductor devices. Processor 802 is electrically coupled to computer-readable storage medium 804 via bus 808. Processor 802 is also electrically coupled to I / O interface 810 via bus 808. Network interface 812 is also electrically connected to processor 802 via bus 808. The network interface 812 is connected to a network 814, enabling the processor 802 and the computer-readable storage medium 804 to connect to external components via the network 814. The processor 802 is configured to execute computer program code 806 encoded in the computer-readable storage medium 804 to enable the system 800 to design and manufacture at least one of the memory devices 100 and 600.

[0198] In some embodiments, the processor 802 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0199] In some embodiments, computer-readable storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, computer-readable storage medium 804 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In some embodiments using optical disks, computer-readable storage medium 804 includes compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disk (DVD).

[0200] In some embodiments, storage medium 804 also stores information required to design and manufacture at least one of memory devices 100 and 600, such as layout design 816, user interface 818, manufacturing unit 820, and / or executable instruction sets for performing operations for designing and manufacturing at least one of memory devices 100 and 600.

[0201] In some embodiments, storage medium 804 stores instructions (e.g., computer program code 806) for interfacing with a manufacturing machine. The instructions (e.g., computer program code 806) enable processor 802 to generate manufacturing instructions readable by the manufacturing machine to efficiently implement the design and manufacture of at least one of memory devices 100 and 600 during the manufacturing process.

[0202] System 800 includes an I / O interface 810. I / O interface 810 is coupled to external circuitry. In some embodiments, I / O interface 810 includes a keyboard, keypad, mouse, trackball, trackpad, and / or cursor arrow keys for transmitting information and commands to processor 802.

[0203] System 800 also includes a network interface 812 coupled to processor 802. Network interface 812 allows system 800 to communicate with a network 814, to which one or more other computer systems are connected. Network interface 812 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA, or a wired network interface such as ETHERNET, USB, or IEEE-13154. In some embodiments, the design and manufacture of at least one of memory devices 100 and 600 are implemented in two or more systems 800, and information such as layout design, user interface, and manufacturing units is exchanged between the different systems 800 via network 814.

[0204] System 800 is configured to receive information related to a layout design via I / O interface 810 or network interface 812. This information is transmitted to processor 802 via bus 808 to determine a layout design for producing an IC. The layout design is then stored in computer-readable medium 804 as layout design 816. System 800 is configured to receive information related to a user interface via I / O interface 810 or network interface 812. This information is stored in computer-readable medium 804 as user interface 818. System 800 is configured to receive information related to a manufacturing unit via I / O interface 810 or network interface 812. This information is stored in computer-readable medium 804 as manufacturing unit 820. In some embodiments, manufacturing unit 820 includes manufacturing information used by system 800.

[0205] In some embodiments, the design and manufacture of at least one of the memory devices 100 and 600 is implemented as a standalone software application for execution by a processor. In some embodiments, the design and manufacture of at least one of the memory devices 100 and 600 is implemented as a software application that is part of an additional software application. In some embodiments, the design and manufacture of at least one of the memory devices 100 and 600 is implemented as a plug-in to a software application. In some embodiments, the design and manufacture of at least one of the memory devices 100 and 600 is implemented as a software application that is part of an EDA tool. In some embodiments, the design and manufacture of at least one of the memory devices 100 and 600 is implemented as a software application used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout design for an integrated circuit device. In some embodiments, the layout design is stored on a non-transitory computer readable medium. In some embodiments, the layout design is generated using, for example, or other suitable layout generation tools. In some embodiments, the layout design is generated based on a netlist created based on a schematic design. In some embodiments, the design and fabrication of at least one of memory devices 100 and 600 is performed by a fabrication device to fabricate an integrated circuit using a mask set fabricated based on one or more layout designs generated by system 800. In some embodiments, system 800 includes a fabrication device (e.g., fabrication tool 822) to fabricate an integrated circuit using a mask set fabricated based on one or more layout designs of the present disclosure.

[0206] Figure 9 FIG. 9 is a block diagram of an integrated circuit (IC) / semiconductor device manufacturing system 900 and an associated IC manufacturing process according to some embodiments of the present disclosure.

[0207] exist Figure 9 In the present invention, IC manufacturing system 900 includes physical units such as design house 920, mask house 930, and IC manufacturer / fab ("wafer fab") 940. These physical units interact with each other during the design, development, and manufacturing cycles and / or services associated with manufacturing IC devices (semiconductor devices) 960. IC devices 960 include at least one of memory devices 100 and 600. The physical units in system 900 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the internet. The communication network includes wired and / or wireless communication channels. Each physical unit interacts with one or more of the other physical units and provides services to and / or receives services from one or more of the other physical units. In some embodiments, two or more of design house 920, mask house 930, and IC wafer fab 940 are owned by a single company. In some embodiments, two or more of the design fab 920 , the mask fab 930 , and the IC fab 940 are co-located in a common facility and use common resources.

[0208] The design house (or design team) 920 generates an IC design layout 922. The IC design layout 922 includes various geometric patterns designed for the IC device 960. The geometric patterns correspond to the patterns of metal, oxide, or semiconductor layers that make up the various components of the IC device 960 to be manufactured. The various layers are combined to form various IC features. For example, a portion of the IC design layout 922 includes various IC features, such as active regions, gate structures, source / drain structures, interconnect structures, and openings for bonding pads formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design house 920 implements an appropriate design program to generate the IC design layout 922. The design program includes one or more of a logical design, a physical design, or placement and routing. The IC design layout 922 is presented in one or more data files containing information about the geometric patterns. For example, the IC design layout 922 can be described using the GDSII file format or the DFII file format.

[0209] The mask factory 930 includes mask data preparation 932 and mask manufacturing 934. The mask factory 930 uses the IC design layout 922 to manufacture one or more masks for manufacturing various layers of the IC device 960 according to the IC design layout 922. The mask factory 930 performs mask data preparation 932, wherein the IC design layout 922 is translated into a representative data file (RDF). The mask data preparation 932 provides the RDF to the mask manufacturing 934. The mask manufacturing 934 includes a mask writer. The mask writer converts the RDF into an image on a substrate (such as a mask (reduction mask) or a semiconductor wafer) or a metal layer, which is formed and then selectively etched to form a redistribution layer in the back-end process of the wafer fab. The design layout is manipulated by the mask data preparation 932 to conform to the specific characteristics of the mask writer and / or the requirements of the IC wafer fab 940. In Figure 9 , mask data preparation 932 and mask manufacturing 934 are depicted as separate components. In some embodiments, mask data preparation 932 and mask manufacturing 934 may be collectively referred to as mask data preparation.

[0210] In some embodiments, mask data preparation 932 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, and the like. OPC adjusts IC design layout 922. In some embodiments, mask data preparation 932 includes other resolution enhancement techniques (RET), such as off-axis illumination, secondary resolution assist features, phase shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0211] In some embodiments, mask data preparation 932 includes a mask rule checker (MRC) that checks the IC design layout, which has undergone processing in the OPC, using a mask creation rule set containing certain geometric and / or connectivity constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, among other things. In some embodiments, the MRC modifies the IC design layout to compensate for the constraints during mask creation 934, which can undo some of the modifications made by the OPC to satisfy the mask creation rules.

[0212] In some embodiments, mask data preparation 932 includes lithography process checking (LPC), which simulates the process implemented by IC fab 940 to manufacture IC device 960. LPC simulates this process based on IC design layout 922 to produce a simulated manufactured device, such as IC device 960. Processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof. In some embodiments, after LPC creates the simulated manufactured device, if the simulated device is not close enough in shape to meet design rules, OPC and / or MRC may be repeated to further refine IC design layout 922.

[0213] It should be understood that the above description of mask data preparation 932 has been simplified for clarity. In some embodiments, mask data preparation 932 includes additional features, such as logic operations (LOPs), to modify the IC design layout according to manufacturing rules. In addition, the processes applied to IC design layout 922 during mask data preparation 932 can be performed in a variety of different orders.

[0214] After mask data preparation 932 and during mask fabrication 934, a mask or a set of masks is fabricated based on the modified IC design layout. In some embodiments, an electron beam (e-beam) or a combination of electron beams is used to form a pattern on a mask (a photomask or a reticle) based on the modified IC design layout. The mask can be formed using various techniques. In some embodiments, the mask is formed using a binary technique. In some embodiments, the mask pattern includes opaque and transparent regions. Radiation (such as an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) overlying the wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, the binary mask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the mask. In another example, the mask is formed using a phase shift technique. In a phase shift mask (PSM), the various features in the pattern formed on the mask have appropriate phase differences to enhance resolution and imaging quality. In various embodiments, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask produced by mask manufacturing 934 is used in various processes. For example, the mask is used in an ion implantation process to form various doped regions in a semiconductor wafer, in an etching process to form various etched regions in a semiconductor wafer, and / or in other suitable processes.

[0215] IC fab 940 is an IC manufacturing entity that includes one or more fabrication facilities for manufacturing a variety of different IC products. In some embodiments, IC fab 940 is a semiconductor foundry. For example, a first fabrication facility may be provided for front-end fabrication of a plurality of IC products (e.g., source / drain structures, gate structures), a second fabrication facility may provide mid-end fabrication of interconnects for IC products (e.g., MD, VD, VG), a third fabrication facility may provide back-end fabrication of interconnects and packaging for IC products (e.g., M0 rails, M1 rails, BM0 rails, BM1 rails), and a fourth fabrication facility may provide other services for the foundry entity.

[0216] IC fab 940 uses the mask (or masks) manufactured by mask fab 930 to manufacture IC device 960. Thus, IC fab 940 at least indirectly uses IC design layout 922 to manufacture IC device 960. In some embodiments, semiconductor wafers are manufactured by IC fab 940 using the mask (or masks) to form IC device 960. Semiconductor wafer 942 includes a silicon substrate or other suitable substrate having material layers formed thereon. The semiconductor wafer further includes one or more of various doped regions, dielectric features, multiple levels of interconnects, and the like (formed in subsequent manufacturing steps).

[0217] One aspect of this disclosure discloses a method for operating a memory device, comprising the steps of: charging a bit line to a read voltage level; coupling the bit line to a memory component; and adjusting the voltage level of the bit line from the read voltage level based on a data bit stored in the memory component. The read voltage level is less than a coercive voltage level of the memory component.

[0218] In some embodiments of the operating method of this aspect, the polarization of the memory device is approximately equal to zero when the voltage difference between the two terminals of the memory device is approximately equal to the coercive voltage level.

[0219] In some embodiments of the operating method of this aspect, the operating method further comprises the following steps: sensing the bit line by a converter; and determining a read voltage level according to a sensing resolution of the converter.

[0220] In some embodiments of the operating method of this aspect, when the converter has a first sensing resolution, the read voltage level has a first value, and when the converter has a second sensing resolution higher than the first sensing resolution, the read voltage level has a second value lower than the first value.

[0221] In some embodiments of the operating method of this aspect, the operating method further includes the following steps: calculating a signal difference based on a first polarization difference and a second polarization difference of the memory component; and determining a read voltage level based on the signal difference. The first polarization difference and the second polarization difference correspond to a first logic value and a second logic value, respectively. The first logic value and the second logic value are different from each other.

[0222] In some embodiments of the operating method of this state, the first polarization difference is the difference between the first polarization and the second polarization, the second polarization difference is the difference between the third polarization and the fourth polarization, each of the first polarization and the third polarization corresponds to a zero voltage level, and each of the second polarization and the fourth polarization corresponds to a read voltage level.

[0223] In some embodiments of the operating method of this aspect, in response to the signal difference having a first difference value, the read voltage level has a first value, and in response to the signal difference having a second difference value greater than the first difference value, the read voltage level has a second value less than the first value.

[0224] In some embodiments of this aspect of the method of operation, the read voltage level decreases as the number of cells on the bit line increases.

[0225] In some embodiments of this aspect of the method of operation, the read voltage level is within a range of 0.3 times the coercive voltage level to 0.8 times the coercive voltage level.

[0226] Another aspect of this disclosure discloses a memory device. The memory device includes a first memory cell, a converter, and a first bit line. The first memory cell is configured to store data bits. The converter is configured to read the data bits. The first bit line is coupled between the first memory cell and the converter. The first memory cell includes a first switch and a first memory component. During a read operation, the first bit line is charged to a read voltage level. The read voltage level is less than a coercive voltage level of the first memory component.

[0227] In some embodiments of the memory device according to this further aspect, when a voltage difference between two terminals of the first memory component is approximately equal to a coercive voltage level, a polarization of the first memory component is approximately equal to zero.

[0228] In some embodiments of this other aspect of the memory device, the memory device further includes a second memory cell and a plate line. The second memory cell is coupled to the first bit line and includes a second switch and a second memory component. The plate line is coupled to each of the first memory component and the second memory component and is maintained at a ground voltage level during a read operation.

[0229] In some embodiments of this other aspect of the memory device, the memory device further includes a first word line and a second word line. The first word line is coupled to a control terminal of the first switch. The second word line is coupled to a control terminal of the second switch. The first word line is located between each of the first word line and the second word line and the plate line.

[0230] In some embodiments of the memory device of this other aspect, the memory device further includes a third memory cell and a second bit line. The third memory cell is coupled to the plate line and the first word line. The second bit line is coupled to the third memory cell and has a read voltage level during a read operation.

[0231] In some embodiments of the memory device according to another aspect, the read voltage level decreases as the sensing resolution of the converter increases.

[0232] In some embodiments of the memory device of this other aspect, the read voltage level is within a range from 0.3 times the coercive voltage level to 0.8 times the coercive voltage level.

[0233] Another aspect of the present disclosure discloses a method for operating a memory device, comprising the steps of: storing a data bit in a memory component; charging a bit line to a read voltage level; closing a switch coupled between the memory component and the bit line; and sensing the bit line using a converter after the switch is closed. The read voltage level is less than a voltage level at which the polarization of the memory component is approximately zero when the voltage difference between two terminals of the memory component is approximately equal to the voltage level.

[0234] In some embodiments of the operating method of the further aspect, the operating method further comprises the step of: reducing the read voltage level when the sensing resolution of the converter increases.

[0235] In some embodiments of this further aspect of the operating method, the operating method further includes the steps of: calculating a signal difference of the memory component based on the first polarization, the second polarization, the third polarization, and the fourth polarization; and decreasing a read voltage level when the signal difference increases. Each of the first polarization and the second polarization corresponds to a first logic value. Each of the third polarization and the fourth polarization corresponds to a second logic value different from the first logic value. Each of the first polarization and the fourth polarization corresponds to a voltage difference as a zero voltage level. Each of the first polarization and the fourth polarization corresponds to a voltage difference as a read voltage level.

[0236] In some embodiments of the operating method of this further aspect, the signal difference varies according to at least one of a thickness of a memory structure in the memory component, a composition of the memory structure, and a plurality of interfaces of the memory component.

[0237] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use this disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for operating a memory device, characterized in that: The following steps are involved: charging a bit line to a read voltage level; coupling the bit line to a memory component; as well as adjusting a voltage level of the bit line starting from the read voltage level according to a data bit stored in the memory component, The read voltage level is lower than a coercive voltage level of the memory component.

2. The operating method according to claim 1, wherein: Further comprising the following steps: sensing the bit line via a transducer; and The read voltage level is determined according to a sensing resolution of the converter.

3. The operating method according to claim 2, wherein: When the converter has a first sensing resolution, the read voltage level has a first value, and When the converter has a second sensing resolution higher than the first sensing resolution, the read voltage level has a second value lower than the first value.

4. The operating method according to claim 1, wherein: Further comprising the following steps: Calculating a signal difference according to a first polarization difference and a second polarization difference of the memory component; and The read voltage level is determined according to the signal difference. The first polarization difference and the second polarization difference correspond to a first logic value and a second logic value, respectively, and The first logic value and the second logic value are different from each other.

5. The operating method according to claim 4, characterized in that: in The first polarization difference is a difference between a first polarization and a second polarization, The second polarization difference is a difference between a third polarization and a fourth polarization, Each of the first polarization and the third polarization corresponds to a zero voltage level, and Each of the second polarization and the fourth polarization corresponds to the read voltage level.

6. The operating method according to claim 5, characterized in that: in In response to the signal difference having a first difference value, the read voltage level has a first value, and In response to the signal difference having a second difference value greater than the first difference value, the read voltage level has a second value less than the first value.

7. A memory device, characterized in that: Include: a first memory unit for storing a data bit; a converter for reading the data bits; and A first bit line is coupled between the first memory unit and the converter, The first memory unit includes a first switch and a first memory component. During a read operation, the first bit line is charged to a read voltage level, and The read voltage level is lower than a coercive voltage level of the first memory component.

8. The memory device according to claim 7, wherein: When a voltage difference between two terminals of the first memory component is equal to the coercive voltage level, a polarization of the first memory component is equal to zero.

9. The memory device according to claim 8, wherein: Further including: a second memory cell coupled to the first bit line and comprising a second switch and a second memory component; and A plate line is coupled to each of the first memory component and the second memory component and is maintained at a ground voltage level during the read operation.

10. A method for operating a memory device, characterized in that: The following steps are involved: storing a data bit via a memory component; charging a bit line to a read voltage level; turning on a switch coupled between the memory device and the bit line; and After the switch is turned on, the bit line is sensed by a converter. wherein the read voltage level is less than a voltage level, and When a voltage difference between the two terminals of the memory component is equal to the voltage level, a polarization of the memory component is equal to zero.

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