Increasing throughput to write memory

Abstract

A method for performing a write operation on a memory, the method comprising: starting a write operation for writing n words in the same row, including loading a first word of the n words during a first clock cycle, where n is an integer greater than 1; loading one or more additional words in the n words, wherein the one or more additional words are loaded during the corresponding one or more additional clock cycles; triggering the n words to be stored in the memory; and during a final clock cycle, turning off the write operation for the writing of the n words, thereby writing the n words in n + 1 clock cycles consisting of the first clock cycle, the corresponding one or more additional clock cycles, and the final clock cycle. The write circuit performing the above operations may also perform a write operation on a single word in two clock cycles.

Description

Background Art

[0001] Random Access Memory (RAM) is a type of volatile memory that is typically used as the main memory for a processing unit and stores programs and data used by the processing unit during program execution. Static Random Access Memory (SRAM) is a type of memory commonly used for cache memory. SRAM is typically configured as an array or matrix of individually addressable memory cells. Read and write operations are performed on data units called words. In other words, a word refers to the data unit used by a specific processor design or instruction set.

[0002] In general, word lines are used to select a row for reading or writing, and bit lines transfer data to / from a column. For a read operation in an SRAM, the address of the storage location of the word is transferred to the address lines, a precharge circuit is used to bring the bit lines to VDD, the word lines are driven high (the precharge circuit is turned off), the cell storing data at the storage location pulls down a bit line, and the sense circuits on the periphery of the array are activated to capture the value on the bit lines. For a write operation in an SRAM, the address of the desired word is transferred to a specific address on the word line and column, the data bits to be stored in the memory are transferred to the bit lines driven by the column driver circuit, and the write control is activated to drive the word line high (while the column driver remains on) and drive the data into the cell being written.

[0003] The speed of a processing unit is determined by the number of computations the processor can perform per clock cycle. However, one limiting factor in processing unit performance is the speed at which data stored in memory can be read and written. Changing rows and columns, changing between commands, and other operations all result in higher latencies. Identifying mechanisms that reduce the number of clock cycles required to deliver data (to memory as writes and to the processing unit as reads) remains important for performance. Summary of the Invention

[0004] Circuits and techniques are described for increasing the throughput of writes to memory. Increased throughput refers to the ability to write, read, or access multiple bit cells of a memory in fewer clock cycles than if the multiple bit cells were written, read, or accessed individually. A "burst mode" is provided in which more than one word is written or read across multiple columns on a given word line, resulting in increased throughput. As described in detail herein, for burst mode write operations, once multiple words are loaded, the word lines are turned on, and the bit lines are precharged, multiple words are written simultaneously to a row of memory, thereby reducing the number of clock cycles required to write the multiple words to the memory.

[0005] A method for performing a write operation on a memory, the method comprising: starting a write operation for writing n words in the same row, including loading a first word of the n words during a first clock cycle, where n is an integer greater than 1; loading one or more additional words of the n words, each of the one or more additional words being loaded during a corresponding one or more additional clock cycles; triggering the n words to be stored in the memory; and during a final clock cycle, disabling the write operation for the n words, thereby writing the n words in n+1 clock cycles consisting of the first clock cycle, the corresponding one or more additional clock cycles, and the final clock cycle. The write circuit performing the above operation can also perform a write operation on a single word, wherein the single word is loaded and triggered to be stored in the memory during the first clock cycle, and the write operation is disabled during a second clock cycle, which is the final clock cycle.

[0006] A memory circuit may include a word line driver for a memory, the word line driver coupled to receive an address and select a corresponding word line for the memory; a write circuit; and a control circuit for operating the word line driver and the write circuit, wherein the control circuit instructs the write circuit to: start a write operation for writing n words in the same row, including loading a first word of the n words during a first clock cycle, where n is an integer greater than 1; loading one or more additional words of the n words, the one or more additional words each being loaded during a corresponding one or more additional clock cycles; triggering the n words to be stored in the memory; and during a final clock cycle, closing the write operation for the writing of the n words, thereby writing the n words in n+1 clock cycles consisting of the first clock cycle, the corresponding one or more additional clock cycles, and the final clock cycle.

[0007] This summary is provided to introduce a series of concepts in a simplified form, which will be further described in the detailed description below. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A A schematic diagram of a memory circuit is shown.

[0009] Figure 1B A schematic diagram of a memory circuit for performing a write operation is shown.

[0010] Figure 2 A method of performing a write operation on a memory for n words in a row is illustrated.

[0011] Figure 3A and Figure 3B An example write circuit and corresponding timing diagram supporting n=2 are illustrated.

[0012] Figure 4A and Figure 4B An example write circuit and corresponding timing diagram supporting n=3 are illustrated. DETAILED DESCRIPTION

[0013] Circuits and techniques for increasing the throughput of writes to memory are described. Increased throughput refers to the ability to write, read, and access multiple bit cells of a memory in fewer clock cycles than if the cells were written, read, or accessed individually. A "burst mode" is provided in which more than one word is written or read across multiple columns on a given word line, resulting in increased throughput.

[0014] As described in detail herein, for burst mode write operations that write more than one word in a manner that increases throughput, once the multiple words are loaded, the word lines are turned on, and the bit lines are precharged, the multiple words are written simultaneously to a row of memory, thereby reducing the number of clock cycles in which the multiple words are written to the memory.

[0015] Typically, when a sequence of words is written to a row of memory, two clock cycles are used to write each word. In the first clock cycle, the words are queued / loaded for writing, and in the second clock cycle, the words are written. In some cases, a precharge operation of the bit line is performed during the first clock cycle. In some cases, a precharge operation of the bit line is performed at the end of the write operation to write the next word. By the described technology, not only can the clock cycle be removed from the subsequent writes in the row, but also the word line (or precharge bit line) between the words does not need to be turned off and on. In other words, the word line is turned on once. Then, in each subsequent clock cycle, the data is loaded for writing (for example, the write queue is captured one by one), and in the final clock cycle, all the data is written at once. In addition, for the write sequence, the bit line can be precharged once.

[0016] Advantageously, significant power savings can be achieved by not precharging the bit line for each write and not turning the word line off and then back on for each write. Thus, when back-to-back writes occur within the same word line, it is possible to write two (or more) words without making two (or more) separate accesses. This reduces power by 50% to 75% because precharging between accesses is not necessary.

[0017] Figure 1A shows a schematic diagram of a memory circuit; and Figure 1B A schematic diagram of a memory circuit for performing a write operation is shown.

[0018] refer to Figure 1A , the memory circuit 100 includes a word line (WL) driver 110 and an input / output circuit 120 for a memory array 130. The WL driver 110 and the input / output circuit 120 operate under the control of a control circuit 140. In some implementations, the memory circuit 100 is a cache circuit.

[0019] Memory 130 is constructed as an array having rows accessed by word lines and columns accessed by bit lines. In some implementations, memory 130 is a static random access memory (SRAM). For example, the structure of each bit cell of the memory can be a 1:1:1 bit cell, a 1:1:2 bit cell, or a 1:2:2 bit cell. The bit cell can be implemented in a FinFET process, a planar process, a nanosheet process, an FDSOI process, or other suitable technology. A bit cell refers to a storage element that stores a single bit of information.

[0020] The control circuit 140 can receive a chip enable signal, a clock signal, a burst enable signal, and an address enable signal, and generate outputs to control the WL driver 110 and the I / O circuit 120. The chip enable signal indicates whether the memory is to be accessed. The clock signal indicates the start of a memory operation and provides an operating frequency for the circuit. The burst enable signal indicates whether the operation being performed at the memory is in burst mode. The address enable signal supports out-of-order bit cell access. Out-of-order bit cell access refers to the ability to write or read (or otherwise access) a bit cell on a non-contiguous basis. That is, multiple words can be read or written to non-contiguous bit cells of a row by using an address enable signal that indicates which bit lines will be accessed during burst mode.

[0021] The WL driver 110 receives an address and turns on a word line indicated by the address in response to receiving a word line enable (WLEN) signal from the control circuit 140 .

[0022] The input / output circuit 120 may include a write circuit and a read circuit. Receive data (D) for a write operation and output data (Q) for a read operation. The input / output circuit 120 receives a sense amplifier enable (SAE) signal, a precharge (PCH) signal, and a write column select (YW) signal from the control circuit 140. In the case of the write circuit 125, the control circuit 140 provides the precharge (PCH) signal and the write column select (YW) signal, as shown in FIG. Figure 1B The memory circuit 100A is shown.

[0023] refer to Figure 1B, the memory circuit 100A includes a word line driver 110 for the memory 130, wherein the word line driver 110 is coupled to receive an address and select a corresponding word line for the memory 130; a write circuit 125; and a control circuit 140 for operating the word line driver 110 and the write circuit 125.

[0024] For a burst mode write operation, the control circuit 140 receives a chip enable signal, a clock signal, a burst enable signal, and an address enable signal, and uses the received signals to generate appropriate signals to output a word line enable (WLEN) signal to the word line driver 110, and a precharge (PCH) signal and an appropriate write column select (YW) signal to the write circuit 125. In some cases, the control circuit 140 performs operations related to Figure 2 Method 200 is described.

[0025] In various implementations, the memory circuits 100, 100A can also be configured to perform a normal write operation. For example, in response to receiving a signal indicating a normal write (e.g., when the burst enable signal does not indicate a burst mode), a write operation can be performed to write a word to the memory, wherein any word written in response to the signal indicating a normal write is written within two clock cycles.

[0026] Figure 2 This section describes a method for writing n words in a row to a memory. Figure 2 , the method 200 includes starting (210) a write operation for writing n words in the same row, including loading a first word of the n words during a first clock cycle, where n is an integer greater than 1; loading (220) one or more additional words of the n words, the one or more additional words each being loaded during a corresponding one or more additional clock cycles; triggering (230) the n words to be stored in the memory; and during a final clock cycle, closing (240) the write operation for writing the n words, thereby writing the n words in n+1 clock cycles consisting of the first clock cycle, the corresponding one or more additional clock cycles, and the final clock cycle.

[0027] Starting (210) a write operation for writing n words in the same row may include precharging the bit lines of the memory and turning on the word lines. In some cases, in response to receiving a signal indicating a burst write, e.g., when a burst is written by Figure 1B When the burst enable signal received by the control circuit 140 indicates that the operation is a burst operation, execution starts (210) a write operation for writing n words in the same row. During the first clock cycle, the write circuit (e.g., Figure 1B The data input of the write circuit 125) is used to perform the loading of the first word of n words.

[0028] This can be done by writing circuits (e.g. Figure 1B The data input of the write circuit 125 of the embodiment of the present invention is used to perform the loading (220) of one or more additional words of the n words, the one or more additional words each being loaded during a corresponding one or more additional clock cycles.

[0029] Triggering (230) n words to be stored in the memory includes various signals associated with triggering n words to be stored in the memory. For example, the various signals may include applying a column select signal and any write driver enable signals (including for boost / write assist circuits when used to control the level of internal voltages). The column select signal may be applied to the column select circuit to select the column to be written. Non-limiting example configurations of the column select circuit include a 4:1 multiplexer (MUX), an 8:1 MUX, a 3:1 MUX, and a 2:1 MUX. As described herein, by, for example, including for example Figure 3A and Figure 4A The additional write drivers for the set of bit lines and the corresponding additional column select circuits shown can store all words simultaneously. With this configuration, n words can be triggered to be stored in the memory during the last clock cycle of the corresponding one or more additional clock cycles, so that n words are stored concurrently during the final clock cycle, such as Figure 3B and Figure 4B It should be noted that the circuitry described for a group of bit cells / a group of bit lines / a group of columns may represent a single fragment of a word (ie, one bit deep).

[0030] Closing (240) the write operation for writing of the n words may include turning off the word lines and signals associated with triggering the n words to be stored in the memory.

[0031] Figure 3A and Figure 3B An example write circuit and corresponding timing diagram supporting n=2 are shown. Figure 3A, a double-word (n=2) configuration 300 of the write circuit 125 can include a first write driver 302 for a group of bit lines and a second write driver 304 for the group of bit lines. The first write driver 302 and the second write driver 304 can each selectively couple to all bit lines of the group of bit lines or a subset of the bit lines of the group of bit lines (including overlapping subsets). The first write driver 302 and the second write driver 304 both receive their inputs through a data input (DIN) 306 of the group of bit lines. In the illustrated scenario, the double-word configuration 300 involves selecting two bit cells from four bit cells 310 in the same row, which are accessible by the group of bit lines coupled to the first write driver 302 and the second write driver 304. To select between the bit cells, a column select circuit is included for each write driver. Depending on the specific implementation, the column select circuit can select between one, two, three, or more bit lines in the group of bit lines.

[0032] like Figure 3A As shown, the write circuitry may include a first column select circuit 322 for selecting a specific bit line of the group of bit lines for the first write driver 302 and a second column select circuit 324 for selecting a corresponding specific bit line of the group of bit lines for the second write driver 304, such that a first word is written to a bit cell (e.g., bit cell 311) coupled to the specific bit line, while a second word is written to another bit cell (e.g., bit cell 312) coupled to the corresponding specific bit line. The specific bit line selected by the first column select circuit 322 is a bit line pair (i.e., a bit line and a bit line bar) selected for the first write driver 302. The corresponding specific bit line selected by the second column select circuit 324 is a bit line pair selected for / corresponds to the second write driver 304. The column select circuits (e.g., first column select circuit 322, second column select circuit 324) may be implemented as a multiplexer (MUX). In some cases, the column select circuits are implemented using transmission gates.

[0033] refer to Figure 3B , for burst write operations, when such as Figure 1AWhen the control circuit 140 of the control circuit receives a chip enable (CEN) signal indicating the start of a write operation for writing two words in the same row, the first word (Din1) is loaded in the first clock cycle. Then, the second word (Din2) is loaded during the second clock cycle, and the two words (Din1, Din2) are triggered to be stored in the memory, so that the two words are written concurrently at the end of the third clock cycle. It can be seen that the write operation of the two words is performed in three clock cycles, so that the first word (Din1) of the two words is loaded during the first clock cycle, the second word (Din2) of the two words is loaded during the second clock cycle, and the write operation is turned off during the third clock cycle, during which the two words (Din1, Din2) are stored in the memory.

[0034] Figure 4A and Figure 4B An example write circuit and corresponding timing diagram supporting n=3 are shown. Figure 4A , a three-word (n=3) configuration 400 for the write circuit 125 can include a first write driver 402 for a group of bit lines, a second write driver 404 for the group of bit lines, and a third write driver 406 for the group of bit lines. The first write driver 402, the second write driver 404, and the third write driver 406 can each selectively couple to all bit lines of the group of bit lines or a subset of the bit lines of the group of bit lines (including overlapping subsets). The first write driver 402, the second write driver 404, and the third write driver 406 each receive their inputs through a data input (DIN) 408 for the group of bit lines. In the illustrated scenario, the three-word configuration 400 involves selecting three bit cells from four bit cells 410 in the same row, which are accessible by the group of bit lines coupled to the first write driver 402, the second write driver 404, and the third write driver 406. To select between the bit cells, column select circuitry is included for each write driver. Depending on the specific implementation, the column select circuitry may select between one, two, three, or more bit lines in the set of bit lines.

[0035] like Figure 4AAs shown, the write circuitry may include a first column select circuit 422 for selecting a specific bit line of the group of bit lines for the first write driver 402, a second column select circuit 424 for selecting a specific bit line of the pair of bit lines of the group for the second write driver 404, and a third column select circuit 426 for selecting a corresponding specific bit line of the group of bit lines for the third write driver 406, so that a first word is written to a bit cell (e.g., bit cell 411) coupled to the specific bit line, a second word is written to another bit cell (e.g., bit cell 412) coupled to the corresponding specific bit line, and a third word is written to yet another bit cell (e.g., bit cell 413) coupled to the corresponding specific bit line. The specific bit line selected by the first column select circuit 422 is the bit line pair (i.e., bit line and bit line bar) selected for the first write driver 402. The corresponding specific bit lines of the second write driver 404 and the third write driver 406 selected by the second column select circuit 424 and the third column select circuit 426 are for / correspond to the bit line pair selected by the second write driver 404 and the third write driver 406. The column selection circuits (eg, the first column selection circuit 422 , the second column selection circuit 424 , and the third column selection circuit 426 ) may be implemented as MUXs. In some cases, the column selection circuits are implemented using transmission gates.

[0036] refer to Figure 4B , for burst write operations, when such as Figure 1A When the control circuit 140 of the control circuit receives a chip enable (CEN) signal indicating the start of a write operation for writing three words in the same row, the first word (Din1) is loaded during the first clock cycle, the second word (Din2) is loaded during the second clock cycle, and the third word (Din3) is loaded during the third clock cycle. Then, the three words (Din1, Din2, Din3) are triggered to be stored in the memory, so that all three words are written at the end of the fourth clock cycle (i.e., written to the memory concurrently). It can be seen that the write operation of the three words is performed in four clock cycles, so that the first word (Din1) of the three words is loaded during the first clock cycle, the second word (Din2) of the three words is loaded during the second clock cycle, the third word (Din3) of the three words is loaded during the third clock cycle, and the write operation ends during the fourth clock cycle, during which the three words (Din1, Din2, Din3) are stored in the memory.

[0037] Certain embodiments of the illustrated method and memory circuit include the following.

[0038] Item 1. A method for performing a write operation on a memory, the method comprising: starting a write operation for writing n words in the same row, including loading a first word of the n words during a first clock cycle, where n is an integer greater than 1; loading one or more additional words of the n words, each of the one or more additional words being loaded during a corresponding one or more additional clock cycles; triggering the n words to be stored in the memory; and during a final clock cycle, closing the write operation for the writing of the n words, thereby writing the n words in n+1 clock cycles consisting of the first clock cycle, the corresponding one or more additional clock cycles, and the final clock cycle.

[0039] Clause 2. The method of clause 1, wherein n=2, and the write operation of the two words is performed in three clock cycles, such that the first word of the two words is loaded during the first clock cycle, the second word of the two words is loaded during the second clock cycle, and the write operation is turned off during a third clock cycle, during which the two words are stored in the memory.

[0040] Clause 3. The method of clause 1 or 2, wherein the write circuitry of the memory comprises a first write driver for a set of bit lines and a second write driver for the set of bit lines.

[0041] Clause 4. The method of any preceding clause, wherein the write circuit further comprises a first column select circuit for selecting a particular bit line of the group of bit lines.

[0042] Clause 5. The method of any preceding clause, wherein the write circuit further comprises a second column select circuit for selecting a corresponding particular bit line of the group of bit lines.

[0043] Clause 6. The method of any preceding clause, wherein the n words are triggered to be concurrently stored in the memory during a last clock cycle of the corresponding one or more additional clock cycles such that the n words are stored during the final clock cycle.

[0044] Item 7. A method according to any preceding item, wherein in response to receiving a signal indicating a burst write, the write operation for writing n words in the same row is started, the method further comprising: receiving a signal indicating a regular write; and in response to receiving the signal indicating the regular write, starting a write operation for writing one word to the memory, whereby any word written in response to the signal indicating the regular write is written within two clock cycles.

[0045] Clause 8. A method according to any preceding clause, wherein starting the write operation for writing the n words in the same row further comprises precharging the bit lines of the memory and turning on the word lines; and wherein closing the write operation for writing the n words comprises turning off the word lines and the signal associated with triggering the n words to be stored in the memory.

[0046] Clause 9. The method of any preceding clause, wherein the memory is static random access memory (SRAM).

[0047] Item 10. A memory circuit, comprising: a word line driver for a memory, the word line driver coupled to receive an address and select a corresponding word line for the memory; a write circuit; and a control circuit for operating the word line driver and the write circuit, wherein the control circuit instructs the write circuit to: start a write operation for writing n words in the same row, including loading a first word of the n words during a first clock cycle, where n is an integer greater than 1; loading one or more additional words of the n words, each of the one or more additional words being loaded during a corresponding one or more additional clock cycles; triggering the n words to be stored in the memory; and during a final clock cycle, turning off the write operation for the writing of the n words, thereby writing the n words in n+1 clock cycles consisting of the first clock cycle, the corresponding one or more additional clock cycles, and the final clock cycle.

[0048] Item 11. The memory circuit of Item 10, wherein n=2, and the write operation of the two words is performed in three cycles such that the first of the two words is loaded during the first clock cycle, the second of the two words is loaded during the second clock cycle, and the write operation is turned off during a third clock cycle, during which the two words are stored in the memory.

[0049] Clause 12. The memory circuit of Clause 10 or 11, wherein the write circuit comprises a first write driver for a set of bit lines and a second write driver for the set of bit lines.

[0050] Clause 13. The memory circuit of any preceding memory circuit clause, wherein the write circuit further comprises a first column select circuit for selecting a particular bit line of the set of bit lines.

[0051] Clause 14. A memory circuit according to any preceding memory circuit clause, wherein the write circuit further comprises a second column select circuit for selecting a corresponding specific bit line of the set of bit lines, wherein the first word is written to a bit cell coupled to the specific bit line and the additional words of the one or more additional words are written to another bit cell coupled to the corresponding specific bit line.

[0052] Clause 15. The memory circuit of any preceding memory circuit clause, wherein the first write driver and the second write driver further comprise a write assist circuit configured to control a level of an internal voltage.

[0053] Clause 16. A memory circuit as described in any preceding memory circuit clause, wherein the n words are triggered to be concurrently stored in the memory during a last clock cycle of the corresponding one or more additional clock cycles, such that the n words are stored during the final clock cycle.

[0054] Clause 17. A memory circuit according to any preceding memory circuit clause, wherein the control circuit is coupled to receive a chip enable signal, a clock signal, a burst mode enable signal, an address signal, and wherein the control circuit is coupled to output a precharge signal and a write column select signal to the write circuit.

[0055] Clause 18. The memory circuit of any preceding memory circuit clause, wherein the memory circuit is a cache circuit.

[0056] Clause 19. The memory circuit of any preceding memory circuit clause, wherein the memory is static random access memory (SRAM).

[0057] Item 20. A memory circuit according to any preceding memory circuit item, wherein the write operation of starting to write n words in the same row is performed in response to receiving a signal indicating a burst write, wherein the control circuit further instructs the write circuit to: receive a signal indicating a normal write; and in response to the signal indicating the normal write, start a write operation for writing one word to the memory, whereby any word written in response to the signal indicating the normal write is written within two clock cycles.

[0058] Although the subject matter has been described in language specific to structural features and / or acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as examples of implementing the claims, and those skilled in the art will recognize that other equivalent features and acts are intended to fall within the scope of the claims.

Claims

1. A method for performing a write operation on a memory, the method comprising: Starting a write operation for writing n words in the same row, including loading a first word of the n words during a first clock cycle, where n is an integer greater than 1; loading one or more additional words from the n words, the one or more additional words each being loaded during a corresponding one or more additional clock cycles; triggering the n words to be stored in the memory; as well as During a final clock cycle, the write operation for the writing of the n words is turned off, thereby writing the n words in n+1 clock cycles consisting of the first clock cycle, the corresponding one or more additional clock cycles, and the final clock cycle.

2. The method of claim 1 , wherein n=2, and the write operation of the two words is performed in three clock cycles, such that the first word of the two words is loaded during the first clock cycle, the second word of the two words is loaded during the second clock cycle, and the write operation is turned off during a third clock cycle, during which the two words are stored in the memory. 3 . The method of claim 1 , wherein a write circuit of the memory comprises a first write driver for a group of bit lines and a second write driver for the group of bit lines.

4. The method according to claim 3, wherein the writing circuit further comprises: A first column selection circuit is provided for selecting a specific bit line of the group of bit lines.

5. The method according to claim 4, wherein the writing circuit further comprises: A second column selection circuit is configured to select a corresponding specific bit line of the group of bit lines.

6. The method of claim 1 , wherein the n words are triggered to be concurrently stored in the memory during a last clock cycle of the corresponding one or more additional clock cycles such that the n words are stored during the final clock cycle.

7. The method according to claim 1 , wherein starting the write operation for writing n words in the same row is performed in response to receiving a signal indicating a burst write, the method further comprising: receiving a signal indicating a regular write; as well as In response to receiving the signal indicating the normal write, a write operation for writing one word to the memory is initiated, whereby any word written in response to the signal indicating the normal write is written within two clock cycles.

8. The method of claim 1 , wherein starting the write operation for writing n words in the same row further comprises precharging bit lines of the memory and turning on word lines; and wherein shutting down the write operation for the writing of the n words comprises turning off the word lines and a signal associated with triggering the n words to be stored in the memory.

9. The method of claim 1, wherein the memory is a static random access memory (SRAM).

10. A memory circuit, comprising: a word line driver for a memory, the word line driver coupled to receive an address and select a corresponding word line for the memory; Write circuit; and a control circuit configured to operate the word line driver and the write circuit, wherein the control circuit instructs the write circuit to: Starting a write operation for writing n words in the same row, including loading a first word of the n words during a first clock cycle, where n is an integer greater than 1; loading one or more additional words from the n words, the one or more additional words each being loaded during a corresponding one or more additional clock cycles; triggering the n words to be stored in the memory; as well as During a final clock cycle, the write operation for the writing of the n words is turned off, thereby writing the n words in n+1 clock cycles consisting of the first clock cycle, the corresponding one or more additional clock cycles, and the final clock cycle.

11. The memory circuit of claim 10 , wherein n=2, and the write operation of the two words is performed in three cycles, such that the first word of the two words is loaded during the first clock cycle, the second word of the two words is loaded during the second clock cycle, and the write operation is turned off during a third clock cycle, during which the two words are stored in the memory. 12 . The memory circuit of claim 10 , wherein the write circuit comprises a first write driver for a group of bit lines and a second write driver for the group of bit lines. 13 . The memory circuit of claim 12 , wherein the write circuit further comprises a first column selection circuit configured to select a specific bit line of the group of bit lines.

14. The memory circuit according to claim 13 , wherein the write circuit further comprises a second column selection circuit configured to select a corresponding specific bit line of the group of bit lines. The first word is written to a bit cell coupled to the specific bit line, and an additional word of the one or more additional words is written to another bit cell coupled to the corresponding specific bit line. 15 . The memory circuit according to claim 12 , wherein the first write driver and the second write driver further include a write assist circuit configured to control a level of an internal voltage.

16. The memory circuit of claim 10, wherein the n words are triggered to be concurrently stored in the memory during a last clock cycle of the corresponding one or more additional clock cycles such that the n words are stored during the final clock cycle.

17. The memory circuit of claim 10, wherein the control circuit is coupled to receive a chip enable signal, a clock signal, a burst mode enable signal, and an address signal, and wherein the control circuit is coupled to output a precharge signal and a write column select signal to the write circuit.

18. The memory circuit of claim 10, wherein the memory circuit is a cache circuit.

19. The memory circuit of claim 10, wherein the memory is a static random access memory (SRAM).

20. The memory circuit of claim 10 , wherein the write operation of starting the writing of n words in the same row is performed in response to receiving a signal indicating a burst write, wherein the control circuit further instructs the write circuit to: receiving a signal indicating a normal write; and In response to the signal indicating the normal write, a write operation for writing one word to the memory is started, whereby any word written in response to the signal indicating the normal write is written within two clock cycles.

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