Enhanced throughput read in static random access memory

Abstract

The invention relates to an improved throughput read in a static random access memory. A read circuitry for a memory includes a column readout multiplexer (MUX) coupled to a set of columns of the memory, where the column readout MUX receives a column selection signal from a control circuit to output a corresponding column output from the set of columns; and a single sense amplifier coupled to receive a corresponding column output of the column readout MUX.

Description

Background Art

[0001] Random access memory (RAM) is a type of volatile memory that is typically used as the main memory for a processing unit and stores programs and data used by the processing unit during program execution. Static random access memory (SRAM) is a type of memory commonly used for cache memory. SRAM is typically configured as an array or matrix of individually addressable memory cells. Read and write operations are performed on data units called words. In other words, a word refers to the data unit used by a specific processor design or instruction set.

[0002] Generally speaking, word lines are used to select rows for reading or writing, and bit lines carry data to or from columns. For a read operation in an SRAM, the address of the storage location of the word is transferred to the address lines, a precharge circuit is used to bring the bit lines to VDD, the word lines are driven high (the precharge circuit is turned off), the cell storing data at the storage location pulls down a bit line, and the sense circuits on the periphery of the array are activated to capture the value on the bit lines. For a write operation in an SRAM, the address of the desired word is transferred to a specific address on the word line and column, the data bits to be stored in the memory are transferred to the bit lines driven by the column driver circuit, and the write control is activated to drive the word line high (while the column driver remains on) and drive the data into the cell being written.

[0003] The speed of a processing unit is determined by the amount of computation the processor can perform per clock cycle. However, one limiting factor in the performance of a processing unit is the speed at which data stored in memory can be read and written. Changing rows and columns, changing between commands, and other operations can result in higher latencies. Identifying mechanisms that reduce the number of clock cycles required to deliver data (to memory as write operations and to the processing unit as read operations) remains important for performance. Summary of the Invention

[0004] Circuitry and techniques are described that support increased throughput for reading from a memory. Increased throughput refers to the ability to write, read, and access multiple bit cells of a memory in fewer clock cycles than if the multiple bit cells were written, read, or accessed individually. A "blast mode" is provided in which more than one word is written or read across multiple columns on a given word line, resulting in increased throughput. Advantageously, the described circuitry and techniques can provide an area- and leakage-efficient readout solution.

[0005] As described in detail herein, a method for a read operation including a burst read operation may include: initiating a read operation during a first clock cycle; operating a column read multiplexer (MUX) coupled to a group of columns of a memory by individually applying one of n column select signals to the column read multiplexer to connect n columns of the group of columns to a single sense amplifier, the single sense amplifier being coupled to the column read MUX in a corresponding clock cycle starting from a second clock cycle so that all n columns are read in (n+1) clock cycles, where n is an integer equal to or greater than 1; and capturing a corresponding column output of the column read MUX at the single sense amplifier in the corresponding clock cycle.

[0006] A read circuit system for a memory includes: a column read multiplexer (MUX) coupled to a group of columns of the memory, wherein the column read multiplexer receives a column select signal from a control circuit to output corresponding column outputs from the group of columns; and a single sense amplifier coupled to receive the corresponding column output of the column read multiplexer. The columns can be read discontinuously.

[0007] The memory circuitry including the above-mentioned read circuitry may further include a word line driver coupled to receive an address and select a corresponding word line for the memory; and a control circuit for operating the word line driver and the read circuitry.

[0008] This summary is provided to introduce a series of concepts in a simplified form, which will be further described in the detailed description below. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A A representation of memory circuitry is shown.

[0010] Figure 1B A representation of memory circuitry for performing a read operation is shown.

[0011] Figure 2A Existing readout circuitry that supports increased throughput reads is illustrated.

[0012] Figure 2B Readout circuitry that can support increased throughput reads is illustrated.

[0013] Figure 3 A method for performing a read operation from a memory is illustrated.

[0014] Figure 4An exemplary circuit for generating a control signal that can be used to pre-charge a sense amplifier for faster burst read performance is illustrated.

[0015] Figure 5 The voltage waveforms of various signals over time in a read operation are shown.

[0016] Figure 6A The operation of the control circuit for controlling the word line driver is shown.

[0017] Figure 6B A control circuit for generating a word line enable signal is shown.

[0018] Figure 7 A specific implementation of an exemplary control circuit for generating a word line enable signal is shown.

[0019] Figure 8 The waveforms of various signals at power-on and the results of combining the power-on protection circuit are shown. DETAILED DESCRIPTION

[0020] Circuitry and techniques are described that support increased throughput for reading from a memory. Increased throughput refers to the ability to write, read, and access multiple bit cells of a memory in fewer clock cycles than if the multiple bit cells were written, read, or accessed individually. A "blast mode" is provided in which more than one word is written or read across multiple columns on a given word line, resulting in increased throughput. Advantageously, the described circuitry and techniques can provide an area- and leakage-efficient readout solution.

[0021] Figure 1A shows a representation of memory circuitry; and Figure 1B A representation of memory circuitry for performing a read operation is shown.

[0022] refer to Figure 1A , memory circuitry 100 includes word line (WL) drivers 110 and input / output circuitry 120 for a memory array 130. WL drivers 110 and input / output circuitry 120 operate under the control of control circuitry 140. In some implementations, memory circuitry 100 is cache circuitry.

[0023] Memory 130 is constructed as an array having rows accessed by word lines and columns accessed by bit lines. In some implementations, memory 130 is a static random access memory (SRAM). For example, the structure of each bit cell of the memory can be a 1:1:1 bit cell, a 1:1:2 bit cell, or a 1:2:2 bit cell. The bit cell can be implemented in a FinFET process, a planar process, a nanosheet process, an FDSOI process, or other suitable technology. A bit cell refers to a memory element that stores a single bit of information.

[0024] Control circuitry 140 can receive a chip enable signal, a clock signal, a burst enable signal, and an address enable signal, and generate outputs to control WL driver 110 and I / O circuitry 120. The chip enable signal indicates whether the memory is to be accessed. The clock signal indicates the start of a memory operation and provides the operating frequency for the circuitry. The burst enable signal indicates whether the operation being performed at the memory is in burst mode. The address enable signal supports out-of-order bit cell access. Out-of-order bit cell access refers to the ability to write to or read (or otherwise access) bit cells on a discontinuous basis. That is, by using address enable signals that indicate which bit lines will be accessed during burst mode, multiple words can be read from or written to discontinuous bit cells in a row. The address enable signal can be implemented using separate address pins. In some cases, the address enable signal is a decoded burst address that indicates which of the columns will be accessed for the burst operation. In some cases, an encoded burst address can be used.

[0025] The WL driver 110 receives an address and turns on a word line indicated by the address in response to receiving a word line enable (WLEN) signal from the control circuit 140 .

[0026] Input / output circuitry 120 may include write circuitry and read circuitry. Receive data (D) for a write operation and output data (Q) for a read operation. Input / output circuitry 120 receives a sense amplifier enable (SAE) signal, a precharge (PCH) signal, and a read column select (YR) signal from control circuitry 140. In the case of read circuitry 125, control circuitry 140 provides the sense amplifier enable (SAE) signal, the precharge (PCH) signal, and the read column select (YR) signal, as Figure 1B As shown in the memory circuit system 100B shown in FIG.

[0027] refer to Figure 1B, the memory circuit system 100B includes: a word line driver 110, which is used for the memory 130, wherein the word line driver 110 is coupled to receive an address and select a corresponding word line for the memory 130; a read circuit system 126; and a control circuit 140, which is used to operate the word line driver 110 and the read circuit system 126.

[0028] For a burst mode read operation, the control circuit 140 receives a chip enable signal, a clock signal, a burst enable signal, and an address enable signal; and using the received signals, generates appropriate signals to output a word line enable (WLEN) signal to the word line driver 110, and a sense amplifier enable (SAE) signal, a precharge (PCH) signal, and an appropriate read column select (YR) signal to the read circuitry 126. The read column select (YR) signal is based on the address enable signal received by the control circuit 140 and can be used to generate local control signals for operating the read circuitry. In some cases, the control circuit 140 performs operations related to Figure 3 Method 300 is described.

[0029] As described above, for a read operation in a memory such as an SRAM, the address of the storage location of a word is transmitted to the address line, a precharge circuit is used to bring the bit line to VDD, the word line is driven high (the precharge circuit is turned off), the cell storing data at the storage location pulls down one bit line, and the sensing circuitry around the array is activated to capture the value on the bit line. In detail, a read cycle can be initiated by precharging the bit lines (e.g., the bit line for each bit cell and the bit line bar). When the word line is asserted, the cell's access transistor is enabled, which may cause one bit line voltage to drop slightly, resulting in a small voltage difference between the bit line and the bit line bar. The sense amplifier can sense which line has a higher voltage, thereby determining whether a 1 or a 0 is stored.

[0030] Figure 2A Existing readout circuitry that supports increased throughput reads is illustrated. Figure 2A Conventional readout circuitry 200 includes a first multiplexer (MUX) 210 for selecting a bitline pair from the set of bitlines. When a wordline (WL) is on, bitline differentials are formed on each column (e.g., column 1, column 2, column 3, column 4) by activating all paths in first MUX 210 using NYR0, NYR1, NYR2, and NYR3. When the SAE signal arrives, these differentials are immediately captured in the corresponding sense amplifiers 220A, 220B, 220C, and 220D. The captured data is then individually read out from the sense amplifiers 220A, 220B, 220C, and 220D in successive clock cycles using a second multiplexer (MUX) 230 at outputs controlled by the SEL0, SEL1, SEL2, and SEL3 signals.

[0031] Figure 2B The present invention illustrates a readout circuit system that can support improved throughput reading. Figure 2B , the readout circuitry 250 that provides an area and leakage efficient readout solution includes a column readout multiplexer (MUX) 260 coupled to a set of columns (eg, column 1, column 2, column 3, column 4) of the memory.

[0032] In operation, the word line (WL) is turned on and all columns begin to form bit line differentials. The column readout MUX 260 receives a column select signal (one of NYR0, NYR1, NYR2, NYR3) from the control circuit 270 (which can be a reference Figure 1A and Figure 1B 140 ), selecting the differential from each column to drive the input of a single sense amplifier 280 in a corresponding clock cycle; and a single sense amplifier 280 coupled to receive the corresponding column output of the column readout MUX 260 selected by the column select signal.

[0033] The control circuit 270 directs the word line driver to turn on a single selected word line (WL) during the first clock cycle. In addition, the control circuit 270 directs the read circuit system to precharge the bit lines of the memory; and operates the column readout MUX 260 to connect n columns in the group of columns to a single sense amplifier 280 (enabled using the SAE signal) in corresponding clock cycles starting from the second clock cycle, thereby reading all n columns in (n+1) clock cycles, where n is an integer equal to or greater than 1. Specifically, no matter which column or columns are desired to be read, one column is read at a time. In addition, columns can be selected discontinuously, thereby allowing out-of-order reading (where columns / bit cells can be skipped). It should be noted that the described circuit system for a group of bit cells / a group of bit lines / a group of columns can represent a single slice of a word (i.e., one bit depth).

[0034] Figure 3 This example shows how to read from memory. Figure 3A method 300 for performing a read operation from a memory may include: initiating (310) a read operation during a first clock cycle; operating (320) a column read multiplexer (MUX) coupled to a group of columns of the memory by individually applying one of n column select signals to a column read multiplexer (MUX) to connect n columns of the group of columns to a single sense amplifier, the single sense amplifier being coupled to the column read MUX in corresponding clock cycles starting from a second clock cycle so that all n columns are read out in (n+1) clock cycles, where n is an integer equal to or greater than 1; and capturing (330) corresponding column outputs of the column read MUX at the single sense amplifier in the corresponding clock cycle.

[0035] Initiating (310) a read operation may include turning on a single selected word line during a first clock cycle. Figure 6A To describe in more detail, a single selected word line may be kept turned on until the (n+1)th clock cycle.

[0036] Initiating (310) a read operation may include precharging the bit lines of the memory. A single sense amplifier may also be precharged during this initiation step.

[0037] When operating (320) the column readout MUX, applying individually one of the n column select signals to the column readout MUX may include selecting non-consecutive columns in consecutive clock cycles.

[0038] By taking advantage of the fact that all columns on the same word line begin generating bit line differentials at the beginning of cycle 1 when the word line goes high, multiple read operations supporting bit cell reads can be sequenced to complete within a single clock cycle. Figure 6A Described in more detail, the word line remains high for the entire duration of the blast operation, thereby providing sufficient differential between the bit lines of the column to be sampled into the sense amplifier.

[0039] In the burst mode read operation, multiple read operations occurring from the rising clock edge of the second clock cycle need to be completed before the next edge of the clock, which will again generate the sense amplifier enable (SAE) signal. The multiple read operations include:

[0040] 1. The local sense amplifier enable signal sae rises, causing the sense amplifier to operate. The new value sao (sense amplifier output) is ready to be stored in the Q holding flip-flop.

[0041] 2. The local clock signal gtp falls, causing the active column select (nyr) signal to turn off and the active local sense amplifier enable signal sae to turn off. At the same time, sao is stored in the Q holding flip-flop.

[0042] 3. With the falling edge of the local clock signal gtp, the falling edge of gtp_sa is detected and this triggers another gtp_pre signal to start another pre-charge of the sense amplifier node.

[0043] 4. The pre-charge control signal gtp_pre is a self-timed signal that is wide enough to pre-charge the sense amplifier node. Figure 4 The circuit shown illustrates an exemplary configuration for generating a precharge control signal.

[0044] 5. When gtp_pre drops, gtp is retriggered, resulting in a new nyr selection.

[0045] 6. Once nyr (e.g. Figure 2B The differential that has been generated on the BL / NBL pair selected in this cycle is transferred to the sense amplifier node, and the circuit waits for the next CLK edge so that the sae signal can rise again and store the value.

[0046] 7. This sequence of events needs to occur before the start of the next CLK cycle, otherwise, SAE will come too early and the differential on the BL will not be transmitted to the SD / NSD (SA) node.

[0047] The precharge control signal supports the ability to perform the above sequence of events within a clock cycle. In operations before the second clock cycle, the precharge control signal is used to control the precharge of the bit line. For example, the width of the gtp_pre signal is optimized during design so that the bit line can be precharged from 0 (worst case) to a high percentage (such as 95%) of VDD. This may be a long duration. For example, a 512rpb architecture may take some time to precharge the bit line. In contrast, in subsequent clock cycles, since the bit line does not have to be precharged and only a single sense amplifier is precharged, the pulse width of gtp_pre can be much smaller and still implement the precharge function. This can reduce the time required between the two nyr signals, allowing the sense amplifier node more time to obtain a differential from the bit line.

[0048] The precharge generation circuit can be used to generate a precharge control signal having two different widths, wherein the larger of the two widths is output for applying a voltage to precharge a bit line of the memory, and the smaller of the two widths is output from the second clock cycle to the (n+1)th clock cycle for applying a voltage to precharge a single sense amplifier. In this way, selective precharging is provided.

[0049] use Figure 4The circuit shown, when the operation is not in the first CLK cycle, can reduce the pulse width of gtp_pre by using the prech_suppress signal that detects the first CLK cycle and goes high when the first operation is completed. This reduces the sense amplifier precharge time and helps optimize the cycle time.

[0050] Figure 4 An exemplary circuit for generating a control signal that can be used to precharge a sense amplifier for faster burst read performance is illustrated. Figure 4 , the precharge generation circuit 400 may include a precharge clock generator 410 that turns on a pulse of a precharge control signal (gtp_pre) in response to receiving a clock signal. The clock signal received by the precharge clock generator 410 may include clks1, which is based on a clock edge of a chip enable (CEN) signal (e.g., about Figure 1A The precharge clock generator 410 may also receive a ctrs1 signal which is based on a sense amplifier enable (SAE) signal (e.g., reference Figure 1A The rising edge of the SAE described in the previous section goes high and the rising edge of the SAE described in the previous section goes low based on the control input of the previous section.

[0051] The precharge generation circuit also includes a reset circuit 420 configured to receive a pulse of a precharge control signal (as dwl_pre) output from the clock generator and a first clock cycle signal (prech_suppress / nprech_suppress) from the first clock cycle detector, and output a reset signal (reset_s1) to the clock generator, which disables the pulse of the precharge control signal (gtp_pre). Reset circuit 420 includes a first path 430 for a first delay period in response to a first clock cycle signal indicating a detected first clock cycle, and a second path 440 for a second delay period in a subsequent clock cycle of an operation following the detected first clock cycle. By introducing a longer signal path for first path 430 than for second path 440, the first delay period in the first clock cycle is greater than the second delay period in the subsequent clock cycle of the operation.

[0052] In operation, the precharge pulse begins when the clock signal is received. The pulse then stops when the feedback loop is completed (eg, via the first path 430 or the second path 440).

[0053] Figure 5 Figure 2 shows the voltage waveforms of various signals over time during the read operation. Figure 5In the scenario shown, two words are read from the memory, one of which is read from the first column and the other from the fourth column (reflected by the column select control signals FNYR0 and FGNYR3). Figure 5 , in the first clock cycle (CLK), the precharge control signal (GTP_PRE) pulse has a first width, which is suitable for precharging the bit line. In the second clock cycle, the sense amplifier enable (SAE) signal is turned on, the first column is selected, and at the falling edge of the second clock, the precharge control signal (GTP_PRE) is asserted. Figure 5 As shown, the second GTP_PRE pulse is a shorter pulse, causing FGNYR3 to arrive earlier and allowing more sense amplifier differential to occur before the second SAE pulse.

[0054] Figure 6A The operation of the control circuit for controlling the word line driver is shown in FIG. Figure 1A and Figure 1B As explained, the control circuit 140 receives input signals including chip enable, clock signal, burst enable signal and address enable signal, and outputs word line enable signal to the word line driver. Figure 6A The timing diagrams in FIGURE 1 show signals for memory operations involving one, two, three, and four words. In a burst read operation, multiple words (n words, where n is an integer greater than 1) in the same physical row can be read in consecutive clock cycles. In fact, given an initial clock cycle for starting a read operation, n words can be read in n additional (to the initial clock cycle) cycles (e.g., 4 words can be read in 5 cycles).

[0055] However, because the number of words may vary for each read access (e.g., one read access may burst read 4 words, while the next read access reads only 3 or 2 words), the length of time the word line is used for burst reads may also vary for each read access. Therefore, for a burst read operation, the control circuit 140 directs the word line driver to keep the single selected word line turned on until the (n+1)th clock cycle. In some cases, the control circuit 140 turns off the single selected word line during the falling edge of the n+1 clock cycle. That is, the word line generated in the first cycle continues to remain high until the last cycle of the burst read operation. This ensures that the bit line differential is continuously generated across all columns that can be read.

[0056] Figure 6B The control circuit for generating the word line enable signal is shown. Figure 6BThe control circuit 600 for generating a wordline enable signal includes a latch 610. Latch 610 can be implemented as, for example, an SR latch. Latch 610 is configured to go high during the first clock cycle to output a wordline enable signal that instructs a wordline driver to turn on a single selected wordline. It is also configured to receive a last cycle signal that resets the wordline enable signal, causing the wordline driver to turn off the single selected wordline in response to the last cycle signal indicating the last (e.g., (n+1)th) clock cycle. Here, the local clock signal and the last cycle signal (last_cycle) are combined to serve as the set and reset inputs of latch 610. As long as last_cycle remains low (i.e., it is not the last cycle), a NAND gate can be used to hold the input high. An OR gate (or equivalent, such as a NOR gate with an inverter) is used to allow the setting value stored in latch 610 to be changed. That is, when last_cycle is high, the reset input is high, and latch 610 will be updated with the value at the set input, which is low because last_cycle is high. In this way, the local clock does not cause the wordline enable signal to go low until the last cycle of the blast operation occurs. In effect, in a blast operation, circuit 600 activates the wordline on the first clock and turns off the wordline on the last clock, which can vary depending on the depth of the blast read operation.

[0057] Figure 7 A specific implementation of an exemplary control circuit for generating a word line enable signal is shown. Figure 7 The control circuit 700 includes a circuit system for generating a word line enable signal (such as reference Figure 6B ) and also includes optional power-on protection circuitry. Specifically, in circuit 700, SR latch 710 generates the igtp_wdx signal, which enters the memory array's wordline decoder to generate the wordline. A set signal is generated when gtp_local rises and last_cycle = 1. A reset signal is generated when gtp_local falls and last_cycle = 0. Glitches in wordline signals can be avoided or minimized through proper signal sequencing.

[0058] A power-up protection circuit 720 may be included to avoid or minimize potential short-term pulse glitches when power-up occurs. For example, the power-up protection circuit 720 may be located on the signal nreset_gtp_wdx. When powering up from retention mode, this signal is guaranteed to be 0 by a combination of the following three signals: 1) BPRDYN - This is a signal on VDDPE that tracks RET power-up and only fully drops after the internal VDDP header has been precharged to a large enough value for all logic to stabilize; 2) NBPRDYN_LOCAL - This is a delayed version of the BPRDYN signal and is inserted into the circuit to ensure that the nreset_gtp_wdx signal itself does not have short-term pulse glitches; and 3) INRESET - This is the normal reset signal, triggered by the first NGTP_PRE or external RESETN pin in normal operation.

[0059] Figure 8 The waveforms of various signals during power-on and the results of combining the power-on protection circuit are shown. Figure 8 , it can be seen that when VDDPE 800 is powered on after RET 802 goes low (indicating the end of retention mode), the NRESET 804 signal does not toggle until VDDPE 800 is fully powered on.

[0060] Certain embodiments of the illustrated method and memory circuitry include the following.

[0061] Item 1. A memory circuit system comprising: a word line driver for a memory and coupled to receive an address and select a corresponding word line for the memory; a read circuit system; and a control circuit for operating the word line driver and the read circuit system; wherein the read circuit system comprises: a column read multiplexer (MUX), the column read MUX coupled to a group of columns of the memory, wherein the column read MUX receives a column select signal from the control circuit to output a corresponding column output from the group of columns; and a single sense amplifier coupled to receive the corresponding column output of the column read MUX.

[0062] Item 2. A memory circuit system according to Item 1, wherein the control circuit instructs the word line driver to turn on a single selected word line during a first clock cycle, and wherein the control circuit directs the read circuit system to perform the following operations: precharge the bit lines of the memory; and operate the column read MUX to connect n columns of the group of columns to the single sense amplifier in corresponding clock cycles starting from the second clock cycle, so that all n columns are read out in (n+1) clock cycles, where n is an integer equal to or greater than 1.

[0063] Item 3. A memory circuit system according to Item 1 or 2, wherein the memory circuit system further includes: a precharge control signal generating circuit, wherein the precharge control signal generating circuit generates a precharge control signal having two different widths, wherein the larger width of the two different widths is output for applying a voltage to precharge the bit line of the memory, and the smaller width of the two different widths is output from the second clock cycle to the (n+1)th clock cycle for applying a voltage to precharge the single sense amplifier.

[0064] Item 4. A memory circuit system according to any of the preceding items, wherein the precharge control signal generating circuit includes: a precharge clock generator, which turns on a pulse of the precharge control signal in response to receiving a clock signal; and a reset circuit, which is constructed to receive the pulse of the precharge control signal from the output of the clock generator and the first clock cycle signal from the first clock cycle detector, and output a reset signal to the clock generator, which turns off the pulse of the precharge control signal, the reset circuit having a first path responsive to a first delay period of the first clock cycle signal indicating a detected first clock cycle and a second path for a second delay period of a subsequent clock cycle of an operation after the detected first clock cycle, wherein the first delay period of the first clock cycle is greater than the second delay period of the subsequent clock cycle of the operation.

[0065] Clause 5. The memory circuitry of any preceding clause, wherein the control circuit directs the word line driver to hold the single selected word line on until the (n+1)th clock cycle.

[0066] Item 6. A memory circuit system according to any preceding item, wherein the control circuit includes a latch, which is constructed to become high during a first clock cycle to output a word line enable signal that instructs the word line driver to turn on the single selected word line, and wherein the latch is also constructed to receive a last cycle signal that resets the word line enable signal, so that the word line driver turns off the single selected word line in response to the last cycle signal indicating the (n+1)th clock cycle.

[0067] Clause 7. The memory circuitry of any preceding clause, further comprising: a Q retention flip-flop coupled to the single sense amplifier to store an output of the single sense amplifier.

[0068] Clause 8. The memory circuitry of any preceding clause, wherein the set of columns comprises four columns of the memory.

[0069] Clause 9. The memory circuitry of any preceding clause, wherein the control circuit is configured to receive an address enable signal and generate a column select signal based on a column identified by the address enable signal.

[0070] Clause 10. The memory circuitry of any preceding clause, wherein the address enable signal is a decoded explosion address that indicates which columns of the set of columns are to be accessed.

[0071] Clause 11. The memory circuitry of any preceding clause, wherein the control circuit has separate address pins for receiving the address enable signal, each pin corresponding to a column in the set of columns.

[0072] Item 12. A method of performing a read operation from a memory, the method comprising: initiating a read operation during a first clock cycle; operating a column read multiplexer (MUX) coupled to a group of columns of the memory by individually applying one of n column select signals to a column read multiplexer (MUX) to connect n columns of the group of columns to a single sense amplifier, the single sense amplifier being coupled to the column read MUX in a corresponding clock cycle starting from a second clock cycle so that all n columns are read out in (n+1) clock cycles, where n is an integer equal to or greater than 1; and capturing a corresponding column output of the column read MUX at the single sense amplifier in the corresponding clock cycle.

[0073] Clause 13. The method of clause 12, wherein individually applying the column select signals to the column readout MUXs comprises selecting non-consecutive columns in consecutive clock cycles.

[0074] Clause 14. The method of Clause 12 or 13, wherein initiating the read operation comprises turning on a single selected word line during a first clock cycle.

[0075] Clause 15. The method of any preceding method clause, further comprising maintaining the single selected word line on until the (n+1)th clock cycle.

[0076] Clause 16. The method of any preceding method clause, wherein initiating the read operation comprises precharging a bit line of the memory.

[0077] Item 17. A method according to any of the preceding method items, the method further comprising: generating a precharge control signal having two different widths, wherein a larger width of the two different widths is output for applying a voltage to precharge the bit line of the memory, and a smaller width of the two different widths is output from the second clock cycle to the (n+1)th clock cycle for applying a voltage to precharge the single sense amplifier.

[0078] Clause 18. The method of any preceding method clause, wherein n=4.

[0079] Clause 19. The method of any preceding clause, wherein operating the column readout MUX comprises: receiving an address enable signal; and generating the n column select signals based on a column identified by the address enable signal.

[0080] Clause 20. The method of any preceding method clause, wherein the address enable signal is a decoded burst address indicating which columns of the set of columns are to be accessed.

[0081] Although the subject matter has been described in language specific to structural features and / or acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as examples of implementing the claims, and other equivalent features and acts that those skilled in the art will recognize are intended to fall within the scope of the claims.

Claims

1. A memory circuit system, comprising: a word line driver for a memory and coupled to receive an address and select a corresponding word line for the memory; Reading circuit system; and a control circuit for operating the word line driver and the read circuitry; The reading circuit system includes: a column readout multiplexer (MUX) coupled to a group of columns of the memory, wherein the column readout MUX receives a column select signal from the control circuit to output corresponding column outputs from the group of columns; and A single sense amplifier is coupled to receive the corresponding column output of the column readout MUX.

2. The memory circuit system of claim 1 , wherein the control circuit directs the word line driver to turn on a single selected word line during a first clock cycle, and The control circuit instructs the reading circuit system to perform the following operations: precharging a bit line of the memory; and The column readout MUX is operated to connect n columns of the group of columns to the single sense amplifier in corresponding clock cycles starting from the second clock cycle so that all n columns are read out in (n+1) clock cycles, where n is an integer equal to or greater than 1.

3. The memory circuit system according to claim 2 , further comprising: A precharge control signal generating circuit that generates a precharge control signal having two different widths, wherein a larger width of the two different widths is output for applying a voltage to precharge the bit line of the memory, and a smaller width of the two different widths is output from the second clock cycle to the (n+1)th clock cycle for applying a voltage to precharge the single sense amplifier.

4. The memory circuit system according to claim 3 , wherein the precharge control signal generating circuit comprises: a precharge clock generator that turns on a pulse for the precharge control signal in response to receipt of a clock signal; and A reset circuit is constructed to receive the pulse of the precharge control signal from the output of the clock generator and the first clock cycle signal from the first clock cycle detector, and output a reset signal to the clock generator, the reset signal turning off the pulse of the precharge control signal, the reset circuit having a first path responsive to a first delay period of the first clock cycle signal indicating a detected first clock cycle and a second path having a second delay period of a subsequent clock cycle of an operation after the detected first clock cycle, wherein the first delay period of the first clock cycle is greater than the second delay period of the subsequent clock cycle of the operation.

5. The memory circuitry of claim 2, wherein the control circuit directs the word line driver to keep the single selected word line turned on until the (n+1)th clock cycle.

6. The memory circuit system of claim 5 , wherein the control circuit includes a latch configured to become high during a first clock cycle to output a word line enable signal instructing the word line driver to turn on the single selected word line, wherein the latch is further configured to receive a last cycle signal that resets the word line enable signal so that the word line driver turns off the single selected word line in response to the last cycle signal indicating the (n+1)th clock cycle.

7. The memory circuit system according to claim 1 , further comprising: A Q holding flip-flop is coupled to the single sense amplifier to store an output of the single sense amplifier.

8. The memory circuitry of claim 1, wherein the set of columns comprises four columns of the memory. 9 . The memory circuit system of claim 1 , wherein the control circuit is configured to receive an address enable signal and generate a column select signal based on a column identified by the address enable signal.

10. The memory circuitry of claim 9, wherein the address enable signal is a decoded explosion address that indicates which columns of the set of columns are to be accessed.

11. The memory circuitry of claim 9, wherein the control circuit has separate address pins for receiving the address enable signal, each pin corresponding to one column of the set of columns.

12. A method for performing a read operation from a memory, the method comprising: initiating a read operation during a first clock cycle; operating a column readout multiplexer (MUX) coupled to a group of columns of the memory by individually applying one of n column select signals to the MUX to connect n columns of the group of columns to a single sense amplifier, the single sense amplifier being coupled to the column readout MUX in corresponding clock cycles starting from a second clock cycle, such that all n columns are read out in (n+1) clock cycles, where n is an integer equal to or greater than 1; as well as During the corresponding clock cycle, a corresponding column output of the column readout MUX is captured at the single sense amplifier.

13. The method of claim 12, wherein individually applying the column select signals to the column readout MUX comprises selecting non-consecutive columns in consecutive clock cycles.

14. The method of claim 12, wherein initiating the read operation comprises turning on a single selected word line during a first clock cycle. 15 . The method of claim 14 , further comprising keeping the single selected word line turned on until the (n+1)th clock cycle.

16. The method of claim 12, wherein initiating the read operation comprises precharging a bit line of the memory.

17. The method according to claim 16, further comprising: A precharge control signal having two different widths is generated, wherein a larger width of the two different widths is output for applying a voltage to precharge the bit line of the memory, and a smaller width of the two different widths is output from the second clock cycle to the (n+1)th clock cycle for applying a voltage to precharge the single sense amplifier. The method according to claim 12 , wherein n=4.

19. The method of claim 12, wherein operating the column readout MUX comprises: Receive address enable signal; as well as The n column select signals are generated based on the column identified by the address enable signal.

20. The method of claim 19, wherein the address enable signal is a decoded explosion address that indicates which columns of the set of columns are to be accessed.

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