Read-write control method for reducing power consumption of SRAM (Static Random Access Memory) in image sensor

Abstract

The invention provides a method for adjusting the pre-charging time of a bit line of an SRAM (Static Random Access Memory) in an image sensor and reducing the starting frequency of a word line. Specifically, multiple times of word line opening and multiple times of pre-charging opening in multiple times of reading are reduced to one time of word line opening and one time of pre-charging, so that the charging power consumption of a word line unit and a bit unit and the flipping dynamic power consumption of a related logic circuit during word line flipping are reduced.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a read-write control method for reducing SRAM power consumption in an image sensor. Background Art

[0002] The mainstream SRAM memory cell is a six-transistor (6T) memory cell. The 6T memory cell is symmetrical and consists of six MOS transistors. MOS transistors M1-M4 form two cross-coupled inverters, latching the signal at the storage node bit / . MOS transistors M5 and M6 are transfer transistors, connecting or disconnecting the memory cell from the bit line during read / write operations on the SRAM memory. The SRAM memory cell has three states: read, write, and hold. When reading, the bit line BL / is first charged to a high level. This then charges the word line WL to a high level, turning on transfer transistors M5 / M6. The storage node bit / bit_ discharges to the bit line BL / , causing the voltage on one bit line to drop by ΔV while the other remains high. A sense amplifier amplifies this voltage difference ΔV, allowing the data to be read. When writing, one bit line is precharged to a high level based on the data to be written, while the other bit line is simultaneously discharged to ground. The word line WL is then charged to a high level, turning on the pass transistors M5 / M6, and the bit line charges and discharges data to the storage node bit / bit_. The charge / discharge current must be greater than the pull-down / pull-up current, ensuring that the voltage on the storage node bit / bit_ is high enough to reverse the inverter. Otherwise, the write will fail.

[0003] In the prior art, before writing new data to an SRAM memory cell, the memory cell is already in a stable state, such as "1" or "0." The traditional SRAM bit-cell write process switches from one stable state to another. If an opposite state is written, such as the stored state is "1" and the newly written state is "0," or the stored state is "0" and the newly written state is "1," the external signal must have a strong driving capability to change the old storage state. Therefore, the state switching speed of the SRAM write process is slow, the time is long, the DC power consumption is high, and because the stored data changes with the full swing, the write noise is also large.

[0004] In existing portable electronic devices, memory cells are commonly used for data storage and reading. For example, in a CIS (CMOS Image Sensor) chip, the pixel unit converts the exposure level into an electrical signal, PXD, which reflects the exposure level. Simultaneously, the design generates a ramp signal, RAMP. When the ramp signal begins to rise or fall, a counter begins counting. The PXD signal is compared with the RAMP signal. When the two values are equal, the counter value at that moment is recorded in the memory cell. After this process is completed, the chip's control module can read the data from the memory cell for further processing.

[0005] The readout circuit of the memory cell in the prior art includes three parts: a precharge module, a memory cell, and an amplifier module. Taking static random access memory (SRAM) as an example, during the data reading process, the precharge module is first enabled to charge the value of the bit line BL / BLB to a high voltage; then the word line WL signal is set high to read the data in the memory cell, resulting in a certain voltage difference between the BL / BLB voltages; finally, the voltage difference is transmitted to the amplifier module, and after the voltage difference is amplified, the data can be read out.

[0006] To avoid excessively long BLTs (Byte Lane Terminations), SRAM in image sensors often utilizes bitline multiplexers (MUXs) to reduce line lengths. By selecting different input signals, the number of signal lines required for transmission is reduced. However, this structure involves redundant bitlines during read and write operations, resulting in additional power consumption. Summary of the Invention

[0007] The object of the present invention is to provide a read-write control method for reducing the power consumption of an SRAM in an image sensor.

[0008] In order to achieve the above objectives, the present invention is implemented through the following technical solutions: In the SRAM of an image sensor, each word line is provided with m multiplexers. A single bit line operation reads 2 to n data and writes 2 to n data, and the bit line is precharged only once. During multiple read operations, a word line is charged once for every n read operations, thereby reducing the charging power consumption of the SRAM.

[0009] Furthermore, the multiple readings are continuous readings of the bit lines coupled to the same multiplexer.

[0010] Furthermore, during the multiple read operations, a bit line is operated once, and a word line is charged at least twice every 2-n read operations, so as to reduce data loss due to factors such as leakage.

[0011] Furthermore, in multiple read operations corresponding to one bit line operation, the bit line is precharged once, and the state of the bit line after the word line is turned on is maintained.

[0012] Furthermore, in multiple write operations corresponding to one bit line operation, the bit line is precharged once, and the state of the bit line after the word line is turned on is maintained.

[0013] Furthermore, the multiple reading or multiple writing may be reading and writing in order of addresses.

[0014] Compared with the prior art, the present invention has the following advantages: Because image sensors in some cases read data from SRAMs in a non-random order, but rather sequentially from all bit cells, the present invention adjusts the bitline precharge timing and reduces the number of wordline activations. Specifically, the x number of wordline activations and x number of precharge activations in x reads is reduced to just one wordline activation and one precharge. This reduces the charging power consumption of wordline and bit cells, as well as the dynamic power consumption of related logic circuits during wordline flipping. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for the description. Obviously, the drawings described below are one embodiment of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive effort: Figure 1 A structural diagram of an SRAM circuit in an image sensor provided by one embodiment of the present invention; Figure 2 A circuit diagram of a multiplexer provided in one embodiment of the present invention; Figure 3 This is a SRAM read and write timing diagram provided by Example 1 of the present invention; Figure 4 The SRAM read and write timing diagram provided by the second embodiment of the present invention; Figures 5A-5B This is a schematic diagram of the SRAM structure provided by other embodiments of the present invention. DETAILED DESCRIPTION

[0016] The scheme proposed in the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the implementation methods of the present invention. In order to make the purposes, features and advantages of the present invention more obvious and easy to understand, please refer to the accompanying drawings. It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no technical substantive significance. Any structural modification, change in proportional relationship or adjustment of size, without affecting the efficacy and purpose that can be achieved by the present invention, should still fall within the scope of the technical content disclosed by the present invention.

[0017] The existing general SRAM is designed so that one word line corresponds to n bit line units contained in an m-bit word. Therefore, during a read operation, each time a word line is selected, n×m bit line units will be selected at the same time, and n×m bit lines will read the data in the bit line units and perform pull-up and pull-down operations. After this read, the n×m bit lines will be precharged back to a high potential, and each n bit lines will be selected by a multiplexer to select the data to be read. In the entire process, only the information reading process of m bit lines is necessary, and the information read on the other (n-1)×m bit lines is lost. For example, Figure 1 As shown in the figure, m=2, n=4, and YS and YSB are a pair of inverting signals. When reading, WBLT and WBLB are both high.

[0018] The following combination Figure 2-4 The method for reducing the power consumption of SRAM reading and writing in image sensors is described in detail. Example 1

[0019] A method for reducing the power consumption of SRAM reading and writing in an image sensor is provided.

[0020] like Figure 1 As shown, each word line corresponds to two multiplexers, and each multiplexer corresponds to four bit lines. A single bit line operation reads two to four pieces of data and writes two to four pieces of data. When WLD1 is turned on once, the data of the four bit line cells (Bitcell 11, Bitcell 12, Bitcell 13, and Bitcell 14) are read and stored on their respective bit lines. Subsequently, as long as the four precharge signals remain high, the information on the bit lines is retained. During this retention period, the corresponding information can be read from RBLT and RBLB by turning on the YSB signal.

[0021] In some other embodiments, each word line may correspond to four multiplexers, and each multiplexer may correspond to eight bit lines. Accordingly, one bit line operation reads 2-8 data and writes 2-8 data.

[0022] like Figure 2 FIG. 1 is a circuit diagram of a multiplexer according to an embodiment 1. Figure 2 The WBLT, WBLB, RBLT, and RBLB shown in Figure 1 The corresponding signal line in .

[0023] like Figure 3 As shown, this is a sequential read and write timing diagram of Example 1. In view of the characteristics of sequential reading, the four word line (WL) openings and four pre-charge openings in the four reads are reduced to one word line (WL) opening and one pre-charge, which reduces the charging power consumption of the word line (WL) and the bit line (BL), as well as the flip dynamic power consumption of the related logic circuit when the word line (WL) is reversed. Example 2

[0024] like Figure 4 As shown, during an SRAM read operation in an image sensor, the bit line floats, causing leakage to gradually lose stored data. This causes the voltage difference between BLT and BLB to gradually decrease. To prevent this voltage difference from affecting data readout, the word line (WL) can be enabled once more during the data retention process to compensate for the voltage difference loss. Compared to the first embodiment, simply enabling the word line once more during the data retention process can reduce the impact of the voltage difference.

[0025] In some other embodiments, the method in the above embodiment can also be applied to sequential write operations. Specifically, precharging is performed once every n write operations. In this case, each time the word line is turned on, the bit line voltage will be closer to the information originally stored in the bit line unit. In this way, when the write operation is performed, if the current value before writing is 0, the same value 0 as before is written, and the charging charge required for the bit line will be reduced; and if the current value before writing is 0, and the opposite value 1 is written, then this method will not save power. In summary, during sequential write operations, changing the scheme of multiple word line turns on and multiple precharges to one word line turn on and one precharge can reduce the SRAM write power consumption when the same value is written in sequential write operations.

[0026] In some other embodiments, a control signal in the same direction as the word line can be introduced into the 6TSRAM to turn off the gateMOSFET during writing, thereby blocking the leakage current of the competing path during the writing process, thereby further reducing the writing power consumption. Figure 5AAs shown, a control signal can be set at the Vdd end, and the P-type MOSFET ( Figure 5A The gate of the dashed box is turned off; or Figure 5B As shown, a control signal is set at the ground end, and the N-type MOSFET ( Figure 5B The gate of the dotted box is turned off.

[0027] In some other embodiments, different voltages can be used in the circuit to further reduce the power consumption during the reading process. For example, during the reading process, the charging and discharging process of the bit line will account for a large proportion of the total power consumption. In order to ensure that the information in the bit line unit is not destroyed during the reading process, a lower pre-charge voltage can be used. For example, the pre-charge voltage can be reduced to 50-80% of the original voltage, thereby reducing the total power consumption during the reading process.

[0028] In summary, the present invention provides a method for adjusting the timing of bitline precharges and reducing the number of wordline activations. Specifically, the method reduces x wordline activations and x precharge activations in x reads to only one wordline activation and one precharge in x reads, thereby reducing the charging power consumption of wordline units and bit units, as well as the dynamic power consumption of related logic circuits during wordline flipping.

[0029] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0030] Although the present invention has been described in detail through the above preferred embodiments, it should be understood that the above description is not intended to limit the present invention. After reading the above description, various modifications and substitutions of the present invention will become apparent to those skilled in the art. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A read / write control method for reducing SRAM power consumption in an image sensor, characterized in that: Each word line corresponds to a multiplexer, and each of the multiplexers corresponds to n bit lines; One bit line operation reads 2 to n data, writes 2 to n data, and precharges the bit line only once; During multiple reads, a word line is charged once every n read operations; To reduce the charging power consumption of the SRAM.

2. The method according to claim 1, wherein The multiple readings are to continuously read the bit lines coupled to the same multiplexer.

3. The method according to claim 1, wherein During the multiple reading periods, a bit line operation is performed once, and a word line is charged at least twice every 2-n reading operations, so as to reduce data loss caused by factors such as leakage.

4. The method according to claim 1, wherein In multiple read operations corresponding to one bit line operation, the bit line is precharged once and the state of the bit line after the word line is turned on is maintained.

5. The method according to claim 1, wherein In multiple write operations corresponding to one bit line operation, the bit line is precharged once and the state of the bit line after the word line is turned on is maintained.

6. The method according to claim 2, wherein The multiple reading or multiple writing may be reading and writing in order of addresses.

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