Chip or wafer and system for detecting chip or wafer

Abstract

The chip or the wafer is provided with at least two conductive alignment marks, and the at least two conductive alignment marks are in contact with the at least two conductive probes on the probe card. The at least two conductive alignment marks each have an electrical signal that is transmittable from the alignment mark to the conductive probe. The two electrical signals may have different voltage levels or different signal frequencies from each other. The electric signal is used for calculating the rotation deviation and / or the transverse deviation of the chip or the wafer relative to the probe card so as to carry out accurate wafer alignment.

Description

Technical Field

[0001] The field of the invention relates to memory testing systems. Background Art

[0002] The Background Description includes information that may be useful in understanding the present invention. No admission is made that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication explicitly or implicitly referenced is prior art.

[0003] DRAM and flash memory technologies have been well-known for many years. While the basic underlying technology has remained largely unchanged over time, the interfaces have evolved over time, with names like Fast Page Mode (FPM), Extended Data Output (EDO), Synchronous DRAM (SDRAM), and Double Data Rates 1-4 (DDR1, DDR2, DDR3, DDR4, and DDR5). In some applications, DRAM components are soldered to a PCB substrate to form a module (e.g., a DIMM module that plugs into a computer system's motherboard).

[0004] Testing of packaged memory components is traditionally done in several steps and multiple insertions. Typically, the packaged DRAM components are first subjected to a burn-in ("BI") test. This test is performed with high parallelism in expensive BI systems. For example, current BI systems may cost between $500,000 and $1,000,000 per test system. Due to the large number of parts tested and contacted, such systems operate at low frequencies of approximately 5MHz-20MHz, which is far from the normal operating frequency of 1GHz for such semiconductors. In order to reduce the need for signals, most methods use on-chip internal test circuits to compress all data signals onto a single external data pin (e.g., reducing 16DQ to a single DQ), and use other test modes to modify internal voltages for more effective stress on memory components. The purpose of BI testing is to age the semiconductor under several hours of stress to avoid infant failures at the customer level. The relevant stress tests are typically performed at elevated voltages and temperatures up to 125 degrees Celsius. Typically, thousands of components are tested in parallel in a single BI test system.

[0005] After a successful BI test, the components are then subjected to weak cell or core testing. These tests are designed to identify weak DRAM memory cells that may have failed at the customer level due to poor memory cell retention or other weaknesses. Testing is performed on expensive automated test equipment, which typically costs $1 million to $3 million, operates at frequencies of 200 MHz to 500 MHz, and tests 200 to 1,000 components in parallel. Because a large number of signals are provided, such as some address / command signals, are shared between multiple components and chip vendor-provided test patterns for data compression, the amount of DQ contact required is reduced (for example, through data compression (read) and copy (write) methods, only 4 data signals are required instead of all 16). This testing can be performed at different temperatures. For example, a group of components can be tested at a high temperature (for example, at 95 degrees Celsius), removed from the system, and later tested at a very low temperature (for example, -40 degrees Celsius) on a different test system. Removal is necessary because the test processor cannot change the temperature so quickly without other adverse effects. The handler is attached to the test system for feeding the DRAM components to be tested to the test head and providing the desired test temperature.

[0006] After the weak unit test is successful, as is known in the art, the component will undergo a speed test performed by a DRAM speed tester. During this test, all electrical signals of the component need to be connected to the speed tester to ensure that all signals and circuits are fully functional. A DRAM with 16DQ will have to be connected to 16 separate DQ signals without compression mode. Therefore, the parallelism of such a test system is relatively low in the range of 50-200 components. In addition, the components must operate at full system speeds in the range of 1GHz. Therefore, such a system is very expensive, typically costing from $3 million to $5 million. It may also be necessary to test at different temperatures (e.g., 95°C and later again at -40°C) to ensure that the customer's specifications for fully functional parts are met.

[0007] As mentioned above, DRAM packaged components are submitted to a set of at least 3 different test systems for BI, weak cell and speed testing. Some test steps may have to be performed at different temperatures, requiring submission to up to 5 tests. This means that if retesting is required, the component is handled up to 5 times or more. This results in damage to contact components (e.g., contact balls of FBGA components) due to handling, which is not desirable but cannot be avoided with today's testing methods. In addition, very expensive tools are required to feed and handle the DRAM components within the test handler and electrically connect them to the test head. For example, Hifix electrically connects the components to the test signal channels. Such tools are product-specific and must be provided for each individual DRAM. A 9mm x 11mm FBGA 78 package requires completely different tools and Hifix than, for example, a 7mm x 10mm FBGA96 package. A single set of tools for one product can easily cost more than $250,000.

[0008] In light of the foregoing, the reader can readily appreciate that existing testing processes for advanced semiconductors are expensive and complex. Furthermore, the nature of the testing carries the risk of damaging the components themselves. Consequently, a need exists for a simpler, safer way to test DRAM components. Furthermore, a need exists for test systems and methods that can be used for both DRAM components and wafers, as well as for precise wafer alignment. Summary of the Invention

[0009] The present invention provides apparatus, systems, and methods in which a chip or wafer includes at least two conductive alignment marks (e.g., alignment marks) configured to contact at least two conductive probes on a probe card, and at least two electrical signals capable of being transmitted from the at least two alignment marks to the at least two conductive probes. The at least two electrical signals preferably have different voltage levels or different signal frequencies from each other.

[0010] In some embodiments, the at least two conductive probes are spaced apart by a or a multiple of a. In such embodiments, the at least two conductive alignment marks are shifted by a distance d along the x-direction or the y-direction on the chip or wafer, where a is not equal to d.

[0011] In other aspects of some embodiments, it is contemplated that distance a is equal to 90 μm and distance d is equal to 45 μm.

[0012] In another aspect of some embodiments, the at least two conductive alignment marks include at least two metal lines that are horizontally or vertically aligned with the row or array of probes. It is also contemplated that the at least two conductive alignment marks can be arranged diagonally relative to the row or array of probes. For example, the at least two conductive alignment marks can form an angle between 5 degrees and 85 degrees relative to the row or array of probes.

[0013] In other aspects, the conductive alignment marks can be straight line segments that are vertically displaced relative to each other. The conductive alignment marks can also be one or more metal crosses configured to be probed by a probe of an array of at least 3 x 3.

[0014] In yet other aspects of some embodiments, at least two conductive alignment marks are spaced at least 10 mm apart.

[0015] The at least two electrical signals are used to calculate a rotational deviation of the chip or wafer relative to the probe card. The at least two electrical signals can also be used to calculate a lateral deviation of the chip or wafer relative to the probe card.

[0016] The present subject matter provides a system for probing a chip or wafer. The system includes a motorized wafer chuck for mounting a chip or wafer for testing; a probe card having a plurality of probes for receiving a plurality of electrical signals from a plurality of conductive alignment marks on the chip or wafer; and a processor and one or more executable software instructions programmed to correct the alignment of the wafer chuck relative to the probe card based on the plurality of electrical signals. The wafer chuck is preferably moved or rotated separately from the lateral movement of the probe card. The processor and the one or more executable software instructions can be programmed to move or rotate the motorized wafer chuck and the laterally moving probe card based on the plurality of electrical signals.

[0017] Various objects, features, aspects, and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, taken in conjunction with the accompanying drawings, in which like reference numerals represent like components.

[0018] All publications mentioned herein are incorporated by reference to the same extent as if each individual publication or patent application was specifically and individually indicated to be incorporated by reference. To the extent that a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.

[0019] The following description includes information that may be useful in understanding the present invention. No admission is made that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication explicitly or implicitly referenced is prior art.

[0020] In certain embodiments, the numerals for describing and claiming the amount of the representation composition of some embodiments of the present invention, characteristic (such as concentration), reaction conditions, etc. should be understood to be modified by the term "about" in some cases. Therefore, in certain embodiments, the numerical parameters set forth in written description and the appended claims are approximate values, and this approximate value can seek to change according to the desired property obtained in a particular embodiment. In certain embodiments, numerical parameters should be interpreted according to the number of reported significant figures and by applying common rounding techniques. Although the numerical range and the parameters of the wide range of some embodiments of the present invention are approximate values, the numerical value set forth in the specific examples is reported as accurately as possible. In certain embodiments of the present invention, the numerical value provided may contain some errors, and this error must be due to the standard deviation found in their respective test measurements causing.

[0021] Unless the context indicates otherwise, all ranges set forth herein should be interpreted as including their endpoints, and open ranges should be interpreted as including only commercially practical values. Similarly, unless the context indicates otherwise, all lists of values should be considered to include intermediate values.

[0022] As used in the specification herein and throughout the appended claims, the meaning of "a," "an," and "the" includes plural references unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of "in" includes "in" and "on" unless the context clearly dictates otherwise.

[0023] The description of value ranges herein is only intended to be used as a shorthand method for individually referring to each individual value falling within the scope. Unless otherwise noted herein, each individual value is incorporated into this specification as if it were individually enumerated herein. Unless otherwise noted herein or context otherwise clearly conflicts, all methods described herein can be performed in any suitable order. The use of any and all examples or exemplary language (such as "such as") provided herein for certain embodiments is only intended to better illustrate the present invention and is not intended to limit the scope of the present invention otherwise claimed. The language in the specification should not be interpreted as indicating any unclaimed element that is crucial to the practice of the present invention.

[0024] The group of alternative elements or embodiments of the present invention disclosed herein should not be construed as limiting. Each group member can be quoted and claimed individually, or can be quoted and claimed in any combination with other members of the group or other elements herein. For convenience and / or patentability, one or more members of the group may be included in the group or deleted from the group. When any such inclusion or deletion occurs, this specification is deemed to comprise the group as modified herein, thereby satisfying the written description of all Markush groups used in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1A and Figure 1B Shown are top views of assembled test board systems according to two variations of embodiments of the inventive subject matter, the test board systems comprising a frame and a plurality of main boards disposed on the frame.

[0026] Figure 1C Shown attached to the frame Figure 1A or Figure 1B Bottom view of multiple motherboards.

[0027] Figure 2 Provides a view of the frame in isolation.

[0028] Figure 3A and Figure 3B An embodiment according to the subject matter of the present invention is shown Figure 1A ( Figure 3A neutral) and Figure 1B ( Figure 3B (center) Front view of the isolated motherboard.

[0029] Figure 3C A bottom view of a motherboard and its components according to an embodiment of the inventive subject matter is provided.

[0030] Figure 3D Shown according to Figure 3B A cross-sectional view of a motherboard of an embodiment.

[0031] Figure 4A-4B A front view and a perspective view are respectively shown of a mainboard according to another embodiment of the inventive subject matter.

[0032] Figure 5A-5B Shown respectively Figure 4A-4B An embodiment wherein the memory module is inserted into the memory module slot.

[0033] Figure 6 The assembled test system is shown with the microclimate chamber arranged on the top side.

[0034] Figure 7A-7BSide and top views of a multi-layer motherboard assembly according to an embodiment of the inventive subject matter are shown.

[0035] Figure 8 Shown are top and side views of multiple motherboard assemblies inserted into a frame to form an assembled test system having memory component slots, according to an embodiment of the inventive subject matter.

[0036] Figure 9 Top and side views of multiple motherboard assemblies inserted into a frame to form an assembled test system having memory module slots are shown, according to an embodiment of the inventive subject matter.

[0037] Figure 10 A perspective view of a wafer test board system is shown, which includes a main board coupled to a probe card and a wafer resting on the probe card.

[0038] Figure 11 Shown Figure 10 Side view of the wafer test board system.

[0039] Figure 12 A top view of a first probe card design is shown.

[0040] Figure 13 A top view of a second probe card design is shown.

[0041] Figure 14A Shown is the first slice orientation of the motherboard design.

[0042] Figure 14B A second sheet orientation of the motherboard design is shown.

[0043] Figure 15 shows the second sheet of 14B oriented with Figure 13 The second probe card is designed side by side.

[0044] Figure 16 Conductive alignment marks of the wafer are shown.

[0045] Figure 17 Another conductive alignment mark of the wafer is shown.

[0046] Figure 18 A wafer with conductive alignment marks is shown.

[0047] Figure 19 Another wafer with conductive alignment marks is shown.

[0048] Figure 20 Another conductive alignment mark of the wafer is shown.

[0049] Figure 21Another conductive alignment mark of the wafer is shown. DETAILED DESCRIPTION

[0050] Throughout the following discussion, many references will be made to servers, services, interfaces, engines, modules, clients, peers, portals, platforms, or other systems formed by computing devices. It should be understood that the use of such terms is considered to mean one or more computing devices having at least one processor (e.g., ASIC, FPGA, DSP, x86, ARM, ColdFire, GPU, multi-core processor, etc.) programmed to execute software instructions stored on a computer-readable tangible, non-transitory medium (e.g., hard drive, solid-state drive, RAM, flash memory, ROM, etc.). For example, a server may include one or more computers operating as a web server, database server, or other type of computer server in a manner that implements the described roles, responsibilities, or functions. It should be further understood that the disclosed computer-based algorithms, processes, methods, or other types of instruction sets may be implemented as a computer program product that includes a non-transitory, tangible, computer-readable medium storing instructions that cause a processor to perform the disclosed steps. Different servers, systems, databases, or interfaces can use standardized protocols or algorithms to exchange data, perhaps based on HTTP, HTTPS, AES, public-private key exchange, web service APIs, known financial transaction protocols, or other electronic information exchange methods. Data exchange can occur over a packet-switched network, the Internet, a LAN, a WAN, a VPN, or other types of packet-switched networks.

[0051] The following discussion provides a number of example embodiments of the inventive subject matter. Although each embodiment represents a single combination of inventive elements, the inventive subject matter is considered to include all possible combinations of the disclosed elements. Thus, if one embodiment includes elements A, B, and C, and a second embodiment includes elements B and D, the inventive subject matter is also considered to include other remaining combinations of A, B, C, or D, even if not explicitly disclosed.

[0052] As used herein, and unless the context dictates otherwise, the term "coupled to" is intended to include both direct coupling (where two elements being coupled to each other are in contact with each other) and indirect coupling (where at least one additional element is located between the two elements). Thus, the terms "coupled to" and "coupled with" are used synonymously.

[0053] Figure 1A and Figure 1BA top view (otherwise referred to as a front view) of an assembled test board system 100 is shown, including a frame 110 and a plurality of main boards 120 disposed thereon according to an embodiment of the present subject matter. Figure 1A The embodiment of FIG. 1 shows a memory channel 123 in the form of a memory component socket 123A that is configured to receive a memory component for testing. Figure 1B The embodiment of FIG. 1 shows a memory channel 123 in the form of a memory module slot 123B that receives a memory module for testing. Figure 1A 、 Figure 1B Each embodiment of Figure 1A-1B In each of the EMBODIMENTS 1 and 2, a CPU 121 (or other processor or computing unit such as an FPGA or ASIC) is shown via dashed lines as being disposed on the underside of the mainboard 120.

[0054] Figure 1C Attached to the frame 110 Figure 1A or Figure 1B For clarity and simplicity in the illustration, the memory channels 123 ( Figure 1A Memory component slot 123A, Figure 1B The memory module slot 123B) is not shown via dashed lines. Figure 1A Memory component slot 123A and Figure 1B The memory module slot 123B may be soldered to the mainboard 120 .

[0055] The main board 120 is attachable to and removable from the frame 110. In a preferred embodiment, the main board 120 is attached to the frame 110 via plastic screws that minimize temperature transfer between the top and bottom sides of the main board 120. Screws made of other types of materials with low heat transfer are also suitable. Other types of suitable attachment methods are also contemplated.

[0056] Without limiting the general applicability of our approach, we further describe the invention by way of an example of a DRAM (Dynamic Random Access Memory) test flow.

[0057] Figure 2An isolated frame 110 is shown. Frame 110 is made of a sturdy material. Suitable materials may include, but are not limited to, metals such as aluminum, or other materials such as carbon composites, fiberglass composites, or other rigid non-metallic materials. Frame 110 includes a space or cavity 111. When motherboard 120 is positioned (e.g., mounted) on the frame, cavity 111 allows underside access to the underside components of motherboard 120. When motherboard 120 is mounted on frame 110, components located on the underside of motherboard 120 (such as CPU 121) will extend into cavity 111.

[0058] Figure 1A-Figure 2 The frame 110 is shown as having six motherboards 120 mounted thereon, but it is contemplated that the frame 110 may have more or fewer motherboards 120 mounted thereon. For example, other configurations are contemplated that may accommodate four to ten motherboards 120.

[0059] Figure 1A-Figure 2 The embodiment shown in FIG is sized to the size of a standard BI board. The reader will appreciate that the system and method of the present invention negate the need for existing large, expensive BI testing systems. However, the use of a standard BI size allows for the use of other aspects of the standard BI process, such as automatic loaders and unloaders for loading and unloading memory components. In addition, software and slot performance analysis can be performed in a manner similar to existing BI systems.

[0060] exist Figure 1A and Figure 1B In the example shown, the top of the motherboard 120 is aligned on the frame 110 so that they touch and the frame 110 is not visible between the motherboards 120. The motherboards 120 are aligned so that the edges touch to form a continuous surface that serves to separate and thermally isolate the top side of the motherboard 120 with the memory channels 123 from the underside of the board with the CPU 121 and other sensitive electronic components.

[0061] The frame 110 includes an electrical connector 124A that is aligned to couple with the electrical connector 124B of the motherboard 120 to provide power to the CPU 121 and other components of the motherboard 120. Figure 1A As seen in FIG, the frame 110 may include an electrical connector 124A to connect with the electrical connectors 124B of all installed motherboards 120 .

[0062] Figure 3A and Figure 3B An embodiment according to the subject matter of the present invention is shown Figure 1A (exist Figure 3A neutral) and Figure 1B (exist Figure 3B ) is an isolated front view of the motherboard 120. Figure 3C Shown Figure 3A、 Figure 3B A back (lower side) view of the main board 120.

[0063] Figure 3A and Figure 3B The motherboard 120 shown in FIG. 1 includes a CPU 121 (shown in dotted lines) electrically connected to a memory component slot 123A ( Figure 3A ) and module slot 123B ( Figure 3B ). The memory component slot 123A is configured to receive a corresponding memory component for testing, and the memory module slot 123B is configured to receive a corresponding memory module containing one or more memory components for testing. Figure 1A-1B and Figure 3A-Figure 3B , the CPU 121 is shown with dotted lines to illustrate that the CPU 121 is located on the opposite side of the main board 120.

[0064] like Figure 3A and Figure 3B As shown, the CPU 121 is arranged on the bottom side (also called the back side) of the motherboard 120 as depicted by the dotted line, while the memory channel 123 (memory component slot 123A and / or module slot 123B) is located on the top side (also called the front side) of the motherboard 120 or near the top side of the motherboard 120.

[0065] This arrangement enables the CPU 121 to be protected from the temperature variations provided by the microclimate chamber when a test memory unit or memory component is inserted into the memory component slot 123A and / or the module slot 123B, respectively. For example, during testing, the temperature surrounding the CPU 121 may differ by at least 5 degrees Celsius from the temperature surrounding the memory channel 123 (and the memory module or memory component connected thereto).

[0066] and Figure 1A to Figure 1B Same, in Figure 3A and Figure 3B In FIG. 1 , the CPU 121 is shown via a dotted line to show that it is located in the motherboard 120 and in the memory component slot 123A ( Figure 3A ) and memory module slot 123B ( Figure 3B On the opposite side. Figure 3C These memory channels 123 are not shown in FIG. 1 via dashed lines to maintain clarity of the figure.

[0067] In an embodiment of the present subject matter, motherboard 120 also includes wireless communication components that include a wireless antenna that is communicatively coupled to CPU 121 and enables CPU 121 to send and receive data to and from external computing devices. The wireless antenna can be integrated into CPU 121, such as in the embodiment shown here, or it can be a separate antenna component. To protect the antenna and other communication components from the temperatures experienced in the test environment, the antenna and other communication components (when separated from CPU 121) are also located on the underside of motherboard 120, opposite memory channel 123. Examples of contemplated wireless data transmission modalities include WiFi, Bluetooth, NFC, etc. In an embodiment of the present subject matter, some or all of the communication functions and / or command functions can be handled by a separate board (such as a Raspberry Pi board) that can issue commands to components on motherboard 120.

[0068] Figure 3D A cross section of the motherboard 120 is shown illustrating the connector 122 running across the width of the motherboard 120 to connect the CPU 121 on the underside of the board with the memory channel 123 (module slot 123B in this example) on the top side of the motherboard 120. Figure 3D The embodiment shown in FIG. 1 shows only module slot 123B, but an embodiment having a memory component socket 123A would be the same, except that component socket 123A replaces module slot 123B.

[0069] exist Figure 1A-1B In each of the illustrated embodiments, the motherboard 120 attached to each frame 110 is shown as being identical. In other embodiments, the motherboard 120 may be different to accommodate a different number of memory cells to be tested, or to allow simultaneous testing of different types of memory cells.

[0070] Figure 1A-1C The test panel system 100 shown in FIG. 1 shows a main panel 120 arranged along a single horizontal plane. In these embodiments, the test panel system 100 (with the main panel 120) has dimensions (including the frame 110) between 30 cm x 30 cm and 2 m x 2 m. In a preferred embodiment, the dimensions are 40 cm x 60 cm, including the frame.

[0071] Figure 4A-4B A top view and a perspective view, respectively, are shown of an embodiment of the inventive subject matter in which the memory channels 123 (module slots 123B in this example) are arranged so that when the memory module is inserted, they are vertically aligned with the motherboard 120 (e.g., the memory channels 123 are oriented perpendicular to the motherboard 120).

[0072] Figure 5A-5B Shown Figure 4A-4B123B. Figure 4A-4B As can be seen in FIG, the memory modules 510 extend vertically from the motherboard 120 (e.g., no more than 15 degrees from vertical). Each memory module 510 may include one or more memory component slots that can receive memory components for testing (e.g., the memory components are connected to the motherboard 120 by the memory module 510). Figure 5B ). denoted by a square on each memory module 510 visible in FIG.

[0073] Figure 6 Pictured Figure 1A 1 , wherein the microclimate chamber 200 is disposed on the upper side or top side of the assembled test board system 100. The microclimate chamber 200 can provide a heated and / or cooled environment for testing memory components attached to the main board 120. The microclimate chamber 200 can have a heat source and / or a cooling source (not shown for clarity) that provides a heated and / or cooled environment for component testing.

[0074] As described above, when the main boards 120 are attached to the frame 110, the edges of the main boards 120 contact each other, thereby forming a continuous or nearly continuous surface without gaps between the main boards 120. This helps to isolate the underside of the main boards 120 from the climate generated by the microclimate chamber 200.

[0075] In the illustrated embodiment, the microclimate chamber 200 is sized to fit over all of the main boards 120 attached to the frame 110. In other embodiments, it is contemplated that the microclimate chamber 200 may be smaller such that it fits over some but not all of the main boards 120. The astute reader will readily recognize that the microclimate chamber 200 negates the need to use large, traditional, expensive BI testing equipment.

[0076] The above embodiments are used to provide a temperature differential between a memory component being tested on a motherboard and a CPU on the same board. However, PCBs can be relatively thin and have layers of metal traces. Therefore, if the memory components on the front side are exposed to very high or low temperatures for an extended period of time, these temperatures will eventually be transferred to the back side, causing damage or excessive thermomechanical stress or water condensation. Thus, it may be desirable to further isolate the CPU and other sensitive electronic components from the excessive temperatures required for testing semiconductor memory components. Therefore, in an embodiment of the present invention, the motherboard further separates the CPU from the memory components being tested by vertically spacing the components from the CPU.

[0077] Figure 7A-7B A side view and a top view, respectively, of a motherboard assembly 710 are shown, in accordance with an embodiment of the inventive subject matter.

[0078] As in Figure 7AAs seen in FIG, the mainboard assembly 710 includes an upper mainboard 711 and a lower mainboard 712 .

[0079] The upper main board 711 includes one or more memory channels 723 . Figure 7A-7B The embodiment includes a memory component socket 723A (which is configured to receive a memory component for testing). However, the general structure of the motherboard assembly 710 applies to the embodiment having a memory module slot 723B (which is configured to receive a memory module for testing), as shown. Figure 9 Thus, for embodiments using module slots 723B, the structure will be similar to Figure 7A-7B The structure shown in FIG is the same, except that the motherboard assembly 710 has a module slot 723B instead of a memory component socket 723A.

[0080] Figure 7A-7B The memory component slot 723A can be used with Figure 1A and Figure 3A The same as the memory component slot 123A, and Figure 9 The memory module slot 723B can be connected to Figure 1B and Figure 3B The same as the memory module slot 123B.

[0081] The lower main board 712 includes a CPU 721 on its underside. The lower main board 712 can be coupled to the upper main board 711 via a support connector 713. The upper and lower main boards 711, 712 are arranged so that the two boards are parallel. In an embodiment, the angle between the upper and lower main boards 711, 712 does not differ by more than 15 degrees.

[0082] In the embodiment of the inventive subject matter shown herein, a gap 715 is present between the upper main board 711 and the lower main board 712. The gap 715 between the upper main board 711 and the lower main board 712 helps to isolate the CPU 721 from the temperature applied to the memory modules and / or memory components being tested. In an embodiment, the width of the gap 715 can be between 1 mm and 100 mm.

[0083] The CPU 721 is connected to the memory component socket 723A and the memory module slot 723B (in Figure 9 In the embodiment of the present invention, the invention is communicatively coupled. Figure 7A As shown, connector 722 connects components of upper main board 711 and lower main board 712 via connection posts 714. Thus, the connector traverses lower main board 712, connection posts 714, and upper main board 711 to connect CPU 721 to memory component socket 723A.

[0084] In an embodiment of the present subject matter, motherboard assembly 710 includes more than one connection post 714. For example, motherboard assembly 710 may have 2-4 connection posts 714.

[0085] Each connection post 714 can carry multiple signals via connector 722. It is contemplated that each connection post 714 can carry 100 to 1000 signals via connector 722.

[0086] In embodiments of the present subject matter, upper main board 711 and lower main board 712 may be connected only via posts 714, and not via support connectors 713. In other embodiments, upper main board 711 and lower main board 712 are connected via support connectors 713, and not via posts 714. In these embodiments, connector 722 is routed via one or more support connectors 713.

[0087] In the embodiment of the inventive subject matter illustrated herein, gap 715 comprises an insulating layer 716 between upper main plate 711 and lower main plate 712 .

[0088] Insulation layer 716 can be air (e.g., ambient air or an enclosure containing air), a vacuum (e.g., an enclosure with a vacuum inside), polystyrene foam, rubber, etc. The insulation layer can be a layer of material (e.g., polystyrene foam) with air or vacuum bubbles. In an embodiment such as that shown here, insulation layer 716 fills at least 70% of gap 715.

[0089] The motherboard assembly 710 can be connected to Figures 1A-6 The motherboard 120 is similar to Figure 2 A plurality of motherboard assemblies 710 can be attached to the frame 110 to test memory modules or memory components.

[0090] When mounted on a frame (such as frame 110), the lower main board 712 can be mounted directly on the frame 110. The insulating layer 716 can be a hard material with air pockets and spacers made of plastic. This can then be screwed together with the upper main board 711 at the top.

[0091] Figure 8 1 and 2 show top and side views of a plurality of motherboard assemblies 710 inserted into the frame 110 to form the assembled test system 800. In this example, the motherboard assembly 710 shown includes only the memory component slot 723A. As described above, Figure 9 Shows top and side views of multiple motherboard assemblies 710 inserted into the frame 110, with only Figure 9 The motherboard assembly has a memory module slot 723B instead of Figure 8 Memory component slot 723A.

[0092] Figure 8 The assembled test system 800 includes six mainboard assemblies 710 inserted into the frame 110 .

[0093] exist Figure 8 In the illustrated embodiment, each motherboard assembly 710 has a CPU 721 connected to two rows of memory component sockets 723A via connection pegs 714. In other embodiments, each motherboard assembly 710 may have more than two rows of memory component sockets 723A for each CPU and may have multiple connection pegs 714.

[0094] For simplicity, Figure 8 and Figure 9 The illustrations do not show the insulating layer 716, but it is contemplated that the assembly may include embodiments that include the insulating layer 716 as described herein.

[0095] With Figures 1A-6 In the same manner as in the embodiment of FIG7- Figure 9 Embodiments may include communication hardware that may include an antenna and other communication components that enable the CPU 721 to exchange data with an external computing device. The antenna may be integrated into the CPU 721 or may be separate from the CPU 721. In embodiments where the antenna is separate from the CPU 721, the antenna is also provided on the lower motherboard 712 to protect it from the test environment.

[0096] and Figures 1A-6 As in the embodiment of the present invention, the motherboard assembly 710 may include a connector configured to connect with a corresponding connector of the frame 110 so that power can be provided to the motherboard assembly 710.

[0097] In an embodiment of the present subject matter, the upper main plate 711 and the lower main plate 712 have the same or substantially the same area (within 10% of the surface area). In other embodiments of the present subject matter, the area of the upper main plate 711 is less than the area of the lower main plate 712, where the difference exceeds 10% of the surface area. In these embodiments, the difference area is protected by an insulating material, such as those discussed herein. Protected by an insulating material means that at least 80% of the difference area is protected by the insulating material.

[0098] Wafer tester

[0099] The wafer test board system 100 can be used to test silicon wafers 980. The test can be a known good die (KGD) test at full production speed. The test is performed by attaching the probe card 900 to the main board 120.

[0100] Figure 10 A probe card 900 is shown connected to the test board system 100 . Figure 11A side view of the test board system 100, the main board 120, the probe card 900, and the wafer 980 is shown. The probe card 900 is connected to the test board system 100 via a high-speed microconnector 930.

[0101] The probe card 900 is thermally isolated from the main board 120 by an air gap and by an insulating foam cover 950 to minimize heat transfer from the heatable electrostatic wafer chuck 970 to the main board 120 during wafer testing. The wafer 980 is attached to the chuck 970 so that it can be heated during testing. It is also contemplated that the chuck 970 can be replaced by a cooling chamber that provides cooling during testing and prevents ice formation. The chuck 970 and the test board system 100 are securely mounted in a frame, while the wafer 980 is movable in the xyz directions so that the probes 955 of the probe card 900 can contact the entire surface of the wafer 980. Typically, a single touchdown is not feasible for testing the entire surface of the wafer 980 due to the large number of probes involved.

[0102] It is contemplated that the probe card 900 may be connected to the mainboard 120 via a single or multiple high-speed microconnectors 930. It is also contemplated that the probe card 900 may be a single probe card or split into multiple smaller probe cards.

[0103] Figure 12 A top view of a separate probe card 900A connected to one of the motherboards 120 is shown. The probe card 900A has multiple probes 955 and a microconnector 960 connected to the motherboard 120. In this case, the probe card 900A is the same size as a single piece of the motherboard 120. However, this makes alignment with the wafer 980 more difficult because the motherboard 120 and the multiple pieces of the probe card 900A must be aligned horizontally very precisely with an accuracy of several microns to exactly align with the contact areas on the wafer 980. In addition, a piece of the motherboard 120 is generally too large to fit six probe cards 900A in the area of a single 300 mm wafer. These problems can be addressed by making a larger probe card that couples to multiple pieces of the motherboard 120.

[0104] Figure 13A top view of a larger probe card 900B is shown. Probe card 900B is sized and dimensioned to cover six pieces on mainboard 120. Probe card 900B combines six probe cards 900A into a single PCB (printed circuit board) so they can be mounted to a single carrier with high precision. Probe card 900B has six microconnectors 960, and each microconnector 960 has its own plurality of probes 955. In addition, the placement of the microconnectors 960 of probe card 900B has been rotated relative to each other to shorten the routing of electrical signals to the test pieces of mainboard 120. This layout also optimizes the placement of probes 955 towards the center area of probe card 900B. The center area of probe card 900B is sized and dimensioned to cover the surface area of wafer 980.

[0105] The probe card 900B is designed to be used with Figure 14B The modified chip layout shown in the main board 120B in FIG. 1 matches the modified chip layout shown in FIG. 1 , where the chips have been changed from Figure 14A 1 has been rotated from its normal orientation as shown in the main board 120A. Main board 120B has the two middle sheets in the middle column that have been rotated so that their microconnectors are placed facing outward, and the two sheets in the right column have been rotated so that their microconnectors are placed facing inward. The two sheets in the left column have their normal orientation with their microconnectors positioned facing inward. The sheet orientation of main board 120B allows probe card 900B to have probes 955 located in its center and also significantly increases signal speed because the microconnectors on the sheet and probe card are positioned closer to each other. At the same time, main board 120B keeps the design of test board system 100 simple because the design of each tester sheet is identical.

[0106] Figure 15 The mainboard 120B is shown in close proximity to the probe card 900B. This side-by-side comparison of their layouts shows how the microconnectors of the mainboard 120B and the microconnectors of the probe card 900B are positioned close to each other when connected (e.g., when the probe card 900B is placed on top of the mainboard 120B), thereby minimizing the length of the electrical connector between the two boards. The surface area of the wafer 980 is also shown on top of the probe card 900B, which shows most of the surface area covered by the probes 955. It should be understood that this arrangement significantly improves the test signal speed and signal integrity. It should also be understood that other arrangements using multiple electrical connectors per tester sheet to further shorten the length of the electrical signal are possible. For simplicity, the accompanying drawings only show a tester sheet with a single electrical connector.

[0107] Precise wafer alignment

[0108] A new method for aligning a wafer to a probe card without optical methods will now be described. The new method comprises a two-step process. In the first step, the wafer will be roughly aligned relative to the probe card and then contacted with the probe card. Electrical structures are provided on the wafer that can be sensed by a portion of the probe card to calculate lateral and operational offsets relative to the ideal position. In the second step, the probe card will be disconnected from the wafer to perform small lateral and rotational corrections for precise alignment. The probe card will then be brought into contact with the wafer again to perform electrical testing of the chips on the wafer.

[0109] exist Figure 16 The principle is shown in FIG. Conductive lines 1001, 1002, 1003 are set on the wafer as conductive alignment marks (e.g., alignment marks). If those lines carry different electrical signals (such as different voltage levels or different signal frequencies), they can be individually identified by the probe. In this example, the conductive lines 1001, 1002, 1003 are different frequencies of 10MHz, 20MHz, and 30MHz. If a row of probes 1004, 1005, 1006 comes into contact with such electrical probe marks, it can determine their position. In this example, when only the top (at position "a") or the bottom (at position "b") of the 20MHz line is touched, the middle probe 1005 senses the 20MHz signal with an accuracy of ±65nm. By sensing the electrical signal on such electrical probe marks made of 90μm wide metal lines with 90μm spacing, the vertical position of the probe can be located by 130μm (window 1007 between position "a" and position "b").

[0110] To improve accuracy, such as Figure 17As shown in , the electrical probe markings can be modified. In this example, an array of several probes 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018 is used to contact the structure. Only one row of probes (e.g., 1010-1012; 1013-1015; 1016-1018) needs to contact the conductive lines 1001, 1002, 1003 to produce a successful reading. This can be achieved by making the structure large enough for absolutely correct placement. With the 20MHz signal picked up by probes 1011, 1014 (needle 1011 slightly touching the 20MHz line), it can be calculated that probe 1011 must be located at the 0μm ± 65nm position (window 1019) and probe 1014 must be somewhere at the 90nm ± 65nm vertical position (window 1020). The overlap of these two regions is now only 40 nm, i.e., we now know that the probe must be at a vertical position of +45 nm ± 20 nm. If the probe moves down 45 nm, it will be centered on the conductive line 1002 with an accuracy of only ± 20 nm. By providing more steps of conductive probe marking and smaller vertical steps, the accuracy can be further increased to any desired value.

[0111] Figure 18 A precise wafer alignment method is shown. The outside of wafer 1080 is not used (3mm edges are excluded during processing), and in fact a 10mm area at the border of the wafer cannot be used due to low yield and partially processed chips. In this position, the proposed electrical probe structure can be installed as shown. Solder joints 1081, 1082, 1083 are electrically supplied with different frequency signals to detect the alignment of the probe card with the wafer. In this example, the vertical displacement between the left conductive alignment mark 1084 and the right conductive alignment mark 1085 is different. For example, if there is a left-right displacement of 30μm, this means that there is a rotational displacement of 0.006 degrees in this case. In order to perfectly align wafer 1080 to the probe card, the wafer must be separated, moved slightly vertically by 90μm toward the bottom, rotated 0.006 degrees clockwise, and then contacted with the probe card again.

[0112] For optimal vertical and horizontal alignment accuracy, electrical probe marks can be placed in all four corners of the wafer rotated 90 degrees relative to each other, such as Figure 19 As shown in FIG. , wafer 1090 has pads 1091 , 1092 , and 1093 powered by signals of different frequencies to detect alignment of the probe card to the wafer using four probe conductive alignment marks 1094 , 1095 , 1096 , and 1097 . In this configuration, x- and y-direction displacements can be sensed with the highest accuracy.

[0113] The electrical probe conductive alignment mark can be as Figure 20A further improvement is shown in . In this embodiment, the electrical probe conductive alignment marks 1200, 1201 are 45 degree straight lines carrying different signal frequencies (10MHz, 20MHz, 30MHz, 40MHz, 50MHz). They are contacted by an array (6 columns, 5 rows) of probes 1202, 1203, which are slightly displaced in rotation (see horizontal lines). The probes that strike and detect the electrical signal are marked with different colors depending on the frequency detected. Since the geometric array of probes is known, it is easy to calculate and average the straight lines passing through the probes carrying signals of different frequencies. Different algorithms can now be used to calculate the rotational displacement. A simple method would be the arithmetic mean of the angles of all measured lines. The more probes there are and the finer the spacing of the metal probe marks, the higher the accuracy can be without limit. Other electrical alignment marks can also be used like traditional cross marks, which are currently commonly used for optical alignment of wafers. This is in Figure 21 . Two metal crosses 1210, 1211 with two different electrical frequencies (10 MHz and 20 MHz) are shown. They are probed with an array of probes 1212 (6 columns, 5 rows) having a repetition factor of a μm. By probing the cross structures, the xy position can be identified with an accuracy of ±a / 2 μm. However, if two or more crosses are placed and the distance d of the metal structures is not a multiple of a, the above measures can be used to improve the position accuracy to any desired value depending on how many cross structures are placed and which distance d is used.

[0114] It should be clear to those skilled in the art that, in addition to those already described, more modifications are possible without departing from the inventive concepts herein. Therefore, the subject matter of the present invention is not limited except in the spirit of the appended claims. In addition, when interpreting both the specification and the claims, all terms should be interpreted in the broadest possible manner consistent with the context. Specifically, the terms "comprises" and "comprising" should be interpreted as representing elements, parts or steps in a non-exclusive manner, indicating that the referenced elements, parts or steps may exist or utilize or be combined with other elements, parts or steps that are not explicitly referenced. Wherein, when the specification claims reference at least one of the groups consisting of A, B, C...N, the text should be interpreted as requiring only one element from the group, rather than A plus N or B plus N, etc.

Claims

1. A chip or wafer comprising: at least two conductive alignment marks configured to contact at least two conductive probes on a probe card; at least two electrical signals capable of being transmitted from the at least two conductive alignment marks to the at least two conductive probes; as well as The at least two electrical signals have different voltage levels or different signal frequencies.

2. The chip or wafer according to claim 1, wherein: The distance between the at least two conductive probes is a or a multiple of a; The at least two conductive alignment marks are shifted by a distance d along the x-direction or the y-direction on the chip or wafer; and Where a is not equal to d.

3. The chip or wafer according to claim 1, wherein: a=90 μm and d=45 μm.

4. The chip or wafer according to claim 1, wherein: The at least two conductive alignment marks include at least two metal lines aligned horizontally or vertically with the rows or arrays of probes.

5. The chip or wafer according to claim 1, wherein: The at least two conductive alignment marks are arranged diagonally relative to the row or array of probes.

6. The chip or wafer according to claim 1, wherein: The at least two conductive alignment marks form an angle between 5 degrees and 85 degrees relative to the row or array of probes.

7. The chip or wafer according to claim 1, wherein: The conductive alignment marks include straight line segments that are vertically displaced relative to each other.

8. The chip or wafer according to claim 1, wherein: The conductive alignment mark includes one or more metal crosses configured to be probed by a probe in an array of at least 3 x 3.

9. The chip or wafer according to claim 1, wherein: The at least two conductive alignment marks are spaced at least 10 mm apart.

10. The chip or wafer according to claim 1, wherein: The at least two electrical signals are used to calculate a rotational deviation of the chip or wafer relative to the probe card.

11. The chip or wafer according to claim 1, wherein: The at least two electrical signals are used to calculate a lateral deviation of the chip or wafer relative to the probe card.

12. A system for probing a chip or wafer, comprising: An electric wafer chuck for mounting a chip or wafer for testing; a probe card having a plurality of probes for receiving a plurality of electrical signals from a plurality of conductive alignment marks on the chip or wafer; as well as A processor and one or more executable software instructions programmed to correct alignment of the wafer chuck relative to the probe card based on the plurality of electrical signals.

13. The system according to claim 12, wherein: The wafer chuck is rotatable separately from the lateral movement of the probe card.

14. The system according to claim 13, wherein: The processor and the one or more executable software instructions are programmed to rotate the motorized wafer chuck and laterally move the probe card based on the plurality of electrical signals.

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