Amorphous silicon film, amorphous silicon gate structure and manufacturing method

Abstract

In order to suppress the recrystallization of amorphous silicon in the subsequent thermal process, the present invention provides an amorphous silicon film, an amorphous silicon gate structure and a manufacturing method; the manufacturing method of the amorphous silicon film comprises: providing a substrate, depositing an amorphous silicon film on the substrate; in the deposition process, the process gas used is 29 The abundance of Si atoms is greater than its natural abundance, and the process gas used is 30 The abundance of Si atoms is greater than their natural abundance, or the process gas used is 29 Si atoms and 30 The abundance of Si atoms is greater than their respective natural abundances.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to an amorphous silicon thin film, an amorphous silicon gate structure, and a manufacturing method. Background Art

[0002] In the HKMG gate-last process, a sacrificial gate typically refers to a silicon gate electrode structure that is formed first and subsequently removed and replaced with a metal gate. Compared to single-crystal or polycrystalline silicon, sacrificial gates are often made of amorphous silicon (also known as amorphous silicon). This is because, in stress memory technology (SMT), the silicon gate plays a role in both stress transfer and stress memory. Since amorphous silicon has the lowest density (favoring stress transfer) and the highest plastic deformation capacity (favoring stress memory), it offers excellent stress transfer and stress memory properties. Furthermore, in the wet gate removal process, the etchant etch rate of amorphous silicon is faster than that of single-crystal and polycrystalline silicon, so choosing amorphous silicon facilitates the complete removal of the sacrificial gate.

[0003] However, after amorphous silicon is formed, its atoms are more likely to rearrange and migrate during subsequent thermal processes driven by thermal energy, making it more susceptible to recrystallization. Once amorphous silicon recrystallizes into polycrystalline silicon, its plastic deformation capacity weakens, affecting the stress transfer of the silicon gate. Furthermore, when removing the sacrificial gate using a wet etching process, the etchant's low etching rate for polycrystalline silicon can easily result in silicon residue, which can affect the performance of semiconductor devices.

[0004] Therefore, it is necessary to suppress the recrystallization of amorphous silicon during the subsequent thermal process as much as possible. Summary of the Invention

[0005] In order to suppress the recrystallization of amorphous silicon during the thermal process of subsequent processes, the present invention provides an amorphous silicon thin film, an amorphous silicon gate structure and a manufacturing method.

[0006] In order to solve the above technical problems, the technical solution of the present invention is:

[0007] The present invention provides a method for manufacturing an amorphous silicon thin film, comprising:

[0008] Providing a substrate, and depositing an amorphous silicon thin film on the substrate;

[0009] During the deposition process, the process gas used 29 The abundance of Si atoms is greater than its natural abundance, and the process gas used is 30 The abundance of Si atoms is greater than their natural abundance, or the process gas used is 29 Si atoms and 30The abundance of Si atoms is greater than their respective natural abundances.

[0010] Furthermore, when the process gas used is 29 When the abundance of Si atoms is greater than its natural abundance, the natural abundance silane and the processed pure 29 Si silane is the process gas;

[0011] When the process gas used 30 When the abundance of Si atoms is greater than its natural abundance, the natural abundance silane and the processed pure 30 Si silane is the process gas;

[0012] When the process gas used 29 Si atoms and 30 When the abundance of Si atoms is greater than their natural abundance, the pure Si atoms obtained by processing with natural abundance silane 29 Si silane and pure 30 Si silane is the process gas.

[0013] Furthermore, the naturally abundant silane can be replaced by silicon chloride or silicon ether made from silicon of natural isotopic ratio.

[0014] Furthermore, when the process gas used is 29 When the abundance of Si atoms is greater than their natural abundance, the pure Si in the process gas 29 The gas volume proportion of Si silane is ≥5%;

[0015] When the process gas used 30 When the abundance of Si atoms is greater than their natural abundance, the pure Si in the process gas 30 The gas volume proportion of Si silane is ≥5%;

[0016] When the process gas used 29 Si atoms and 30 When the abundance of Si atoms is greater than their natural abundance, the pure Si in the process gas 29 Si silane and pure 30 The gas volume proportion of Si silane is ≥5%.

[0017] Furthermore, when the process gas used is 29 When the abundance of Si atoms is greater than their natural abundance, the pure Si in the process gas 29 The gas volume proportion of Si silane is between 5% and 30%;

[0018] When the process gas used 30 When the abundance of Si atoms is greater than their natural abundance, the pure Si in the process gas 30 The gas volume proportion of Si silane is between 5% and 30%;

[0019] When the process gas used 29 Si atoms and 30 When the abundance of Si atoms is greater than their natural abundance, the pure Si in the process gas 29 Si silane and pure 30 The gas volume proportion of Si silane is between 5% and 30%.

[0020] Furthermore, the amorphous silicon thin film is formed by a chemical vapor deposition process.

[0021] Furthermore, the reaction temperature of the chemical vapor deposition process is 500°C to 540°C.

[0022] The present invention provides an amorphous silicon thin film, which is manufactured by adopting the above-mentioned method for preparing the amorphous silicon thin film.

[0023] The present invention also provides a method for manufacturing an amorphous silicon gate structure, comprising:

[0024] Providing a substrate, and sequentially forming a gate oxide layer and a gate dielectric layer on the substrate;

[0025] forming a sacrificial gate layer on the gate dielectric layer;

[0026] forming a hard mask layer on the sacrificial gate layer;

[0027] Sequentially etching the hard mask layer, the sacrificial gate layer, the gate dielectric layer, and the gate oxide layer to form an amorphous silicon gate structure;

[0028] The sacrificial gate layer is manufactured by using the above-mentioned method for manufacturing an amorphous silicon thin film.

[0029] The present invention also provides an amorphous silicon gate structure, which is manufactured using the above-mentioned method for manufacturing the amorphous silicon gate structure.

[0030] The unexpected beneficial effects of the present invention are as follows:

[0031] Since the process gas used in the deposition process contains 29 Si atoms and / or 30 The abundance of Si atoms is greater than their natural abundance, so the deposited amorphous silicon film is doped with more 29 Si atoms and / or 30 Si atoms, these more 29 Si atoms and / or 30Si atoms cause more severe distortion and defects in the amorphous silicon lattice, severely damaging the integrity and periodic structure of the crystal surface, making the damaged crystals less likely to recrystallize during subsequent thermal processes. Furthermore, when this amorphous silicon film is used as a sacrificial gate layer and removed using a wet etching process, the etching rate of the sacrificial gate layer remains close to that of pure amorphous silicon. This reduces silicon residue in the sacrificial gate layer within the same etching time, thereby improving the device's electrical performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic cross-sectional view of a device structure in a method for manufacturing an amorphous silicon thin film according to an embodiment of the present application;

[0033] Figure 2 This is a flow chart of a method for manufacturing an amorphous silicon gate structure according to an embodiment of the present application;

[0034] Figure 3 Schematic diagram of a cross-sectional view of a device structure in a method for manufacturing an amorphous silicon gate structure according to an embodiment of the present application;

[0035] Figure 4 Schematic diagram of a cross-sectional view of a device structure in a method for manufacturing an amorphous silicon gate structure according to an embodiment of the present application;

[0036] Description of reference numerals: 11 - first substrate; 12 - amorphous silicon thin film;

[0037] 21 - second substrate; 22 - gate oxide layer; 23 - gate dielectric layer; 231 - first gate dielectric layer; 232 - second gate dielectric layer; 24 - sacrificial gate layer; 25 - hard mask layer; 251 - first hard mask layer; 252 - second hard mask layer. DETAILED DESCRIPTION

[0038] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0039] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense including "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense including "at least one", unless the content clearly indicates otherwise. The term "at least two" as used in the present invention is generally used in a sense including "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second" and "third" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of the features.

[0040] Because amorphous silicon is in a high-energy state, its free energy is higher than that of its crystalline counterpart. Thermodynamically, a system always tends to transition to a state with lower free energy, that is, from an amorphous state to a crystalline state. Therefore, after formation, amorphous silicon spontaneously reduces its free energy through a recrystallization process, achieving a more stable state. Furthermore, the atomic arrangement in amorphous silicon is disordered. During subsequent thermal processing, when amorphous silicon is thermally excited, the thermal motion of the atoms intensifies, disrupting the original disorder. Localized atomic rearrangements may occasionally resemble a crystalline structure, allowing these regions to serve as crystal nuclei. Under appropriate conditions, such as elevated temperature or metal induction, these nuclei will gradually grow. The larger the nucleus, the smaller its surface energy to volume energy ratio, and the greater the reduction in the system's free energy. Therefore, once a nucleus is formed, it continuously absorbs surrounding amorphous silicon atoms, gradually growing, ultimately leading to recrystallization of the entire amorphous silicon film.

[0041] In order to suppress the recrystallization of amorphous silicon thin films during the subsequent thermal process, refer to Figure 1 An embodiment of the present application provides a method for manufacturing an amorphous silicon thin film, specifically comprising:

[0042] A first substrate 11 is provided, and an amorphous silicon thin film 12 is deposited on the first substrate 11 .

[0043] The first substrate 11 can be any material suitable for forming a semiconductor device, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, a silicon wafer, or other semiconductor materials formed from III / V compounds, including stacked structures composed of these semiconductor materials, or silicon-on-insulator (SOI), stacked silicon-on-insulator (SLSI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). For example, the first substrate 11 is a silicon wafer semiconductor substrate. In other embodiments, the type of first substrate 11 is selected based on the semiconductor device being manufactured. The present invention does not limit the type of semiconductor device. The semiconductor device may be, for example, a field effect transistor (FET), a metal-oxide-semiconductor field-effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS), an insulated gate bipolar transistor (IGBT), a gate turn-off thyristor (GTO), or a thyristor, and one or more of the semiconductor devices.

[0044] During the deposition of the amorphous silicon film 12, the process gas used may be adjusted according to actual needs, for example, 29 The abundance of Si atoms is set to be greater than its natural abundance, or the process gas used is 30 The abundance of Si atoms is set to be greater than its natural abundance, or the process gas used is 29 Si atoms and 30 The abundance of Si atoms is greater than their respective natural abundances.

[0045] 29 Si and 30 It is common knowledge among those skilled in the art that Si can cause lattice defects in crystals. According to studies by Ruf, Kremer, and others, at room temperature, the use of Si with an abundance of more than 99.85% 28 The thermal conductivity of semiconductor components made of Si materials is 10% to 60% higher than that of natural silicon materials. 28 The improvement of thermal conductivity of Si nanowires is more significant (150%). Therefore, it can be seen that in the prior art, those skilled in the art generally hope to improve the thermal conductivity of amorphous silicon thin films. 28 The abundance of Si and the reduction of 29 Si and30 The abundance of Si.

[0046] In this embodiment, when manufacturing the amorphous silicon thin film 12, a technical idea completely opposite to the existing amorphous silicon thin film manufacturing process is adopted, that is, it is expected to improve the manufacturing material of the amorphous silicon thin film 12. 29 Si and / or 30 The abundance of Si. The purpose of adopting this technical idea is to: 29 Si and / or 30 When the abundance of Si is increased, the deposited amorphous silicon film 12 can be doped with more 29 Si atoms and / or 30 Si atoms, doped with these more 29 Si atoms and / or 30 Si atoms will cause more severe distortion and defects in the amorphous silicon lattice, thereby seriously damaging the integrity and periodic structure of the crystal surface, making it more difficult for the damaged crystal to recrystallize during the subsequent thermal process. More specifically, since the recrystallization process of amorphous silicon requires the rearrangement of atoms to form an orderly lattice structure, the distortion and defects in the lattice increase the difficulty of atomic rearrangement to form an ordered state, making it more difficult for amorphous silicon to recrystallize during the subsequent thermal process.

[0047] Furthermore, when the amorphous silicon film 12 is used as a sacrificial gate layer in an amorphous silicon structure, when a wet etching process is used to remove the sacrificial gate layer, the etching rate of the etching solution on the sacrificial gate layer can be maintained at a rate close to that of etching pure amorphous silicon, thereby reducing the silicon residue in the sacrificial gate layer within the same etching time, which helps to improve the conductivity and reliability of the device.

[0048] In addition, due to 28 4. 29 Si and 30 Si has the same chemical properties, so the prepared amorphous silicon film 12 will not affect the normal progress of subsequent dry etching, wet etching, wet cleaning and other processes.

[0049] In this embodiment, when depositing the above-mentioned amorphous silicon thin film 12, for example, a low pressure chemical vapor deposition process (LPCVD) or other methods can be used. 29 Si silane, pure 30 At least one of Si silane and natural abundance silane is used as process gas, more specifically, natural abundance silane and pure 29 Si silane as process gas, or, with natural abundance silane and pure 30 Si silane as process gas, or natural abundance silane, pure 29 Si silane and pure29 Si silane is used as the process gas; of course, according to actual needs, the above-mentioned natural abundance silane can also be replaced with silicon chloride (SiCl4) or silicon ether (C6H 18 OSi2).

[0050] In this embodiment, natural abundance silane refers to silane made from silicon with natural isotopic ratios. 29 Si silane and pure 30 Si silane is produced using existing technologies, such as gas diffusion method, chemical synthesis method, isotope enrichment method and the like.

[0051] Gas diffusion is a common isotope separation method that uses the differences in diffusion rates of different isotopes in a gas to achieve separation. The specific steps of the gas diffusion method are as follows:

[0052] Preparation of natural abundance silane: First, prepare high-purity natural abundance silane, the purity of which should be higher than 99.9%; natural abundance silane is silane (SiH4) that occurs naturally in nature, and contains three isotopes of silicon: silicon-28 ( 28 Si), silicon-29 ( 29 Si) and silicon-30 ( 30 Si). The natural abundances of these three isotopes are: 28 Si accounts for 92.22%, 29 Si accounts for 4.69%, 30 Si accounts for 3.09%;

[0053] Gas Diffusion Cascade: Natural abundance silane is fed into the gas diffusion cascade, and a high-speed magnetically levitated gas compressor is used to compress the silane gas before it enters each gas diffusion separation device;

[0054] Separation process: Through multi-stage gas diffusion separation device, gradually improve 29 Si and 30 The abundance of Si; the total number of gas diffusion cascades is usually 200 to 600, preferably 280 to 300;

[0055] Collect pure isotopes: obtain high abundance from the light end of the gas diffusion cascade 29 Si silane, obtained from the heavy fraction 30 Si silane byproduct.

[0056] Chemical synthesis can produce high-purity 29 Si and 30 Si silane.

[0057] Combined with the above analysis, it can be seen that in the embodiment of the present application, the process gas used in depositing the amorphous silicon film 12 is pure 29 Si silane and / or pure 30 The higher the volume ratio of Si silane gas, the less likely the amorphous silicon film 12 will recrystallize during the subsequent thermal process. 29 Si silane and / or pure 30 The higher the volume ratio of Si silane gas, the higher the production cost of amorphous silicon film 12 will be. 29 When the abundance of Si atoms is greater than their natural abundance, for example, 29 The volume ratio of Si silane gas is set to ≥5%, specifically between 5% and 30%; when the process gas used is 30 When the abundance of Si atoms is greater than its natural abundance, pure 30 The volume ratio of Si silane gas is set to ≥5%, specifically between 5% and 30%; when the process gas used is 29 Si atoms and 30 When the abundance of Si atoms is greater than their natural abundance, pure 29 Si silane and pure 30 The volume ratio of Si-silane gas is set to ≥5%, specifically, for example, between 5% and 30%. In other words, the volume ratio of natural abundance silane, silicon chloride, or silicon ether gas is 95% to 70%, for example, 70%, 80%, 85%, 90%, or 95%.

[0058] In this embodiment, for example, the first substrate 11 is placed in a gas chamber filled with 80% natural abundance silane and 20% pure silane by volume. 29 Si silane reacts in a furnace tube at a pressure of, for example, 2T to 10T and a temperature of, for example, 500°C to 540°C, to deposit and form an amorphous silicon film 12. The thickness of the amorphous silicon film 12 can be adjusted by controlling the heating time. The thickness of the amorphous silicon film 12 is, for example, 500nm to 700nm, specifically 500nm, 600nm, or 700nm. The amorphous silicon film 12 deposited using the LPCVD process exhibits low stress, high density, and uniformity.

[0059] For example, the first substrate 11 is placed in a mixture filled with 90% natural abundance silane and 10% pure 30 In the furnace tube, Si silane reacts at a pressure of, for example, 2T to 10T and a temperature of, for example, 500° C. to 540° C. to form the amorphous silicon thin film 12 .

[0060] The above method for manufacturing an amorphous silicon thin film is as follows: when depositing the amorphous silicon thin film 12, the process gas used is 29 Si atoms and / or 30 The abundance of Si atoms is greater than the natural abundance, and the deposited amorphous silicon film 12 is doped with more 29 Si atoms and / or 30 Si atoms, these more 29 Si atoms and / or 30 Si atoms will cause more serious distortion and defects in the amorphous silicon lattice, seriously damaging the integrity and periodic structure of the crystal surface, making the damaged crystal more difficult to recrystallize in the subsequent thermal process.

[0061] The present invention also provides an amorphous silicon thin film manufactured by the above-mentioned amorphous silicon thin film manufacturing method. Based on the above description, the obtained amorphous silicon thin film is not easily recrystallized during the subsequent thermal process.

[0062] Reference Figure 2 and Figure 3 Another embodiment of the present application provides a method for manufacturing an amorphous silicon gate structure, the method comprising:

[0063] S1, providing a second substrate 21, and sequentially forming a gate oxide layer 22 and a gate dielectric layer 23 on the second substrate 21;

[0064] S2, forming a sacrificial gate layer 24 on the gate dielectric layer 23;

[0065] S3, forming a hard mask layer 25 on the sacrificial gate layer 24;

[0066] S4 , etching the hard mask layer 25 , the sacrificial gate layer 24 , the gate dielectric layer 23 and the gate oxide layer 22 in sequence to form an amorphous silicon gate structure.

[0067] In this embodiment, the gate oxide layer 22 is, for example, silicon oxide (SiO2), and is formed, for example, by an in-situ steam growth method (ISSG). The thickness of the gate oxide layer 22 is, for example, 1 nm to 2 nm, specifically, 1 nm, 1.5 nm, or 2 nm. By forming the gate oxide layer 22, the problem of poor interface quality between the first gate dielectric layer 231 and the second substrate 21 can be improved, thereby improving the performance of the semiconductor device.

[0068] In this embodiment, the gate dielectric layer 23 includes a first gate dielectric layer 231 and a second gate dielectric layer 232 sequentially formed on the gate oxide layer 22 .

[0069] The material of the first gate dielectric layer 231 is, for example, one or more high-k dielectrics such as hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), zirconium oxynitride (ZrON), zirconium oxynitride (ZrSiON), hafnium silicate (HfSiO), hafnium oxynitride (HfSiON), hafnium lanthanum oxynitride (HfLaON), or hafnium aluminum oxide (HfAlO). The first gate dielectric layer 231 can be formed on the second substrate 21 by, for example, atomic layer deposition (ALD), metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), chemical vapor deposition, or physical vapor deposition (PVD). The thickness of the first gate dielectric layer 231 is, for example, 1-3 nm, more specifically, 1 nm, 2 nm, or 3 nm. For example, when an HfOX thin film is deposited using atomic layer deposition (ALD), tetrakis(dimethylamino)hafnium (TDMAHf) gas is used as a precursor, water vapor (H2O) and oxygen (O2) are used as reaction gases, and the temperature is, for example, 200°C-300°C and the pressure is, for example, 1-10 Torr, to deposit HfOX.

[0070] The second gate dielectric layer 232 is, for example, titanium nitride (TiN) or titanium (Ti), and is formed on the first gate dielectric layer 231 using methods such as DC magnetron sputtering or atomic layer deposition (ALD). The thickness of the second gate dielectric layer 232 is, for example, 1-2 nm, more specifically, 1 nm, 1.5 nm, or 2 nm. Specifically, the TiN layer is deposited on the first gate dielectric layer 231 using TiCl4 as a precursor and ammonia (NH3) as a reaction gas at a temperature of, for example, 300°C to 500°C and a pressure of, for example, 1-10 Torr. The provision of the second gate dielectric layer 232 prevents contamination or damage to the first gate dielectric layer 231 during subsequent fabrication processes, thereby improving the performance of the subsequently fabricated metal gate.

[0071] In this embodiment, the sacrificial gate layer 24 is formed on the second gate dielectric layer 232 using a method such as low pressure chemical vapor deposition (LPCVD). 29 Si silane and pure 29 At least one of Si silane and natural abundance silane as process gas; or use pure 29 Si silane and pure 29At least one of Si silane and silicon chloride (SiCl4) as process gas; or pure 29 Si silane and pure 29 At least one of Si silane and silyl ether (C6H 18 OSi2) as the process gas. Specifically, the gas volume ratio is 80% of natural abundance silane and the gas volume ratio is 20% of pure 29 Si silane is used as the process gas, with a pressure of, for example, 2T to 10T and a temperature of, for example, 500°C to 540°C, to deposit a sacrificial gate layer 24 on the second gate dielectric layer 232. The thickness of the sacrificial gate layer 24 can be adjusted by controlling the heating time. The thickness of the sacrificial gate layer 24 is, for example, 500nm to 700nm, specifically 500nm, 600nm, or 700nm.

[0072] When depositing the sacrificial gate layer 24, the process gas used is 29 Si atoms and / or 30 The abundance of Si atoms is greater than their natural abundance, and the deposited sacrificial gate layer 24 is doped with more Si atoms. 29 Si atoms and / or 30 Si atoms, these 29 Si atoms and / or 30 Si atoms will cause more serious distortion and defects in the lattice of amorphous silicon, making the sacrificial gate layer 24 less likely to recrystallize during the thermal process of subsequent processes; therefore, when wet etching is used to remove the sacrificial gate layer 24, the etching rate of the etchant on the sacrificial gate layer 24 can be maintained close to the etching rate of pure amorphous silicon, and the silicon residue in the sacrificial gate layer 24 can be reduced within the same etching time, thereby improving the electrical performance and reliability of the device structure.

[0073] In addition, due to 28 4. 29 Si and 30 Because Si has the same chemical properties, the three isotopes exhibit similar etching characteristics during dry etching, thus not affecting etching uniformity and consistency. Furthermore, during wet etching, their reaction rates and products in the chemical solution are identical. During wet cleaning, their reaction rates and removal efficiency in the cleaning solution are also identical. Therefore, the deposited sacrificial gate layer 24 does not affect subsequent dry etching, wet etching, and wet cleaning processes.

[0074] In this embodiment, two hard mask layers 25 are formed on the sacrificial gate layer 24, namely, a first hard mask layer 251 and a second hard mask layer 252. In other embodiments, only one hard mask layer 25 may be formed on the sacrificial gate layer 24, or more than two hard mask layers 25 may be formed, and the present invention is not limited thereto.

[0075] In this embodiment, the first hard mask layer 251 is, for example, silicon nitride (SiN). The thickness of the first hard mask layer 251 is, for example, 200-400 nm, specifically 200 nm, 300 nm, or 400 nm. The first hard mask layer 251 is formed on the sacrificial gate layer 24 using, for example, chemical vapor deposition (CVD). During the deposition of the first hard mask layer 251, silane (SiH4) is used as a precursor, ammonia (NH3) is used as a reaction gas, and the temperature is, for example, 700°C-800°C, and the pressure is, for example, 0.1-1 Torr, to deposit SiN.

[0076] The second hard mask layer 252 is, for example, silicon oxide (SiO2). The thickness of the second hard mask layer 252 is, for example, between 500 and 1000 nm, specifically, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, or 1000 nm. The second hard mask layer 252 is formed on the first hard mask layer 251 using, for example, chemical vapor deposition (CVD). During the deposition of the second hard mask layer 252, tetraethyl orthosilicate (TEOS) is used as a precursor, oxygen (O2) is used as a reaction gas, and the temperature is set to, for example, 700°C to 800°C and the pressure is set to, for example, 0.1 to 1 Torr, to deposit SiO2.

[0077] By setting two hard mask layers, the second hard mask layer 252 protects the first hard mask layer 251 to prevent the first hard mask layer 251 from being completely etched when the structure is subsequently formed, resulting in the sacrificial gate layer 24 being etched. The second hard mask layer 252 can ensure the height of the sacrificial gate layer 24 in the process before removing the sacrificial gate layer 24, thereby ensuring the height of the metal gate subsequently produced.

[0078] Then, the hard mask layer 25, the sacrificial gate layer 24, the gate dielectric layer 23, and the gate oxide layer 22 are etched using, for example, dry etching, wet etching, or a combination of dry etching and wet etching. When etching the first hard mask layer 251 and the second hard mask layer 252, for example, dry etching is used, using carbon tetrafluoride (CF4) as the etching gas; when etching the sacrificial gate layer 24, for example, dry etching is used, using carbon tetrafluoride (CF4), hydrogen bromide (HBr), and oxygen (O2) as the etching gases. The remaining portion of the sacrificial gate layer 24 after etching serves as the sacrificial gate; when etching the first gate dielectric layer 231 and the second gate dielectric layer 232, for example, dry etching is used, using chlorine (Cl2) and argon (Ar) as the etching gases.

[0079] After etching the first gate dielectric layer 231, the gate oxide layer 22 is wet-etched using an etchant such as hydrofluoric acid to avoid damaging the second substrate 21. The gate oxide layer 22 can isolate residues generated during the etching process and prevent them from diffusing to the surface of the second substrate 21 and affecting subsequent processes.

[0080] After the gate oxide layer 22 is cleaned, the following Figure 4 The amorphous silicon gate structure is shown.

[0081] From the above method, it can be seen that when depositing the sacrificial gate layer 24, the process gas used is 29 Si atoms and / or 30 The abundance of Si atoms is greater than the natural abundance, so that the deposited sacrificial gate layer 24 is doped with more Si atoms. 29 Si atoms and / or 30 Si atoms, these 29 Si atoms and / or 30 Si atoms will cause more serious distortion and defects in the lattice of amorphous silicon, making the sacrificial gate layer 24 less likely to recrystallize during the thermal process of subsequent processes; therefore, when using a wet etching process to remove the sacrificial gate, the etching rate of the etchant on the sacrificial gate can be maintained close to the etching rate of pure amorphous silicon, and the silicon residue on the sacrificial gate can be reduced within the same etching time, thereby improving the electrical performance and reliability of the device.

[0082] In addition, the amorphous silicon gate structure obtained by adopting the above-mentioned manufacturing method of the amorphous silicon gate structure has low density and strong plastic deformation ability, which is beneficial to the stress transfer and memory of the sacrificial gate in the SMT process.

[0083] Furthermore, the high temperature and high electric field experienced during the recrystallization process of amorphous silicon can cause surface bond destruction, such as hydrogen bond breakage. This surface bond destruction can lead to the formation of interface states and increase leakage current paths, thereby causing NBTI (Negative-bias temperature instability) and TDDB (Time-Dependent Dielectric Breakdown) degradation. In the amorphous silicon gate structure of this embodiment, the sacrificial gate layer 24 is manufactured in a manner that inhibits recrystallization during subsequent thermal processes. This reduces the generation of interface states and leakage current paths caused by surface bond breakage, effectively reducing the NBTI effect and extending the TDDB lifetime of the device.

[0084] After the above-mentioned amorphous silicon gate structure is manufactured, sidewall spacers may be further formed on the sidewalls of the gate structure, and other processing steps may be performed to obtain the desired semiconductor device structure.

[0085] An embodiment of the present application also provides an amorphous silicon gate structure manufactured using the above-mentioned amorphous silicon gate structure manufacturing method; based on the above description, the sacrificial gate layer 24 in the above-mentioned amorphous silicon gate structure is not easy to form silicon residue when it is subsequently removed, which can improve the electrical performance of the device structure.

[0086] The above description of the illustrated embodiments of the present invention (including that described in the Abstract) is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. Although specific embodiments of the present invention and examples of the present invention are described herein for illustrative purposes only, as those skilled in the art will recognize and appreciate, various equivalent modifications are possible within the spirit and scope of the present invention. As noted, modifications may be made to the present invention in light of the above description of the illustrated embodiments of the present invention, and such modifications will be within the spirit and scope of the present invention.

[0087] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solutions formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, such as the technical solutions formed by replacing the above features with (but not limited to) technical features with similar functions disclosed in this application. In addition to the technical features described in the specification, the remaining technical features are known technologies to those skilled in the art. In order to highlight the innovative features of the present invention, the remaining technical features will not be repeated here.

Claims

1. A method for manufacturing an amorphous silicon gate structure, characterized in that: include: Providing a substrate, and sequentially forming a gate oxide layer and a gate dielectric layer on the substrate; forming a sacrificial gate layer on the gate dielectric layer; forming a hard mask layer on the sacrificial gate layer; Sequentially etching the hard mask layer, the sacrificial gate layer, the gate dielectric layer, and the gate oxide layer to form an amorphous silicon gate structure; The method for manufacturing the sacrificial gate layer comprises: in the deposition process, the process gas used is 29 The abundance of Si atoms is greater than its natural abundance, and the process gas used is 30 The abundance of Si atoms is greater than their natural abundance, or the process gas used is 29 Si atoms and 30 The abundance of Si atoms is greater than their respective natural abundances.

2. The method for manufacturing an amorphous silicon gate structure according to claim 1, wherein: When the process gas used 29 When the abundance of Si atoms is greater than its natural abundance, the natural abundance silane and the processed pure 29 Si silane is the process gas; When the process gas used 30 When the abundance of Si atoms is greater than its natural abundance, the natural abundance silane and the processed pure 30 Si silane is the process gas; When the process gas used 29 Si atoms and 30 When the abundance of Si atoms is greater than their natural abundance, the pure Si atoms obtained by processing with natural abundance silane 29 Si silane and pure 30 Si silane is the process gas.

3. The method for manufacturing an amorphous silicon gate structure according to claim 2, wherein: The naturally abundant silanes may be replaced with chlorosilanes or silyl ethers made from silicon in natural isotopic ratios.

4. The method for manufacturing an amorphous silicon gate structure according to claim 2, wherein: When the process gas used 29 When the abundance of Si atoms is greater than their natural abundance, the pure Si in the process gas 29 The gas volume proportion of Si silane is ≥5%; When the process gas used 30 When the abundance of Si atoms is greater than their natural abundance, the pure Si in the process gas 30 The gas volume proportion of Si silane is ≥5%; When the process gas used 29 Si atoms and 30 When the abundance of Si atoms is greater than their natural abundance, the pure Si in the process gas 29 Si silane and pure 30 The gas volume proportion of Si silane is ≥5%.

5. The method for manufacturing an amorphous silicon gate structure according to claim 4, wherein: When the process gas used 29 When the abundance of Si atoms is greater than their natural abundance, the pure Si in the process gas 29 The gas volume proportion of Si silane is between 5% and 30%; When the process gas used 30 When the abundance of Si atoms is greater than their natural abundance, the pure Si in the process gas 30 The gas volume proportion of Si silane is between 5% and 30%; When the process gas used 29 Si atoms and 30 When the abundance of Si atoms is greater than their natural abundance, the pure Si in the process gas 29 Si silane and pure 30 The gas volume proportion of Si silane is between 5% and 30%.

6. The method for manufacturing an amorphous silicon gate structure according to claim 1, wherein: The sacrificial gate layer is formed by a chemical vapor deposition process.

7. The method for manufacturing an amorphous silicon gate structure according to claim 6, wherein: The reaction temperature of the chemical vapor deposition process is 500° C. to 540° C.

8. An amorphous silicon gate structure, characterized in that: The amorphous silicon gate structure is manufactured using the manufacturing method of any one of claims 1 to 7.

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