3D hybrid bonding packaging method and product thereof

Abstract

The invention discloses a 3D hybrid bonding packaging method and a product thereof, and the method comprises the following steps: providing at least two chips, carrying out the hybrid bonding of the two chips, obtaining a composite chip structure, and carrying out the hybrid bonding of the composite chip structure with the remaining chips or functional chips. According to the 3D hybrid bonding packaging method provided by the invention, a thought of hybrid bonding in pairs and then bonding with other chips as a whole is adopted, and a multi-layer complex packaging structure is divided into at least two parts which are manufactured respectively and then bonded into a whole, so that complexity is changed into simplicity, the high-temperature baking frequency in a technological process can be reduced, warping can be counteracted mutually, and the packaging quality is improved. The method has the advantages that the final total warping is reduced, the yield and long-term reliability of products are improved, various chips or elements can be integrated, the integration level is improved, the preparation process is simpler and more convenient, and the method has higher popularization and application value.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a 3D hybrid bonding packaging method and a product thereof. Background Art

[0002] As market demands for electronic product performance and size increase, advanced packaging, with its advantages of miniaturization, low cost, and high-density connections, has become a hot topic in the semiconductor packaging field. However, due to the complex structure of advanced packaging and the mismatch in thermal expansion coefficients between different materials, warping can occur, affecting the gripping and adsorption of automated equipment, and even causing cracks and peeling failures. Furthermore, the lengthy process and the need for multiple high-temperature bakes can affect the reliability of the adhesives used, especially temporary bonding adhesives, reducing product yield and long-term reliability. Summary of the Invention

[0003] In order to solve the technical problems existing in the prior art, the purpose of the present invention is to provide a 3D hybrid bonding packaging method and a product thereof.

[0004] In order to achieve the above-mentioned purpose and the above-mentioned technical effect, the technical solution adopted by the present invention is:

[0005] A 3D hybrid bonding packaging method comprises the following steps:

[0006] First, at least two chips are provided, two of the chips are hybrid-bonded to obtain a composite chip structure, and then the composite chip structure is hybrid-bonded with the remaining chips and / or functional chips.

[0007] Furthermore, the present invention discloses a 3D hybrid bonding packaging method comprising the following steps:

[0008] First, three chips are provided, two of the chips are mixed and bonded to obtain a composite chip structure, the composite chip structure is then mixed and bonded with the remaining chip, and finally the functional chip is bonded.

[0009] Furthermore, the 3D hybrid bonding packaging method includes the following steps:

[0010] First, make chip A, chip B, and chip C; then perform hybrid bonding on chip A and chip B; debond the bottom of chip A; perform hybrid bonding on chip A, chip B, and chip C; then debond the bottom of chip C and the top of chip B, make C4 bumps on the bottom of chip C, and bond a functional chip on the top of chip B.

[0011] Furthermore, the steps of manufacturing the chip A include:

[0012] Step 1: Apply temporary bonding glue on the first substrate to form several layers of first metal circuits;

[0013] Step 2: bonding several devices;

[0014] Step 3: Make an insulating layer, and then smooth the surface by mechanical grinding or chemical mechanical polishing;

[0015] Step 4: Make a metal circuit layer to obtain chip A.

[0016] Furthermore, the steps of manufacturing the chip B include:

[0017] Several layers of second metal circuits are prepared on the second substrate to obtain chip B.

[0018] Furthermore, the steps of manufacturing the chip B include:

[0019] Several layers of third metal circuits are prepared on the third substrate to obtain chip C.

[0020] Furthermore, the present invention also discloses a 3D hybrid bonding packaging method, comprising the following steps:

[0021] First, two chips are provided, and then the two chips are hybrid-bonded to obtain a composite chip structure, and then the composite chip structure is hybrid-bonded with a functional chip.

[0022] Furthermore, the functional chip includes a logic chip, a memory chip, an active chip, a routing chip or an IO chip.

[0023] The present invention also discloses a 3D hybrid bonding packaging structure prepared by a 3D hybrid bonding packaging method, comprising chip A, chip B and chip C, wherein the bottom of chip A is bonded to chip C and the top is bonded to chip B, the top of chip B is bonded to a functional chip, and a C4 bump is provided at the bottom of chip C.

[0024] The present invention also discloses a 3D hybrid bonding packaging structure prepared by a 3D hybrid bonding packaging method, comprising a chip B and a chip C, wherein the chip B and the chip C are bonded to meet the following conditions:

[0025] The top of the chip B is bonded to the functional chip, and the bottom of the chip C is provided with a C4 bump;

[0026] Alternatively, the top of the chip C is bonded to the functional chip, and the bottom of the chip B is provided with a C4 bump.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] The present invention discloses a 3D hybrid bonding packaging method and its product. The method adopts the idea of first hybrid bonding two by two and then bonding the whole with other chips. A multi-layer complex packaging structure is disassembled into at least two parts, which are manufactured separately and then bonded into one. This simplifies the process, can reduce the number of high-temperature baking times in the process flow, can achieve mutual offset of warpage, reduce the final total warpage, improve the yield and long-term reliability of the product, and can also integrate multiple chips or components to improve the integration level. The preparation process is simpler and has great promotion and application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a schematic structural diagram of step 1 of Example 1 of the present invention;

[0030] Figure 2 This is a schematic structural diagram of step 2 of Example 1 of the present invention;

[0031] Figure 3 This is a schematic structural diagram of step three of Example 1 of the present invention;

[0032] Figure 4 This is a schematic structural diagram of step 4 of Example 1 of the present invention;

[0033] Figure 5-6 This is a schematic structural diagram of step five of Example 1 of the present invention;

[0034] Figure 7 This is a schematic structural diagram of step six of Example 1 of the present invention;

[0035] Figure 8 This is a schematic structural diagram of step seven of Example 1 of the present invention;

[0036] Figure 9 This is a schematic structural diagram of step eight of embodiment 1 of the present invention;

[0037] Figure 10 This is a schematic structural diagram of step nine of Example 1 of the present invention;

[0038] Figure 11 This is a schematic structural diagram of step 2 of embodiment 2 of the present invention;

[0039] Figure 12 This is a structural diagram of step three of Example 2 of the present invention. DETAILED DESCRIPTION

[0040] The present invention is described in detail below so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more precise definition of the protection scope of the present invention.

[0041] The following is a brief summary of one or more aspects to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all conceivable aspects and is neither intended to identify key or critical elements of all aspects nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that will be provided later.

[0042] like Figure 1-12 As shown, the present invention discloses a 3D hybrid bonding packaging method, comprising the following steps:

[0043] First, at least two chips are provided, and two of the chips are hybrid-bonded to obtain a composite chip structure, and then the composite chip structure is hybrid-bonded with the remaining chips and / or functional chips 12 .

[0044] In some embodiments, the 3D hybrid bonding packaging method of the present invention includes the following steps:

[0045] First, three chips are provided, two of the chips are hybrid-bonded to obtain a composite chip structure, the composite chip structure is hybrid-bonded with the remaining chip, and finally the functional chip 12 is bonded.

[0046] In some more specific embodiments, the 3D hybrid bonding packaging method of the present invention includes the following steps:

[0047] First, make chip A, chip B, and chip C; then perform hybrid bonding on chip A and chip B; debond the bottom of chip A; perform hybrid bonding on chip A, chip B, and chip C; then debond the bottom of chip C and the top of chip B, make C4 bumps 10 on the bottom of chip C, and bond a functional chip 12 on the top of chip B.

[0048] The fabrication steps of chip A include:

[0049] Step 1: Apply temporary bonding glue on the first substrate 1 to form several layers of first metal circuits 2;

[0050] Step 2: bonding several devices 3;

[0051] Step 3: forming an insulating layer 4, and then smoothing the surface by mechanical grinding or chemical mechanical polishing;

[0052] Step 4: Make the metal circuit layer 5 to obtain chip A.

[0053] The fabrication steps of chip B include:

[0054] Several layers of second metal circuits 7 are prepared on the second substrate 6 to obtain a chip B.

[0055] The fabrication steps of chip B include:

[0056] Several layers of third metal circuits 9 are prepared on the third substrate 8 to obtain a chip C.

[0057] The present invention also discloses a 3D hybrid bonding packaging structure prepared by the above-mentioned 3D hybrid bonding packaging method, comprising chip A, chip B and chip C, wherein the bottom of chip A is bonded to chip C and the top is bonded to chip B, the top of chip B is bonded to a functional chip 12, and a C4 bump 10 is provided at the bottom of chip C.

[0058] In some other embodiments, the 3D hybrid bonding packaging method of the present invention includes the following steps:

[0059] First, two chips are provided, and then the two chips are hybrid-bonded to obtain a composite chip structure, and then the composite chip structure is hybrid-bonded with the functional chip 12 .

[0060] The present invention also discloses a 3D hybrid bonding packaging structure prepared by the above-mentioned 3D hybrid bonding packaging method, comprising a chip B and a chip C, wherein the chip B and the chip C are bonded to satisfy:

[0061] The top of chip B is bonded to the functional chip 12, and the bottom of chip C is provided with C4 bumps 10;

[0062] Alternatively, the top of chip C is bonded to the functional chip 12 , and the bottom of chip B is provided with C4 bumps 10 .

[0063] In some embodiments, the functional chip 12 includes but is not limited to: a logic chip, a memory chip, an active network device (PDN), a routing chip (router), and an IO chip.

[0064] Example 1

[0065] like Figure 1-10 As shown, this embodiment discloses a 3D hybrid bonding packaging method, including the following steps:

[0066] Step 1: Figure 1 As shown, conventional temporary bonding glue is coated on the first substrate 1 to form several layers of first metal circuits 2;

[0067] Step 2: Figure 2 As shown, several devices 3 (chips or components) are bonded, wherein the chips include but are not limited to: silicon bridge, active chip PDN, routing chip router, IO chip, and the components include but are not limited to: capacitors, resistors, and inductors;

[0068] Step 3: Figure 3As shown, an insulating layer 4 is formed (by pressing a dry film or coating an insulating material), and then the surface is flattened by mechanical grinding or chemical mechanical polishing. The dry film and insulating material include but are not limited to: PI, ABF, EMC;

[0069] Step 4: Figure 4 As shown, a metal circuit layer 5 is manufactured to obtain a chip A;

[0070] Step 5: Figure 5 As shown, several layers of second metal circuits 7 are prepared on the second substrate 6 to obtain a chip B; Figure 6 As shown, several layers of third metal circuits 9 are prepared on the third substrate 8 to obtain a chip C;

[0071] Step 6: Figure 7 As shown, chip A and chip B are hybrid bonded;

[0072] Step 7: Figure 8 As shown, the bottom of chip A is debonded and the first substrate 1 is removed;

[0073] Step 8: Figure 9 As shown, chip A, chip B and chip C are hybrid bonded;

[0074] Step 9: Figure 10 As shown, the bottom of chip C is first debonded, the third substrate 8 is removed, and C4 bumps 10 are made; then the top of chip B is debonded, the second substrate 6 is removed, micro bumps 11 are made, and functional chips 12 are bonded, wherein the functional chips 12 include but are not limited to: logic chips, memory chips, active network chips (PDNs), routing chips (router), and IO chips.

[0075] This embodiment also discloses a 3D hybrid bonding packaging structure prepared by the 3D hybrid bonding packaging method as described above, including chip A, chip B and chip C, wherein the bottom of chip A is bonded to chip C and the top is bonded to chip B, the top of chip B is bonded to the functional chip 12, and a C4 bump 10 is provided on the bottom of chip C.

[0076] Example 2

[0077] like Figure 5 、 6 As shown in , 11, and 12, this embodiment discloses a 3D hybrid bonding packaging method, including the following steps:

[0078] Step 1: Figure 5 As shown, several layers of second metal circuits 7 are prepared on the second substrate 6 to obtain a chip B; Figure 6 As shown, several layers of third metal circuits 9 are prepared on the third substrate 8 to obtain a chip C;

[0079] Step 2: Figure 11 As shown, chip B and chip C are hybrid bonded;

[0080] Step 3: Figure 12 As shown, the bottom of chip C is debonded, the third substrate 8 is removed, and C4 bumps 10 are made. The top of chip B is debonded, the second substrate 6 is removed, micro bumps 11 are made, and a functional chip 12 is bonded.

[0081] A 3D hybrid bonding packaging structure prepared by a 3D hybrid bonding packaging method includes a chip B and a chip C. Chip B and chip C are bonded to each other and meet the following requirements:

[0082] The top of chip B is bonded to the functional chip 12 , and the bottom of chip C is provided with C4 bumps 10 .

[0083] The rest is the same as Example 1.

[0084] Parts or structures not specifically described in the present invention may adopt existing technologies or existing products and will not be described in detail here.

[0085] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A 3D hybrid bonding packaging method, characterized in that: The following steps are involved: First, at least two chips are provided, two of the chips are hybrid-bonded to obtain a composite chip structure, and then the composite chip structure is hybrid-bonded with the remaining chips and / or functional chips.

2. A 3D hybrid bonding packaging method according to claim 1, characterized in that: The following steps are involved: First, three chips are provided, two of the chips are mixed and bonded to obtain a composite chip structure, the composite chip structure is then mixed and bonded with the remaining chip, and finally the functional chip is bonded.

3. The 3D hybrid bonding packaging method according to claim 2, characterized in that: The following steps are involved: First, make chip A, chip B, and chip C; then perform hybrid bonding on chip A and chip B; debond the bottom of chip A; perform hybrid bonding on chip A, chip B, and chip C; then debond the bottom of chip C and the top of chip B, make C4 bumps on the bottom of chip C, and bond a functional chip on the top of chip B.

4. The 3D hybrid bonding packaging method according to claim 3, characterized in that: The steps of manufacturing the chip A include: Step 1: Apply temporary bonding glue on the first substrate to form several layers of first metal circuits; Step 2: bonding several devices; Step 3: Make an insulating layer, and then smooth the surface by mechanical grinding or chemical mechanical polishing; Step 4: Make a metal circuit layer to obtain chip A.

5. The 3D hybrid bonding packaging method according to claim 3, characterized in that: The steps of making the chip B include: Several layers of second metal circuits are prepared on the second substrate to obtain chip B.

6. The 3D hybrid bonding packaging method according to claim 3, characterized in that: The steps of making the chip B include: Several layers of third metal circuits are prepared on the third substrate to obtain chip C.

7. The 3D hybrid bonding packaging method according to claim 1, characterized in that: The following steps are involved: First, two chips are provided, and then the two chips are hybrid-bonded to obtain a composite chip structure, and then the composite chip structure is hybrid-bonded with a functional chip.

8. The 3D hybrid bonding packaging method according to claim 1, characterized in that: The functional chip includes a logic chip, a memory chip, an active chip, a routing chip or an IO chip.

9. The 3D hybrid bonding packaging structure prepared by the 3D hybrid bonding packaging method according to any one of claims 1 to 6, characterized in that: The 3D hybrid bonding packaging structure includes chip A, chip B and chip C. The bottom of chip A is bonded to chip C and the top is bonded to chip B. The top of chip B is bonded to the functional chip, and a C4 bump is provided at the bottom of chip C.

10. The 3D hybrid bonding packaging structure prepared by the 3D hybrid bonding packaging method according to claim 1 or 7, characterized in that: The 3D hybrid bonding package structure includes a chip B and a chip C, wherein the chip B and the chip C are bonded to each other and meet the following requirements: The top of the chip B is bonded to the functional chip, and the bottom of the chip C is provided with a C4 bump; Alternatively, the top of the chip C is bonded to the functional chip, and the bottom of the chip B is provided with a C4 bump.

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