Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, the semiconductor structure comprises a semiconductor substrate, the semiconductor substrate comprises a well region, and the well region comprises a first region, a second region and a third region; the first fin, the second fin and the third fin are respectively positioned in the well regions of the first region, the second region and the third region; the first source-drain region, the second source-drain region and the third source-drain region are respectively positioned in the well regions at the two sides of the first fin, the second fin and the third fin; the insulating isolation layer is positioned on the surfaces of the first source-drain region and the second source-drain region; the gate layer is positioned on the side walls of the first fin and the second fin and the surface of the insulating isolation layer; and the interlayer dielectric layer is positioned on the surface of the well region and covers the well region, and the top surface of the interlayer dielectric layer is flush with the top surfaces of the first fin, the second fin and the third fin. According to the invention, the contact area of the emitting electrode and the base electrode of the BJT can be increased, and the amplification performance of the BJT is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] The increased integration density of integrated circuits has benefited from the scaling of underlying field-effect transistors. However, with the recent advancement of process nodes, lateral fin field-effect transistors (FinFETs) have been unable to meet the requirements of processes below 5nm. The new generation of vertical gate-all-around field-effect transistors (VFETs) overcomes the limitations of lateral gate spacing and can meet sub-5nm process requirements, making them an ideal alternative to lateral FinFETs.

[0003] Because the VFET's channel is no longer parallel to the wafer surface, the formation of other components integrated with the VFET differs significantly from traditional methods, sometimes even requiring the development of additional process steps, which increases process difficulty and cost. For example, there is currently no suitable process for integrating a VFET with a bipolar junction transistor (BJT). Summary of the Invention

[0004] The present application provides a semiconductor structure and a method for forming the same, which integrates a BJT structure with a VFET structure, thereby increasing the contact area between the BJT emitter and the base and improving the amplification performance of the BJT.

[0005] One aspect of the present application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, the semiconductor substrate including a well region, the well region including a first region, a second region and a third region; etching the well regions of the first region, the second region and the third region to form a first fin, a second fin and a third fin, respectively, wherein the width of the third fin is greater than the width of the first fin; forming a first source-drain region, a second source-drain region and a third source-drain region in the well regions on both sides of the first fin, the second fin and the third fin, respectively, wherein the doping type of the second source-drain region is opposite to the doping type of the third source-drain region; forming an insulating isolation layer on the surfaces of the first source-drain region and the second source-drain region, and forming a gate layer on the sidewalls of the first fin and the second fin and on the surface of the insulating isolation layer; forming an interlayer dielectric layer covering the well region on the surface of the well region, wherein the top surface of the interlayer dielectric layer is flush with the top surfaces of the first fin, the second fin and the third fin; and forming a first epitaxial layer, a second epitaxial layer and a third epitaxial layer on the top surfaces of the first fin, the second fin and the third fin, respectively.

[0006] In some embodiments of the present application, the well regions of the second region and the third region further include a channel doping region, and the second fin and the third fin are formed by etching the channel doping region.

[0007] In some embodiments of the present application, the doping type of the channel doping region is opposite to the doping type of the well region.

[0008] In some embodiments of the present application, the doping type of the second source and drain regions is the same as the doping type of the well region.

[0009] In some embodiments of the present application, the method for forming the semiconductor structure further includes: forming an isolation structure for isolating the first region, the second region, and the third region in a well region between the first region, the second region, and the third region.

[0010] In some embodiments of the present application, the doping type of the first epitaxial layer and the second epitaxial layer is the same as the doping type of the well region.

[0011] Another aspect of the present application also provides a semiconductor structure, including: a semiconductor substrate, the semiconductor substrate including a well region, the well region including a first region, a second region and a third region; a first fin, a second fin and a third fin respectively located in the well regions of the first region, the second region and the third region, the width of the third fin being greater than the width of the first fin; a first source / drain region, a second source / drain region and a third source / drain region respectively located in the well regions on both sides of the first fin, the second fin and the third fin, the doping type of the second source / drain region being opposite to the doping type of the third source / drain region; an insulating isolation layer located on the surfaces of the first source / drain region and the second source / drain region, and a gate layer located on the sidewalls of the first fin and the second fin and on the surface of the insulating isolation layer; an interlayer dielectric layer located on the surface of the well region and covering the well region, the top surface of the interlayer dielectric layer being flush with the top surfaces of the first fin, the second fin and the third fin; a first epitaxial layer, a second epitaxial layer and a third epitaxial layer respectively located on the top surfaces of the first fin, the second fin and the third fin.

[0012] In some embodiments of the present application, the well regions of the second region and the third region further include a channel doping region, and the second fin and the third fin are formed by etching the channel doping region.

[0013] In some embodiments of the present application, the doping type of the channel doping region is opposite to the doping type of the well region.

[0014] In some embodiments of the present application, the doping type of the second source and drain regions is the same as the doping type of the well region.

[0015] In some embodiments of the present application, the semiconductor structure further includes: an isolation structure located in a well region between the first region, the second region, and the third region for isolating the first region, the second region, and the third region.

[0016] In some embodiments of the present application, the doping type of the first epitaxial layer and the second epitaxial layer is the same as the doping type of the well region.

[0017] The present application provides a semiconductor structure and a method for forming the same, which integrates a BJT structure with a VFET structure, thereby increasing the contact area between the BJT emitter and the base and improving the amplification performance of the BJT. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The following figures describe in detail exemplary embodiments disclosed in this application. Like reference numerals denote similar structures throughout the several views of the drawings. Those skilled in the art will appreciate that these embodiments are non-limiting, exemplary embodiments, and that the drawings are provided for illustration and description purposes only and are not intended to limit the scope of this application. Other embodiments may also achieve the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0019] in:

[0020] Figures 1 to 8 Schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application. DETAILED DESCRIPTION

[0021] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content of this application. Various local modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but is intended to be of the widest scope consistent with the claims.

[0022] The technical solution of the present invention is described in detail below with reference to the embodiments and drawings.

[0023] Figures 1 to 8 The following is a structural diagram of each step in the method for forming a semiconductor structure according to an embodiment of the present application. The method for forming a semiconductor structure according to an embodiment of the present application is described in detail with reference to the accompanying drawings.

[0024] refer to Figure 1 As shown, a semiconductor substrate 100 is provided. The semiconductor substrate 100 includes a well region 110 . The well region 110 includes a first region 101 , a second region 102 , and a third region 103 .

[0025] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.

[0026] In some embodiments of the present application, the well region 110 is formed by performing an ion implantation process in the semiconductor substrate 100. The doping type of the well region 110 is set according to device requirements and can be P-type or N-type. This application uses the well region 110 as an example of being P-type doped.

[0027] The semiconductor structure described in this application is a structure that integrates a vertical gate-all-around field-effect transistor (VFET) and a bipolar junction transistor (BJT). The first region 101 is used to form a VFET structure, and the second region 102 and the third region 103 are used to form a BJT structure.

[0028] In some embodiments of the present application, the well regions 110 of the second region 102 and the third region 103 further include a channel doping region 111. The channel doping region 111 and the portion of the well region 110 that is horizontally flush with the channel doping region 111 serve as a channel layer. The channel layer 110 may be formed by an ion implantation process in the well region 110 or by an in-situ doping epitaxial growth process on the surface of the well region 110.

[0029] In some embodiments of the present application, the doping type of the channel doping region 111 is opposite to the doping type of the well region 110 , for example, N-type.

[0030] In some embodiments of the present application, the surface of the well region 110 further includes a hard mask layer 120 . The material of the hard mask layer 120 includes silicon nitride. The hard mask layer 120 serves as a mask for subsequent etching of the well region 110 .

[0031] refer to Figure 2 As shown, the well regions 110 of the first region 101 , the second region 102 and the third region 103 are etched using the hard mask layer 120 as a mask to form a first fin 131 , a second fin 132 and a third fin 133 , respectively. The width of the third fin 133 is greater than that of the first fin 131 .

[0032] The semiconductor structure of the present application is a structure that integrates a vertical gate-all-around field-effect transistor (VFET) with a bipolar junction transistor (BJT). Therefore, the first region 101 is used to form a conventional VFET structure. The size of the first fin 131 is also the same as the fin size set in a conventional VFET structure. In some embodiments of the present application, unless otherwise specified, the VFET structure and formation process in the first region 101 are the same as those of a conventional VFET structure.

[0033] In some embodiments of the present application, the width of the second fin 132 is equal to the width of the first fin 131 .

[0034] Since the second region 102 and the third region 103 are used to form a BJT structure, the width of the third fin 133 of the third region 103 is not the same as the fin width of a conventional VFET, but is set according to the requirements of the BJT structure.

[0035] In some embodiments of the present application, the heights of the first fin 131 , the second fin 132 , and the third fin 133 are the same as the depth of the channel doping region 111 .

[0036] refer to Figure 3 As shown, a first source / drain region 141, a second source / drain region 142, and a third source / drain region 143 are respectively formed in the well region 110 on both sides of the first fin 131, the second fin 132, and the third fin 133. The doping type of the second source / drain region 142 is opposite to the doping type of the third source / drain region 143. Depending on the device requirements, the first source / drain region 141 serves as the source or drain of the VFET structure.

[0037] In some embodiments of the present application, the method of forming the first source and drain region 141 , the second source and drain region 142 , and the third source and drain region 143 is an ion implantation process.

[0038] In some embodiments of the present application, the doping type of the first source / drain region 141 is opposite to the doping type of the well region 110, for example, N-type. The doping type of the second source / drain region 142 is the same as the doping type of the well region 110, for example, P-type. The doping type of the third source / drain region 143 is opposite to the doping type of the well region 110, for example, N-type.

[0039] refer to Figure 4 As shown, an isolation structure 150 is formed in the well region 110 between the first region 101 , the second region 102 and the third region 103 to isolate the first region 101 , the second region 102 and the third region 103 .

[0040] In some embodiments of the present application, the material of the isolation structure 150 includes silicon oxide.

[0041] refer to Figure 5 As shown, an insulating isolation layer 160 is formed on the surfaces of the first source / drain region 141 and the second source / drain region 142 , and a gate layer 170 is formed on the sidewalls of the first fin 131 and the second fin 132 and on the surface of the insulating isolation layer 160 .

[0042] In some embodiments of the present application, it is possible to freely choose whether to simultaneously form the corresponding insulating isolation layer 160 and the gate layer 170 on the sidewalls of the third fin 133 in the third region 103 according to the actual process simplification requirements. In other words, the corresponding insulating isolation layer 160 and the gate layer 170 can also be simultaneously formed on the sidewalls of the third fin 133 in the third region 103.

[0043] In some embodiments of the present application, the insulating isolation layer 160 is made of silicon oxide. The gate layer 170 is made of polysilicon.

[0044] refer to Figure 6 and Figure 7 As shown, an interlayer dielectric layer 180 covering the well region 110 is formed on the surface of the well region 110 , and a top surface of the interlayer dielectric layer 180 is flush with top surfaces of the first fin 131 , the second fin 132 and the third fin 133 .

[0045] Specifically, refer to Figure 6 As shown, an interlayer dielectric layer 180 is first formed with a top surface flush with the surface of the hard mask layer 120; then, referring to Figure 7 As shown, a chemical mechanical polishing process is used to polish the interlayer dielectric layer 180 and the hard mask layer 120 to the top surfaces of the first fin 131, the second fin 132 and the third fin 133, remove the hard mask layer 120 and make the top surface of the interlayer dielectric layer 180 flush with the top surfaces of the first fin 131, the second fin 132 and the third fin 133.

[0046] In some embodiments of the present application, the material of the interlayer dielectric layer 180 includes silicon oxide.

[0047] refer to Figure 8 As shown, a first epitaxial layer 191 , a second epitaxial layer 192 and a third epitaxial layer 193 are formed on the top surfaces of the first fin 131 , the second fin 132 and the third fin 133 , respectively.

[0048] In some embodiments of the present application, in-situ doping ions may be present in the first epitaxial layer 191 , the second epitaxial layer 192 , and the third epitaxial layer 193 . The doping type of the first epitaxial layer 191 and the second epitaxial layer 192 is the same as the doping type of the well region 110 .

[0049] In some embodiments of the present application, the doping type of the first epitaxial layer 191 is opposite to the doping type of the well region 110, for example, N-type. The doping type of the second epitaxial layer 192 is the same as the doping type of the well region 110, for example, P-type. The doping type of the third epitaxial layer 193 is the same as the doping type of the well region 110, for example, P-type.

[0050] In some embodiments of the present application, the doping concentrations of the first epitaxial layer 191 , the second epitaxial layer 192 , and the third epitaxial layer 193 are greater than the doping concentration of the well region 110 .

[0051] In some embodiments of the present application, the method of forming the first epitaxial layer 191, the second epitaxial layer 192, and the third epitaxial layer 193 includes an epitaxial growth process or an in-situ doping epitaxial growth process. In some embodiments of the present application, moderate over-epitaxial growth can be performed so that the first epitaxial layer 191 and the second epitaxial layer 192 in the first region 101 and the second region 102 extend to cover the gate layer 170.

[0052] The technical solution of the present application provides a method for forming a semiconductor structure that integrates a vertical gate-all-around field-effect transistor (VFET) with a bipolar junction transistor (BJT). The first region 101 is used to form a VFET structure, the first fin 131 serves as a channel, the first source / drain region 141 serves as a source or drain, and the first epitaxial layer 191 serves as the corresponding drain or source. The second region 102 and the third region 103 are used to form a BJT structure, the third source / drain region 143 serves as a base, the second source / drain region 142 serves as a collector, and the third epitaxial layer 193 serves as a collector.

[0053] The technical solution of the present application utilizes the vertical channel structure of the VFET so that the upper source / drain end (the third epitaxial layer 193) serves as an electrode (collector) at one end of the bipolar transistor. By adjusting the size of the fin (the width of the third fin 133), the contact area between different electrodes of the bipolar transistor can be changed.

[0054] The technical solution of the present application is compatible with the process of vertical field-effect transistors, and can also increase the contact area between the base and the emitter, improve the injection efficiency, and increase the amplification factor of the bipolar transistor.

[0055] The present application provides a method for forming a semiconductor structure, which integrates a BJT structure with a VFET structure, thereby increasing the contact area between the BJT emitter and the base and improving the amplification performance of the BJT.

[0056] This application also provides a semiconductor structure, referring to Figure 8As shown, the present invention comprises: a semiconductor substrate 100, the semiconductor substrate 100 includes a well region 110, the well region 110 includes a first region 101, a second region 102 and a third region 103; a first fin 131, a second fin 132 and a third fin 133 respectively located in the well region 110 of the first region 101, the second region 102 and the third region 103, wherein the width of the third fin 133 is greater than the width of the first fin 131; a first source / drain region 141, a second source / drain region 142 and a third source / drain region 143 respectively located in the well region 110 on both sides of the first fin 131, the second fin 132 and the third fin 133, wherein the doping of the second source / drain region 142 is greater than the doping of the first fin 131. The doping type is opposite to the doping type of the third source and drain region 143; the insulating isolation layer 160 located on the surface of the first source and drain region 141 and the second source and drain region 142, and the gate layer 170 located on the side walls of the first fin 131 and the second fin 132 and the surface of the insulating isolation layer 160; the interlayer dielectric layer 180 located on the surface of the well region 110 and covering the well region 110, the top surface of the interlayer dielectric layer 180 is flush with the top surfaces of the first fin 131, the second fin 132 and the third fin 133; the first epitaxial layer 191, the second epitaxial layer 192 and the third epitaxial layer 193 located on the top surfaces of the first fin 131, the second fin 132 and the third fin 133 respectively.

[0057] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.

[0058] In some embodiments of the present application, the doping type of the well region 110 is set according to device requirements and can be P-type or N-type. The present application uses the well region 110 as a P-type doping example.

[0059] The semiconductor structure described in this application is a structure that integrates a vertical gate-all-around field-effect transistor (VFET) and a bipolar junction transistor (BJT). The first region 101 is used to form a VFET structure, and the second region 102 and the third region 103 are used to form a BJT structure.

[0060] In some embodiments of the present application, the well regions 110 of the second region 102 and the third region 103 further include a channel doping region 111. The channel doping region 111 and the portion of the well region 110 that is horizontally flush with the channel doping region 111 serve as a channel layer. The second fin 132 and the third fin 133 are formed by etching the channel doping region 111.

[0061] In some embodiments of the present application, the doping type of the channel doping region 111 is opposite to the doping type of the well region 110 , for example, N-type.

[0062] The semiconductor structure of the present application is a structure that integrates a vertical gate-all-around field-effect transistor (VFET) with a bipolar junction transistor (BJT). Therefore, the first region 101 is used to form a conventional VFET structure. The size of the first fin 131 is also the same as the fin size set in a conventional VFET structure. In some embodiments of the present application, unless otherwise specified, the VFET structure in the first region 101 is the same as a conventional VFET structure.

[0063] In some embodiments of the present application, the width of the second fin 132 is equal to the width of the first fin 131 .

[0064] Since the second region 102 and the third region 103 are used to form a BJT structure, the width of the third fin 133 of the third region 103 is not the same as the fin width of a conventional VFET, but is set according to the requirements of the BJT structure.

[0065] In some embodiments of the present application, the heights of the first fin 131 , the second fin 132 , and the third fin 133 are the same as the depth of the channel doping region 111 .

[0066] In some embodiments of the present application, the doping type of the first source / drain region 141 is opposite to the doping type of the well region 110, for example, N-type. The doping type of the second source / drain region 142 is the same as the doping type of the well region 110, for example, P-type. The doping type of the third source / drain region 143 is opposite to the doping type of the well region 110, for example, N-type.

[0067] Continue to refer Figure 8 As shown, an isolation structure 150 is formed in the well region 110 between the first region 101 , the second region 102 and the third region 103 to isolate the first region 101 , the second region 102 and the third region 103 .

[0068] In some embodiments of the present application, the material of the isolation structure 150 includes silicon oxide.

[0069] In some embodiments of the present application, it is possible to freely choose whether to simultaneously form the corresponding insulating isolation layer 160 and the gate layer 170 on the sidewalls of the third fin 133 in the third region 103 according to the actual process simplification requirements. In other words, the corresponding insulating isolation layer 160 and the gate layer 170 can also be simultaneously formed on the sidewalls of the third fin 133 in the third region 103.

[0070] In some embodiments of the present application, the insulating isolation layer 160 is made of silicon oxide. The gate layer 170 is made of polysilicon.

[0071] In some embodiments of the present application, the material of the interlayer dielectric layer 180 includes silicon oxide.

[0072] In some embodiments of the present application, in-situ doping ions may be present in the first epitaxial layer 191 , the second epitaxial layer 192 , and the third epitaxial layer 193 . The doping type of the first epitaxial layer 191 and the second epitaxial layer 192 is the same as the doping type of the well region 110 .

[0073] In some embodiments of the present application, the doping type of the first epitaxial layer 191 is opposite to the doping type of the well region 110, for example, N-type. The doping type of the second epitaxial layer 192 is the same as the doping type of the well region 110, for example, P-type. The doping type of the third epitaxial layer 193 is the same as the doping type of the well region 110, for example, P-type.

[0074] In some embodiments of the present application, the doping concentrations of the first epitaxial layer 191 , the second epitaxial layer 192 , and the third epitaxial layer 193 are greater than the doping concentration of the well region 110 .

[0075] In some embodiments of the present application, the first epitaxial layer 191 and the second epitaxial layer 192 in the first region 101 and the second region 102 extend to cover the gate layer 170 .

[0076] The technical solution of the present application provides a semiconductor structure that integrates a vertical gate-all-around field-effect transistor (VFET) with a bipolar junction transistor (BJT). The first region 101 is used to form a VFET structure, the first fin 131 serves as a channel, the first source / drain region 141 serves as a source or drain, and the first epitaxial layer 191 serves as the corresponding drain or source. The second region 102 and the third region 103 are used to form a BJT structure, the third source / drain region 143 serves as a base, the second source / drain region 142 serves as a collector, and the third epitaxial layer 193 serves as a collector.

[0077] The technical solution of the present application utilizes the vertical channel structure of the VFET so that the upper source / drain end (the third epitaxial layer 193) serves as an electrode (collector) at one end of the bipolar transistor. By adjusting the size of the fin (the width of the third fin 133), the contact area between different electrodes of the bipolar transistor can be changed.

[0078] The technical solution of the present application is compatible with the process of vertical field-effect transistors, and can also increase the contact area between the base and the emitter, improve the injection efficiency, and increase the amplification factor of the bipolar transistor.

[0079] The present application provides a semiconductor structure and a method for forming the same, which integrates a BJT structure with a VFET structure, thereby increasing the contact area between the BJT emitter and the base and improving the amplification performance of the BJT.

[0080] In summary, after reading the contents of this application, those skilled in the art will understand that the foregoing contents are presented by way of example only and are not intended to be limiting. Although not expressly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0081] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may also be present.

[0082] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In contrast, the term "directly" indicates that there are no intervening elements. It should also be understood that the terms "comprising," "including," "include," or "comprising," when used in this specification, indicate the presence of recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0083] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present application, the first element in some embodiments may be referred to as the second element in other embodiments. The same reference numerals or the same reference designators represent the same elements throughout the specification.

[0084] In addition, this specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a semiconductor substrate, the semiconductor substrate comprising a well region, the well region comprising a first region, a second region, and a third region; Etching the well regions of the first region, the second region, and the third region to form a first fin, a second fin, and a third fin, respectively, wherein the width of the third fin is greater than the width of the first fin; forming a first source-drain region, a second source-drain region, and a third source-drain region in the well regions on both sides of the first fin, the second fin, and the third fin, respectively, wherein the doping type of the second source-drain region is opposite to the doping type of the third source-drain region; forming an insulating isolation layer on surfaces of the first source / drain region and the second source / drain region, and forming a gate layer on sidewalls of the first fin and the second fin and on surfaces of the insulating isolation layer; forming an interlayer dielectric layer covering the well region on a surface of the well region, wherein a top surface of the interlayer dielectric layer is flush with top surfaces of the first fin, the second fin, and the third fin; A first epitaxial layer, a second epitaxial layer and a third epitaxial layer are formed on top surfaces of the first fin, the second fin and the third fin, respectively.

2. The method for forming a semiconductor structure according to claim 1, wherein: The well regions of the second region and the third region further include channel doping regions, and the second fin and the third fin are formed by etching the channel doping regions.

3. The method for forming a semiconductor structure according to claim 2, wherein: The doping type of the channel doping region is opposite to the doping type of the well region.

4. The method for forming a semiconductor structure according to claim 1, wherein: The doping type of the second source and drain regions is the same as the doping type of the well region.

5. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: An isolation structure is formed in a well region between the first region, the second region, and the third region to isolate the first region, the second region, and the third region.

6. The method for forming a semiconductor structure according to claim 1, wherein: The doping type of the first epitaxial layer and the second epitaxial layer is the same as the doping type of the well region.

7. A semiconductor structure, characterized in that include: a semiconductor substrate comprising a well region, wherein the well region comprises a first region, a second region, and a third region; a first fin, a second fin, and a third fin respectively located in the well regions of the first region, the second region, and the third region, wherein the width of the third fin is greater than the width of the first fin; a first source / drain region, a second source / drain region, and a third source / drain region in the well regions on both sides of the first fin, the second fin, and the third fin, respectively, wherein the doping type of the second source / drain region is opposite to the doping type of the third source / drain region; an insulating isolation layer located on surfaces of the first source / drain region and the second source / drain region, and a gate layer located on sidewalls of the first fin and the second fin and on a surface of the insulating isolation layer; an interlayer dielectric layer located on the surface of the well region and covering the well region, wherein a top surface of the interlayer dielectric layer is flush with top surfaces of the first fin, the second fin, and the third fin; A first epitaxial layer, a second epitaxial layer and a third epitaxial layer are respectively located on top surfaces of the first fin, the second fin and the third fin.

8. The semiconductor structure according to claim 7, wherein: The well regions of the second region and the third region further include channel doping regions, and the second fin and the third fin are formed by etching the channel doping regions.

9. The semiconductor structure according to claim 8, wherein: The doping type of the channel doping region is opposite to the doping type of the well region.

10. The semiconductor structure according to claim 7, wherein: The doping type of the second source and drain regions is the same as the doping type of the well region.

11. The semiconductor structure according to claim 7, wherein: Also includes: An isolation structure is located in a well region between the first region, the second region and the third region and isolates the first region, the second region and the third region.

12. The semiconductor structure according to claim 7, wherein: The doping type of the first epitaxial layer and the second epitaxial layer is the same as the doping type of the well region.

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