Semiconductor structure, manufacturing method thereof and memory system

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof and a storage system. The semiconductor structure includes: a substrate; a semiconductor device located on the substrate; the passivation layer is located on the side, away from the substrate, of the semiconductor device and extends in the first direction; and the sealing ring is located on the substrate, surrounds the semiconductor device and comprises a plurality of conductive layers which are sequentially stacked to be in contact with the passivation layer in the second direction, at least two adjacent conductive layers close to the passivation layer are made of the same material, and the second direction intersects with the first direction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, a method for manufacturing the semiconductor structure, and a storage system. Background Art

[0002] During the semiconductor fabrication process, multiple semiconductor structures are typically fabricated simultaneously on a single wafer. The semiconductor structures are then separated from the wafer, packaged, and used in integrated circuits.

[0003] When designing device layouts in semiconductor structures, a seal ring (SR) is typically placed around the device area of the semiconductor structure. The seal ring maintains a certain distance from the semiconductor device to effectively isolate the edge of the semiconductor device, thereby reducing mechanical damage to the device during the sawing process and moisture intrusion. Summary of the Invention

[0004] The embodiments proposed in this application can solve or partially solve the deficiencies proposed in the above background technology section or other deficiencies in the prior art.

[0005] The present application provides a semiconductor structure. The semiconductor structure includes: a substrate; a semiconductor device located on the substrate; a passivation layer located on a side of the semiconductor device away from the substrate and extending along a first direction; and a sealing ring located on the substrate and surrounding the semiconductor device, and including a plurality of conductive layers stacked sequentially along a second direction until they contact the passivation layer, wherein at least two adjacent conductive layers adjacent to the passivation layer are made of the same material, and the second direction intersects the first direction.

[0006] In one embodiment, the two adjacent conductive layers include a first conductive layer and a second conductive layer. In the first direction, an extension length of the first conductive layer is greater than a width of the second conductive layer.

[0007] In one embodiment, the width of the second conductive layer is greater than or equal to 1 micron.

[0008] In one embodiment, the semiconductor device includes: a first semiconductor structure located on the substrate; and a second semiconductor structure bonded to the first semiconductor structure along the second direction, wherein the passivation layer is located on a side of the second semiconductor structure away from the first semiconductor structure, and the first conductive layer and the second conductive layer are located in an area corresponding to the second semiconductor structure.

[0009] In one embodiment, the second semiconductor structure includes a memory array, wherein the plurality of conductive layers further include a third conductive layer extending to the second conductive layer along the second direction, wherein the third conductive layer is located in a region corresponding to the memory array.

[0010] In one embodiment, the multiple conductive layers further include a first bonded conductive layer and a second bonded conductive layer, wherein the first bonded conductive layer is located in an area corresponding to the first semiconductor structure, the second bonded conductive layer is located in an area corresponding to the second semiconductor structure, the second bonded conductive layer is coupled to the second conductive layer, and the first bonded conductive layer is coupled to the substrate.

[0011] In one embodiment, the multiple conductive layers include: multiple first transition conductive layers, located between the first bonding conductive layer and the substrate, wherein the first bonding conductive layer is coupled to the substrate through the multiple first transition conductive layers; and multiple second transition conductive layers, located between the second bonding conductive layer and the third conductive layer, wherein the second bonding conductive layer is coupled to the third conductive layer through the multiple second transition conductive layers.

[0012] In one embodiment, the first semiconductor structure and the second semiconductor structure each include a plurality of metal wiring layers, wherein the conductive layer and the metal wiring layers at corresponding heights are formed in the same process.

[0013] In one embodiment, the first conductive layer contacts a plurality of second conductive layers spaced apart along the first direction.

[0014] In one embodiment, the shape of the sealing ring includes at least one of an annular groove and an annular column.

[0015] In one embodiment, the semiconductor structure further includes: a pad lead-out structure penetrating the passivation layer; and a covering layer located on a surface of the passivation layer, wherein the covering layer is made of an insulating material.

[0016] In one embodiment, the substrate comprises a doped substrate.

[0017] In one embodiment, the first conductive layer and the second conductive layer are an integral structure, wherein the integral structure extends along the first direction and protrudes along the second direction.

[0018] Another aspect of the present application provides a method for manufacturing a semiconductor structure. The method includes: providing a seal ring surrounding the semiconductor device, wherein the seal ring includes a plurality of conductive layers stacked in sequence; and forming a passivation layer extending along a first direction on a side of the semiconductor device away from the substrate, wherein the conductive layer extends along a second direction to the passivation layer, wherein at least two adjacent conductive layers adjacent to the passivation layer are made of the same material, and the second direction intersects the first direction.

[0019] In one embodiment, the conductive layer includes a first conductive layer and a second conductive layer that are adjacent to each other along the second direction and form an integral structure, and the step of forming a sealing ring surrounding the semiconductor device on the substrate includes: forming the second conductive layer and the first conductive layer covering the second conductive layer using the same material in the same process.

[0020] In one embodiment, the semiconductor device includes a first semiconductor structure located on the substrate and a second semiconductor structure bonded to the first semiconductor structure along the second direction, the passivation layer is located on a side of the second semiconductor structure away from the first semiconductor structure, and the steps of forming the second conductive layer and the first conductive layer covering the second conductive layer using the same material in the same process include: forming the first conductive layer and the second conductive layer in an area corresponding to the second semiconductor structure.

[0021] In one embodiment, the second semiconductor structure includes a memory array, and the step of forming a seal ring surrounding the semiconductor device on the substrate includes: forming a third conductive layer extending along the second direction to the second conductive layer in a region corresponding to the memory array.

[0022] In one embodiment, the multiple conductive layers include a first bonded conductive layer located in a region corresponding to the first semiconductor structure and a second bonded conductive layer located in a region corresponding to the second semiconductor structure, wherein the method includes: bonding the first semiconductor structure and the second semiconductor structure and bonding the first bonded conductive layer and the second bonded conductive layer in the same process.

[0023] In one embodiment, the multiple conductive layers include multiple first transition conductive layers located between the first bonding conductive layer and the second conductive layer, and multiple second transition conductive layers located between the second bonding conductive layer and the substrate, wherein forming a sealing ring surrounding the semiconductor device on the substrate includes: stacking the multiple first transition conductive layers and the first bonding conductive layer in sequence on the substrate; stacking the second bonding conductive layer, the multiple second transition conductive layers, the third conductive layer, the second conductive layer and the first conductive layer in sequence; and bonding the first bonding conductive layer and the second bonding conductive layer.

[0024] In one embodiment, the first semiconductor structure and the second semiconductor structure each include a plurality of metal wiring layers, wherein a metal wiring layer at a height corresponding to the conductive layer is also formed in the same process while the conductive layer is formed.

[0025] In one embodiment, the steps of forming the second conductive layer and the first conductive layer covering the second conductive layer using the same material in the same process include: forming a plurality of second conductive layers spaced apart along the first direction; and forming the first conductive layer extending along the first direction and in contact with the plurality of second conductive layers.

[0026] In one embodiment, the method further includes: forming a pad lead-out structure penetrating the passivation layer; and forming a covering layer on a surface of the passivation layer.

[0027] In one embodiment, the method includes: forming an annular groove and / or a plurality of through holes arranged in an annular shape; and filling the annular groove and / or the plurality of through holes with a conductive material to form the conductive layer.

[0028] On the other hand, the present application provides a storage system, which includes the semiconductor structure as described above; and a controller coupled to the semiconductor structure and configured to control the semiconductor structure to store data. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Other features, purposes and advantages of the present application will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0030] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present application;

[0031] Figures 2 to 4 are schematic block diagrams of semiconductor structures provided in different planes according to exemplary embodiments of the present application;

[0032] Figure 5is a schematic diagram of a partial structure of a semiconductor device provided according to an exemplary embodiment of the present application;

[0033] Figure 6 is a partial structural diagram of a sealing ring provided according to an exemplary embodiment of the present application; and

[0034] Figure 7 is an exemplary block diagram of a system having a storage system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application and are not intended to limit the scope of the present application in any way.

[0036] It should be noted that in this specification, the terms "first," "second," "third," etc., are used solely to distinguish one feature from another and do not limit the features, and in particular do not indicate any order of precedence. Therefore, without departing from the teachings of this application, the first semiconductor structure discussed in this application may also be referred to as the second semiconductor structure, and the first conductive layer may also be referred to as the second conductive layer, and vice versa.

[0037] In the accompanying drawings, the thickness, size, and shape of components have been slightly adjusted for ease of illustration. The accompanying drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used to indicate approximations, not degrees, and are intended to account for the inherent variations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0038] In addition, in this document, when describing that one part is located "on" another part, the meaning of "on...", "above..." and "over..." should be interpreted in the broadest manner, so that "on..." means not only "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above..." or "over..." does not absolutely mean being above based on the direction of gravity, nor does it mean not only "on something" or "above something", but also includes the meaning of "on something" or "over something" with no intervening features or layers in between (i.e., directly on something).

[0039] It should also be understood that expressions such as "comprises," "including," "having," "includes," and / or "comprising" are open rather than closed expressions in this specification, indicating the presence of the stated features, elements, and / or components, but do not exclude the presence of one or more other features, elements, components, and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application." And, the term "exemplary" is intended to refer to an example or illustration.

[0040] This document describes exemplary embodiments with reference to schematic diagrams. The exemplary embodiments disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather encompass various equivalent structures capable of performing the same functions, as well as deviations in shape and size resulting, for example, from manufacturing. The positions shown in the figures are schematic in nature and are not intended to limit the positions of components.

[0041] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0042] As used herein, the term "layer" refers to a portion of a material comprising an area having a height. A layer can be an area of a uniform or non-uniform continuous structure whose height is less than the height of the continuous structure. For example, a layer can be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes therebetween. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above, and / or below. A layer can include multiple layers.

[0043] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0044] It should be noted that, unless there is a conflict, the embodiments and features of the embodiments in this application can be combined with each other. In addition, unless explicitly limited or inconsistent with the context, the specific steps included in the methods described in this application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0045] Figure 1 is a flow chart of a method 1000 of fabricating a semiconductor structure according to an exemplary embodiment of the present application.

[0046] like Figure 1 As shown, method 1000 for manufacturing a semiconductor structure may include: S1100, forming a semiconductor device and a seal ring surrounding the semiconductor device on a substrate, wherein the seal ring includes a plurality of conductive layers stacked in sequence; and S1200, forming a passivation layer extending along a first direction on a side of the semiconductor device away from the substrate. Steps S1100 and S1200 will be described in detail below.

[0047] Figures 2 to 4 They are schematic block diagrams of semiconductor structures at different planes according to exemplary embodiments of the present application.

[0048] In the exemplary embodiment of the present application, Figures 2 to 4 As shown, a semiconductor device 1200 and a sealing ring 1300 surrounding the semiconductor device 1200 may be formed on a substrate 1100. For example, the sealing ring 1300 may circumferentially surround the semiconductor device 1200. The sealing ring 1300 may extend along a first direction X, a second direction Z, and a third direction Y, wherein the first direction X, the second direction Z, and the third direction Y may intersect with each other.

[0049] It should be emphasized that the sealing ring 1300 in this application surrounds the semiconductor device 1200, which refers to the side of the semiconductor device 1200 and does not involve covering the top surface of the semiconductor device 1200. The sealing ring 1300 may not be in direct contact with the semiconductor device 1200.

[0050] In the semiconductor structure, the sealing ring 1300 can surround the semiconductor device 1200, and there can be a certain distance between the sealing ring 1300 and the semiconductor device 1200 to effectively protect the semiconductor device 1200 and reduce cutting damage to the semiconductor device 1200 caused by the cutting process and moisture intrusion.

[0051] It should be understood that Figures 2 to 4 The one semiconductor device 1200 shown in the figure is only for illustration, and the present application does not limit the number of semiconductor devices 1200 , and for example, two semiconductor devices 1200 , three semiconductor devices 1200 or more may be included.

[0052] Exemplarily, the material of the substrate 1100 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0053] By way of example, substrate 1100 may include a doped substrate. Seal ring 1300 may be coupled to a doped region in substrate 1100, with the doped region grounded to achieve grounding of seal ring 1300. Grounded seal ring 1300 can better discharge static charge, reducing damage to semiconductor device 1200 caused by static discharge. By way of example, the doped region may include a P-type doped region or an N-type doped region. It should be emphasized that a doped region may only be of one doping type.

[0054] Exemplarily, the P-type doped region is composed of a P-type semiconductor material. In the P-type doped region, the hole concentration is much greater than the free electron concentration, holes are the majority carriers, and free electrons are the minority carriers, and electrical conduction is primarily due to holes. Exemplarily, the N-type doped region is composed of an N-type semiconductor material. In the N-type doped region, the free electron concentration is much greater than the hole concentration, free electrons are the majority carriers, and holes are the minority carriers, and electrical conduction is primarily due to free electrons.

[0055] In an exemplary embodiment of the present application, the sealing ring 1300 may include a plurality of conductive layers 1310 stacked in sequence. Exemplarily, forming the conductive layer 1310 may include: forming an annular groove and / or a plurality of annular through-holes; and filling the annular groove and / or the plurality of through-holes with a conductive material to form the conductive layer 1310. In other words, the conductive layer 1310 may be a groove-shaped and / or a through-hole-shaped. The shape of the sealing ring 1300 may include at least one of an annular groove and an annular column. Exemplarily, the conductive material includes, but is not limited to, copper, aluminum, nickel, tungsten, silver, gold, titanium, and the like.

[0056] In an exemplary embodiment of the present application, Figure 3 As shown, the conductive layer 1310 may be a groove type, and the conductive material is filled in the groove. In other words, the shape of the sealing ring 1300 may include an annular groove, that is, the sealing ring 1300 may include a metal wall. In another exemplary embodiment of the present application, as shown in FIG. Figure 4 As shown, conductive layer 1310 may be a through-hole type, with conductive material filled in the through-hole. In other words, the shape of sealing ring 1300 may include an annular column, that is, sealing ring 1300 may include a metal column. It should be understood that compared to metal columns, metal walls can provide improved reinforcement and improved protection against moisture and mobile ion contaminants.

[0057] Figure 5 1 is a partial structural diagram of a semiconductor device 1200 provided according to an exemplary embodiment of the present application.

[0058] The semiconductor device 1200 may include a first semiconductor structure 1210 located on a substrate 1100 and a second semiconductor structure 1220 bonded to the first semiconductor structure 1210 along a second direction Z.

[0059] The first semiconductor structure 1210 may include a peripheral circuit 1211. The peripheral circuit 1211 (also referred to as a control and sensing circuit) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory cell array. For example, the peripheral circuit 1211 may include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., a subcircuit) of the aforementioned functional circuits, or any active or passive component of the circuit (e.g., a peripheral transistor, diode, resistor, or capacitor).

[0060] Illustratively, the first semiconductor structure 1210 may further include a first interconnect layer 1212 located on the peripheral circuit 1211 to transmit electrical signals to and from the peripheral circuit 1211. The first interconnect layer 1212 may include multiple interconnect structures (also referred to as "contact structures"), wherein the interconnect structures may include lateral interconnect lines and interconnect contacts. The first interconnect layer 1212 may also include one or more dielectric layers for separating the multiple interconnect lines and / or interconnect contacts. That is, the first interconnect layer 1212 may include interconnect lines and interconnect contacts in multiple dielectric layers. Illustratively, the peripheral circuits 1211 may be coupled to each other via the interconnect structures in the first interconnect layer 1212. The material of the interconnect structures in the first interconnect layer 1212 may include a conductive material, such as, but not limited to, tungsten (W), copper (Cu), aluminum (Al), doped silicon, silicide, or any combination thereof. The dielectric layer may be formed of a dielectric material, such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k material layer, or any combination thereof.

[0061] For example, the first semiconductor structure 1210 may further include a first bonding layer 1213 located on the first interconnect layer 1212. The first bonding layer 1213 may include a plurality of first bonding contacts 1213-1 and a dielectric isolating the first bonding contacts 1213-1. The first bonding contacts 1213-1 may include a conductive material, such as copper (Cu). The remaining area of the first bonding layer 1213 may be formed with a dielectric material (e.g., silicon oxide). The first bonding contacts 1213-1 and the surrounding dielectric in the first bonding layer 1213 may be used for hybrid bonding.

[0062] The second semiconductor structure 1220 may include a memory array 1221. The memory array 1221 may include a plurality of memory cells, such as NAND memory cells. NAND memory cells are capable of maintaining a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped within the memory cell region. Each memory cell may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0063] It should be understood that the memory array 1221 provided in the present application may also include DRAM memory cells, etc., and this application is not limited to this. A DRAM memory cell may include a capacitor for storing a data bit as a positive charge or a negative charge and one or more transistors (also known as pass transistors) for controlling (e.g., switching and selecting) access to the memory cell.

[0064] For example, the second semiconductor structure 1220 may further include a second interconnect layer 1222 located on one side of the memory array 1221. The second interconnect layer 1222 may include an interconnect structure (also referred to as a "contact structure") in a plurality of dielectric layers to electrically connect to the memory cells through the bit lines.

[0065] For example, the second semiconductor structure 1220 may further include a second bonding layer 1223 located on the second interconnect layer 1222. The second bonding layer 1223 may include a plurality of second bonding contacts 1223-1 and a dielectric isolating the second bonding contacts 1223-1, wherein the second bonding contacts 1223-1 may be connected to an interconnect structure (such as a bit line contact and / or a word line contact) in the second interconnect layer 1222.

[0066] By way of example, the second semiconductor structure 1220 may further include a contact structure 1224 for leading out memory cells in the memory array 1221, and a semiconductor layer 1225 located on a side of the memory array 1221 away from the second interconnect layer 1222. By way of example, the contact structure 1224 may include a conductive material, may be connected to the memory cells, and may be connected to the first semiconductor structure 1210 via the second interconnect layer 1222 and the second bonding layer 1223. Multiple metal wiring layers, such as power line layers, may be disposed within the semiconductor layer 1225.

[0067] Figure 6 FIG. 1 is a partial structural diagram of a sealing ring 1300 provided according to an exemplary embodiment of the present application. Figure 6As shown, the sealing ring 1300 may include a plurality of conductive layers 1310 stacked in sequence. The plurality of conductive layers 1310 may include a plurality of first transition conductive layers 1316, a first bonding conductive layer 1314, a second bonding conductive layer 1315, a plurality of second transition conductive layers 1317, a third conductive layer 1313, a second conductive layer 1312, and a first conductive layer 1311 arranged along the second direction Z.

[0068] Exemplarily, the step of forming a sealing ring 1300 surrounding the semiconductor device 1200 on the substrate 1100 may include: stacking a plurality of first transition conductive layers 1316 and a first bonding conductive layer 1314 in sequence on the substrate 1100; stacking a second bonding conductive layer 1315, a plurality of second transition conductive layers 1317, a third conductive layer 1313, a second conductive layer 1312 and a first conductive layer 1311 in sequence; and bonding the first bonding conductive layer 1314 and the second bonding conductive layer 1315.

[0069] In the exemplary embodiment of the present application, the plurality of first transition conductive layers 1316 and the first bonding conductive layer 1314 may be located in a region corresponding to the first semiconductor structure 1210. The second bonding conductive layer 1315, the plurality of second transition conductive layers 1317, the third conductive layer 1313, the second conductive layer 1312, and the first conductive layer 1311 may be located in a region corresponding to the second semiconductor structure 1220.

[0070] Both the first semiconductor structure 1210 and the second semiconductor structure 1220 may include multiple metal wiring layers. For example, the first semiconductor structure 1210 may include multiple metal wiring layers, such as a first interconnect layer 1212 and a first bonding layer 1213. The second semiconductor structure 1220 may include multiple metal wiring layers, such as a second bonding layer 1223, a second interconnect layer 1222, a contact structure 1224, and a semiconductor layer 1225.

[0071] For example, at least a portion of the plurality of first transition conductive layers 1316 may be located at the same height as the first interconnect layer 1212. At least a portion of the first bonding conductive layer 1314 may be located at the same height as the first bonding layer 1213. At least a portion of the second bonding conductive layer 1315 may be located at the same height as the second bonding layer 1223. At least a portion of the plurality of second transition conductive layers 1317 may be located at the same height as the second interconnect layer 1222. The third conductive layer 1313 may be located at the same height as the contact structure 1224. The second conductive layer 1312 and the first conductive layer 1311 may be located at the same height as the semiconductor layer 1225.

[0072] For example, while forming the conductive layer 1310, a metal wiring layer at a height corresponding to the conductive layer 1310 may also be formed in the same process. In other words, the conductive layer 1310 and the metal wiring layers at corresponding heights of the first semiconductor structure 1210 and the second semiconductor structure 1220 may be formed in the same process.

[0073] For example, at least a portion of the plurality of first transition conductive layers 1316 can be formed in the same process as the interconnect structure in the first interconnect layer 1212. At least a portion of the first bonding conductive layer 1314 can be formed in the same process as the first bonding contact 1213-1 in the first bonding layer 1213. At least a portion of the second bonding conductive layer 1315 can be formed in the same process as the second bonding contact 1223-1 in the second bonding layer 1223. At least a portion of the plurality of second transition conductive layers 1317 can be formed in the same process as the interconnect structure in the second interconnect layer 1222. The third conductive layer 1313 can be formed in the same process as the contact structure 1224. The second conductive layer 1312 and the first conductive layer 1311 can be formed in the same process as the metal wiring layer, such as the power line layer, in the semiconductor layer 1225.

[0074] In the present application, the sealing ring 1300 can be formed simultaneously with the metal wiring layer in the semiconductor device 1200. The metal wiring layer is used for electrical signal transmission in the semiconductor device 1200, while the sealing ring 1300 does not participate in the electrical signal transmission of the semiconductor device 1200. The sealing ring 1300 and the metal wiring layer can share a photomask, and the photolithography and development process of the sealing ring 1300 and the metal wiring layer can be completed in a single photolithography process, thereby reducing manufacturing costs. In the second direction Z, the height of the sealing ring 1300 can be greater than or equal to the height of the semiconductor device 1200 to provide sufficient protection for the semiconductor device 1200, reduce mechanical damage to the semiconductor device 1200 during the cutting process, and reduce moisture intrusion into the semiconductor device 1200 after cutting.

[0075] For example, the first semiconductor structure 1210 and the second semiconductor structure 1220 may be bonded, and the first bonding conductive layer 1314 and the second bonding conductive layer 1315 may be bonded in the same process.

[0076] For example, the first conductive layer 1311 and the second conductive layer 1312 may be adjacently arranged along the second direction Z and may be made of the same material, such as aluminum. In the first direction X, the extension length of the first conductive layer 1311 may be greater than the width of the second conductive layer 1312. The width of the second conductive layer 1312 may be greater than or equal to 1 micron. For example, the first conductive layer 1311 and the second conductive layer 1312 may be integrally formed and protrude toward the third conductive layer 1313 along the second direction X to achieve contact between the second conductive layer 1312 and the third conductive layer 1313. For example, the second conductive layer 1312 and the first conductive layer 1311 covering the second conductive layer 1312 may be formed in the same process using the same material.

[0077] In this application, by configuring the second conductive layer 1312 and the first conductive layer 1311 as an integrated structure, the contact interface between the two can be reduced, and both conductive layers can be formed simultaneously in a single process, which is beneficial for improving packaging effects, reducing process steps, lowering production costs, and shortening production cycles. In addition, configuring the width of the second conductive layer 1312 to be greater than or equal to 1 micron helps increase the contact area of the second conductive layer 1312 and increases the space for forming the third conductive layer 1313 in contact with the second conductive layer 1312.

[0078] For example, a plurality of second conductive layers 1312 may be formed spaced apart along the first direction X; and a first conductive layer 1311 may be formed extending along the first direction X and contacting the plurality of second conductive layers 1312. The cross-sections of the plurality of second conductive layers 1312 along a direction parallel to the substrate 1100 may be in the shape of a U-shaped triangle. For example, Figure 6 As shown, multiple third conductive layers 1313, second transition conductive layers 1317, second bonding conductive layers 1315, first bonding conductive layers 1314, and first transition conductive layers 1316 may be formed spaced apart along the first direction X, so that the sealing ring 1300 forms a multi-layer metal wall structure. This provides more stringent protection for the semiconductor device 1200, further reduces mechanical damage and moisture intrusion to the semiconductor device 1200 during the cutting process, shields external electromagnetic interference, and reduces damage to the device caused by electrostatic discharge. Furthermore, during the subsequent chemical mechanical polishing process of the semiconductor device 1200, the U-shaped sealing ring 1300 provides better support for the semiconductor device 1200.

[0079] For example, conductive materials may be deposited by one or more thin film deposition processes (including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, or any combination thereof) to form multiple conductive layers 1310 such as a first transition conductive layer 1316, a first bonding conductive layer 1314, a second bonding conductive layer 1315, multiple second transition conductive layers 1317, a third conductive layer 1313, a second conductive layer 1312, and a first conductive layer 1311. Furthermore, the manufacturing process for forming the multiple conductive layers 1310 may further include photolithography, chemical mechanical polishing (CMP), wet / dry etching, or any other suitable process.

[0080] In the exemplary embodiment of the present application, Figure 2 、 Figure 5 and Figure 6 As shown, a passivation layer 1400 extending along a first direction X may be formed on a side of the semiconductor device 1200 away from the substrate 1100, wherein the conductive layer 1310 extends to the passivation layer 1400 along a second direction Z, and the first conductive layer 1311 may be close to the passivation layer 1400. For example, the passivation layer 1400 may be located on a side of the second semiconductor structure 1220 away from the first semiconductor structure 1210. The passivation layer 1400 may cover the semiconductor layer 1225.

[0081] For example, a pad lead-out structure 1410 may be formed extending through the passivation layer 1400. The pad lead-out structure 1410 may be connected to the first semiconductor structure 1210 via a plurality of conductive structures, such as the second interconnect layer 1222 and the second bonding layer 1223. The pad lead-out structure 1410 may transmit electrical signals between the semiconductor structure and an external circuit. The pad lead-out structure 1410 may comprise a conductive material, including but not limited to W, Cu, Al, doped silicon, silicide, or any combination thereof. The pad lead-out interconnect layer may comprise a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric constant material layer, or any combination thereof.

[0082] For example, a cover layer 1500 may be formed on the surface of the passivation layer 1400. The cover layer 1500 may extend along the first direction X and may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material layer, or any combination thereof, to better isolate external pollutants such as water vapor and ions.

[0083] Figure 2 is a schematic block diagram of a semiconductor structure according to an exemplary embodiment of the present application.

[0084] like Figure 2 As shown, the semiconductor structure may include a substrate 1100 , a semiconductor device 1200 , a seal ring 1300 , and a passivation layer 1400 .

[0085] The substrate 1100 may extend along a first direction X. The semiconductor device 1200 may be located on the substrate 1100. The passivation layer 1400 may be located on a side of the semiconductor device 1200 away from the substrate 1100 and extend along the first direction X. The sealing ring 1300 may be located on the substrate 1100 and surround the semiconductor device 1200. For example, Figure 6 As shown, the sealing ring 1300 may include a plurality of conductive layers 1310 sequentially stacked along a second direction Z until they contact the passivation layer 1400, wherein at least two adjacent conductive layers (e.g., the first conductive layer 1311 and the second conductive layer 1312) near the passivation layer 1400 are made of the same material. For example, the first direction X, the second direction Z, and the third direction Y may intersect each other.

[0086] like Figures 2 to 4 As shown, the sealing ring 1300 may surround the semiconductor device 1200 along a circumferential direction. The sealing ring 1300 may extend along a first direction X, a second direction Z, and a third direction Y. It should be emphasized that the sealing ring 1300 surrounding the semiconductor device 1200 in this application refers to surrounding the side surfaces of the semiconductor device 1200 and does not involve covering the top surface of the semiconductor device 1200. The sealing ring 1300 may not be in direct contact with the semiconductor device 1200.

[0087] In the semiconductor structure, the sealing ring 1300 can surround the semiconductor device 1200, and there can be a certain distance between the sealing ring 1300 and the semiconductor device 1200 to effectively protect the semiconductor device 1200 and reduce cutting damage to the semiconductor device 1200 caused by the cutting process and moisture intrusion.

[0088] It should be understood that Figures 2 to 4 The one semiconductor device 1200 shown in the figure is only for illustration, and the present application does not limit the number of semiconductor devices 1200 , and for example, two semiconductor devices 1200 , three semiconductor devices 1200 or more may be included.

[0089] Exemplarily, the material of the substrate 1100 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0090] By way of example, substrate 1100 may include a doped substrate. Seal ring 1300 may be coupled to a doped region in substrate 1100, with the doped region grounded to achieve grounding of seal ring 1300. Grounded seal ring 1300 can better discharge static charge, reducing damage to semiconductor device 1200 caused by static discharge. By way of example, the doped region may include a P-type doped region or an N-type doped region. It should be emphasized that a doped region may only be of one doping type.

[0091] Exemplarily, the P-type doped region is composed of a P-type semiconductor material. In the P-type doped region, the hole concentration is much greater than the free electron concentration, holes are the majority carriers, and free electrons are the minority carriers, and electrical conduction is primarily due to holes. Exemplarily, the N-type doped region is composed of an N-type semiconductor material. In the N-type doped region, the free electron concentration is much greater than the hole concentration, free electrons are the majority carriers, and holes are the minority carriers, and electrical conduction is primarily due to free electrons.

[0092] For example, the shape of the sealing ring 1300 may include at least one of an annular groove and an annular column. The plurality of conductive layers 1310 include, but are not limited to, conductive materials such as copper, aluminum, nickel, tungsten, silver, gold, and titanium. In an exemplary embodiment of the present application, as shown in FIG. Figure 3 As shown, the conductive layer 1310 may be groove-shaped. In other words, the shape of the sealing ring 1300 may include an annular groove, that is, the sealing ring 1300 may include a metal wall. In another exemplary embodiment of the present application, as shown in FIG. Figure 4 As shown, the conductive layer 1310 may be a through-hole type. In other words, the shape of the sealing ring 1300 may include an annular column, that is, the sealing ring 1300 may include a metal column. It should be understood that compared to metal columns, metal walls can provide improved reinforcement and improved protection against moisture and mobile ion contaminants.

[0093] like Figure 5 As shown, the semiconductor device 1200 may include a first semiconductor structure 1210 located on a substrate 1100 and a second semiconductor structure 1220 bonded to the first semiconductor structure 1210 along a second direction Z.

[0094] The first semiconductor structure 1210 may include a peripheral circuit 1211. The peripheral circuit 1211 (also referred to as a control and sensing circuit) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory cell array. For example, the peripheral circuit 1211 may include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., a subcircuit) of the aforementioned functional circuits, or any active or passive component of the circuit (e.g., a peripheral transistor, diode, resistor, or capacitor).

[0095] Illustratively, the first semiconductor structure 1210 may further include a first interconnect layer 1212 located on the peripheral circuit 1211 to transmit electrical signals to and from the peripheral circuit 1211. The first interconnect layer 1212 may include multiple interconnect structures (also referred to as "contact structures"), wherein the interconnect structures may include lateral interconnect lines and interconnect contacts. The first interconnect layer 1212 may also include one or more dielectric layers for separating the multiple interconnect lines and / or interconnect contacts. That is, the first interconnect layer 1212 may include interconnect lines and interconnect contacts in multiple dielectric layers. Illustratively, the peripheral circuits 1211 may be coupled to each other via the interconnect structures in the first interconnect layer 1212. The material of the interconnect structures in the first interconnect layer 1212 may include a conductive material, such as, but not limited to, tungsten (W), copper (Cu), aluminum (Al), doped silicon, silicide, or any combination thereof. The dielectric layer may be formed of a dielectric material, such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k material layer, or any combination thereof.

[0096] For example, the first semiconductor structure 1210 may further include a first bonding layer 1213 located on the first interconnect layer 1212. The first bonding layer 1213 may include a plurality of first bonding contacts 1213-1 and a dielectric isolating the first bonding contacts 1213-1. The first bonding contacts 1213-1 may include a conductive material, such as copper (Cu). The remaining area of the first bonding layer 1213 may be formed with a dielectric material (e.g., silicon oxide). The first bonding contacts 1213-1 and the surrounding dielectric in the first bonding layer 1213 may be used for hybrid bonding.

[0097] The second semiconductor structure 1220 may include a memory array 1221. The memory array 1221 may include a plurality of memory cells, such as NAND memory cells. NAND memory cells are capable of maintaining a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped within the memory cell region. Each memory cell may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0098] It should be understood that the memory array 1221 provided in the present application may also include DRAM memory cells, etc., and this application is not limited to this. A DRAM memory cell may include a capacitor for storing a data bit as a positive charge or a negative charge and one or more transistors (also known as pass transistors) for controlling (e.g., switching and selecting) access to the memory cell.

[0099] For example, the second semiconductor structure 1220 may further include a second interconnect layer 1222 located on one side of the memory array 1221. The second interconnect layer 1222 may include an interconnect structure (also referred to as a "contact structure") in a plurality of dielectric layers to electrically connect to the memory cells through the bit lines.

[0100] For example, the second semiconductor structure 1220 may further include a second bonding layer 1223 located on the second interconnect layer 1222. The second bonding layer 1223 may include a plurality of second bonding contacts 1223-1 and a dielectric isolating the second bonding contacts 1223-1, wherein the second bonding contacts 1223-1 may be connected to an interconnect structure (such as a bit line contact and / or a word line contact) in the second interconnect layer 1222.

[0101] By way of example, the second semiconductor structure 1220 may further include a contact structure 1224 for leading out memory cells in the memory array 1221, and a semiconductor layer 1225 located on a side of the memory array 1221 away from the second interconnect layer 1222. By way of example, the contact structure 1224 may include a conductive material, may be connected to the memory cells, and may be connected to the first semiconductor structure 1210 via the second interconnect layer 1222 and the second bonding layer 1223. Multiple metal wiring layers, such as power line layers, may be disposed within the semiconductor layer 1225.

[0102] like Figure 6 As shown, the multiple conductive layers 1310 may include multiple first transition conductive layers 1316, a first bonding conductive layer 1314, a second bonding conductive layer 1315, multiple second transition conductive layers 1317, a third conductive layer 1313, a second conductive layer 1312 and a first conductive layer 1311 arranged along the second direction Z.

[0103] In the exemplary embodiment of the present application, the plurality of first transition conductive layers 1316 and the first bonding conductive layer 1314 may be located in a region corresponding to the first semiconductor structure 1210. The second bonding conductive layer 1315, the plurality of second transition conductive layers 1317, the third conductive layer 1313, the second conductive layer 1312, and the first conductive layer 1311 may be located in a region corresponding to the second semiconductor structure 1220.

[0104] Both the first semiconductor structure 1210 and the second semiconductor structure 1220 may include multiple metal wiring layers. For example, the first semiconductor structure 1210 may include multiple metal wiring layers, such as a first interconnect layer 1212 and a first bonding layer 1213. The second semiconductor structure 1220 may include multiple metal wiring layers, such as a second bonding layer 1223, a second interconnect layer 1222, a contact structure 1224, and a semiconductor layer 1225.

[0105] For example, at least a portion of the plurality of first transition conductive layers 1316 may be located at the same height as the first interconnect layer 1212. At least a portion of the first bonding conductive layer 1314 may be located at the same height as the first bonding layer 1213. At least a portion of the second bonding conductive layer 1315 may be located at the same height as the second bonding layer 1223. At least a portion of the plurality of second transition conductive layers 1317 may be located at the same height as the second interconnect layer 1222. The third conductive layer 1313 may be located at the same height as the contact structure 1224. The second conductive layer 1312 and the first conductive layer 1311 may be located at the same height as the semiconductor layer 1225.

[0106] For example, the conductive layer 1310 and the metal wiring layers at corresponding heights of the first semiconductor structure 1210 and the second semiconductor structure 1220 can be formed in the same process. For example, at least a portion of the plurality of first transition conductive layers 1316 can be formed in the same process as the interconnect structure in the first interconnect layer 1212. At least a portion of the first bonding conductive layer 1314 can be formed in the same process as the first bonding contact 1213-1 in the first bonding layer 1213. At least a portion of the second bonding conductive layer 1315 can be formed in the same process as the second bonding contact 1223-1 in the second bonding layer 1223. At least a portion of the plurality of second transition conductive layers 1317 can be formed in the same process as the interconnect structure in the second interconnect layer 1222. The third conductive layer 1313 can be formed in the same process as the contact structure 1224. The second conductive layer 1312 and the first conductive layer 1311 can be formed in the same process as the metal wiring layers, such as the power line layer, in the semiconductor layer 1225.

[0107] In the present application, the sealing ring 1300 can be formed simultaneously with the metal wiring layer in the semiconductor device 1200. The metal wiring layer is used for electrical signal transmission in the semiconductor device 1200, while the sealing ring 1300 does not participate in the electrical signal transmission of the semiconductor device 1200. The sealing ring 1300 and the metal wiring layer can share a photomask, and the photolithography and development process of the sealing ring 1300 and the metal wiring layer can be completed in a single photolithography process, thereby reducing manufacturing costs. In the second direction Z, the height of the sealing ring 1300 can be greater than or equal to the height of the semiconductor device 1200 to provide sufficient protection for the semiconductor device 1200, reduce mechanical damage to the semiconductor device 1200 during the cutting process, and reduce moisture intrusion into the semiconductor device 1200 after cutting.

[0108] For example, the first conductive layer 1311 and the second conductive layer 1312 may be adjacently arranged along the second direction Z and may be made of the same material, such as aluminum. In the first direction X, the extension length of the first conductive layer 1311 may be greater than the width of the second conductive layer 1312. The width of the second conductive layer 1312 may be greater than or equal to 1 micron. For example, the first conductive layer 1311 and the second conductive layer 1312 may be integrally formed and protrude toward the third conductive layer 1313 along the second direction X to achieve contact between the second conductive layer 1312 and the third conductive layer 1313. For example, the second conductive layer 1312 and the first conductive layer 1311 covering the second conductive layer 1312 may be formed in the same process using the same material.

[0109] In this application, by configuring the second conductive layer 1312 and the first conductive layer 1311 as an integrated structure, the contact interface between the two can be reduced, and both conductive layers can be formed simultaneously in a single process, which is beneficial for improving packaging effects, reducing process steps, lowering production costs, and shortening production cycles. In addition, configuring the width of the second conductive layer 1312 to be greater than or equal to 1 micron helps increase the contact area of the second conductive layer 1312 and increases the space for forming the third conductive layer 1313 in contact with the second conductive layer 1312.

[0110] For example, the first conductive layer 1311 may be in contact with a plurality of second conductive layers 1312 spaced apart along the first direction X. The cross-sections of the plurality of second conductive layers 1312 along a direction parallel to the substrate 1100 may be in the shape of a Chinese y-square. Figure 6 As shown, the plurality of second conductive layers 1312 can be respectively connected to the plurality of third conductive layers 1313, the second transition conductive layer 1317, the second bonding conductive layer 1315, the first bonding conductive layer 1314, and the first transition conductive layer 1316 corresponding to each other along the second direction Z, so that the sealing ring 1300 forms a multi-layer metal wall structure, providing more stringent protection for the semiconductor device 1200, further reducing mechanical damage and moisture intrusion to the semiconductor device 1200 during the cutting process, shielding the semiconductor device 1200 from external electromagnetic interference, and reducing damage to the device caused by electrostatic discharge. In addition, during the subsequent chemical mechanical polishing process of the semiconductor device 1200, the U-shaped sealing ring 1300 can provide better support for the semiconductor device 1200.

[0111] In the exemplary embodiment of the present application, Figure 2 、 Figure 5 and Figure 6 As shown, the conductive layer 1310 may extend to the passivation layer 1400 along the second direction Z, such as the first conductive layer 1311 may extend to the passivation layer 1400. For example, the passivation layer 1400 may be located on a side of the second semiconductor structure 1220 away from the first semiconductor structure 1210. The passivation layer 1400 may cover the semiconductor layer 1225.

[0112] For example, the semiconductor structure may further include a pad lead-out structure 1410 extending through the passivation layer 1400. The pad lead-out structure 1410 may be connected to the first semiconductor structure 1210 via a plurality of conductive structures, such as the second interconnect layer 1222 and the second bonding layer 1223. The pad lead-out structure 1410 may transmit electrical signals between the semiconductor structure and an external circuit. The pad lead-out structure 1410 may include a conductive material, including but not limited to W, Cu, Al, doped silicon, silicide, or any combination thereof. The pad lead-out interconnect layer may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric constant material layer, or any combination thereof.

[0113] For example, the semiconductor structure may further include a capping layer 1500 located on a surface of the passivation layer 1400. The capping layer 1500 may extend along the first direction X. The capping layer 1500 may be made of an insulating material, such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric constant material layer, or any combination thereof, to better isolate the semiconductor structure from external contaminants such as water vapor and ions.

[0114] Since the contents and structures involved in the method 1000 for manufacturing a semiconductor structure described above may be fully or partially applicable to the semiconductor structure described herein, related or similar contents will not be described in detail herein.

[0115] Although the exemplary structure and fabrication method of the semiconductor structure are described herein, it is understood that one or more features may be omitted, replaced, or added to the fabrication method of the semiconductor structure. In addition, the illustrated layers and their materials are merely exemplary.

[0116] Figure 7 is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of the present application.

[0117] The system 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having the storage system 12 located therein. Figure 7As shown, system 10 may include a host 18 and a storage system 12 having one or more three-dimensional memories 14 and a controller 16. Host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). Host 18 may be configured to send or receive data to or from three-dimensional memories 14.

[0118] The three-dimensional memory 14 may include a semiconductor structure as described in any embodiment of the present application. According to some embodiments, a controller 16 is coupled to the three-dimensional memory 14 and a host 18 and is configured to control the three-dimensional memory 14. The controller 16 may manage data stored in the three-dimensional memory 14 and communicate with the host 18. For example, the controller 16 may communicate with an external device (e.g., the host 18) according to a specific communication protocol.

[0119] The above description is merely a preferred embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this application is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but also encompasses other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the inventive concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor structure, characterized in that include: substrate; a semiconductor device located on the substrate; a passivation layer, located on a side of the semiconductor device away from the substrate and extending along a first direction; as well as A sealing ring is located on the substrate and surrounds the semiconductor device, and includes a plurality of conductive layers stacked in sequence along a second direction to contact the passivation layer, wherein at least two adjacent conductive layers close to the passivation layer are made of the same material, and the second direction intersects with the first direction.

2. The semiconductor structure according to claim 1, wherein: The two adjacent conductive layers include a first conductive layer and a second conductive layer. In the first direction, an extension length of the first conductive layer is greater than a width of the second conductive layer.

3. The semiconductor structure according to claim 2, wherein: The width of the second conductive layer is greater than or equal to 1 micron.

4. The semiconductor structure according to claim 2, wherein: The semiconductor device comprises: A first semiconductor structure is located on the substrate; and A second semiconductor structure is bonded to the first semiconductor structure along the second direction, wherein the passivation layer is located on a side of the second semiconductor structure away from the first semiconductor structure, and the first conductive layer and the second conductive layer are located in a region corresponding to the second semiconductor structure.

5. The semiconductor structure according to claim 4, wherein: The second semiconductor structure includes a memory array, The plurality of conductive layers further include a third conductive layer extending along the second direction to the second conductive layer, wherein the third conductive layer is located in a region corresponding to the memory array.

6. The semiconductor structure according to claim 5, wherein: The plurality of conductive layers further include a first bonding conductive layer and a second bonding conductive layer bonded to each other, wherein: The first bonding conductive layer is located in a region corresponding to the first semiconductor structure, the second bonding conductive layer is located in a region corresponding to the second semiconductor structure, the second bonding conductive layer is coupled to the second conductive layer, and the first bonding conductive layer is coupled to the substrate.

7. The semiconductor structure according to claim 6, wherein: The plurality of conductive layers include: a plurality of first transition conductive layers located between the first bonding conductive layer and the substrate, wherein the first bonding conductive layer is coupled to the substrate through the plurality of first transition conductive layers; and A plurality of second transition conductive layers are located between the second bonding conductive layer and the third conductive layer, wherein the second bonding conductive layer is coupled to the third conductive layer through the plurality of second transition conductive layers.

8. The semiconductor structure according to claim 6, wherein: The first semiconductor structure and the second semiconductor structure each include a plurality of metal wiring layers, wherein: The conductive layer and the metal wiring layer at a corresponding height are formed in the same process.

9. The semiconductor structure according to any one of claims 2 to 8, wherein: The first conductive layer contacts a plurality of second conductive layers spaced apart along the first direction.

10. The semiconductor structure according to any one of claims 1 to 8, characterized in that The shape of the sealing ring includes at least one of an annular groove shape and an annular column shape.

11. The semiconductor structure according to any one of claims 1 to 8, wherein: The semiconductor structure further comprises: a pad lead-out structure, penetrating the passivation layer; and The covering layer is located on the surface of the passivation layer, wherein the material of the covering layer includes an insulating material.

12. The semiconductor structure according to any one of claims 1 to 8, wherein: The substrate includes a doped substrate.

13. The semiconductor structure according to any one of claims 2 to 8, wherein: The first conductive layer and the second conductive layer are an integral structure, wherein the integral structure extends along the first direction and protrudes along the second direction.

14. A method for manufacturing a semiconductor structure, characterized in that: The method comprises: forming a semiconductor device and a sealing ring surrounding the semiconductor device on a substrate, wherein the sealing ring comprises a plurality of conductive layers stacked in sequence; and forming a passivation layer extending along a first direction on a side of the semiconductor device away from the substrate, The conductive layer extends to the passivation layer along a second direction, at least two adjacent conductive layers close to the passivation layer are made of the same material, and the second direction intersects with the first direction.

15. The method according to claim 14, characterized in that The conductive layer includes a first conductive layer and a second conductive layer adjacent to each other along the second direction and forming an integral structure, The step of forming a sealing ring surrounding the semiconductor device on a substrate includes: The second conductive layer and the first conductive layer covering the second conductive layer are formed using the same material in the same process.

16. The method according to claim 15, characterized in that The semiconductor device includes a first semiconductor structure located on the substrate and a second semiconductor structure bonded to the first semiconductor structure along the second direction, wherein the passivation layer is located on a side of the second semiconductor structure away from the first semiconductor structure. The steps of forming the second conductive layer and the first conductive layer covering the second conductive layer using the same material in the same process include: The first conductive layer and the second conductive layer are formed in a region corresponding to the second semiconductor structure.

17. The method according to claim 16, characterized in that The second semiconductor structure includes a memory array, The step of forming a sealing ring surrounding the semiconductor device on a substrate includes: A third conductive layer is formed in a region corresponding to the memory array and extends along the second direction to the second conductive layer.

18. The method according to claim 17, characterized in that The plurality of conductive layers include a first bonding conductive layer located in a region corresponding to the first semiconductor structure and a second bonding conductive layer located in a region corresponding to the second semiconductor structure. The method includes: bonding the first semiconductor structure and the second semiconductor structure and bonding the first bonding conductive layer and the second bonding conductive layer in the same process.

19. The method according to claim 18, characterized in that The plurality of conductive layers include a plurality of first transition conductive layers located between the first bonding conductive layer and the second conductive layer, and a plurality of second transition conductive layers located between the second bonding conductive layer and the substrate. Wherein, forming a sealing ring surrounding the semiconductor device on the substrate includes: stacking the plurality of first transition conductive layers and the first bonding conductive layer in sequence on the substrate; stacking the second bonding conductive layer, the plurality of second transition conductive layers, the third conductive layer, the second conductive layer, and the first conductive layer in sequence; and The first bonding conductive layer and the second bonding conductive layer are bonded.

20. The method according to claim 18 or 19, characterized in that The first semiconductor structure and the second semiconductor structure each include a plurality of metal wiring layers, Wherein, while forming the conductive layer, a metal wiring layer at a height corresponding to the conductive layer is also formed in the same process.

21. The method according to any one of claims 15 to 19, characterized in that The steps of forming the second conductive layer and the first conductive layer covering the second conductive layer using the same material in the same process include: forming a plurality of second conductive layers spaced apart along the first direction; and The first conductive layer extending along the first direction and contacting the plurality of second conductive layers is formed.

22. The method according to any one of claims 14 to 19, characterized in that The method further comprises: forming a pad lead-out structure penetrating the passivation layer; and A covering layer is formed on the surface of the passivation layer.

23. The method according to any one of claims 14 to 19, characterized in that The method comprises: forming an annular groove and / or a plurality of through holes arranged in an annular manner; and A conductive material is filled in the annular trench and / or the plurality of through holes to form the conductive layer.

24. A storage system, characterized in that: include: The semiconductor structure according to any one of claims 1 to 13; as well as The controller is coupled to the semiconductor structure and is used to control the semiconductor structure to store data.

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