Circuit-heat sink monolithic integrated substrate based on semiconductor substrate and preparation method thereof

Abstract

The invention relates to a power device packaging and heat dissipation technology, and aims to provide a circuit-heat sink monolithic integrated substrate based on a semiconductor substrate and a preparation method of the circuit-heat sink monolithic integrated substrate. The integrated substrate has a multi-layer structure and comprises a semiconductor substrate, an insulating epitaxial layer, a buffer metal layer and an active circuit layer, a micro-channel structure is arranged in the semiconductor substrate, the active circuit layer comprises a power chip and a lead frame layer, and the insulating epitaxial layer, the buffer metal layer and the lead frame layer are all in an epitaxial growth mode; the buffer metal layers, the active circuit layers and the micro-channel structures are divided into a plurality of groups and are not connected with one another, and the arrangement areas of each group of micro-channel structures respectively correspond to the area where the lead frame layer is located. According to the invention, a growth process on a wafer is adopted, and a circuit and a heat sink are synchronously processed on a semiconductor substrate, so that pores among all layers of structures can be eliminated, and more compact integration is realized on the structure; compared with a traditional liquid cooling structure, a thermal interface material is omitted, and the packaging keeps extremely low conduction thermal resistance.

Description

Technical Field

[0001] The present invention relates to power device packaging and heat dissipation technology, and more particularly to a circuit-heat sink monolithic integrated substrate based on a semiconductor substrate and a preparation method thereof. Background Art

[0002] With the advancement of modern power electronics technology, power modules are moving towards smaller, lighter weight, higher efficiency, and higher power. This trend is driven by wide-bandgap semiconductor materials, which offer superior properties such as wide bandgap, high thermal conductivity, and high breakdown field strength, enabling operation at higher temperatures, voltages, and frequencies. Compared to traditional silicon-based devices, wide-bandgap semiconductors enable even greater miniaturization, higher frequency, and higher integration of power electronic converters, thus garnering significant attention and widespread application. However, the further application of wide-bandgap semiconductors is limited by the parasitic parameters and thermal management capabilities of their packaging.

[0003] On the one hand, traditional wire-bond packaging struggles to meet the high-frequency operating requirements of wide-bandgap semiconductor devices. This is primarily due to the high parasitic inductance of bond wires (over 10nH), which can lead to voltage overshoot, switching losses, and electromagnetic interference. These effects are particularly pronounced in wide-bandgap semiconductor devices, where higher switching speeds make them more sensitive to parasitic parameters. Therefore, to maximize the high-frequency advantages of wide-bandgap semiconductor devices, it is necessary to reduce or eliminate the inductance in the package and mitigate parasitic effects. Currently, leadless packaging technologies such as planar interconnect (Cu-Clip) packaging, press-pack packaging, and embedded packaging have proven to have extremely low parasitic inductance, significantly improving the electrical performance of devices.

[0004] On the other hand, wide bandgap semiconductor devices have higher breakdown field strength and lower specific on-resistance, so they have smaller volume, which also leads to higher heat flux density of wide bandgap semiconductor devices, often exceeding 500W / cm 2Conventional cooling solutions struggle to cool such high heat flux densities, preventing heat from being removed promptly. This results in an increase in device junction temperature, impacting performance. Currently, traditional liquid cooling solutions often utilize a post-bonded cold plate to conduct heat from the package to the coolant. Cold plates are often made of metal materials such as copper and aluminum, making them bulky and heavy, making them difficult to integrate with the compact layout of high-density packages. Furthermore, thermal interface materials such as insulating thermal grease and ceramic gaskets are required between the cold plate and the package substrate. These materials have low thermal conductivity and are thick, significantly increasing thermal resistance. Currently, liquid cooling solutions for power modules mostly utilize indirect cold plate cooling, where heat is dissipated through a path from chip to copper layer to thermal interface material to heat sink. However, due to the typically low thermal conductivity of thermal interface materials (approximately 0.5-3 W / (mK)), this introduces extremely high conduction thermal resistance. Furthermore, the thermal interface material, device copper layer, and heat sink are difficult to tightly bond, easily forming air gaps at the contact surface, further increasing the interface thermal resistance. These issues are key factors in improving the heat dissipation efficiency of existing packaging solutions. Clearly, thermal management challenges have become a bottleneck hindering the further development of wide-bandgap semiconductor devices. Currently, aluminum nitride ceramic substrate technology can reduce the thermal resistance of the path from the heat source to the coolant, while copper-based cooling microchannels and pin-fin cold plate technologies can improve heat transfer efficiency per unit area. However, these solutions are still insufficient in ultra-compact applications. Furthermore, direct cooling technology has emerged, which involves applying coolant directly to the bare chip, but its safety in high-voltage applications remains underdeveloped.

[0005] Despite extensive research efforts to optimize both electrical and thermal performance, current efforts have failed to achieve simultaneous improvements in both. In the field of wide-bandgap power semiconductor device packaging, high integration (low inductance) and efficient heat dissipation have become mutually exclusive. To achieve low parasitics, package volume must be sacrificed, leading to a dramatic increase in heat flux, making thermal management a difficult problem. Furthermore, current efficient electronic cooling solutions require a large heat exchange area, which reduces package integration and increases current loops, leading to increased parasitics. To overcome this trade-off between thermal and electrical performance, designing near-junction cooling structures at localized high-heat-flux heat sources within the package is a promising solution. For example, integrating cooling channels with extremely low thermal resistance beneath the heat source chip can remove extremely high heat flux within an ultra-compact space, enabling the package to maintain a highly integrated layout while maintaining high heat dissipation efficiency.

[0006] Given the demand for ultra-compact packaging structures, miniaturized circuit layouts, and efficient thermal management systems for wide-bandgap devices, there is an urgent need to develop a solution that can achieve efficient heat dissipation in ultra-miniaturized circuit systems. This solution must overcome the inherent contradiction between high circuit integration (low parasitic inductance) and efficient heat dissipation. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to overcome the deficiencies in the existing technology and provide a circuit-heat sink monolithic integrated substrate structure based on a semiconductor substrate and an electro-thermal collaborative design method thereof, which can be applied to the ultra-compact integration of wide bandgap devices.

[0008] To solve the technical problem, the solution of the present invention is:

[0009] Provided is a circuit-heat sink monolithic integrated substrate based on a semiconductor substrate, wherein the integrated substrate has a multi-layer structure, comprising a semiconductor substrate, an insulating epitaxial layer, a buffer metal layer, and an active circuit layer arranged in sequence from bottom to top;

[0010] The semiconductor substrate is a ground and polished wafer having a micro-channel structure for cooling liquid circulation inside or on the lower surface thereof;

[0011] An insulating epitaxial layer is attached to the upper surface of the semiconductor substrate by epitaxial growth;

[0012] A buffer metal layer is attached to the upper surface of the insulating epitaxial layer by epitaxial growth and is etched to form a pattern;

[0013] The active circuit layer includes a bare-die power chip and a metal lead frame layer, which are connected to realize the circuit function. The lead frame layer is attached to the surface of the buffer metal layer by epitaxial growth and etched to form the same pattern as the buffer metal layer. The chip pins and the lead frame layer are electrically connected by welding, sintering or bonding.

[0014] The buffer metal layer, active circuit layer and microfluidic structure are divided into multiple groups, and each group is independent and not connected to each other; the internal flow channels of each group of microfluidic structures form a coherent passage, and the arrangement area of each group of microfluidic structures corresponds to the area where the lead frame layer is located.

[0015] As a preferred embodiment of the present invention, the thermal expansion coefficients of the insulating epitaxial layer, the buffer metal layer, and the lead frame layer increase sequentially, and the thermal expansion coefficient of the buffer metal layer is in the middle range for buffering thermal stress and strain; alternatively, the buffer metal layer is composed of multiple components, each component is arranged in a layered manner and the thermal expansion coefficient of each layer increases sequentially from bottom to top; the component located in the bottom layer has a thermal expansion coefficient close to that of the insulating epitaxial layer, and the component located in the top layer has a thermal expansion coefficient close to that of the lead frame layer.

[0016] As a preferred solution of the present invention, the arrangement of the channels in each group of microchannel structures is uneven. In the lead frame layer area corresponding to the chip installation, the arrangement density of the channels is greater than that in the non-chip installation area.

[0017] As a preferred solution in the present invention, the microfluidic structure is arranged on the lower surface of the semiconductor substrate by etching, and the collecting plate is fixedly connected to the lower surface of the semiconductor substrate by adhesion, bonding or welding to seal the microfluidic structure, and a water inlet and outlet are provided on the collecting plate.

[0018] As a preferred solution of the present invention, the material of the current collecting plate is any one of epoxy resin, copper, aluminum or polydimethylsiloxane (PDMS).

[0019] As a preferred embodiment of the present invention, the material of the semiconductor substrate is silicon, diamond or silicon carbide; the material of the insulating epitaxial layer is one or more of aluminum nitride, diamond, silicon carbide or aluminum oxide; the material of the buffer metal layer is at least one of metal, metal oxide and metal-ceramic composite material; the material of the lead frame layer is copper, silver or gold; the power chip is a silicon-based, silicon carbide-based or gallium nitride-based chip, and its conductivity type is vertical or planar.

[0020] The present invention also provides a method for preparing the aforementioned circuit-heat sink monolithic integrated substrate, comprising the following steps:

[0021] (1) Select a wafer of appropriate size and thickness as the semiconductor substrate, grind and polish it, and then prepare an insulating epitaxial layer on its upper surface through an epitaxial growth process;

[0022] (2) In the effective arrangement area on the upper surface of the insulating epitaxial layer, multiple groups of buffer metal layers, lead frame layers, and chips are planned that are independently arranged; corresponding multiple groups of microchannel structures are planned on the semiconductor substrate; wherein the lead frame layer and the buffer metal layer have the same pattern; the flow channels of the microchannel structure are arranged non-uniformly, and their arrangement area corresponds to the arrangement area of the lead frame layer and the chip, so as to achieve point-to-point local near-junction cooling;

[0023] (3) forming a first metal film for preparing a buffer metal layer by an epitaxial growth process in an effective arrangement area on the upper surface of the insulating epitaxial layer;

[0024] (4) forming a second metal film for preparing a lead frame layer in the same area on the upper surface of the first metal film by an epitaxial growth process;

[0025] (5) using a combination of a photolithography mask and an etching process to simultaneously process the first metal film and the second metal film to form a buffer metal layer and a lead frame layer having the same pattern;

[0026] (6) Using a combination of photoresist mask and etching process, multiple groups of microfluidic channel structures are produced in the effective arrangement area of the bottom surface of the wafer, and the flow channels within each group of microfluidic channels form a coherent path; the microfluidic channel structures between different groups are separated from each other, and their respective arrangement areas correspond to the lead frame layer and chip position on the upper surface of the wafer;

[0027] (7) Using sintering, welding or metal bonding processes, the chip is mounted on the lead frame layer according to the planned scheme to obtain a circuit-heat sink monolithic integrated substrate based on a semiconductor substrate.

[0028] As a preferred embodiment of the present invention, the epitaxial growth process for preparing the insulating epitaxial layer is any one or more of the following: physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) or hydride vapor phase epitaxy (HVPE); the epitaxial growth process for preparing the first metal film is any one or more of the following: physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD); the epitaxial growth process for preparing the second metal film is any one or more of the following: physical vapor deposition (PVD), chemical vapor deposition (CVD) or electroplating.

[0029] Technical principle description:

[0030] 1. Heat sink technology refers to the use of radiators or other heat dissipation structures in electronic devices to effectively conduct and disperse the generated heat to maintain the normal operating temperature of the device. Heat sink technology is particularly important for high-power chips because high-power chips generate a lot of heat during operation. If the heat cannot be effectively dissipated, it will lead to device performance degradation or even damage. Optimizing the heat dissipation solution is crucial to ensure the long-term stable operation of high-power chips. A good heat dissipation solution can not only reduce chip temperature, improve device performance and reliability, but also extend the service life of the chip. Therefore, a well-designed heat dissipation solution is an indispensable part of electronic device design. Its key strategies generally include the application of technologies such as thermal conductive material selection, heat dissipation structure design, temperature monitoring and control, and thermal interface material application.

[0031] In current power chip packaging technology, power semiconductor chips typically utilize a DBC (direct-bonded copper ceramic) substrate as a carrier, onto which the chip is soldered or sintered, with a heat sink attached to the back. The basic structure of a DBC substrate is a three-layer "copper-ceramic-copper" structure. The ceramic layer is produced using a tape-casting process, copper foil is bonded to both sides of the ceramic by hot pressing and sintering, and then the copper layer is etched to form a metallic pattern. Functionally, the copper and ceramic layers can only perform their respective functions of electrical conductivity, insulation, and thermal conductivity. To achieve heat dissipation, an additional heat sink must be added through welding or silicone grease bonding, which introduces a new thermal interface material and increases the thermal resistance.

[0032] 2. It is worth noting that fabricating microfluidics directly within or on the backside of a semiconductor substrate with a built-in leadframe is a relatively novel design concept with the potential to overcome thermal management challenges encountered under localized high heat flux densities in small and miniaturized systems. However, this design concept is only applicable in the chip manufacturing sector. This is primarily because after chip processing, a substantial amount of unused substrate layer often remains beneath the functional layers, allowing this layer to be directly used to fabricate microfluidic heat dissipation structures. However, even within the chip manufacturing sector, this structure and processing method have significant limitations. In terms of applicability, this process is only suitable for relatively simple planar chips (including analog and digital chips). Because the circuitry flows only on the surface of the semiconductor substrate and the operating voltage and current are generally low, insulation issues do not arise, allowing the substrate layer to be utilized. In the power semiconductor sector, however, power chips (such as SiC MOSFETs, SiC IGBTs, SiMOSFETs, Si IGBTs, and SiC SBDs) typically have vertical conductive structures (i.e., conductive pads on both the front and back sides of the chip). After chip processing, there is little remaining substrate available for fabricating microfluidic heat dissipation structures. In addition, power chips usually have an operating voltage of thousands of volts and an operating current of hundreds of amperes. In such complex high-voltage and high-current application scenarios, it is impossible to make a microchannel heat sink inside the chip, otherwise it will be easily broken down under high voltage conditions.

[0033] Not only that, in terms of application methods, this process is also limited to single-sided pin application scenarios. Because once the back is equipped with a microchannel heat sink, coolant needs to be passed through for heat dissipation, so that the conductive pins cannot be led out. In the field of power semiconductors, the back pins of the power chip usually need to be connected to the lead frame of the substrate by welding or sintering, and then the lead frame leads the back pins to the external circuit. Therefore, this makes it impossible for the power chip to directly integrate a microchannel heat sink inside or on the back, so the industry usually does not consider continuing to process the heat sink structure based on the wafer used to prepare the power chip.

[0034] To address this issue, the present invention innovatively proposes growing a leadframe directly on the surface of a semiconductor substrate using a large-scale on-chip metal epitaxy process. It should be noted that the semiconductor substrate in this case has no electrical properties and merely serves as a base for supporting the leadframe. This structural design allows the chip to be sintered onto the leadframe on the semiconductor substrate, and then a microchannel heat sink can be fabricated on the back of the semiconductor substrate using etching techniques. However, even this structure cannot address the impact of the high-voltage and high-current characteristics of power chips. Because the leadframe and chip pads are at the same electrical potential, when multiple chips are operating (power semiconductor chips are typically connected to form a specific circuit topology), the semiconductor substrate cannot withstand such a high potential difference, posing a risk of breakdown. Therefore, to further improve the product structure, the present invention further proposes adding an insulating medium between the leadframe and the semiconductor substrate to decouple the cooling layer from the circuit layer. Obviously, traditional insulation solutions such as ceramics and thermal grease are not suitable for this monolithic integration scenario. To this end, the present invention innovatively proposes epitaxially growing an insulating film layer on the surface of the semiconductor substrate to mitigate the effects of high voltage while also providing insulation between the leadframes and between the leadframe and the heat sink. A metal leadframe is then grown on the surface of the insulating epitaxial layer, achieving monolithic integration of the leadframe, insulating film, and microchannel heat sink.

[0035] It is worth noting that the above innovative solution involves major technical difficulties: semiconductor substrates are usually made of hard and brittle materials, which are difficult to process and easily damaged. Therefore, in production practice, they are rarely used alone to be processed into heat dissipation structures such as microchannels. Due to this characteristic of semiconductor substrates, compared with traditional ceramic substrates, the large-scale metal lead frame grown on the semiconductor substrate in the present invention needs to overcome the problem that the heat sink part of the integrated product is prone to warping and fragmentation due to the large difference in thermal stress and mechanical stress between the two layers of materials. In order to meet the requirements of pin welding and large current paths of power semiconductor chips, the metal lead frame is usually more than 30μm thick. The thermal stress generated during the preparation and use process can easily lead to problems such as delamination, warping and even substrate fragmentation. To solve this problem, the present invention further proposes an innovative solution. By adding a buffer metal layer with a medium thermal expansion coefficient between the insulating epitaxial layer of the semiconductor substrate and the grown metal layer, the thermal stress between the two interfaces can be effectively alleviated, thereby greatly reducing or even eliminating the risk of delamination and fragmentation. Here, the thermal expansion coefficient of the buffer metal layer should generally be within the average value range of the materials on both sides. For the growth of metal layers with greater thickness, a buffer layer with a gradient thermal expansion coefficient can also be used to achieve a better buffering effect.

[0036] 3. The present invention uses a semiconductor substrate as a starting carrier, on which a microfluidic heat sink is fabricated through an etching process. An insulating layer is then epitaxially grown on the wafer (a circular semiconductor substrate). A buffer metal layer and a lead frame layer are then fabricated through processes such as PVD (physical vapor deposition), electroplating, and etching. This innovatively integrates the four core structures of the lead frame layer, buffer metal layer, insulating epitaxial layer, and heat sink onto the same substrate. Traditionally, the substrate and heat sink are separate and then later combined to introduce a connection interface, increasing both the conductive and contact thermal resistances. The proposed substrate circuit and heat sink are integrated during the processing phase, eliminating the contact thermal resistance associated with heat transfer from the circuit layer to the heat sink and improving heat dissipation efficiency.

[0037] The semiconductor-based circuit-heat sink monolithic integrated substrate proposed in this invention comprises four main structures: a semiconductor substrate, an insulating epitaxial layer, a buffer metal layer, and a leadframe layer. It is suitable for module-level and system-level packaging of various complex chips, including power chips. By innovatively introducing micro-nanofabrication technologies such as heteroepitaxial growth into the packaging field, epitaxial growth is achieved on the surface of the semiconductor substrate. The resulting thermal interface (insulating epitaxial layer) differs from ceramic thermal interfaces produced by tape casting. The epitaxially grown material typically exhibits highly consistent crystal orientation and minimal lattice defects, resulting in higher thermal conductivity and lower thermal resistance. Furthermore, the atomic-level layer-by-layer growth avoids intergranular voids within the insulating layer and between the insulating layer and the adjacent materials, completely eliminating contact thermal resistance. By combining epitaxial growth with photolithography and etching processes to create a fan-out metal leadframe, it can also support the electrical interconnection of multiple power chips in complex circuit topologies. This demonstrates that this technology is not limited to power module-level packaging but also has the potential to directly enable system-level packaging. In addition, the innovative introduction of a buffer metal layer enables compatible integration of large-scale metal lead frames and semiconductor substrates, greatly eliminating the risk of fragmentation and improving the reliability of the substrate.

[0038] Therefore, the present invention breaks through the inherent design thinking of technical personnel in this field, breaks through the traditional design method of designing the circuit structure and the heat dissipation structure separately and then combining them, and innovatively replaces the traditional welding and bonding processing methods with micro-nano processing technologies such as heteroepitaxiality. It develops a circuit-heat sink monolithic integrated substrate in which the microchannel structure, insulating epitaxial layer, buffer metal layer and lead frame layer are prepared on the same wafer, which can realize the monolithic integration of the circuit and cooling structure in the power chip packaging substrate, and at the same time optimizes the conduction thermal resistance and contact thermal resistance.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] 1. The semiconductor-based circuit-heat sink monolithic integrated substrate proposed in this invention utilizes a wafer-level integrated on-chip growth process. This process involves simultaneously fabricating the circuit and microfluidic heat sink on the semiconductor substrate, eliminating gaps between the layers and achieving a more tightly integrated structure. In traditional packaging, the layers are typically connected by bonding or welding, often resulting in numerous gaps between the layers (e.g., loose bonding or weld voids). These gaps introduce significant interfacial thermal resistance, limiting the package's heat dissipation efficiency. However, through this integrated growth method, the resulting layers are tightly interconnected at the molecular scale, thus avoiding this problem.

[0041] 2. The circuit-heat sink monolithic integrated substrate based on a semiconductor substrate proposed in the present invention eliminates the need for thermal interface materials compared to traditional liquid cooling structures, allowing the package to maintain extremely low conduction thermal resistance. In traditional packaging, in order to achieve electrical insulation between the liquid cooling radiator and the chip, a layer of thermal interface material is usually added between the radiator and the package shell. The thermal conductivity coefficient of the thermal interface material is usually only 0.8~3W / (mK), and the thickness is usually around 100μm. Therefore, a large conduction thermal resistance is introduced, which is an unavoidable bottleneck in traditional liquid cooling structures. In the circuit-heat sink monolithic integrated substrate based on a semiconductor substrate proposed in the present invention, insulation between the circuit and the microchannel is achieved by epitaxially growing an insulating layer between the microchannel and the electrical functional layer, thereby eliminating the traditional thermal interface and allowing the package to maintain extremely low conduction thermal resistance.

[0042] 3. The circuit-heat sink monolithic integrated substrate based on a semiconductor substrate proposed in the present invention proposes a method of adding a buffer metal layer to solve the problem that large-scale metal lead frames grown on semiconductor substrates generate large thermal stress and mechanical stress, which leads to substrate fragmentation and warping. By adding a layer of buffer metal with a medium thermal expansion coefficient between the insulating epitaxial layer of the semiconductor substrate and the grown metal layer, the thermal stress between the two interfaces can be effectively alleviated, thereby reducing or even eliminating the risk of delamination and fragmentation. Here, the thermal expansion coefficient of the buffer metal layer should generally be within the average value range of the materials on both sides. For the growth of metal layers with greater thickness, a buffer layer with a gradient thermal expansion coefficient can be designed to achieve a better buffering effect.

[0043] 4. The present invention proposes an electrical and thermal collaborative design method based on a circuit-heat sink monolithic integrated substrate structure. This method can achieve point-to-point near-junction cooling of local hotspots in highly integrated circuit systems. The advantages of this method are even more pronounced in complex circuit systems with uneven hotspot distribution. This method enhances the coupling between the circuit layout and the thermal management system. During the design process, by collaboratively designing the microchannel layout and the chip layout, precise local hotspot cooling can be achieved in complex circuit systems.

[0044] 5. The substrate structure and design methods proposed in this invention are easily compatible with various existing subsequent packaging processes. The substrate features a specifically patterned metal lead frame, allowing for convenient soldering or sintering of power chips. Furthermore, the substrate's inherent microfluidic structure eliminates the need for a separate heat sink. Therefore, after processing, the substrate can be directly used as a subsequent packaging substrate, enabling subsequent packaging preparation and circuit application without changing conventional packaging design methods.

[0045] 6. The present invention uses wafer-level and MEMS processes to prepare each functional layer. Therefore, the substrate process is highly compatible with traditional micro-nano processing technology, and can achieve a high degree of integration between the substrate process and the chip processing process. Without affecting the electrical design of the chip, by adding circuit wiring epitaxy and microchannel preparation steps, the microchannel cooling process, packaging circuit wiring process, and chip manufacturing process can be integrated. Therefore, this technology is expected to achieve a more integrated chip-circuit-heat sink monolithic integration technology in the future, and is also expected to achieve chip-wiring-thermal management collaborative design in the chip design process.

[0046] 7. Based on the above advantages, the present invention enables monolithic integration of circuits and cooling structures within a power chip package substrate, while simultaneously optimizing both conductive and contact thermal resistances. Given its adaptability to high-voltage, high-current operating environments, the present invention is suitable for the application of a variety of high-heat-flux-density chips in highly integrated circuit systems, including but not limited to vertical power semiconductor chips in power electronic converter systems and planar analog or digital semiconductor chips in integrated circuit systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A cross-sectional view of a circuit-heat sink monolithic integrated substrate based on a semiconductor substrate according to the present invention;

[0048] Figure 2 A wafer used as a semiconductor substrate;

[0049] Figure 3 for Figure 2 Schematic diagram of a local section.

[0050] Figure 4 is a schematic diagram of forming an insulating epitaxial layer on the upper surface of a wafer;

[0051] Figure 5 for Figure 4 Schematic diagram of a local section.

[0052] Figure 6 is a schematic diagram of forming a first metal film on the upper surface of the insulating epitaxial layer;

[0053] Figure 7 for Figure 6 Schematic diagram of a local section.

[0054] Figure 8 A schematic diagram showing a second metal film formed on the upper surface of the first metal film and simultaneously etched;

[0055] Figure 9 for Figure 8 Schematic diagram of a local section.

[0056] Figure 10 Schematic diagram of forming a microfluidic channel structure on the lower surface of a wafer;

[0057] Figure 11 for Figure 10 Schematic diagram of a local section.

[0058] Figure 12 A schematic diagram of mounting a chip on the upper surface of a lead frame layer;

[0059] Figure 13 for Figure 12 Schematic diagram of a local section.

[0060] Figure 14 Schematic diagram of independently grouped microfluidic channel structures on a semiconductor substrate.

[0061] Figure 15 Schematic diagram of the grouping and correspondence between the active circuit layer and the microfluidic channel structure.

[0062] Figure 16 Schematic diagram of the internal channel of the collecting plate.

[0063] Figure 17 This is an example diagram of a wire bonding package obtained based on the substrate of the present invention.

[0064] Figure 18 This is an example diagram of a substrate embedded package obtained based on the substrate of the present invention.

[0065] The reference numerals in the figure are: semiconductor substrate 1; insulating epitaxial layer 2; buffer metal layer 3; lead frame layer 4; 101 is a microchannel structure; 102 is a current collecting plate; 103 is a water inlet; 104 is a water outlet; 105 is a coolant inflow path; 106 is a coolant outflow path; 107 is a microchannel structure cooling area; 501 is a chip, 502 is a chip; 503 is a bonding wire; 504 is a blind hole; 505 is a copper pad; 506 is a redistribution layer (RDL); 507 is a plastic encapsulation filler; 508 is a package terminal; 509 is a chip heat concentration area. DETAILED DESCRIPTION

[0066] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are further described in detail below with reference to the accompanying drawings.

[0067] The serial numbers assigned to components in this application, such as "first" and "second", are used only to distinguish the objects being described and do not have any order or technical meaning. The terms "connection" and "coupling" used in this application include both direct and indirect connections (couplings) unless otherwise specified. In the description of this application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc., indicating positions or positional relationships, are based on the positions or positional relationships shown in the accompanying drawings and are intended only to facilitate the description of this application and simplify the description. They do not indicate or imply that the device or element referred to must have a specific position, be constructed and operate in a specific position, and therefore should not be understood as limiting this application.

[0068] In this application, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0069] 1. Specific description of product structure

[0070] like Figure 1As shown, the semiconductor-based circuit-heat sink monolithic integrated substrate of the present invention has a multi-layer structure, comprising, from bottom to top, a semiconductor substrate 1, an insulating epitaxial layer 2, a buffer metal layer 3, and an active circuit layer. The semiconductor substrate 1 is a ground and polished wafer with microchannel structures 101 on its interior and lower surface for coolant circulation. The insulating epitaxial layer 2 is epitaxially grown onto the upper surface of the semiconductor substrate 1, and the buffer metal layer 3 is deposited onto the upper surface of the insulating epitaxial layer 2 and etched to form a pattern. The active circuit layer includes bare power chips (such as chips 501 and 502) and a metal leadframe layer 4, which are connected to implement circuit functions. The leadframe layer 4 is attached to the surface of the buffer metal layer 3 using one or more processes such as PVD (physical vapor deposition), CVD (chemical vapor deposition), and electroplating, and is etched to form a pattern identical to that of the buffer metal layer 3. The wiring portions of the power chips are electrically connected to the leadframe layer 4 via welding, sintering, or bonding. The buffer metal layer 3, the active circuit layer and the microfluidic structure 101 are divided into multiple groups, and each group is independent and not connected to each other; the microfluidic structure 101 is formed on the lower surface of the semiconductor substrate 1 by etching, and the internal flow channel of each group of microfluidic structure 101 forms a coherent passage, and the arrangement area of each group of microfluidic structures 101 corresponds to the area where each group of lead frame layers 4 on the upper surface of the semiconductor substrate 1 is located.

[0071] Since the materials used for the insulating epitaxial layer 2 and the lead frame layer 4 have a serious mismatch in thermal expansion coefficients and there is a huge thermal stress, a buffer metal layer 3 is designed between the two; the thermal expansion coefficients of the insulating epitaxial layer 2, the buffer metal layer 3, and the lead frame layer 4 increase in sequence, and the thermal expansion coefficient of the buffer metal layer 3 is in the middle range to buffer thermal stress and strain. The buffer metal layer 3 can be a single-component material, such as a metal, a metal oxide, or a metal-ceramic composite material. Alternatively, a more sophisticated solution can be adopted to design the buffer metal layer 3 to be composed of multiple components, each component is arranged in a layered manner, and the thermal expansion coefficient of each layer increases sequentially from bottom to top. Among them, the component located in the bottom layer has a thermal expansion coefficient close to that of the insulating epitaxial layer 2, and the component located in the top layer has a thermal expansion coefficient close to that of the lead frame layer 4, so as to achieve a gradient buffering effect.

[0072] In the active circuit layer, the lead frame layer 4 will have more layout area relative to the chip. In order to reduce the etching area, maintain the strength of the semiconductor substrate 1, and realize targeted point-to-point cooling at the same time, the layout scheme of the microfluidic structure 101 can be designed accordingly according to the layout scheme of the upper surface lead frame layer 4 and the chip. For the area on the cutting line or the edge of the wafer, there is no need to arrange the etching area. Even in the microfluidic structure 101 in the area where the same group of lead frame layers are located, the arrangement of the internal flow channels can be uneven, and the arrangement density of the flow channels can be greater than the non-installed chip position corresponding to the position where the chip is installed. Targeted arrangement of the chip and the microfluidic structure 101 to achieve point-to-point local near-junction cooling helps to improve the energy efficiency ratio of the cooling system, that is, to cool higher heat at lower pumping power.

[0073] Based on the circuit-heat sink monolithic integrated substrate of the present invention, it is also possible to connect the subsequent packaging process to obtain an integrated package with an integrated cooling system. The substrate designed by the present invention has structural universality, and the subsequent packaging process connected can be a packaging method based on wire bonding ( Figure 17 ), or it can be a fan-out embedded packaging method based on blind vias and rewiring layers ( Figure 18 ). In addition, the packaging structures that can be realized based on the present invention are not limited to the two above. For example, by using a plastic encapsulation filler 507 to plastic-encapsulate the substrate front structure including the chip 501 and the lead frame layer 4, providing a blind hole 504 and a redistribution layer 506 electrically connected to the chip above the chip, and connecting a collector plate 102 for enclosing the microchannel structure 101 below the semiconductor substrate 1, a cooling system integrated packaging structure based on a semiconductor wafer substrate can be obtained. If the wafer structure is cut into pieces, multiple packaging structures with independent functions can be obtained. If a system-level circuit design is performed on the wafer structure, a large-scale integrated packaging module with complex integrated functions can also be obtained.

[0074] In the present invention, the semiconductor substrate 1 can be made of silicon, diamond, or silicon carbide; the insulating epitaxial layer 2 can be made of one or more of aluminum nitride, diamond, silicon carbide, and aluminum oxide; the buffer metal layer 3 can be made of at least one of a metal, a metal oxide, and a metal-ceramic composite; the lead frame layer 4 can be made of copper, silver, or gold; and the power chip can be silicon-based, silicon carbide-based, or gallium nitride-based, with either vertical or planar conductivity. The current collecting plate 102 can be made of epoxy resin, copper, aluminum, or polydimethylsiloxane (PDMS). The current collecting plate 102 is fixedly connected to the lower surface of the semiconductor substrate 1 by adhesive bonding, welding, or welding, and seals the microchannel structure 101. The current collecting plate 102 is provided with a water inlet 103 and a water outlet 104.

[0075] 2. Description of product preparation method

[0076] 1. If Figure 2-Figure 15 The method for preparing the circuit-heat sink monolithic integrated substrate of the present invention comprises the following steps:

[0077] (1) Select wafers of appropriate size and thickness ( Figure 2 、 Figure 3 ), after grinding and polishing, an insulating epitaxial layer 2 is prepared on its upper surface by one or more processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), hydride vapor phase epitaxy (HVPE), etc. ( Figure 4 、 Figure 5 );

[0078] (2) In the effective arrangement area on the upper surface of the insulating epitaxial layer 2, multiple groups of independently arranged buffer metal layers 3, lead frame layers 4, and chips are planned; multiple groups of correspondingly arranged microfluidic structures 101 are planned on the semiconductor substrate; during the design process, the electrical and thermal coordinated design of the chip and the microfluidic structure should be considered. Among them, the lead frame layer 4 and the buffer metal layer 3 have the same pattern; the flow channels of the microfluidic structure 101 are arranged non-uniformly, and their arrangement area corresponds to the arrangement area of the lead frame layer 4 and the chip, so as to achieve point-to-point local near-junction cooling ( Figure 14 、 Figure 15 );

[0079] (3) In the effective arrangement area on the upper surface of the insulating epitaxial layer 2, a first metal film for preparing the buffer metal layer 3 is formed by one or more processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). Figure 6 、 Figure 7 ), waiting for subsequent etching to form a pattern;

[0080] (4) In the same area on the upper surface of the first metal film, a second metal film for preparing the lead frame layer 4 is formed by one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD) or electroplating processes, and then the first metal film and the second metal film are etched simultaneously by combining a photolithography mask with an etching process to form N groups of buffer metal layers 3 and lead frame layers 4 having the same pattern ( Figure 8 、 Figure 9 );

[0081] (6) Flip the wafer and use a combination of photoresist mask and etching process to make N groups of microfluidic channel structures 101 in the effective arrangement area on the bottom surface of the wafer. The flow channels inside each group of microfluidic channel structures 101 form a coherent path ( Figure 10 、 Figure 11The micro-channel structures 101 in different groups are independent of each other, and their respective arrangement areas correspond to the lead frame layer 4 and the position of the chip on the upper surface of the wafer ( Figure 14 、 Figure 15 );

[0082] (7) Flip the wafer again, and use sintering, welding or metal bonding technology to mount the chip on the lead frame layer 4 according to the planned scheme to obtain a circuit-heat sink monolithic integrated substrate based on a semiconductor substrate ( Figure 12 、 Figure 13 This substrate can easily be integrated with various subsequent packaging processes to create different types of packaging structures. For example, by adding bonding wires, blind vias, and rewiring layers to the active circuit layer and leading out the chip pins, a variety of packaging structures can be obtained that can be directly used.

[0083] 2. Figure 17 Taking the example of FIG. 1 , based on the circuit-heat sink monolithic integrated substrate of the present invention, a wire bonding package based on the power device used can be further prepared, including the following steps:

[0084] (1) Add bonding wires 503 to the chip 501 and the lead frame layer 4 according to the design plan;

[0085] (2) Laminating or pouring plastic encapsulation filler 507 into the gaps and cavities in the upper structure of the substrate;

[0086] (3) Installing the current collecting plate 102 on the outside of the microchannel structure by means of bonding, gluing or welding;

[0087] (4) The composite substrate is divided into multiple independent units by cutting or dicing, each unit being a power device packaging structure with independent functions; each independent packaging structure has a collector plate 102 to realize the inflow and outflow of the coolant ( Figure 16 ).

[0088] 3. Figure 18 Taking the example of FIG. 1 as an example, based on the circuit-heat sink monolithic integrated substrate of the present invention, a substrate embedded package based on the power device used can be further prepared, including the following steps:

[0089] (1) First, a number of copper pads 505 having a height close to that of the chip are mounted on the lead frame layer 4 of the substrate by sintering, welding, etc.;

[0090] (2) Laminating or pouring plastic encapsulation filler 507 into the gaps and cavities in the upper structure of the substrate to completely cover the chip 501, the copper pad 505 and the lead frame layer 4;

[0091] (3) According to the design plan, blind holes 504 and a redistribution layer 506 are prepared above the plastic encapsulation filler 507 at the corresponding positions of the chip 501 and the lead frame layer 4 by combining laser drilling, electroplating, photolithography and etching;

[0092] (4) Installing the current collecting plate 102 on the outside of the microchannel structure by means of bonding, adhesive bonding or welding;

[0093] (5) The composite substrate is divided into multiple independent units by cutting or dicing, each unit being a power device packaging structure with independent functions; each independent packaging structure has a collector plate 102 to realize the inflow and outflow of the coolant ( Figure 16 ).

[0094] 4. It is understandable that if the system-level circuit design is based on the wafer structure, Figure 17 、 18 In the example of the present invention, after the circuit-heat sink monolithic integrated substrate is packaged, a large package module with complex integrated functions can be obtained without any cutting process.

[0095] 5. In preparing the integrated substrate, the present invention adopts epitaxial growth processes (such as PVD, CVD, ALD, HVPE, electroplating, etc.) and photolithography, etching and other processes commonly used in the chip manufacturing field, and also uses other commonly used circuit substrate integrated packaging technologies; the present invention does not make special requirements on the specific operating details of these processes, so they will not be repeated.

[0096] 3. More specific product or processing details

[0097] 1. In the semiconductor substrate-based circuit-heat sink monolithic integrated substrate of the present invention, each layer structure does not use welding, bonding and other processes commonly used in traditional power chip packaging technology, but is formed by wafer-level metallization technology.

[0098] The semiconductor substrate 1 serves as the substrate for the insulating epitaxial layer 2 and provides a preparation carrier for the microchannel heat sink structure, that is, the semiconductor substrate 1 serves as a common substrate for the circuit structure and the cooling structure. The microchannel structure 101 is located inside the semiconductor substrate 1 and is formed by a deep etching process. The position of the microchannel precisely corresponds to the heat source area of the circuit chip to achieve local high-temperature near-junction cooling. The semiconductor substrate 1 is preferably made of silicon to obtain a larger microchannel aspect ratio; its upper and lower surfaces should be polished surfaces, and its surface roughness should be as small as possible to reduce the interface thermal resistance and achieve a good on-chip growth effect. The microchannel structure 101 can optionally be composed of a plurality of parallel grooves arranged end to end.

[0099] The insulating epitaxial layer 2 is used to achieve insulation between the microchannel structure 101 and the active circuit layer and is formed by an epitaxial growth process. The thickness of the insulating epitaxial layer 2 should be sufficient to withstand the chip voltage.

[0100] The buffer metal layer 3, located between the active circuit layer and the insulating epitaxial layer, is formed through an epitaxial growth process. It is composed of a metal (such as titanium, molybdenum, etc.), a metal oxide, or a metal-ceramic composite material with a thermal expansion coefficient between the two. It can also be formed through a wafer-level metallization process. The presence of the buffer metal layer 3 alleviates the thermal expansion coefficient mismatch between the insulating epitaxial ceramic layer and the active circuit metal layer, thereby reducing thermal stress and preventing substrate cracking.

[0101] The chip is attached to the leadframe layer 4 through methods such as nanosilver sintering, welding, and metal bonding to implement circuit functions. The leadframe layer 4 is formed through an epitaxial growth process. The leadframe layer 4 should have sufficient current capacity and be thick enough to withstand the current flowing through the substrate.

[0102] The structural design of the present invention is first of all aimed at the application of power chips, whose types include but are not limited to silicon-based, silicon carbide-based, and gallium nitride-based power chips. Their conductive types can be vertical (chip electrodes are distributed on both the front and back sides of the chip) and planar (chip electrodes are only distributed on one side of the chip). Of course, analog chips or digital chips can be arranged according to actual needs. The lead frame layer 4 is designed with a pattern according to the requirements of the power chip function and is matched with different numbers and types of chips. A variety of circuit functions can be combined. For example, a circuit structure can be composed of multiple areas, and different metal areas are not connected to each other to achieve insulation between different chips.

[0103] The thickness of each layer can be selected as follows: 100-1000μm for the semiconductor substrate, 1-100μm for the insulating epitaxial layer, 1-100μm for the buffer metal layer, and 10-300μm for the lead frame layer. The thickness range of each layer should be properly matched, otherwise excessive thermal stress will be generated due to thermal expansion coefficient mismatch, leading to delamination and cracking defects.

[0104] The collecting plate 102 includes an inlet 103 and an outlet 104 which are not connected to each other; the coolant flows from the inlet 103 through the coolant inflow path 105 into different microchannel areas, and then converges to the outlet 104 through the coolant outflow path 106 .

[0105] like Figure 14 、 Figure 15As shown, the microfluidic structure 101, the lead frame layer 4, and the chips 501 and 502 are all located in the effective arrangement area of the semiconductor substrate 1, and are arranged one by one to form N independent and evenly arranged unit structures. The number N is determined by the size of the selected semiconductor substrate and the size of the designed unit structure. Each unit structure has the same hierarchical arrangement relationship, but the structural components and connection methods in different unit structures remain consistent or different according to the design scheme. Adjacent unit structures can be separated by cutting or dicing. For example, in this substrate structure, the chips 501 and 502 in different unit structures can be different; and based on the differences between the chips 501 and 502, the design of the lead frame layer 4 pattern may also change accordingly. Such a design can realize the design and production of multiple circuit layouts on the same semiconductor substrate 1, thereby providing flexibility in design and production.

[0106] Figure 17 、 18 This is an actual packaging application example based on the circuit-heat sink monolithic integrated substrate of the present invention. The given structure is only for demonstrating the adaptability and rationality of the circuit-heat sink monolithic integrated substrate and various packaging solutions.

[0107] For example, Figure 18 The example shown in the figure is an integrated liquid-cooled embedded package structure based on the circuit-heat sink monolithic integrated substrate of the present invention, connected through lamination or injection molding, laser drilling, and redistribution layer processes. The example structure shown in the figure includes, from top to bottom, a redistribution layer 506, blind vias 504, plastic encapsulation filler 507, chip 501, copper pads 505, leadframe layer 4, buffer metal layer 3, insulating epitaxial layer 2, semiconductor substrate 1, microchannel structure 101, and current collector plate 102, forming a multilayer plate-like structure. Figure 18 The example is a half-bridge power module composed of two power MOSFET chips connected in series, but the present invention does not limit the module function and chip type. The pattern of the lead frame layer 4 and the redistribution layer 506 can be determined according to the module function, chip type and chip connection method. The number, position and layout of the chips 501 and the corresponding microchannel structure 101 can be determined according to the function to be achieved by the module. Figure 18 In this example, chip 501 is a vertical power MOSFET chip with electrodes located on both the front and back sides of the chip. The MOSFET drain is located on the back side of the chip, while the MOSFET source and gate are located on the front side. The MOSFET chip's drain (back side) is directly connected to leadframe layer 4 via solder or silver sintering, while the MOSFET chip's source (front side) is connected to redistribution layer 506 via blind vias 504. Finally, the chip's pins are connected to the outside through various regions of redistribution layer 506.

[0108] In summary, the present invention applies wafer-level on-chip growth technology and MEMS technology to achieve monolithic integration of cooling structure and circuit structure based on the same semiconductor substrate, and proposes an electro-thermal collaborative design and preparation method for cooling structure and circuit structure; the proposed substrate structure eliminates the thermal interface layer of each layer to the greatest extent, and can maintain extremely low interface thermal resistance; the proposed substrate adopts an original electro-thermal collaborative design method, which can achieve precise local hotspot cooling in complex circuit systems with uneven hotspot distribution.

[0109] The circuit-heat sink monolithic integrated substrate based on a semiconductor substrate proposed in the present invention has the advantages of small size, light weight, and high integration. In addition, the electrical and thermal collaborative design methods of the substrate structure are flexible and diverse. Without affecting the electrical design of the chip, by adding a microchannel preparation process, the microchannel preparation process, the packaging circuit wiring process, and the chip connection process can be integrated. Therefore, under the premise of this high degree of process collaboration, this technology is expected to achieve a more integrated chip-circuit-heat sink monolithic integration technology in the future, and it is also expected to achieve chip-wiring-thermal management collaborative design in the chip design link.

[0110] The above description is only a preferred embodiment of the present invention. It is understood that the above description is exemplary and not exhaustive, and cannot be understood as limiting the present invention. The scope of protection of the present invention is not limited thereto. Any process change, structural change, material change or process replacement that can be easily thought of by any person skilled in the art within the technical scope disclosed by the present invention should be included in the scope of protection of the present invention. It should be understood by those skilled in the art that in the embodiments given in the present invention, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by the process conditions during actual execution.

Claims

1. A circuit-heat sink monolithic integrated substrate based on a semiconductor substrate, characterized in that: The integrated substrate has a multi-layer structure, including a semiconductor substrate, an insulating epitaxial layer, a buffer metal layer and an active circuit layer arranged in sequence from bottom to top; The semiconductor substrate is a ground and polished wafer having a micro-channel structure for cooling liquid circulation inside or on the lower surface thereof; An insulating epitaxial layer is attached to the upper surface of the semiconductor substrate by epitaxial growth; A buffer metal layer is attached to the upper surface of the insulating epitaxial layer by epitaxial growth and is etched to form a pattern; The active circuit layer includes a bare-die power chip and a metal lead frame layer, which are connected to realize the circuit function. The lead frame layer is attached to the surface of the buffer metal layer by epitaxial growth and etched to form the same pattern as the buffer metal layer. The chip pins and the lead frame layer are electrically connected by welding, sintering or bonding. The buffer metal layer, active circuit layer and microfluidic structure are divided into multiple groups, and each group is independent and not connected to each other; the internal flow channels of each group of microfluidic structures form a coherent passage, and the arrangement area of each group of microfluidic structures corresponds to the area where the lead frame layer is located on the upper surface of the semiconductor substrate.

2. The circuit-heat sink monolithic integrated substrate according to claim 1, characterized in that: The thermal expansion coefficients of the insulating epitaxial layer, the buffer metal layer, and the lead frame layer increase sequentially, and the thermal expansion coefficient of the buffer metal layer is in the middle range for buffering thermal stress and strain; alternatively, the buffer metal layer is composed of multiple components, each component is arranged in a layered manner and the thermal expansion coefficient of each layer increases sequentially from bottom to top; the component located in the bottom layer has a thermal expansion coefficient close to that of the insulating epitaxial layer, and the component located in the top layer has a thermal expansion coefficient close to that of the lead frame layer.

3. The circuit-heat sink monolithic integrated substrate according to claim 1, characterized in that: The arrangement of the flow channels in each group of micro-channel structures is uneven. In the lead frame layer area corresponding to the chip installation, the arrangement density of the flow channels is greater than that in the non-chip installation position.

4. The circuit-heat sink monolithic integrated substrate according to claim 1, characterized in that: The microchannel structure is arranged on the lower surface of the semiconductor substrate by etching, and the collecting plate is fixedly connected to the lower surface of the semiconductor substrate by bonding, welding or adhesion and seals the microchannel structure. The collecting plate is provided with a water inlet and a water outlet.

5. The circuit-heat sink monolithic integrated substrate according to claim 4, characterized in that: The material of the current collecting plate is any one of epoxy resin, copper, aluminum or polydimethylsiloxane.

6. The circuit-heat sink monolithic integrated substrate according to claim 1, characterized in that: The material of the semiconductor substrate is silicon, diamond or silicon carbide; the material of the insulating epitaxial layer is one or more of aluminum nitride, diamond, silicon carbide or aluminum oxide; the material of the buffer metal layer is at least one of metal, metal oxide and metal-ceramic composite material; the material of the lead frame layer is copper, silver or gold; the power chip is a silicon-based, silicon carbide-based or gallium nitride-based chip, and its conductivity type is vertical or planar.

7. A method for preparing a circuit-heat sink monolithic integrated substrate according to any one of claims 1 to 6, characterized in that: The following steps are involved: (1) Select a wafer of appropriate size and thickness as the semiconductor substrate, grind and polish it, and then prepare an insulating epitaxial layer on its upper surface through an epitaxial growth process; (2) In the effective arrangement area on the upper surface of the insulating epitaxial layer, multiple groups of buffer metal layers, lead frame layers, and chips are planned that are independently arranged; corresponding multiple groups of microchannel structures are planned on the semiconductor substrate; wherein the lead frame layer and the buffer metal layer have the same pattern; the flow channels of the microchannel structure are arranged non-uniformly, and their arrangement area corresponds to the arrangement area of the lead frame layer and the chip, so as to achieve point-to-point local near-junction cooling; (3) forming a first metal film for preparing a buffer metal layer by an epitaxial growth process in an effective arrangement area on the upper surface of the insulating epitaxial layer; (4) forming a second metal film for preparing a lead frame layer in the same area on the upper surface of the first metal film by an epitaxial growth process; (5) using a combination of a photolithography mask and an etching process to simultaneously process the first metal film and the second metal film to form a buffer metal layer and a lead frame layer having the same pattern; (6) Using a combination of photoresist mask and etching process, multiple groups of microfluidic channel structures are produced in the effective arrangement area of the bottom surface of the wafer, and the flow channels within each group of microfluidic channels form a coherent path; the microfluidic channel structures between different groups are separated from each other, and their respective arrangement areas correspond to the lead frame layer and chip position on the upper surface of the wafer; (7) Using sintering, welding or metal bonding processes, the chip is mounted on the lead frame layer according to the planned scheme to obtain a circuit-heat sink monolithic integrated substrate based on a semiconductor substrate.

8. The method according to claim 7, characterized in that The epitaxial growth process for preparing the insulating epitaxial layer is any one or more of the following: physical vapor deposition, chemical vapor deposition, atomic layer deposition or hydride vapor phase epitaxy; The epitaxial growth process for preparing the first metal film is any one or more of the following: physical vapor deposition, chemical vapor deposition or atomic layer deposition; The epitaxial growth process for preparing the second metal film is any one or more of the following: physical vapor deposition, chemical vapor deposition or electroplating.

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