High-density redistributed interconnect packaging structure and preparation method thereof

Abstract

The high-density redistributed interconnect packaging structure and its preparation method provided by the embodiment of the present invention relate to the field of chip packaging technology. The packaging structure includes a base redistribution layer, a first chip, a first plastic package, a coating layer, an integrated redistribution layer, a first stacked redistribution layer, a second chip and a second plastic package. Compared with the existing technology, the high-density redistributed interconnect packaging structure provided by the embodiment of the present invention can greatly improve the heat dissipation performance and reduce overheating by additionally designing a first heat dissipation column. At the same time, the first heat dissipation column can be embedded in the first plastic package and the coating layer at the same time, thereby greatly improving the bonding force of the layers of the packaging structure, ensuring structural stability, and reducing the warping phenomenon of the packaging structure. At the same time, the first conductive column and the second conductive column are used to achieve electrical conduction, reduce the parasitic inductance of the wiring layer, and reduce the short circuit, overheating and other phenomena between the wiring layers caused by leakage.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a high-density redistributed interconnect packaging structure and a preparation method thereof. Background Art

[0002] With the rapid development of the semiconductor industry, chiplet technology, a new design approach, combines small chips with different functions. However, inconsistent thermal expansion coefficients and Young's moduli of various materials within the package structure can easily lead to warping or inconsistent deformation between upper and lower layers. This can lead to delamination (for example, between the dielectric layer and the plastic package, or between the wiring layer and the dielectric), resulting in poor product reliability and performance.

[0003] Furthermore, the thermal expansion coefficient of the stacked materials on one side of a conventional package structure is greater than that of the underlying redistribution layer due to the presence of the stacked chips, wiring layers, and plastic encapsulation. This inconsistent contraction due to thermal expansion can easily lead to package warping. Furthermore, conventional technology uses wiring layers for electrical conduction, creating an inductive effect between the wiring layers. This creates parasitic inductance, which in turn causes leakage, leading to short circuits and overheating between the wiring layers. Furthermore, the heat dissipation achieved with conventional technology is insufficient to meet practical requirements. Summary of the Invention

[0004] The purpose of the present invention is to provide a high-density redistributed interconnect packaging structure and its preparation method, which can greatly improve the heat dissipation performance, and can greatly improve the bonding strength of each layer of the packaging structure, ensure structural stability, and slow down the warping of the packaging structure, and use conductive columns to achieve electrical conduction and reduce the parasitic inductance of the wiring layer.

[0005] In a first aspect, the present invention provides a high-density redistributed interconnect packaging structure, comprising:

[0006] substrate redistribution layer;

[0007] a first chip, wherein the first chip is mounted on the substrate redistribution layer and electrically connected to the substrate redistribution layer;

[0008] a first plastic package body, the first plastic package body being coated on the first chip, and having a first conductive column, a second conductive column, and a first heat dissipation column formed therein, wherein one end of the first conductive column is connected to the base redistribution layer and the other end is exposed from the first plastic package body, the second conductive column and the first heat dissipation column are located outside the first conductive column, one end of the second conductive column is connected to the base redistribution layer and the other end extends out of the first plastic package body, and one end of the first heat dissipation column is connected to the base redistribution layer and the other end extends out of the first plastic package body;

[0009] a covering layer, the covering layer being disposed on the first plastic package body and covering the second conductive column and the portion of the first heat dissipation column extending out of the first plastic package body, with one end of the second conductive column away from the base redistribution layer being exposed to the covering layer;

[0010] an integrated redistribution layer, the integrated redistribution layer being arranged on a side of the first plastic package away from the base redistribution layer and connected to the first conductive pillar;

[0011] a first stacked redistribution layer, the first stacked redistribution layer being arranged on a side of the cladding layer away from the base redistribution layer and connected to the second conductive pillar;

[0012] a second chip mounted on the first stacked redistribution layer and electrically connected to the first stacked redistribution layer;

[0013] A second plastic package is provided on the first stacked redistribution layer and covers the second chip.

[0014] In an optional embodiment, a height of the first heat dissipation column relative to the base redistribution layer is lower than a height of the second conductive column relative to the base redistribution layer, so that the first heat dissipation column is spaced apart from the first stacked redistribution layer.

[0015] In an optional embodiment, the first heat dissipation column is located outside the second conductive column and is spaced apart from the second conductive column.

[0016] In an optional embodiment, the cladding layer covers the sidewalls of the integrated redistribution layer, and the second conductive pillars are arranged on at least two sides of the integrated redistribution layer.

[0017] In an optional embodiment, the thickness of the integrated redistribution layer is the same as the protrusion height of the second conductive column extending out of the first plastic package body, so that the first stacked redistribution layer is bonded to a side surface of the integrated redistribution layer away from the base redistribution layer.

[0018] In an optional embodiment, a ground pad is provided on the base redistribution layer, and the bottom end of the first heat dissipation column is connected to the ground pad.

[0019] In an optional embodiment, the high-density redistribution interconnect packaging structure also includes a third chip, the back side of the third chip is mounted on the base redistribution layer, and the third chip is arranged on at least two sides of the first chip and is located between the first conductive column and the second conductive column, and the integrated redistribution layer is electrically connected to the third chip.

[0020] In an optional embodiment, the integrated redistribution layer includes a first integrated wiring layer and at least one second integrated wiring layer, the first integrated wiring layer is arranged on a side surface of the first plastic package away from the base redistribution layer, and is electrically connected to the first conductive column, the second integrated wiring layer is arranged on the first integrated wiring layer, the front side of the third chip protrudes from the first plastic package, and the protruding height of the third chip relative to the first plastic package is the same as the thickness of the first integrated wiring layer.

[0021] In an optional embodiment, a protection layer is further provided on the front side of the third chip.

[0022] In an optional embodiment, the high-density redistribution interconnect packaging structure also includes a fourth chip and a third plastic package body, the fourth chip is arranged on the integrated redistribution layer and electrically connected to the integrated redistribution layer, the third plastic package body is arranged on the integrated redistribution layer and covers the fourth chip, and the first stacked redistribution layer is arranged on a side surface of the third plastic package body away from the base redistribution layer.

[0023] In an optional embodiment, the high-density redistributed interconnect packaging structure also includes a fifth chip, a fourth plastic package and a second stacked redistribution layer, the second stacked redistribution layer is arranged on the side of the second plastic package away from the base redistribution layer, the fifth chip is arranged on the second stacked redistribution layer, the fourth plastic package is arranged on the second stacked redistribution layer and covers the outside of the fifth chip, and a third conductive column and a second heat dissipation column are also arranged on the base redistribution layer, and the third conductive column is connected to the second stacked redistribution layer.

[0024] In an optional embodiment, the high-density redistribution interconnect packaging structure also includes a third chip, a fourth chip and a third plastic package body, the back of the third chip is mounted on the base redistribution layer, and the third chip is arranged on at least two sides of the first chip and is located between the first conductive column and the second conductive column, the integrated redistribution layer is arranged around the third chip, the fourth chip is arranged on the integrated redistribution layer and the third chip, and the fourth chip is electrically connected to the third chip and the integrated redistribution layer at the same time, and the third plastic package body is arranged on the integrated redistribution layer and covers the front of the third chip and the fourth chip.

[0025] In an optional embodiment, the high-density redistributed interconnect packaging structure also includes a fourth chip and a shielding coating layer, the front side of the fourth chip is mounted on the integrated redistribution layer, and a filling glue layer is also provided on the front side of the fourth chip. The shielding coating layer is provided on the integrated redistribution layer and is wrapped around the fourth chip and the filling glue layer.

[0026] In an optional embodiment, the covering layer covers the outside of the shielding coating layer.

[0027] In an optional embodiment, the first heat dissipation column is located inside the second conductive column, and the shielding coating layer covers the portion of the first heat dissipation column extending out of the second plastic package body.

[0028] In a second aspect, the present invention provides a method for preparing a high-density redistributed interconnect packaging structure, which is used to prepare the high-density redistributed interconnect packaging structure as described in the above embodiment, and the preparation method comprises:

[0029] providing a vehicle;

[0030] Mounting a first chip on the carrier;

[0031] forming a first plastic package on the carrier, wherein the first plastic package covers the first chip;

[0032] A first conductive column, a second conductive column, and a first heat dissipation column are formed on the first plastic package body, wherein the first conductive column is formed within the first plastic package body, one end of the first conductive column is connected to the base redistribution layer, and the other end is exposed from the first plastic package body, the second conductive column and the first heat dissipation column are both formed in the first plastic package body, one end of the second conductive column is connected to the base redistribution layer, and the other end extends out of the first plastic package body, and one end of the first heat dissipation column is connected to the base redistribution layer, and the other end extends out of the first plastic package body;

[0033] A covering layer and an integrated redistribution layer are formed on a side of the first plastic package body away from the carrier, wherein the covering layer covers the second conductive pillar and the portion of the first heat dissipation pillar extending out of the first plastic package body, and one end of the second conductive pillar away from the base redistribution layer is exposed from the covering layer, and the integrated redistribution layer is connected to the first conductive pillar;

[0034] forming a first stacked redistribution layer on a side of the cladding layer away from the carrier, wherein the first stacked redistribution layer is connected to the second conductive pillar;

[0035] Mounting a second chip on the first stacked redistribution layer;

[0036] forming a second plastic package on the first stacked redistribution layer, wherein the second plastic package covers the second chip;

[0037] Peeling off the carrier to expose the first plastic package and the first chip;

[0038] A base redistribution layer is formed on a surface of the first plastic package body at a side away from the second plastic package body, wherein the base redistribution layer is connected to the first chip, the first conductive pillar, and the second conductive pillar.

[0039] In an optional embodiment, the step of forming a first conductive column, a second conductive column, and a first heat dissipation column on the first plastic package body includes:

[0040] Cutting grooves in the first plastic package body to form a first opening, a second opening, and a third opening;

[0041] Electroplating a metal layer on the first plastic package body, wherein the metal layer fills the first opening, the second opening, and the third opening;

[0042] The metal layer is etched to form the first conductive column, the second conductive column and the first heat dissipation column.

[0043] In an optional embodiment, before the step of forming the first plastic package body on the carrier, the method further includes:

[0044] Mounting a third chip on the carrier, wherein the back side of the third chip is mounted on the carrier, and the third chip is disposed on at least two sides of the first chip;

[0045] A protection layer is mounted on the front surface of the third chip.

[0046] The beneficial effects of the embodiments of the present invention include:

[0047] The high-density redistributed interconnect packaging structure and its preparation method provided by the embodiment of the present invention are as follows: a first chip is mounted on a base redistribution layer and electrically connected to the base redistribution layer, and a first plastic package is coated on the first chip, and a first conductive column, a second conductive column and a first heat dissipation column are formed in the first plastic package. One end of the first conductive column is connected to the base redistribution layer and the other end is exposed from the first plastic package. The second conductive column and the first heat dissipation column are located outside the first conductive column. One end of the second conductive column is connected to the base redistribution layer and the other end extends out of the first plastic package. One end of the first heat dissipation column is connected to the base redistribution layer and the other end extends out of the first plastic package. At the same time, a covering layer is provided on the first plastic package, which covers the second conductive column and the portion of the first heat dissipation column extending out of the first plastic package, and the second conductive column is exposed from the covering layer. An integrated redistribution layer is also formed on the first plastic package, and the integrated redistribution layer is connected to the first conductive column. A first stacked redistribution layer is also formed on the covering layer, and the first stacked redistribution layer is connected to the second conductive column. Finally, a second chip and a second plastic package are disposed on the first stacked redistribution layer, wherein the second plastic package covers the second chip.

[0048] Compared to existing technologies, the high-density redistributed interconnect packaging structure provided by the present invention significantly improves heat dissipation performance and mitigates overheating through the additional design of a first heat dissipation column. Furthermore, the first heat dissipation column can be embedded in both the first plastic package and the coating layer, significantly improving the bonding strength of the packaging structure's layers, ensuring structural stability, and mitigating warping. Furthermore, the use of the first and second conductive columns to achieve electrical conduction reduces the parasitic inductance of the wiring layer, mitigating short circuits and overheating between wiring layers caused by leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0050] Figure 1 A schematic diagram of a high-density redistributed interconnect packaging structure provided by a first embodiment of the present invention;

[0051] Figures 2 to 11 A process flow chart of a method for preparing a high-density redistributed interconnect packaging structure provided by the first embodiment of the present invention;

[0052] Figure 12 A schematic diagram of a high-density redistributed interconnect packaging structure provided by a second embodiment of the present invention;

[0053] Figure 13 and Figure 14 A partial process flow chart of a method for preparing a high-density redistributed interconnect packaging structure provided by a second embodiment of the present invention;

[0054] Figure 15 A schematic diagram of a high-density redistributed interconnect packaging structure provided by a third embodiment of the present invention;

[0055] Figure 16 A schematic diagram of a high-density redistributed interconnect packaging structure provided by a fourth embodiment of the present invention;

[0056] Figure 17a 、 Figure 17b and Figure 17c A schematic diagram of a high-density redistributed interconnect packaging structure provided by a fifth embodiment of the present invention;

[0057] Figures 18 to 20 A partial process flow chart of a method for preparing a high-density redistributed interconnect package structure provided by a fifth embodiment of the present invention;

[0058] Figure 21 Schematic diagram of a high-density redistributed interconnect packaging structure provided by a sixth embodiment of the present invention.

[0059] Icons: 100 - high-density redistributed interconnect packaging structure; 110 - substrate redistribution layer; 111 - ground pad; 120a - first chip; 120b - second chip; 120c - third chip; 120d - fourth chip; 120e - fifth chip; 121 - protective layer; 130a - first plastic package; 130b - second plastic package; 130c - third plastic package; 130d - fourth plastic package; 131 - first conductive column; 132 - Second conductive column; 133-first heat dissipation column; 134-first opening; 135-second opening; 136-third opening; 137-third conductive column; 138-second heat dissipation column; 140-cladding layer; 150-integrated redistribution layer; 151-first integrated wiring layer; 152-second integrated wiring layer; 160-first stacked redistribution layer; 170-shielding coating layer; 180-filling glue layer; 190-second stacked redistribution layer; 200-carrier. DETAILED DESCRIPTION

[0060] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0061] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0062] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0063] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the product of the invention is usually placed when in use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be understood as a limitation on the present invention.

[0064] In addition, the terms "first", "second", etc., if used, are merely used to distinguish and describe, and should not be understood as indicating or implying relative importance.

[0065] As disclosed in the background, conventional packaging structures have a higher coefficient of thermal expansion (CTE) than the underlying redistribution layer due to the presence of laminated chips, wiring layers, and a plastic encapsulation layer on one side of the stack. This leads to inconsistent shrinkage due to thermal expansion, which can easily cause the package structure to warp. Furthermore, conventional technology uses wiring layers for electrical conduction, creating an inductive effect between the wiring layers, which creates parasitic inductance and leads to leakage, short circuits between the wiring layers, overheating, and other phenomena. Furthermore, the heat dissipation achieved with conventional technology is insufficient to meet practical requirements.

[0066] In addition, the conventional stacked packaging structure has low wiring density and chip integration, which affects the electrical performance.

[0067] In order to solve the above problems, the embodiments of the present invention provide a novel high-density redistributed interconnect packaging structure and a preparation method thereof. It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict.

[0068] First embodiment

[0069] See also Figure 1 The embodiment of the present invention provides a high-density redistributed interconnect packaging structure 100, which can significantly improve the heat dissipation performance, and can significantly improve the bonding strength of each layer of the packaging structure, ensure structural stability, and slow down the warping of the packaging structure, and use conductive columns to achieve electrical conduction and reduce the parasitic inductance of the wiring layer.

[0070] The high-density redistributed interconnect packaging structure 100 provided in an embodiment of the present invention includes a base redistribution layer 110, a first chip 120a, a first plastic package 130a, a covering layer 140, an integrated redistribution layer 150, a first stacked redistribution layer 160, a second chip 120b and a second plastic package 130b. The first chip 120a is mounted on the base redistribution layer 110 and is electrically connected to the base redistribution layer 110; the first plastic package 130a is coated on the first chip 120a, and a first conductive column 131, a second conductive column 132 and a first heat dissipation column 133 are formed in the first plastic package 130a, one end of the first conductive column 131 is connected to the base redistribution layer 110, and the other end is exposed to the first plastic package 130a, the second conductive column 132 and the first heat dissipation column 133 are located outside the first conductive column 131, one end of the second conductive column 132 is connected to the base redistribution layer 110, and the other end extends out of the first plastic package 130a, and one end of the first heat dissipation column 133 is connected to the base redistribution layer 110, and the other end extends out of the first plastic package 130a; the covering layer 140 is provided The first plastic package 130a is covered on the second conductive column 132 and the first heat dissipation column 133 extending out of the first plastic package 130a, and the end of the second conductive column 132 away from the base redistribution layer 110 is exposed on the covering layer 140; the integrated redistribution layer 150 is arranged on the side of the first plastic package 130a away from the base redistribution layer 110, and is connected to the first conductive column 131; the first stacked redistribution layer 160 is arranged on the side of the covering layer 140 away from the base redistribution layer 110, and is connected to the second conductive column 132; the second chip 120b is mounted on the first stacked redistribution layer 160 and is electrically connected to the first stacked redistribution layer 160; the second plastic package 130b is arranged on the first stacked redistribution layer 160 and covered by the second chip 120b.

[0071] It should be noted that the front side of the chip in the embodiments of the present invention refers to its electrical connection surface, i.e., the side surface with micro-bumps. There may be multiple second chips 120b, for example, four, spaced apart on the first stacked redistribution layer 160. The two second chips 120b at the edge may correspond to the second conductive pillars 132 on either side. The second conductive pillars 132 and first heat dissipation pillars 133 are distributed around the first chip 120a. The cladding layer 140, which may be made of a dielectric material and covers the second conductive pillars 132 and first heat dissipation pillars 133 for protection, also forms a heat dissipation layer. The additional design of the first heat dissipation pillars 133 significantly improves heat dissipation performance, mitigates overheating, and reduces warping caused by thermal stress. The first heat dissipation pillars 133 can also be embedded in both the first plastic package 130a and the cladding layer 140, significantly improving the bonding strength of the various layers of the package structure, ensuring structural stability, and mitigating warping. At the same time, the first conductive pillar 131 and the second conductive pillar 132 are used to achieve electrical conduction, that is, the electrical connection between the base redistribution layer 110 and the integrated redistribution layer 150 is achieved through the first conductive pillar 131, and the electrical connection between the first stacked redistribution layer 160 and the base redistribution layer 110 is achieved through the second conductive pillar 132, thereby avoiding the solution of relying entirely on the wiring layer to achieve current conduction, reducing the parasitic inductance of the wiring layer, and slowing down the short circuit, overheating and other phenomena between the wiring layers caused by leakage, and at the same time greatly improving the transmission efficiency.

[0072] In this embodiment, the height of the first heat dissipation pillar 133 relative to the base redistribution layer 110 is lower than the height of the second conductive pillar 132 relative to the base redistribution layer 110, so that the first heat dissipation pillar 133 is spaced apart from the first stacked redistribution layer 160. Specifically, the first conductive pillar 131, the second conductive pillar 132, and the first heat dissipation pillar 133 can all be metal pillars. The first heat dissipation pillar 133 does not serve as an electrical connection between the wiring layers, and therefore, the first heat dissipation pillar 133 is relatively low to avoid short circuit leakage.

[0073] It should be noted that the second conductive post 132 here can directly electrically connect the first stacked redistribution layer 160 and the base redistribution layer 110, and the first stacked redistribution layer 160 and the base redistribution layer 110 can at least partially overlap in the extension direction of the second conductive post 132. The first stacked redistribution layer 160 and the base redistribution layer 110 are separated by the coating layer 140, so a capacitor structure is formed. It is easy to understand that the calculation formula of the capacitance value is C=εS / d, where C is the capacitance value, ε is the dielectric constant, S is the overlapping area between the wiring layers, and d is the vertical distance between the wiring layers. Assuming that the overlapping area of ​​the S wiring is the same, increasing the vertical distance between the wiring layers is conducive to reducing the capacitance value, thereby reducing the capacitance effect. In the present embodiment, electrical connection is achieved by providing the second conductive post 132, which is conducive to increasing the distance between the base redistribution layer 110 and the first stacked redistribution layer 160, thereby further reducing the capacitance effect.

[0074] In this embodiment, the first heat dissipation pillars 133 are located outside the second conductive pillars 132 and spaced apart from the second conductive pillars 132. Specifically, the second conductive pillars 132 can be arranged around the first chip 120a, while the first heat dissipation pillars 133 can be arranged on the side of the second conductive pillars 132 away from the first chip 120a, that is, outside the second conductive pillars 132, while the second conductive pillars 132 are located outside the first conductive pillars 131. By arranging the first heat dissipation pillars 133 at the edge of the package structure, the bonding strength between the encapsulation layer 140 and the first plastic package body 130a can be improved, further mitigating warping and delamination.

[0075] In this embodiment, the cladding layer 140 covers the sidewalls of the integrated redistribution layer 150, and the second conductive pillars 132 are disposed on at least two sides of the integrated redistribution layer 150. Specifically, the cladding layer 140 only covers the second conductive pillars 132 and the first heat dissipation pillars 133, thereby forming a recessed structure in the central region. The integrated redistribution layer 150 is formed within this recessed structure, enabling the cladding layer 140 to cover and protect the sidewalls of the integrated redistribution layer 150. Furthermore, because the integrated redistribution layer 150 is disposed within this recessed structure, a wiring layer can be formed within the recessed structure, increasing wiring density and, in turn, improving electrical performance.

[0076] In this embodiment, the thickness of the integrated redistribution layer 150 is the same as the height of the protrusion of the second conductive pillar 132 extending from the first plastic package 130a, so that the first stacked redistribution layer 160 is bonded to the surface of the integrated redistribution layer 150 on the side away from the base redistribution layer 110. Specifically, the integrated redistribution layer 150 can be precisely filled in the groove structure formed by the cladding layer 140, and the surface of the integrated redistribution layer 150 on the side away from the base redistribution layer 110 is flush with the surface of the cladding layer 140, thereby improving the flatness of the upper surface and further facilitating the preparation of the first stacked redistribution layer 160.

[0077] In this embodiment, a ground pad 111 is provided on the substrate redistribution layer 110, and the bottom end of the first heat dissipation column 133 is connected to the ground pad 111. Specifically, the bottom end of the first heat dissipation column 133 is grounded through the ground pad 111, so that the first heat dissipation column 133 can achieve static discharge function while achieving heat dissipation effect.

[0078] In this embodiment, the integrated redistribution layer 150 includes a first integrated wiring layer 151 and at least one second integrated wiring layer 152. The first integrated wiring layer 151 is disposed on a surface of the first plastic package 130a away from the base redistribution layer 110 and is electrically connected to the first conductive pillars 131. The second integrated wiring layer 152 is disposed on the first integrated wiring layer 151. Specifically, during actual preparation, the first integrated wiring layer 151 can be formed simultaneously with the formation of the cladding layer 140, and then multiple layers of the second integrated wiring layer 152 can be formed through conventional wiring processes until the second integrated wiring layer 152 is flush with the surface of the cladding layer 140.

[0079] An embodiment of the present invention further provides a method for preparing a high-density redistributed interconnect package structure 100, which is used to prepare the aforementioned high-density redistributed interconnect package structure 100. The method comprises the following steps:

[0080] S1: Provide a carrier 200.

[0081] See also Figure 2 Specifically, a carrier 200, which can be a substrate, is first taken. An adhesive layer is then applied to the surface of the carrier 200 using a spin coating method, and then soft-baked on a hot plate to form a film. The adhesive layer can be a UV adhesive layer, such as a polymer composite material such as epoxy resin, polyimide, or benzocyclobutene.

[0082] S2 : Mounting the first chip 120 a on the carrier 200 .

[0083] See also Figure 3Specifically, the first chip 120 a is flip-mounted on the adhesive layer of the carrier 200 , that is, the first chip 120 a is mounted with its bumps facing downward and the back surface of the first chip 120 a facing upward.

[0084] S3: forming a first plastic package 130 a on the carrier 200 , wherein the first plastic package 130 a covers the first chip 120 a .

[0085] See also Figure 4 Specifically, through the plastic packaging process, a first plastic packaging body 130a is formed on the carrier 200, and the first plastic packaging body 130a can cover the first chip 120a. Then, the first plastic packaging body 130a is thinned to expose the back side of the first chip 120a. Of course, in some other preferred embodiments, the first plastic packaging body 130a does not need to be thinned here.

[0086] S4: forming a first conductive column 131 , a second conductive column 132 and a first heat dissipation column 133 on the first plastic package body 130 a .

[0087] See also Figure 5 , wherein the first conductive column 131 is formed in the first plastic package 130a, one end of the first conductive column 131 is connected to the base redistribution layer 110, and the other end is exposed from the first plastic package 130a, the second conductive column 132 and the first heat dissipation column 133 are both formed in the first plastic package 130a, one end of the second conductive column 132 is connected to the base redistribution layer 110, and the other end extends out of the first plastic package 130a, and one end of the first heat dissipation column 133 is connected to the base redistribution layer 110, and the other end extends out of the first plastic package 130a.

[0088] Specifically, during actual preparation, grooves can be firstly formed on the first plastic package 130a, for example, by laser drilling, to form a first opening 134, a second opening 135, and a third opening 136, wherein the first opening 134 is located on at least two sides of the first chip 120a, the second opening 135 is located outside the first opening 134, and the third opening 136 is located outside the second opening 135. A metal layer is then formed on the first plastic package 130a by electroplating, and the metal layer fills the first opening 134, the second opening 135, and the third opening 136, thereby forming a metal column. The thickness of the surface metal layer is 20 μm to 500 μm, and the metal layer can preferably be a copper layer. Finally, the metal layer is etched to form a first conductive column 131, a second conductive column 132, and a first heat dissipation column 133. During the etching, a mask can be used to cover the metal layer, and an etching solution (such as sulfuric acid, chromic acid etching solution, acidic copper chloride etching solution, etc.) is used to etch the metal layer, thereby forming the first conductive column 131, the second conductive column 132, and the first heat dissipation column 133.

[0089] It should be noted that a metal layer above the first conductive pillars 131 and between the second conductive pillars 132 may be retained during etching to facilitate subsequent fabrication of an integrated wiring layer.

[0090] S5 : forming a covering layer 140 and an integrated redistribution layer 150 on a side of the first plastic package body 130 a away from the carrier 200 .

[0091] See also Figure 6 , wherein the covering layer 140 covers the second conductive column 132 and the portion of the first heat dissipation column 133 extending out of the first plastic package 130a, and one end of the second conductive column 132 away from the base redistribution layer 110 is exposed in the covering layer 140, and the integrated redistribution layer 150 is connected to the first conductive column 131.

[0092] Specifically, during actual preparation, a coating layer 140 can be formed first, and a dielectric material layer can be formed on the second conductive pillar 132 and the first heat dissipation pillar 133 using a spin coating process. The dielectric material can be silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, etc. At the same time, the remaining metal layer above the first metal pillar is also coated with the dielectric material, thereby forming the first integrated wiring layer 151 of the integrated redistribution layer 150. Then, a wiring process is again used to form a multi-layer second integrated wiring layer 152 on the first integrated wiring layer 151, completing the preparation of the integrated redistribution layer 150. After preparation, the integrated redistribution layer 150 is flush with the coating layer 140.

[0093] S6 : forming a first stacked redistribution layer 160 on a side of the cladding layer 140 away from the carrier 200 .

[0094] See also Figure 7 , wherein the first stacked redistribution layer 160 is connected to the second conductive pillar 132. Specifically, the first stacked redistribution layer 160 is formed on the surface of the cladding layer 140 and the integrated redistribution layer 150 by utilizing the wiring process again. Since the second conductive pillar 132 is exposed on the cladding layer 140, the first stacked redistribution layer 160 can be directly connected to the second conductive pillar 132.

[0095] S7 : Mounting the second chip 120 b on the first stacked redistribution layer 160 .

[0096] See also Figure 8 Specifically, the second chip 120 b may be flip-chip mounted on the first stacked redistribution layer 160 and fixed by soldering through a reflow process.

[0097] S8 : forming a second plastic package 130 b on the first stacked redistribution layer 160 .

[0098] See also Figure 9Specifically, the second plastic package body 130 b is coated on the second chip 120 b and the second plastic package body 130 b can be formed on the first stacked redistribution layer 160 through a plastic packaging process.

[0099] S9: peeling off the carrier 200 to expose the first plastic package 130 a and the first chip 120 a.

[0100] See also Figure 10 Specifically, UV light is irradiated on the back side of the carrier 200 to debond the adhesive layer from the carrier 200 , thereby peeling off the carrier 200 .

[0101] S10: forming a substrate redistribution layer 110 on a surface of the first plastic package body 130 a away from the second plastic package body 130 b .

[0102] See also Figure 11 The base redistribution layer 110 is connected to the first chip 120a, the first conductive pillars 131, and the second conductive pillars 132. Specifically, the base redistribution layer 110 is formed through a wiring process and can be directly connected to the front surface of the first chip 120a, the first conductive pillars 131, and the second conductive pillars 132. Solder balls are then formed on the base redistribution layer 110, and finally, the individual products are cut.

[0103] The high-density redistributed interconnect packaging structure 100 and its preparation method provided by an embodiment of the present invention mount a first chip 120a on a base redistribution layer 110 and electrically connect the first chip 120a to the base redistribution layer 110, and a first plastic package 130a is coated on the first chip 120a, and a first conductive column 131, a second conductive column 132 and a first heat dissipation column 133 are formed in the first plastic package 130a, one end of the first conductive column 131 is connected to the base redistribution layer 110, and the other end is exposed from the first plastic package 130a, the second conductive column 132 and the first heat dissipation column 133 are located outside the first conductive column 131, one end of the second conductive column 132 is connected to the base redistribution layer 110, and the other end extends out of the first plastic package 130a, and one end of the first heat dissipation column 133 is connected to the base redistribution layer 110, and the other end extends out of the first plastic package 130a. At the same time, a covering layer 140 is provided on the first plastic package, and the covering layer 140 covers the second conductive column 132 and the portion of the first heat dissipation column 133 extending out of the first plastic package body 130a, and the second conductive column 132 is exposed on the covering layer 140. An integrated redistribution layer 150 is also formed on the first plastic package body 130a, and the integrated redistribution layer 150 is connected to the first conductive column 131. A first stacked redistribution layer 160 is also formed on the covering layer 140, and the first stacked redistribution layer 160 is connected to the second conductive column 132. Finally, the second chip 120b and the second plastic package body 130b are provided on the first stacked redistribution layer 160, wherein the second plastic package body 130b covers the outside of the second chip 120b. By additionally designing the first heat dissipation column 133, the heat dissipation performance can be greatly improved and overheating can be alleviated. The first heat dissipation pillars 133 can be embedded in both the first plastic package 130a and the coating 140, significantly enhancing the bonding strength of the various layers of the package structure, ensuring structural stability, and mitigating package warping. Furthermore, the first and second conductive pillars 131 and 132 enable electrical conduction, reducing the parasitic inductance of the wiring layers and mitigating short circuits and overheating between wiring layers caused by leakage.

[0104] Second embodiment

[0105] See also Figure 12 The embodiment of the present invention provides a high-density redistributed interconnect packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, please refer to the corresponding content in the first embodiment.

[0106] In this embodiment, the high-density redistributed interconnect packaging structure 100 further includes a third chip 120c, the back side of which is mounted on the base redistribution layer 110, and the third chip 120c is disposed on at least two sides of the first chip 120a and located between the first conductive pillar 131 and the second conductive pillar 132, and the integrated redistribution layer 150 is electrically connected to the third chip 120c. Specifically, there can be two third chips 120c, with the two third chips 120c being disposed on either side of the first chip 120a, thereby forming a heterogeneous stacking structure, with the front side of the third chip 120c mounted upward, and the integrated redistribution layer 150 being able to electrically contact the third chip 120c. By providing the third chip 120c, the integration of the chip stack can be further improved.

[0107] Furthermore, the integrated redistribution layer 150 includes a first integrated wiring layer 151 and at least one second integrated wiring layer 152. The first integrated wiring layer 151 is disposed on a surface of the first plastic package 130a away from the base redistribution layer 110 and is electrically connected to the first conductive pillar 131. The second integrated wiring layer 152 is disposed on the first integrated wiring layer 151. The front surface of the third chip 120c protrudes from the first plastic package 130a, and the protrusion height of the third chip 120c relative to the first plastic package 130a is the same as the thickness of the first integrated wiring layer 151. Specifically, the relative protrusion of the third chip 120c can enhance the bonding strength between the integrated redistribution layer 150 and the first plastic package 130a. In addition, the third chip 120c has the same thickness as the first integrated wiring layer 151, which also enhances its flatness and facilitates the subsequent preparation of the second integrated wiring layer 152. In addition, the third chip 120 c protrudes from the first plastic package 130 a , which can also reduce the electrical transmission height of the integrated redistribution layer 150 , and utilize the height difference to integrate more wiring structures, thereby improving its performance.

[0108] It should be noted that the dielectric material at the first integrated wiring layer 151 and the dielectric material at the bottom second integrated wiring layer 152 are integrated together and wrapped around the raised portion of the third chip 120c. This structure can further enhance the bonding force between the dielectric material and the third chip 120c, thereby further enhancing the overall structural stability.

[0109] In this embodiment, a protective layer 121 is also provided on the front surface of the third chip 120c. This protective layer 121 is made of a dielectric material, thereby protecting the front pads and transistors of the third chip 120c from chemical and foreign matter contamination during the chemical milling, laser grooving, and electroplating processes. Furthermore, when the second integrated wiring layer 152 is subsequently formed, the protective layer 121 can be opened to allow direct electrical connection between the second integrated wiring layer 152 and the third chip 120c.

[0110] An embodiment of the present invention also provides a method for preparing a high-density redistributed interconnect packaging structure 100, which is used to prepare the aforementioned high-density redistributed interconnect packaging structure 100. The basic steps and principles of this preparation method and the technical effects produced are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding content in the first embodiment.

[0111] The preparation method comprises the following steps:

[0112] S1: Provide a carrier 200.

[0113] S2 : Mounting the first chip 120 a on the carrier 200 .

[0114] S3 : Mounting the third chip 120 c on the carrier 200 , and mounting the protection layer 121 on the front surface of the third chip 120 c .

[0115] See also Figure 13 The backside of the third chip 120c is mounted on the carrier 200, and the third chip 120c is disposed on at least two sides of the first chip 120a. Specifically, the first chip 120a can be flip-chip mounted on the carrier 200, while the third chip 120c is face-up mounted on the carrier 200, with the third chip 120c located on both sides of the first chip 120a. A dielectric material is then coated on the front side of the third chip 120c to form a protective layer 121. The third chip 120c is taller than the first chip 120a.

[0116] S4: forming a first plastic package 130 a on the carrier 200 , and the first plastic package 130 a covers the first chip 120 a and the third chip 120 c .

[0117] See also Figure 14 Specifically, the first plastic package body 130a is formed by a plastic packaging process and then thinned to expose the back surface of the first chip 120a and the front surface of the third chip 120c.

[0118] S5: forming a first conductive column 131 , a second conductive column 132 and a first heat dissipation column 133 on the first plastic package body 130 a .

[0119] Specifically, a hole is first opened in the first plastic package 130a, then a plated metal layer is formed, and finally etching is performed to form the first conductive pillar 131, the second conductive pillar 132, and the first heat dissipation pillar 133. Since the front surface of the third chip 120c has a protective layer 121, the pads and transistors on the front surface of the third chip 120c can be effectively protected during etching.

[0120] S6 : forming a covering layer 140 and an integrated redistribution layer 150 on a side of the first plastic package body 130 a away from the carrier 200 .

[0121] S7 : forming a first stacked redistribution layer 160 on a side of the cladding layer 140 away from the carrier 200 .

[0122] S8 : Mounting the second chip 120 b on the first stacked redistribution layer 160 .

[0123] S9 : forming a second plastic package 130 b on the first stacked redistribution layer 160 .

[0124] S10 : peeling off the carrier 200 to expose the first plastic package 130 a and the first chip 120 a .

[0125] S11: forming a substrate redistribution layer 110 on a surface of the first plastic package body 130a away from the second plastic package body 130b.

[0126] For steps S5 to S11 , reference may be made to the first embodiment.

[0127] It should be noted that, by providing the third chip 120 c , this embodiment can improve chip integration and increase overall packaging density. At the same time, the protective layer 121 can protect the third chip 120 c during the manufacturing process.

[0128] Third embodiment

[0129] See also Figure 15 The embodiment of the present invention provides a high-density redistributed interconnect packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, please refer to the corresponding content in the first embodiment.

[0130] In this embodiment, the high-density redistribution interconnection packaging structure 100 also includes a fourth chip 120d and a third plastic package 130c. The fourth chip 120d is arranged on the integrated redistribution layer 150 and is electrically connected to the integrated redistribution layer 150. The third plastic package 130c is arranged on the integrated redistribution layer 150 and is wrapped around the fourth chip 120d. The first stacked redistribution layer 160 is arranged on a side surface of the third plastic package 130c away from the base redistribution layer 110.

[0131] In this embodiment, there may be two fourth chips 120d, which are spaced apart and flip-chip mounted on the integrated redistribution layer 150. The pins on both sides of each fourth chip 120d may correspond to the first chip 120a and the first conductive pillars 131, respectively. By providing the fourth chips 120d, a stacked chip structure can be achieved, further improving chip integration.

[0132] Fourth embodiment

[0133] See also Figure 16 The embodiment of the present invention provides a high-density redistributed interconnect packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, please refer to the corresponding content in the first embodiment.

[0134] In this embodiment, the high-density redistributed interconnect packaging structure 100 also includes a third chip 120c, a fourth chip 120d and a third plastic package 130c. The back of the third chip 120c is mounted on the base redistribution layer 110, and the third chip 120c is arranged on at least two sides of the first chip 120a and is located between the first conductive column 131 and the second conductive column 132. The integrated redistribution layer 150 is arranged around the third chip 120c, and the fourth chip 120d is arranged on the integrated redistribution layer 150 and the third chip 120c, and the fourth chip 120d is electrically connected to the third chip 120c and the integrated redistribution layer 150 at the same time. The third plastic package 130c is arranged on the integrated redistribution layer 150 and covers the front of the third chip 120c and the fourth chip 120d.

[0135] It should be noted that there are two third chips 120c and two fourth chips 120d here, and the two third chips 120c are respectively arranged on both sides of the first chip 120a, and the fourth chip 120d is arranged at intervals on the integrated redistribution layer 150. At the same time, the third plastic package 130c can simultaneously cover the front surface of the third chip 120c and the fourth chip 120d, and the third plastic package 130c is flush with the covering layer 140, thereby facilitating the preparation of the first stacked redistribution layer 160. In addition, a solder pad is provided at a corresponding position on the upper side of the first conductive column 131. The solder pad is correspondingly connected to the solder pin of the fourth chip 120d. Therefore, the fourth chip 120d and the base redistribution layer 110 can be connected through the first conductive column 131, shortening the transmission path and improving transmission efficiency.

[0136] It is worth noting that here the fourth chip 120d is simultaneously overlapped on the third chip 120c and the integrated redistribution layer 150, and the bumps of the fourth chip 120d can be welded and fixed to the bumps of the third chip 120c, thereby achieving a direct connection between the third chip 120c and the fourth chip 120d. Here, the fourth chip 120d can serve as a bridge chip to improve chip performance and reduce the wiring layer design, thereby integrating more chips. At the same time, a chip stacking structure is formed, which improves chip integration. The third chip 120c protrudes from the first plastic package 130a, and the front of the third chip 120c is flush with the surface of the integrated redistribution layer 150, which can achieve bump consistency of the fourth chip 120d and facilitate flip-chip mounting of the fourth chip 120d.

[0137] Fifth embodiment

[0138] See also Figure 17a The embodiment of the present invention provides a high-density redistributed interconnect packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, please refer to the corresponding content in the first embodiment.

[0139] In this embodiment, the high-density redistributed interconnect packaging structure 100 further includes a fourth chip 120d and a shielding coating layer 170. The front of the fourth chip 120d is mounted on the integrated redistribution layer 150. A filling adhesive layer 180 is also provided on the front of the fourth chip 120d. The shielding coating layer 170 is provided on the integrated redistribution layer 150 and covers the fourth chip 120d and the filling adhesive layer 180. Specifically, the filling adhesive layer 180 can cover the soldering parts of the fourth chip 120d to prevent the shielding coating layer 170 from contacting the bumps of the fourth chip 120d. At the same time, the shielding coating layer 170 can be made of a conductive adhesive layer or can be doped with a conductive material, so that it can play a shielding role and prevent the first stacked redistribution layer 160 from affecting the fourth chip 120d.

[0140] Furthermore, the covering layer 140 covers the shielding film layer 170. The covering layer 140 can be made of a plastic material and can encapsulate the shielding film layer 170, the second conductive pillars 132, and the first heat dissipation pillars 133. It is worth noting that the covering layer 140 can be formed after the shielding film layer 170 is prepared and then plastic-encapsulated to ensure a good covering effect.

[0141] In this embodiment, the first heat dissipation column 133 is located inside the second conductive column 132, and the shielding coating layer 170 covers the portion of the first heat dissipation column 133 that extends out of the second plastic package 130b. Specifically, the shielding coating layer 170 can cover the first heat dissipation column 133, greatly improving the bonding strength between the shielding coating layer 170 and the first heat dissipation column 133, thereby reducing delamination and warping of the shielding coating layer 170.

[0142] See also Figure 17b In another preferred embodiment of the present invention, a fifth chip 120e is attached to the back of the fourth chip 120d. The fifth chip 120e and the fourth chip 120d are bonded back-to-back, and the front of the fifth chip 120e is bonded to the first stacked redistribution layer 160 and similarly protected with a filler. This arrangement further enhances chip integration. Furthermore, because the shielding film layer 170 is made of a conductive material, it provides electromagnetic shielding and electrostatic discharge for the fourth and fifth chips 120d and 120e.

[0143] See also Figure 17cIn other preferred embodiments of the present invention, a fifth chip 120e is further provided on the side of the shielding coating layer 170 away from the base redistribution layer 110, and the front of the fifth chip 120e is attached to the first stacked redistribution layer 160. This arrangement can also improve the chip integration, and because the shielding coating layer 170 is made of conductive material, it can achieve electromagnetic shielding between the fourth chip 120d and the fifth chip 120e, and can achieve the electrostatic discharge function of the fourth chip 120d. Of course, it is also possible to dig a groove on the shielding coating layer 170 and partially accommodate the fifth chip 120e in the groove. While reducing the package height, it can also achieve electromagnetic shielding and electrostatic discharge functions, and the heat dissipation effect is better.

[0144] An embodiment of the present invention provides a method for preparing a high-density redistributed interconnect packaging structure 100, which is used to prepare the aforementioned high-density redistributed interconnect packaging structure 100. The basic steps and principles of the preparation method and the technical effects produced are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding content in the first embodiment.

[0145] The preparation method comprises the following steps:

[0146] S1: Provide a carrier 200.

[0147] S2 : Mounting the first chip 120 a on the carrier 200 .

[0148] S3: forming a first plastic package 130 a on the carrier 200 , wherein the first plastic package 130 a covers the first chip 120 a .

[0149] S4: forming a first conductive column 131 , a second conductive column 132 and a first heat dissipation column 133 on the first plastic package body 130 a .

[0150] For steps S1 to S4, reference may be made to the first embodiment.

[0151] S5 : forming an integrated redistribution layer 150 on a side of the first plastic package 130 a away from the carrier 200 .

[0152] Specifically, an integrated redistribution layer 150 may be formed on the surface of the first plastic package body 130 a inside the first heat dissipation column 133 .

[0153] S6 : Mounting the fourth chip 120 d on the integrated redistribution layer 150 .

[0154] See also Figure 18 Specifically, the fourth chip 120d can be flip-chip mounted on the surface of the integrated redistribution layer 150, and the bottom filling glue is completed to form a filling glue layer 180 to achieve bottom protection of the fourth chip 120d.

[0155] S7 : forming a shielding coating layer 170 on the integrated redistribution layer 150 .

[0156] See also Figure 19 Specifically, a shielding coating layer 170 can be formed on the integrated redistribution layer 150 through a coating process. The shielding coating layer 170 can be coated on the outside of the fourth chip 120d. At the same time, the shielding coating layer 170 can be coated on the outside of the first heat dissipation column 133 to enhance its bonding strength.

[0157] S8: forming a coating layer 140 on the first plastic package body 130a.

[0158] See also Figure 20 Specifically, the covering layer 140 is formed by a plastic packaging process, and the covering layer 140 can cover the shielding film layer 170 and the second conductive column 132 .

[0159] S9 : forming a first stacked redistribution layer 160 on the cladding layer 140 .

[0160] S10 : Mounting the second chip 120 b on the first stacked redistribution layer 160 .

[0161] S11 : forming a second plastic package 130 b on the first stacked redistribution layer 160 .

[0162] S12 : peeling off the carrier 200 to expose the first plastic package 130 a and the first chip 120 a .

[0163] S13: forming a substrate redistribution layer 110 on a surface of the first plastic package body 130 a away from the second plastic package body 130 b .

[0164] It should be noted that the shielding coating layer 170 here can, on the one hand, achieve a shielding effect on the fourth chip 120d, preventing the first stacked redistribution layer 160 from affecting the fourth chip 120d. On the other hand, the shielding coating layer 170 can also cover the first heat dissipation column 133, greatly improving the bonding strength between the shielding coating layer 170 and the first heat dissipation column 133, thereby reducing the delamination and warping of the shielding coating layer 170.

[0165] Sixth embodiment

[0166] See also Figure 21 The embodiment of the present invention provides a high-density redistributed interconnect packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, please refer to the corresponding content in the first embodiment.

[0167] In this embodiment, the high-density redistribution interconnection packaging structure 100 also includes a fourth chip 120d and a third plastic package 130c. The fourth chip 120d is arranged on the integrated redistribution layer 150 and is electrically connected to the integrated redistribution layer 150. The third plastic package 130c is arranged on the integrated redistribution layer 150 and is wrapped around the fourth chip 120d. The first stacked redistribution layer 160 is arranged on a side surface of the third plastic package 130c away from the base redistribution layer 110.

[0168] Furthermore, a second stacked redistribution layer 190 is provided on a side of the second plastic package 130b away from the base redistribution layer 110. A fifth chip 120e and a fourth plastic package 130d are also provided on the second stacked redistribution layer, with the fourth plastic package 130d covering the fifth chip 120e. Furthermore, a third conductive column 137 and a second heat dissipation column 138 are provided on the base redistribution layer 110. The third conductive column 137 sequentially passes through the first plastic package 130a, the third plastic package 130c, the first stacked redistribution layer 160, and the second plastic package 130b before connecting to the second stacked redistribution layer 190, thereby electrically connecting the second stacked redistribution layer 190 to the base redistribution layer 110 via the third conductive column 137. The second heat dissipation column 138 sequentially passes through the first plastic package 130a, the third plastic package 130c, and the first stacked redistribution layer 160 before being embedded in the second plastic package 130b, thereby also providing a heat dissipation effect.

[0169] By setting up a multi-layer stacking structure, electrical connection between multiple wiring layers can be achieved by only using conductive columns without using TSV perforation technology, thereby improving chip stacking density and improving integration.

[0170] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A high-density redistributed interconnect packaging structure, characterized in that: include: substrate redistribution layer; a first chip, wherein the first chip is mounted on the substrate redistribution layer and electrically connected to the substrate redistribution layer; a first plastic package body, the first plastic package body being coated on the first chip, and having a first conductive column, a second conductive column, and a first heat dissipation column formed therein, wherein one end of the first conductive column is connected to the base redistribution layer and the other end is exposed from the first plastic package body, the second conductive column and the first heat dissipation column are located outside the first conductive column, one end of the second conductive column is connected to the base redistribution layer and the other end extends out of the first plastic package body, and one end of the first heat dissipation column is connected to the base redistribution layer and the other end extends out of the first plastic package body; a covering layer, the covering layer being disposed on the first plastic package body and covering the second conductive column and the portion of the first heat dissipation column extending out of the first plastic package body, with one end of the second conductive column away from the base redistribution layer being exposed to the covering layer; an integrated redistribution layer, the integrated redistribution layer being arranged on a side of the first plastic package away from the base redistribution layer and connected to the first conductive pillar; a first stacked redistribution layer, the first stacked redistribution layer being arranged on a side of the cladding layer away from the base redistribution layer and connected to the second conductive pillar; a second chip mounted on the first stacked redistribution layer and electrically connected to the first stacked redistribution layer; A second plastic package is provided on the first stacked redistribution layer and covers the second chip.

2. The high-density redistributed interconnect packaging structure according to claim 1, wherein: A height of the first heat dissipation column relative to the base redistribution layer is lower than a height of the second conductive column relative to the base redistribution layer, so that the first heat dissipation column is spaced apart from the first stacked redistribution layer.

3. The high-density redistributed interconnect packaging structure according to claim 2, wherein: The first heat dissipation column is located outside the second conductive column and is spaced apart from the second conductive column.

4. The high-density redistributed interconnect packaging structure according to claim 3, wherein: The cladding layer covers the sidewalls of the integrated redistribution layer, and the second conductive pillars are arranged on at least two sides of the integrated redistribution layer.

5. The high-density redistributed interconnect packaging structure according to claim 4, wherein: The thickness of the integrated redistribution layer is the same as the height of the second conductive pillar protruding from the first plastic package body, so that the first stacked redistribution layer is bonded to a surface of the integrated redistribution layer away from the base redistribution layer.

6. The high-density redistributed interconnect packaging structure according to claim 2, wherein: A ground pad is provided on the base redistribution layer, and the bottom end of the first heat dissipation column is connected to the ground pad.

7. The high-density redistributed interconnect packaging structure according to claim 2, wherein: The high-density redistribution interconnect packaging structure also includes a third chip, the back side of which is mounted on the substrate redistribution layer, and the third chip is arranged on at least two sides of the first chip and located between the first conductive pillar and the second conductive pillar, and the integrated redistribution layer is electrically connected to the third chip.

8. The high-density redistributed interconnect packaging structure according to claim 7, wherein: The integrated redistribution layer includes a first integrated wiring layer and at least one second integrated wiring layer. The first integrated wiring layer is arranged on a surface of the first plastic package body away from the base redistribution layer and is electrically connected to the first conductive column. The second integrated wiring layer is arranged on the first integrated wiring layer. The front side of the third chip protrudes from the first plastic package body, and the protruding height of the third chip relative to the first plastic package body is the same as the thickness of the first integrated wiring layer.

9. The high-density redistributed interconnect packaging structure according to claim 7, wherein: A protective layer is further provided on the front side of the third chip.

10. The high-density redistributed interconnect packaging structure according to claim 2, wherein: The high-density redistribution interconnect packaging structure also includes a fourth chip and a third plastic package. The fourth chip is arranged on the integrated redistribution layer and is electrically connected to the integrated redistribution layer. The third plastic package is arranged on the integrated redistribution layer and covers the fourth chip. The first stacked redistribution layer is arranged on a side surface of the third plastic package away from the base redistribution layer.

11. The high-density redistributed interconnect packaging structure according to claim 10, wherein: The high-density redistribution interconnect packaging structure also includes a fifth chip, a fourth plastic package and a second stacked redistribution layer. The second stacked redistribution layer is arranged on a side of the second plastic package away from the base redistribution layer. The fifth chip is arranged on the second stacked redistribution layer. The fourth plastic package is arranged on the second stacked redistribution layer and covers the outside of the fifth chip. A third conductive column and a second heat dissipation column are also arranged on the base redistribution layer. The third conductive column is connected to the second stacked redistribution layer.

12. The high-density redistributed interconnect packaging structure according to claim 2, wherein: The high-density redistribution interconnect packaging structure also includes a third chip, a fourth chip and a third plastic package. The back of the third chip is mounted on the base redistribution layer, and the third chip is arranged on at least two sides of the first chip and is located between the first conductive column and the second conductive column. The integrated redistribution layer is arranged around the third chip, the fourth chip is arranged on the integrated redistribution layer and the third chip, and the fourth chip is electrically connected to the third chip and the integrated redistribution layer at the same time. The third plastic package is arranged on the integrated redistribution layer and covers the front of the third chip and the fourth chip.

13. The high-density redistributed interconnect packaging structure according to claim 2, wherein: The high-density redistributed interconnect packaging structure also includes a fourth chip and a shielding coating layer. The front of the fourth chip is mounted on the integrated redistribution layer. The front of the fourth chip is also provided with a filling glue layer. The shielding coating layer is provided on the integrated redistribution layer and covers the fourth chip and the filling glue layer.

14. The high-density redistributed interconnect packaging structure according to claim 13, wherein: The covering layer covers the outside of the shielding coating layer.

15. The high-density redistributed interconnect packaging structure according to claim 13, wherein: The first heat dissipation column is located inside the second conductive column, and the shielding coating layer covers the portion of the first heat dissipation column extending out of the second plastic package body.

16. A method for preparing a high-density redistributed interconnect packaging structure, for preparing the high-density redistributed interconnect packaging structure according to claim 1, characterized in that: The preparation method comprises: providing a vehicle; Mounting a first chip on the carrier; forming a first plastic package on the carrier, wherein the first plastic package covers the first chip; A first conductive column, a second conductive column, and a first heat dissipation column are formed on the first plastic package body, wherein the first conductive column is formed within the first plastic package body, one end of the first conductive column is connected to the base redistribution layer, and the other end is exposed from the first plastic package body, the second conductive column and the first heat dissipation column are both formed in the first plastic package body, one end of the second conductive column is connected to the base redistribution layer, and the other end extends out of the first plastic package body, and one end of the first heat dissipation column is connected to the base redistribution layer, and the other end extends out of the first plastic package body; A covering layer and an integrated redistribution layer are formed on a side of the first plastic package body away from the carrier, wherein the covering layer covers the second conductive pillar and the portion of the first heat dissipation pillar extending out of the first plastic package body, and one end of the second conductive pillar away from the base redistribution layer is exposed from the covering layer, and the integrated redistribution layer is connected to the first conductive pillar; forming a first stacked redistribution layer on a side of the cladding layer away from the carrier, wherein the first stacked redistribution layer is connected to the second conductive pillar; Mounting a second chip on the first stacked redistribution layer; forming a second plastic package on the first stacked redistribution layer, wherein the second plastic package covers the second chip; Peeling off the carrier to expose the first plastic package and the first chip; A base redistribution layer is formed on a surface of the first plastic package body at a side away from the second plastic package body, wherein the base redistribution layer is connected to the first chip, the first conductive pillar, and the second conductive pillar.

17. The method for preparing a high-density redistributed interconnect packaging structure according to claim 16, wherein: The step of forming a first conductive column, a second conductive column and a first heat dissipation column on the first plastic package body includes: Cutting grooves in the first plastic package body to form a first opening, a second opening, and a third opening; Electroplating a metal layer on the first plastic package body, wherein the metal layer fills the first opening, the second opening, and the third opening; The metal layer is etched to form the first conductive column, the second conductive column and the first heat dissipation column.

18. The method for preparing a high-density redistributed interconnect packaging structure according to claim 16, wherein: Before the step of forming the first plastic package on the carrier, the method further includes: Mounting a third chip on the carrier, wherein the back side of the third chip is mounted on the carrier, and the third chip is disposed on at least two sides of the first chip; A protection layer is mounted on the front surface of the third chip.

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