Power substrate, power module and preparation method of power substrate

Abstract

The invention discloses a power substrate, a power module and a preparation method of the power substrate, which are applied to the technical field of power devices, a first metal layer is located on the bottom surface of an insulating layer and covers a first region of the top surface of the insulating layer along at least one side surface of the insulating layer, and a second metal layer is located on a second region of the top surface of the insulating layer. The first metal layer and the second metal layer are isolated from each other on the top surface of the insulating layer; the insulating layer comprises a main body layer made of the same material as a substrate in a power chip to be bonded, the main body layer is at least provided with an insulating film layer in a second area of the top surface, and the second metal layer is isolated from the main body layer through the insulating film layer. The main body layer and the substrate in the power chip to be bonded are made of the same material, so that the thermal expansion coefficients of the insulating layer and the power chip can be ensured to be approximately the same, and the insulating layer can be set to be a flat plate. And the first metal layer wrapping the insulating layer is arranged, so that the structural strength of the whole insulating layer can be improved, and the power substrate can meet the required structural performance.

Description

Technical Field

[0001] The present invention relates to the technical field of power devices, and in particular to a power substrate, a power module and a method for preparing the power substrate. Background Art

[0002] A power semiconductor module is a device capable of high-frequency, high-voltage, and high-current output. It consists of multiple power chips arranged according to a specific electrical topology and packaged into an integrated module, making it easily applicable in the industrial, new energy, and electronics sectors. As a key component of power modules, the power substrate plays a vital role in industries such as new energy vehicles. With continuous technological advancements and market development, power substrates are expected to exhibit higher performance, lower costs, smaller size, and lighter weight.

[0003] In existing power module packaging structures, the power substrate plays a crucial role, providing electrical interconnection and insulation, corrosion protection, mechanical support, and heat dissipation for semiconductor chips. Currently, commonly used power substrates can be categorized by material, including polymer substrates, insulated metal substrates, and ceramic substrates. Due to the high voltage, high power, and high heat generation characteristics of power semiconductor modules, the use of polymer and insulated metal substrates is significantly limited. Ceramic substrates, however, are the most widely used due to their high thermal conductivity, excellent heat resistance, high insulation, high strength, and thermal compatibility with chip materials.

[0004] At present, welding power substrates and power chips usually requires a vacuum and high-temperature environment. In this environment, the difference in thermal expansion coefficients between the two will cause the power substrate to bend. Therefore, the power substrate is currently required to have a certain curvature. This curvature is opposite to the bending deformation caused by welding. Therefore, the power substrate cannot be flat before welding. A pre-curvature must be reserved for compensation and suppression. The pre-curvature requires high precision and is difficult to process. Too large a curvature will lead to a thick solder layer that is prone to voids and high installation stress. Too small a curvature will result in high interface thermal resistance or poor sealing and leakage. Therefore, how to provide a power substrate with a flat structure that can ensure good welding with the power chip is an urgent problem that technicians in this field need to solve. Summary of the Invention

[0005] The purpose of the present invention is to provide a power substrate, a power module and a method for preparing the power substrate, which can ensure good welding between the power substrate and the power chip.

[0006] In order to solve the above technical problems, the present invention provides a power substrate, comprising: a first metal layer, an insulating layer and a second metal layer;

[0007] The insulating layer includes a top surface facing the power chip and a bottom surface away from the power chip, the first metal layer is located on the bottom surface of the insulating layer and covers a first area of the top surface of the insulating layer along at least one side surface of the insulating layer, the second metal layer is located in a second area of the top surface of the insulating layer, and the first metal layer and the second metal layer are isolated from each other on the top surface of the insulating layer;

[0008] The insulating layer includes a main body layer made of the same material as the substrate of the power chip to be bonded, the main body layer is provided with an insulating film layer at least in the second area of the top surface, and the second metal layer is isolated from the main body layer by the insulating film layer.

[0009] By using the same material as the substrate of the power chip to be bonded, the thermal expansion coefficients of the insulating layer and the power chip are roughly the same, preventing them from bending in high-temperature environments and allowing the insulating layer to be configured as a flat plate. Furthermore, by providing a first metal layer covering the insulating layer, the structural strength of the entire insulating layer is increased, ensuring that the power substrate meets the required structural performance.

[0010] The thermal expansion coefficient of the insulation layer provided by this application closely matches that of the power chip. Whether undergoing vacuum high-temperature reflow soldering during production or operating in the high-temperature environment of the module, the insulation layer's deformation remains consistent with that of the power chip, reducing the risk of power chip failure and improving device reliability. Furthermore, the power module of this solution utilizes a silicon wafer as its substrate, offering low material cost and high thermal conductivity, which helps reduce the size of the power chip and device volume.

[0011] Optionally, the main layer includes a silicon wafer, and the insulating film layer includes an oxide layer.

[0012] The insulating layer of the present application uses the same silicon material as the power chip, which is conducive to synchronous thermal expansion consistency and can solve the problem of deformation caused by thermal stress during the welding of the power chip, which in turn causes the chip to tear. At the same temperature, the two have the same deformation and the error is not large, which avoids the deformation difference caused by the different thermal expansion coefficients of the power substrate during the welding process of the power chip and the resulting damage to the power chip. The solution provided by the present application greatly reduces the terminal application cost by 1 / 3, which is conducive to industrial and commercial mass production and application. At the same time, the power module of this solution uses silicon wafers as the substrate, which has low material cost and high thermal conductivity, which is conducive to reducing the size of the power chip and the volume of the device.

[0013] Optionally, the oxide layer at least covers the top surface of the silicon wafer.

[0014] Optionally, the first metal layer covers all side surfaces of the insulating layer from the bottom surface of the insulating layer to the edge of the top surface of the insulating layer.

[0015] The first metal layer in this application can be used as a heat dissipation structure. Compared with traditional power modules, the power module of this application reduces the copper foil layer between the power substrate and the heat sink, significantly reducing the overall thermal resistance of the power module. At the same time, the use of a metal that is fluid at high temperatures as the second metal layer further avoids power chip failure caused by inconsistent thermal expansion coefficients due to its good flexibility at high temperatures, further improving the production yield of the power module. The power module of this application has a lightweight structure, reduces the number of layers of metal and solder, and has the characteristics of low cost and high reliability.

[0016] The power substrate in this application does not require curved or micro-curved designs, and features a thin solder layer, high solder quality, low residual stress, low leakage risk, and high reliability. This application reduces thermal resistance, and while reducing material, the lateral heat dissipation capacity of the power module increases by 1 to 10 times, improving heat dissipation performance while ensuring reliability.

[0017] Optionally, the second metal layer is a metal layer having fluidity when fixing the power chip at the first temperature.

[0018] This application uses a metal that is fluid at high temperatures as the second metal layer. Its excellent flexibility at high temperatures further avoids power chip failure caused by inconsistent thermal expansion coefficients, further improving the production yield of power modules. This power module is lightweight, reduces the number of metal layers and solder, and offers low cost and high reliability.

[0019] Optionally, a solder layer is provided on a surface of the second metal layer facing away from the insulating layer, and the solder layer is used to fix the power chip.

[0020] The present invention further provides a power module, comprising a power chip and a power substrate as described in any one of the above items, wherein the power chip is fixedly connected to the second metal layer.

[0021] The present invention also provides a method for preparing a power substrate, comprising:

[0022] A first metal layer is provided on the surface of the insulating layer, covering the insulating layer; the insulating layer is an insulating layer made of the same material as the substrate of the power chip to be bonded, the insulating layer includes a top surface facing the power chip and a bottom surface away from the power chip, the first metal layer is located on the bottom surface of the insulating layer and covers a first area of the top surface of the insulating layer along at least one side surface of the insulating layer;

[0023] A second metal layer is arranged on the surface of the insulating layer covered with the first metal layer; the second metal layer is located in the second area of the top surface of the insulating layer, and the first metal layer and the second metal layer are isolated from each other on the top surface of the insulating layer; the insulating layer includes a main body layer made of the same material as the substrate in the power chip to be bonded, and the main body layer is provided with an insulating film layer at least in the second area of the top surface, and the second metal layer is isolated from the main body layer by the insulating film layer.

[0024] Optionally, providing a first metal layer covering the insulating layer on the surface of the insulating layer includes:

[0025] Place the insulation layer into the jig;

[0026] A molten metal material is injected along the jig into the surface of the insulating layer to form a first metal layer covering the insulating layer.

[0027] Optionally, providing a second metal layer on the surface of the insulating layer coated with the first metal layer includes:

[0028] A patterned metal layer is provided on the surface of the insulating layer coated with the first metal layer as the second metal layer; the metal layer is a metal layer having fluidity when fixing the power chip at a first temperature.

[0029] This preparation method has undergone significant changes compared to the existing technology. By using a metal layer that is fluid at the first temperature as the second metal layer, the production yield can be improved, the void rate can be reduced, and the product reliability and product qualification rate can be improved, making it suitable for industrial mass production applications.

[0030] By heating the metal layer to a semi-molten state and welding it to the power chip, compared with the existing technology of connecting through solder, the process of this application is simpler and less expensive. At the same time, due to the good toughness of the metal flexible layer of this material and the low void rate, the product yield is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 A schematic structural diagram of a power substrate provided by an embodiment of the present invention;

[0033] Figure 2 for Figure 1 Schematic diagram of the structure of the medium-power substrate after welding the power chip;

[0034] Figure 3 A schematic structural diagram of another power substrate provided by an embodiment of the present invention;

[0035] Figure 4 A schematic diagram of the exploded structure of a power module provided by an embodiment of the present invention;

[0036] Figure 5 A schematic structural diagram of a power module provided by an embodiment of the present invention;

[0037] Figure 6 A flow chart of a method for preparing a power substrate provided in this embodiment;

[0038] Figure 7 A schematic diagram of a top view of a power substrate prepared in this embodiment;

[0039] Figure 8 for Figure 7 Sectional view along line AA;

[0040] Figure 9 The present invention provides a flow chart of a specific method for preparing a power substrate.

[0041] In the figure: 1. Insulation layer, 2. First metal layer, 3. Second metal layer, 4. Power chip, 5. Mounting hole, 6. Raised structure, 7. Bonding wire, 8. Power pin, 9. Housing, 10. Encapsulation colloid, 11. Cover. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of illustration and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowcharts can be implemented out of sequence, and steps without logical context can be reversed or implemented simultaneously. In addition, those skilled in the art, under the guidance of the contents of this application, can add one or more other operations to the flowchart, or remove one or more operations from the flowchart.

[0043] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0044] The heat sink baseplate structure for existing power semiconductor modules is typically made of solid metal (copper or aluminum silicon carbide (AlSiC)) plates with a thickness of 3mm to 8mm. It is generally divided into a flat baseplate indirect heat dissipation structure and an integrated pin-fin direct cooling structure. Based on the application requirements, the power module substrate must have high thermal conductivity (the material must have good thermal conductivity to effectively dissipate the heat generated by the power module), a reasonable thermal expansion coefficient (similar to that of the chip to avoid thermal stress at the bonding interface under high temperature conditions, which may lead to fracture or damage of the material bonding interface), high strength (sufficient mechanical strength to operate normally in high-vibration environments), long life (meeting the design life requirements of the vehicle, typically 15 years or more, with zero failure), small size, and low cost (the assembly volume should not be too large to reduce manufacturing costs). The ceramic substrate materials of the DBC ceramic substrate or AMB ceramic substrate used in existing power modules are generally made of Al2O3, AlN, Si3N4 or zirconium-doped Al2O3. Although they meet the needs of most application scenarios, they cannot have the advantages of high thermal conductivity, reasonable thermal expansion, low cost, and high strength. Therefore, adaptive selection is required in different application scenarios and the compatibility is low.

[0045] At the same time, the overall structure of the conventional standard power module in the existing technology is a chip, a DBC (Direct Bonded Copper) ceramic substrate, and a heat dissipation metal plate. The power chip realizes electrical function transmission through bonding wires or bonding copper ribbons. The power chip, DBC ceramic substrate, and heat dissipation metal plate are connected by solder vacuum reflow to achieve thermal conductivity, insulation, and corresponding electrical performance. When the power chip is working, it will generate a lot of heat. Most of this heat is transferred to the heat dissipation metal plate through the DBC ceramic substrate and dissipated by the flow of coolant. This packaging has at least the following technical problems:

[0046] 1. Because this classic packaging module needs to be manufactured in a vacuum and high-temperature environment, the heat dissipation metal plate bends toward the back because its thermal expansion coefficient is smaller than that of the DBC ceramic substrate (see "CN103794571A"). This bending causes fatigue damage to the solder, and solder voids are prone to occur between the DBC ceramic substrate and the heat dissipation base plate, directly affecting the heat dissipation of the entire system. At the same time, during welding, the DBC ceramic substrate and the power chip will also cause deformation due to thermal stress generated by high temperature, which can easily cause excessive deformation and failure of the power chip. Overall reliability is low, the production process requires strict settings, the fixture design is complex, and the production process is complicated and cumbersome.

[0047] Specifically, the power chip, ceramic substrate, and metal baseplate are connected via solder. Each layer of material has a different coefficient of thermal expansion. Temperature changes during the soldering process and operation can cause the baseplate to bend and deform, generating stress on the weld surface. Appropriate mounting pressure is required between the baseplate and the heat sink or cooling water tank to ensure optimal thermal contact, reduce interfacial thermal resistance, and seal the cooling water. This requires the finished module baseplate (heat sink) to have a certain curvature. This curvature is in the opposite direction of the bending deformation caused by soldering. Therefore, the baseplate cannot be flat before soldering and a pre-set curvature must be reserved for compensation and suppression. This pre-set curvature requires high precision and is difficult to process. Excessive curvature results in a thick solder layer that is prone to voids and high mounting stress. Excessive curvature leads to high interfacial thermal resistance or leaks due to poor sealing.

[0048] 2. Due to the differences in thermal expansion coefficients of various materials in the existing power module substrate, the existing process production control is relatively complex and the defect rate is high, which further leads to high production costs and is not conducive to the industrial application of power modules.

[0049] 3. In the existing technology, the ceramic substrate usually includes an electrical connection layer, a ceramic layer and a metal connection layer from top to bottom. The metal connection layer is used to connect to the heat sink, and a heat dissipation structure is provided on the outside of the heat sink. At this time, the heat dissipation path starting from the power chip usually includes welding layer → electrical connection layer → ceramic layer → metal layer connection layer → welding layer → heat sink → heat dissipation structure. The heat dissipation path is long and the heat dissipation efficiency is low.

[0050] Based on this, the present invention provides a power substrate, comprising: a first metal layer, an insulating layer, and a second metal layer; the insulating layer comprises a top surface facing the power chip and a bottom surface away from the power chip, the first metal layer is located on the bottom surface of the insulating layer and is coated along at least one side surface of the insulating layer to a first area of the top surface of the insulating layer, the second metal layer is located in a second area of the top surface of the insulating layer, and the first metal layer and the second metal layer are isolated from each other on the top surface of the insulating layer; the insulating layer comprises a main body layer made of the same material as the substrate in the power chip to be bonded, the main body layer is provided with an insulating film layer at least in the second area of the top surface, and the second metal layer is isolated from the main body layer by the insulating film layer.

[0051] By using the same material as the substrate of the power chip to be bonded, the thermal expansion coefficients of the insulating layer and the power chip are roughly the same, preventing them from bending in high-temperature environments and allowing the insulating layer to be configured as a flat plate. Furthermore, by providing a first metal layer covering the insulating layer, the structural strength of the entire insulating layer is increased, ensuring that the power substrate meets the required structural performance.

[0052] In order to enable those skilled in the art to better understand the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0053] Example 1

[0054] Please refer to Figure 1 as well as Figure 2 , Figure 1 A schematic structural diagram of a power substrate provided by an embodiment of the present invention; Figure 2 for Figure 1 Schematic diagram of the structure after the power chip is soldered to the medium-power substrate.

[0055] See also Figure 1 as well as Figure 2 In this embodiment, the power substrate includes a first metal layer 2, an insulating layer 1 and a second metal layer 3; the insulating layer 1 includes a top surface facing the power chip 4 and a bottom surface away from the power chip 4, the first metal layer 2 is located on the bottom surface of the insulating layer 1 and is coated along at least one side surface of the insulating layer 1 to the first area of the top surface of the insulating layer 1, the second metal layer 3 is located in the second area of the top surface of the insulating layer 1, and the first metal layer 2 and the second metal layer 3 are isolated from each other on the top surface of the insulating layer 1; the insulating layer 1 includes a main body layer of the same material as the substrate in the power chip 4 to be bonded, and the main body layer is provided with an insulating film layer at least in the second area of the top surface, and the second metal layer 3 is isolated from the main body layer by the insulating film layer.

[0056] The insulating layer 1 is the main structure of the power substrate and must not only provide certain mechanical properties but also possess good heat dissipation and insulation properties. In this embodiment, the insulating layer 1 can be a flat plate, meaning its surface is flat and has no curvature. Therefore, its preparation is relatively simple.

[0057] Specifically, in this embodiment, the insulating layer 1 includes a main body layer of the same material as the substrate material in the power chip 4 to be bonded, and an insulating film layer is provided on the surface of the main body layer. That is, in this embodiment, the insulating layer 1 specifically includes a main body layer and an insulating film layer covering the surface of the main body layer. The main body layer is the main structure of the insulating layer 1, so the main body layer can be a flat plate structure, that is, the surface of the main body layer is flat and has no curvature. In this embodiment, the material of the main body layer needs to be the same as the substrate material in the power chip 4 to be bonded, so that the thermal expansion coefficient of the insulating layer 1 can be roughly the same as the thermal expansion coefficient of the power chip 4. This setting can ensure that in a high-temperature environment, the insulating layer 1 will not bend due to the large difference in thermal expansion coefficient compared with the power chip 4, and ensure that in a high-temperature environment, no gap will be generated between the power substrate and the power chip 4 due to the difference in thermal expansion coefficient. Therefore, the main body layer can be set to a flat plate structure, and the corresponding power substrate can be set to a flat plate structure.

[0058] Since the material of the main body layer is the same as the substrate material of the power chip 4, it is generally a semiconductor material. This material generally has excellent thermal conductivity. However, to ensure its insulation properties, in this embodiment, an insulating film layer is required to be provided at least on the surface of the main body layer. This insulating film layer is usually attached to the surface of the main body layer in the form of a film layer. It generally does not excessively affect the thermal expansion coefficient of the insulating layer 1, but can greatly improve its insulation properties, making the semiconductor main body layer suitable for power substrates.

[0059] The above-mentioned second metal layer 3 is mainly used for welding the power substrate and the power chip 4. The first metal layer 2 is used in this application for heat dissipation on the one hand, and on the other hand, it can also improve the structural strength of the insulating layer 1, so that the insulating layer 1 can achieve the structural strength required by the power substrate. Specifically, in this embodiment, the surface of the insulating layer 1 is divided into a top surface, a bottom surface and a side surface, wherein the top surface is the surface facing the power chip 4, and the bottom surface is the surface away from the power chip 4. The above-mentioned first metal layer 2 is specifically located on the bottom surface of the insulating layer 1 and is coated along at least one side surface of the insulating layer 1 to the first area of the top surface of the insulating layer 1, that is, the above-mentioned first metal layer 2 covers the insulating layer 1 from bottom to top along at least one side surface of the insulating layer 1, that is, the first metal layer 2 generally covers the bottom surface, at least one side surface and part of the top surface of the insulating layer 1 to increase the structural strength of the insulating layer 1. The second metal layer 3 is only located in a partial area of the top surface of the insulating layer 1, and in the top surface of the insulating layer 1, the first area covered by the first metal layer 2 and the second area covered by the second metal layer 3 need to be isolated from each other to avoid direct contact between the first metal layer 2 and the second metal layer 3.

[0060] It should be noted that the above-mentioned insulating film layer needs to be set at least in the second area of the top surface of the main layer, that is, the insulating film layer will isolate the second metal layer 3 from the main layer. The second metal layer 3 is used for welding with the power chip 4. At this time, the second metal layer 3 is electrically isolated from the main layer by the insulating film layer in the thickness direction, and the second metal layer 3 is physically separated from the first metal layer 2 in the horizontal direction. Therefore, this structure can make the second metal layer 3 electrically insulated from the first metal layer 2, avoiding the first metal layer 2 from interfering with the circuit of the power chip 4. In addition to the second area, the above-mentioned insulating film layer can further cover the gap between the first area and the second area, so as to ensure that the first metal layer 2 and the second metal layer 3 are insulated from each other. In a feasible example, the above-mentioned insulating film layer can at least cover the top surface of the main layer to ensure that the first metal layer 2 and the second metal layer 3 are insulated from each other. In another feasible example, in order to facilitate the setting of the insulating film layer, the insulating film layer can cover the entire surface of the main layer.

[0061] Specifically, in this embodiment, the main body layer includes a silicon wafer, and the insulating film layer includes an oxide layer. That is, in this embodiment, a silicon wafer can be selected as the main body layer, and silicon is also the material used for the substrate of the conventional power chip 4. The silicon wafer can be either a single crystal silicon wafer or a polycrystalline silicon wafer, which is not specifically limited here. The selection of a silicon material of the same material as the power chip 4 for the main body layer is conducive to the consistency of the thermal expansion coefficient, and can solve the technical problem of deformation caused by thermal stress during the welding process of the power chip 4, which leads to chip failure. In this embodiment, the insulating layer 1 adopts the same silicon-based material as the power chip 4, and the thermal expansion coefficient is the same or similar. At the same temperature, the deformation is the same, and the error is not large, which avoids the deformation difference caused by the different thermal expansion coefficients of the power substrate during the welding process of the power chip 4, which leads to failure and damage of the power chip 4.

[0062] The oxide layer is specifically required to serve as the insulating film layer to ensure electrical isolation between the first metal layer 2 and the second metal layer 3. Typically, the oxide layer can cover at least the top surface of the silicon wafer. Of course, the oxide layer can further cover the entire surface of the silicon wafer to enhance its insulation properties. It should be noted that the oxide layer needs to be a dense oxide layer, rather than an oxide layer formed by natural oxidation, to enhance its insulation properties.

[0063] Furthermore, the first metal layer 2 can cover all sides of the insulating layer 1 from the bottom surface of the insulating layer 1 to the edge of the top surface of the insulating layer 1. That is, the first metal layer 2 can cover all side walls from the bottom surface to the edge of the top surface of the insulating layer 1. In this case, the second metal layer 3 will be specifically arranged in the central area of the top surface of the insulating layer 1, and the two will be isolated from each other. The spacing between the first metal layer 2 and the second metal layer 3 needs to be determined based on parameters such as the electrical performance of the power substrate and the insulation performance of its insulating film layer, and is not specifically limited here. Assuming that the spacing width between the first metal layer 2 and the second metal layer 3 is D1, the value of D1 is between 0.5mm and 1mm, preferably 0.8mm. Since the first metal layer 2 fully covers the sides of the insulating layer 1, this structure can greatly increase the structural strength of the power substrate and can also help increase the heat dissipation performance of the power substrate. In this embodiment, multiple insulating layers 1 can be connected into a whole based on one first metal layer 2. The specific number of insulating layers 1 can be set according to actual conditions and is again not specifically limited.

[0064] In this embodiment, the material of the above-mentioned first metal layer 2 can be aluminum or copper, and the material of the second metal layer 3 can be aluminum or copper or other metals, which are not specifically limited here. The thickness of the above-mentioned insulating layer 1 is usually 0.2mm to 1.0mm, and the thickness of the above-mentioned second metal layer 3 is usually 0.1mm to 0.3mm. The thickness of the first metal layer 2 needs to be set according to the requirements of heat dissipation performance, structural strength, etc., which are not specifically limited here. It should be noted that the above-mentioned second metal layer 3 is usually a patterned metal layer, which facilitates the electrical connection of the power chip 4. In this embodiment, the power chip 4 and the second metal layer 3 can be interconnected by solder, such as solder paste, solder sheet or active metal solder, and it is necessary to set up additional bonding wires 7 or bonding metal strips based on the power substrate and the power chip 4 for electrical connection and transmission. The required circuit needs to be set according to the actual situation, which is not specifically limited here.

[0065] Furthermore, in this embodiment, the first metal layer 2 attached to the side of the insulating layer 1 can be provided with a connection structure connected to the outer shell 9. The connection structure is used to enable the power substrate to be fixedly connected to the outer shell 9 when packaging the power module. The specific content of the connection structure can be set according to actual conditions and is not specifically limited here. Specifically, in this embodiment, the first metal layer 2 attached to the side of the insulating layer 1 is provided with a mounting hole 5 extending in the thickness direction. The above-mentioned mounting hole 5 serves as a connection structure and can be connected to the outer shell 9 by screws. It should be noted that the mounting hole 5 is provided on the first metal layer 2 attached to the side of the insulating layer 1, and it specifically extends in the thickness direction, such as Figure 1As shown, it does not pass through the insulating layer 1. Therefore, the provision of the mounting hole 5 can avoid affecting the structure of the insulating layer 1, that is, avoiding drilling holes in semiconductor materials such as silicon to ensure that the insulating layer 1 has sufficient structural strength. In addition to providing the mounting hole 5 as a connecting structure, other structures can also be provided as connecting structures, which are not specifically limited here.

[0066] The power substrate provided in this embodiment utilizes the same substrate material for the main layer and the power chip 4 to be bonded. This ensures that the thermal expansion coefficients of the insulating layer 1 and the power chip 4 are substantially the same, preventing them from bending in high-temperature environments and allowing the insulating layer 1 to be configured as a flat plate. Furthermore, the provision of a first metal layer 2 covering the insulating layer 1 increases the structural strength of the entire insulating layer 1, ensuring that the power substrate meets the required structural performance.

[0067] The thermal expansion coefficient of the insulating layer 1 provided in this application is highly compatible with that of the power chip 4. Whether undergoing vacuum high-temperature reflow soldering during production or operating in the high-temperature environment of the module, the deformation of the insulating layer 1 is consistent with that of the power chip 4, reducing the risk of power chip 4 failure and improving device reliability. Furthermore, the power module of this solution utilizes silicon wafers as the main layer, which offers low material cost and high thermal conductivity, thus reducing the size of the power chip 4 and the device volume.

[0068] The specific contents of a power substrate provided in this application will be described in detail in the following embodiments.

[0069] Example 2

[0070] Please refer to Figure 3 , Figure 3 This is a schematic structural diagram of another power substrate provided by an embodiment of the present invention.

[0071] Different from the above embodiment, this embodiment further defines the structure of the power substrate based on the above embodiment. The rest of the contents have been described in detail in the above embodiment and will not be repeated here.

[0072] See also Figure 3In this embodiment, a protruding structure 6 for heat dissipation is provided on the surface of the first metal layer 2 facing away from the insulating layer 1. The protruding structure 6 needs to be fixedly connected to the first metal layer 2 so that heat can be transferred to the protruding structure 6 through the first metal layer 2 for heat dissipation. The protruding structure 6 can increase the heat dissipation area relative to the first metal layer 2, and the protruding structure 6 can be further combined with heat dissipation components such as water cooling to improve the heat dissipation performance of the power substrate. It should be noted that the combination of the protruding structure 6 and the first metal layer 2 is equivalent to a traditional heat sink, that is, in this embodiment, the power substrate and the heat sink can be combined with each other by directly providing the protruding structure 6 on the surface of the first metal layer 2. The heat conduction path is very short, which helps to improve the heat dissipation performance of the power substrate.

[0073] Specifically, in this embodiment, the raised structure 6 includes heat dissipation columns extending along a side away from the insulating layer 1, with the columns arranged in an array. These columns, combined with the first metal layer 2, form a PIN-FIN heat dissipation structure, with the first metal layer 2 serving as the base of the PIN-FIN heat dissipation structure. This structure ensures excellent heat dissipation performance of the power substrate, ultimately further enhancing the heat dissipation capability of the power module.

[0074] In this embodiment, the second metal layer 3 is a metal layer that is fluid when fixing the power chip 4 at the first temperature. In this application, the soldering of the power substrate and the power chip 4 will be carried out at a higher temperature, which is recorded as the first temperature in this embodiment. In this embodiment, the second metal layer 3 needs to be fluid when it is heated to the first temperature for soldering the power substrate and the power chip 4. At this time, the second metal layer 3 itself can be used as solder to solder the insulating layer 1 and the power chip 4 to each other, without the need for additional solder to solder the power chip 4 to the second metal layer 3. Therefore, after packaging the power chip 4, the structure can further reduce the use of a layer of solder in the heat dissipation path from the power chip 4 to the heat dissipation structure, thereby further improving the heat dissipation performance. And setting the second metal layer 3 to be a metal layer that is fluid at the first temperature can further avoid warping between the second metal layer 3 and the insulating layer 1 due to the difference in thermal expansion coefficient when soldering the power chip 4. At this time, the fluid second metal layer 3 can effectively fill the gap between the insulating layer 1 and the power chip 4, ensuring a close bond between the two. The second metal layer 3 may be in a liquid state or a semi-solid state at the first temperature, and no specific limitation is made here, as long as it has fluidity.

[0075] Typically, the metal layer, which is liquid or semi-solid at the first temperature, requires patterning. The purpose of patterning is to ensure that a specific circuit is formed to facilitate electrical connection to the power chip 4, while also preventing the second metal layer 3 from flowing off the surface of the insulating layer 1 and contacting the first metal layer 2 at the first temperature. Because this metal layer is fluid at the first temperature, gaps created by differences in thermal expansion coefficients between the second metal layer 3 and the insulating layer 1 during soldering can be further avoided. Furthermore, the second metal layer 3 can directly fill gaps created by slight differences in thermal expansion coefficients between the insulating layer 1 and the power chip 4, ensuring that the insulating layer 1 maintains a flat plate structure. In this embodiment, the second metal layer 3 may be an aluminum-based active metal (Al-Si-Ti series). Its specific material can be customized based on actual conditions and is not specifically limited herein.

[0076] In another feasible example, a solder layer is provided on the surface of the second metal layer 3 facing away from the insulating layer 1, and the solder layer is used to fix the power chip 4. When the second metal layer 3 is a metal layer that is still solid at the first temperature, such as an aluminum layer, a copper layer, etc., in this example, a solder layer can be further provided on the surface of the second metal layer 3 facing away from the insulating layer 1, and the solder layer can ensure the fixed connection between the power chip 4 and the second metal layer 3 during welding. The solder layer also needs to have fluidity at the first temperature, and can further avoid the gap between the second metal layer 3 and the power chip 4 due to the difference in thermal expansion coefficient during the welding process, ensuring that the insulating layer 1 can be a flat plate structure. The specific material of the solder layer can be set according to actual conditions and is not specifically limited here. A power substrate provided in this embodiment can integrate the function of a heat sink in the power substrate by providing a raised structure 6, reduce the length of the heat dissipation path, and help improve the heat dissipation performance. Using a metal layer that is fluid at the first temperature as the second metal layer 3 can further ensure that the power substrate can still form a good electrical connection with the power chip 4 under the flat structure, further reducing the failure problem caused by the inconsistent thermal expansion coefficient of the power chip 4 and the insulating layer 1, improving the reliability of the power module, and ensuring the product production yield.

[0077] Specifically, the second metal layer 3 is formed using a metal layer that is liquid at the first temperature, further avoiding failure of the power chip 4 due to inconsistent thermal expansion coefficients, improving the production yield of the power module and reducing cost losses. Compared with the thermal stress compensation structure of the existing heat sink base plate, the present application does not require an arc design, has a thin solder layer, good soldering quality, low residual stress, low leakage risk, and high reliability.

[0078] Example 3

[0079] Please refer to Figure 4 as well as Figure 5 , Figure 4A schematic diagram of the exploded structure of a power module provided by an embodiment of the present invention; Figure 5 A schematic structural diagram of a power module provided by an embodiment of the present invention.

[0080] See also Figure 4 as well as Figure 5 This embodiment further provides a power module, which includes a power chip 4 and a power substrate as provided in any of the above-mentioned embodiments of the invention. The power chip 4 is specifically fixedly connected to the second metal layer 3, thereby achieving a fixed connection between the power chip 4 and the power substrate. The structure of the power substrate can be referred to the above-mentioned embodiment and will not be described in detail here. The specific structure of the power chip 4 can be referred to the existing technology and will not be described in detail here.

[0081] In addition to the aforementioned power chip 4 and power substrate, a power module typically includes a cover plate 11, a housing 9, power pins 8, bonding wires 7, and an encapsulant 10. Specifically, the power module can be formed using the standard HPD (High Power Device) packaging format. Specifically, the power chip 4 can be arranged on the second metal layer 3 in a bridge circuit configuration. The bonding wires 7 provide direct electrical connections between the power chips 4 and with external circuits. The power pins 8 are used to control and sample the power chip 4. The entire module is encapsulated in the housing 9, then potted with glue and dried to form a finished product.

[0082] For example, the power module shown in this application is a three-phase full-bridge power module, and the packaging form is HPD. It can also be a half-bridge module or an H-bridge module, and the packaging form can also be selected as ME4, HP1, etc. This application does not impose fixed restrictions.

[0083] Since the power module of this embodiment is provided with the power substrate provided by the above-mentioned embodiment of the invention, the preparation cost of the power module is lower, the structure is simpler, the heat dissipation is more efficient, and thus the performance is more stable.

[0084] Example 4

[0085] A method for preparing a power substrate provided in this embodiment is introduced below. The method for preparing the power substrate described below and the power substrate described above can be referred to in correspondence with each other.

[0086] Please refer to Figures 6 to 8 , Figure 6 A flow chart of a method for preparing a power substrate provided in this embodiment; Figure 7 A schematic diagram of a top view of a power substrate prepared in this embodiment; Figure 8 for Figure 7 Sectional view along line AA.

[0087] See also Figures 6 to 8 In this embodiment, the method for preparing a power substrate includes:

[0088] S101: Disposing a first metal layer covering the insulating layer on the surface of the insulating layer.

[0089] In this embodiment, the insulating layer 1 includes a top surface facing the power chip 4 and a bottom surface facing away from the power chip 4. The first metal layer 2 is located on the bottom surface of the insulating layer 1 and covers the first area of the top surface of the insulating layer 1 along at least one side surface of the insulating layer 1. The specific structures of the first metal layer 2 and the insulating layer 1 have been described in detail in the above embodiments and will not be repeated here.

[0090] Prior to this step, an insulating film layer must be formed on the surface of the main body layer. The details of this process will be described in detail in the following embodiments. In this step, a first metal layer 2 is formed to cover the insulating layer 1. This first metal layer 2 must be directly formed on the surface of the insulating layer 1, rather than being bonded to the insulating layer 1 via solder or other structures. The specific preparation process will be described in detail in the following embodiments and will not be repeated here.

[0091] S102: Disposing a second metal layer on the surface of the insulating layer coated with the first metal layer.

[0092] In this embodiment, the second metal layer 3 is located in the second region of the top surface of the insulating layer 1. The first metal layer 2 and the second metal layer 3 are isolated from each other on the top surface of the insulating layer 1. The insulating layer 1 includes a main body layer made of the same material as the substrate of the power chip 4 to be bonded. The main body layer is provided with an insulating film layer at least in the second region of the top surface. The second metal layer 3 is isolated from the main body layer by the insulating film layer. The specific structures of the second metal layer 3 and the insulating layer 1 have been described in detail in the above embodiment and will not be repeated here.

[0093] In this step, a second metal layer 3 is provided on the surface of the insulating layer 1. The material of the second metal layer 3 can be the same as or different from that of the first metal layer 2. The specific content will be described in detail in the following embodiments and will not be repeated here.

[0094] This embodiment provides a method for fabricating a power substrate. By arranging the main body layer and the substrate material of the power chip 4 to be bonded to the substrate to be bonded to the substrate, the thermal expansion coefficients of the insulating layer 1 and the power chip 4 are substantially the same, preventing them from bending in high-temperature environments and allowing the insulating layer 1 to be configured as a flat plate. Furthermore, by providing a first metal layer 2 covering the insulating layer 1, the structural strength of the entire insulating layer 1 is increased, ensuring that the power substrate meets the required structural performance.

[0095] The specific contents of the power substrate preparation method provided by the present invention will be described in detail in the following embodiments.

[0096] Example 5

[0097] Please refer to Figure 9 , Figure 9 The present invention provides a flow chart of a specific method for preparing a power substrate.

[0098] See also Figure 9 In this embodiment, the method for preparing a power substrate includes:

[0099] S201: Oxidizing at least the top surface of the silicon wafer based on a dry oxygen oxidation process to form an oxide layer covering at least the top surface of the silicon wafer.

[0100] Before this step, the silicon wafer surface is typically cleaned to remove contaminants. Specifically, in this embodiment, an RCA cleaning method (SC1 (ammonia + hydrogen peroxide + water) or SC2 solution (hydrochloric acid + hydrogen peroxide + water)) can be used to remove organic matter, metallic impurities, and particulate contaminants from the silicon wafer surface. The silicon wafer is then immersed in a dilute hydrofluoric acid (HF) solution (1:50 dilution) for 5 to 15 minutes to remove the naturally occurring thin oxide layer. In addition to the aforementioned methods, plasma cleaning can also be used in this embodiment to remove contaminants and the naturally oxidized loose oxide layer from the silicon wafer surface. The specific cleaning process is not specified here and will depend on the specific circumstances.

[0101] In this step, a dense oxide layer needs to be formed on the surface of the silicon wafer to ensure its insulation and mechanical properties. The oxidation method of this embodiment can be dry oxygen oxidation, specifically:

[0102] S2011: Place the silicon wafer with the natural oxide film removed in 99.9% anhydrous alcohol and perform ultrasonic cleaning at a frequency of 10kHz to 15kHz for 5 minutes to 10 minutes, then place the silicon wafer in a hot air circulation oven and bake it at 100℃ to 120℃ for 5-10 minutes to keep it dry.

[0103] S2012: Place the dried silicon wafer in a quartz boat and send it into a high-temperature furnace tube, heating it to 1000°C at a rate of 5°C / min to 10°C / min to avoid warping of the silicon wafer due to thermal stress.

[0104] S2013: Inert gas, such as N2, is introduced to keep the temperature in the high-temperature furnace tube stable and ensure temperature uniformity in the furnace.

[0105] S2014: High-purity oxygen is introduced at a rate of 1 L / min to 10 L / min for 30 to 60 minutes to form a dense oxide layer as an insulating film layer.

[0106] S2015: After the oxide layer is formed, cool down to room temperature at a rate of 3°C / min to 5°C / min to prevent cracks caused by thermal shock.

[0107] S2016: Place the oxidized silicon wafer in 99.9% anhydrous alcohol and perform ultrasonic cleaning at 5kHz to 15kHz for 5 minutes to 10 minutes. Then place it in a hot air circulation oven and bake it at 50℃ to 75℃ for 10 minutes to 15 minutes to keep the silicon wafer dry.

[0108] Through the above steps, a dense oxide layer can be formed on the surface of the silicon wafer to form the insulating layer 1.

[0109] S202: Place the insulating layer into the jig.

[0110] In this step, a jig, such as an aluminizing mold, can be used to deposit the first metal layer 2 on the surface of the insulating layer 1. Specifically, in this step, the insulating layer 1 is first placed in a jig, such as an aluminizing mold, and then placed in a vacuum reaction chamber and preheated to 500°C to 700°C to reduce thermal shock to the insulating layer 1 in subsequent steps.

[0111] S203: injecting molten metal material into the surface of the insulating layer along the jig to form a first metal layer covering the insulating layer.

[0112] Taking aluminum metal as the first metal layer 2 as an example, it is usually necessary to prepare a molten metal material before this step, which can specifically include: placing a high-purity aluminum ingot (purity ≥99.5%) in a graphite crucible, heating it to a molten state (660°C to 750°C), and adding a covering agent, such as a mixture of KCl and NaCl to prevent the molten aluminum water from oxidizing, or passing an inert gas such as Ar gas for protection.

[0113] In this step, it is first necessary to introduce aluminum source gas, such as trimethylaluminum Al(CH3)3 or AlCl3 and carrier gas, such as H2 or Ar, into the above-mentioned vacuum reaction chamber at 10 L / min to 15 L / min, and slowly inject the molten aluminum water along the jig into the surface of the insulating layer 1 until a Si-Al layer in a coated state is formed. Then, the injection of the aluminum source gas is stopped, and an inert atmosphere such as Ar and / or N2 is introduced at 20 L / min to 30 L / min and cooled to room temperature to ensure the density of the first metal layer 2 and the insulating layer 1.

[0114] After this step, diffusion annealing can be performed, which specifically involves placing the insulating layer 1 coated with the first metal layer 2 in a tube furnace, introducing Ar gas, raising the temperature to 400°C to 600°C, and maintaining the temperature for 1 to 3 hours to ensure that an Al-Si diffusion layer is formed between the first metal layer 2 and the insulating layer 1, forming a Si-Al substrate to improve the reliability of the power substrate; and then naturally cooling to room temperature in the tube furnace.

[0115] Afterwards, the excess aluminum layer on the surface of the Si-Al substrate can be removed using dilute hydrochloric acid (HCl, concentration 5% to 10%) or mechanical polishing. The Si-Al substrate is then ultrasonically cleaned in 99.9% anhydrous alcohol at 5kHz-15kHz for 5-10 minutes. The substrate is then placed in a hot air circulating oven at 50°C to 75°C for 10-15 minutes to keep it dry. It should be noted that depending on the material of the first metal layer 2, the aluminum in the above process can be replaced with other metals, and the relevant parameters can be adjusted, without specific limitations here.

[0116] In this embodiment, depending on the structure of the jig, a first metal layer 2 can be formed to cover different surfaces of the insulating layer 1. At this time, the second metal layer 3 can be prepared in different ways according to different needs. For example, when it is determined that the material of the second metal layer 3 is the same as that of the first metal layer 2, a first metal layer 2 that fully covers all surfaces of the insulating layer 1 can be formed by the jig in the above steps. At this time, the first metal layer 2 covers the top surface of the insulating layer 1. Correspondingly, when forming the second metal layer 3, it can be prepared by the following steps: etching the first metal layer 2 on the top surface of the insulating layer 1 to form a second metal layer 3 isolated from the first metal layer 2. This method is relatively simple, but it is necessary to ensure that the second metal layer 3 is made of the same material as the first metal layer 2. And because the first metal layer 2 needs to ensure good heat dissipation performance and is used to improve the structural strength of the insulating layer 1, this method cannot form a second metal layer 3 that has fluidity at high temperatures.

[0117] If it is necessary to form a second metal layer 3 that is fluid at high temperatures, in this step, when the excess aluminum layer is removed by a jig and the above-mentioned use of dilute hydrochloric acid or mechanical polishing, the first metal layer 2 of the final structure in the above embodiment can be formed. At this time, the second area of the top surface of the insulating layer 1 will be exposed, and the first metal layer 2 only covers the first area of the surface of the insulating layer 1 to facilitate the execution of subsequent steps.

[0118] S204: providing a patterned metal layer as a second metal layer on the surface of the insulating layer coated with the first metal layer.

[0119] In this embodiment, the metal layer is a metal layer that is fluid when the power chip is fixed at the first temperature. In this step, a metal layer that is fluid at the first temperature can be used as the second metal layer 3. Taking aluminum-based active metal (Al-Si-Ti series) as an example, in this step, the second metal layer 3 is fixed to the second area on the top surface of the insulating layer 1 according to the required circuit using a mold, and then the substrate is placed in a vacuum soldering furnace for vacuum reflow sintering, maintaining the vacuum level in the furnace less than <1×10 -3 Pa, and step-by-step heating to 200°C to 300°C at a heating rate of 5°C / min to 10°C / min, maintaining the constant temperature for 30min to 45min, and then cooling to room temperature at a rate of 3°C / min to 5°C / min to form a second metal layer 3.

[0120] For example, this embodiment may also use traditional metals such as Cu, Al, etc. for sintering to form the second metal layer 3, or the second metal layer 3 may be set by an electroplating process. There is no fixed restriction here. This application preferably uses active metals with fluidity at high temperatures for sintering to perform circuit layout to produce the power substrate of this application.

[0121] The present embodiment provides a method for preparing a power substrate. By improving the traditional substrate and integrating it with the heat sink, and through the aluminum infiltration process, complete contact between the aluminum heat sink and the silicon plate is ensured. Compared with the traditional welding process, the process of the present application directly and significantly increases the contact area between the substrate and the heat sink, thereby improving the heat dissipation capacity.

[0122] Example 6

[0123] The following is an introduction to a method for preparing a power module provided in this embodiment. The method for preparing the power module described below and the power module described above can be referenced to each other.

[0124] In this embodiment, based on the method for preparing a power substrate provided in the above embodiment, a complete power module is further prepared based on the prepared power substrate. Specifically, after the above power substrate is prepared, this embodiment may further include:

[0125] S1: Provide a power substrate and several power chips, and fix the power chips on the second metal layer.

[0126] When the above-mentioned second metal layer 3 is a metal layer that remains solid at the first temperature, such as an aluminum layer or a copper layer, this step can specifically include soldering the power chip 4 to the second metal layer 3 through solder. At this time, this step can specifically include: passing a number of power chips 4 and solder through an automatic placement machine, mounting the power chip 4 on the second metal layer 3, and then placing it in a vacuum reflow soldering fixture at 150°C to 200°C for vacuum soldering for 30 minutes to 35 minutes, and then step-cooling it down to room temperature at a rate of reducing 20°C per minute.

[0127] When the second metal layer 3 is a metal layer that is fluid at the first temperature, the second metal layer 3 can be directly treated as solder, allowing the power chip 4 and the insulating layer 1 to be soldered to each other. In this embodiment, using solder or treating the second metal layer 3 as solder can avoid deformation caused by inconsistent thermal expansion coefficients between the power chip 4, the second metal layer 3, and the insulating layer 1, which could lead to tensile failure of the power chip 4. This method also reduces the probability of voids, effectively reducing the void rate between the power chip 4 and the power substrate, and effectively ensuring the product's heat dissipation performance and reliability.

[0128] Subsequently, in this embodiment, the welded semi-finished power module with power chip 4 can be placed in an X-ray device with a voltage of 80V to 120V, a current of 100μA to 300μA, and a focal length (SOD / SDD) preferably set to: SOD [Optimized Source-Object Distance] ϵ (100, 300) mm, SDD [Object-Detector Distance] ϵ (300, 500) mm. After adding a copper filter or aluminum filter with a thickness of 0.5mm to 0.8mm, the power chip 4 and the solder layer between the power chip 4 and the power substrate are inspected and feedback is provided. If the solder void rate (defect area / total solder joint area × 100%) is not less than 3%, the module is deemed unqualified and the semi-finished product is scrapped. At this point, the relevant welding parameters need to be adjusted. If the solder void rate is less than 3%, the module is deemed qualified.

[0129] This step adds copper or aluminum filters to filter low-energy rays, reduce noise, improve verification accuracy, and effectively ensure product reliability.

[0130] S2: Provide several bonding wires and perform bonding connections between chips according to the electrical structure diagram.

[0131] The bonding wire 7 includes aluminum wire, copper wire, etc., and aluminum wire is preferred in this application. This step specifically includes:

[0132] Provide a number of bonding wires 7 and / or bonding metal strips, and use ultrasonic bonding to perform electrical connections of the power chip 4 and realize the electrical functions of the power module in accordance with a bridge circuit. Specifically, it includes:

[0133] Provide several bonding wires 7, place the semi-finished power module in a bonding jig, fix it, and then place it in an ultrasonic bonding device. Set the ultrasonic frequency to 20 kHz to 60 kHz, the pressure to 0.5N to 1.5N, the bonding temperature to 100°C to 150°C, and use nitrogen circulation to prevent oxidation. After controlling the arc height to 1mm to 1.5mm, according to the bridge electrical topology, realize the connection between the upper bridge and the lower bridge, the power chip 4 and the signal layer.

[0134] S3: Provide several power pins, pins, and thermal-sensitive resistors, which are connected to the corresponding sampling positions and control positions of the second metal layer according to the electrical structure.

[0135] This step specifically includes:

[0136] Place the power pin 8, pin and thermistor in a soldering jig, and vacuum solder them in a vacuum reflow soldering equipment at 100°C to 150°C for 10 to 15 minutes using any solder, and then cool them to room temperature at a rate of 15°C / min. The power pin 8 includes a sampling pin and a control pin according to its setting position and function. The sampling pin and control pin are set at the sampling position and control position corresponding to the bridge circuit.

[0137] S4: providing a housing to encapsulate the semi-finished power module and form a cavity, and pouring the encapsulation colloid 10 into the cavity, drying and curing it.

[0138] This step specifically includes:

[0139] S41: The welded semi-finished power module is placed in a fixed mold or fixed machine tool. A housing 9 of the desired packaging form is provided, and a strong bonding adhesive is applied to the outline of the housing 9 and also to the vertical projection of the housing 9 on the heat dissipation substrate. This vertical projection is typically provided with a connection structure such as the aforementioned mounting hole 5.

[0140] S42: Provide fixing members, such as screws, bolts, etc., and connect the housing 9 to the power substrate through the fixing holes of the housing 9 and the mounting holes 5 of the power substrate.

[0141] S43: placing the fixed semi-finished module with the housing 9 in an oven, and baking it in a vacuum environment at 50° C. to 75° C. for 15 to 30 minutes to completely solidify the strong connection colloid.

[0142] The above-mentioned strong connection colloid is preferably epoxy resin or silicone, and its thermal conductivity is usually 1 W / m·K to 5 W / m·K. The strong connection colloid fills the gap between the shell 9 and the power substrate. The thickness of the glue layer is usually not more than 100μm, and the amount of glue overflow is usually less than 0.5mm. The amount of glue overflow needs to be precisely controlled by a glue dispensing machine.

[0143] S44: After heating the semi-finished power module with the shell 9 to 40°C to 60°C, place it in a glue potting jig, machine tool or assembly line, and use the glue potting equipment to encapsulate the power module, power chip 4, and bonding wire 7 at a speed of 5mm / s to 25mm / s. Stop the glue potting when the encapsulation glue 10 is encapsulated to two-thirds of the height of the shell 9.

[0144] S45: Place the semi-finished product after encapsulation in an oven for vacuum baking. First, bake it at 40°C to 60°C for 1 to 2 hours to slowly cross-link it and reduce internal stress; then bake it at 100°C to 150°C for 2 to 4 hours to completely cure the encapsulation glue 10.

[0145] In this embodiment, the encapsulating colloid 10 is preferably silicone gel, and other encapsulating materials such as epoxy resin may also be selected.

[0146] S5: Cover the cover to form a power module. Spray anti-oxidation material on the exposed part and pack it for storage.

[0147] In this step, a cover plate 11 is provided that can be snapped onto the housing 9. An anti-oxidation agent, such as silicone gel or polyurethane, is then sprayed onto the exposed portion of the power substrate. The substrate is then dried at 50°C to 75°C for 30 to 45 minutes, packaged, and stored at room temperature, preferably in a vacuum. In this embodiment, the silicon wafer can be either an intrinsic silicon wafer or a multicrystalline silicon wafer.

[0148] The method for preparing a power module provided in this embodiment can prepare a power module with high heat dissipation performance at a relatively low cost.

[0149] The thermal expansion coefficient of the power substrate in this application closely matches that of the power chip 4. Whether undergoing vacuum high-temperature reflow soldering during production or operating in the high-temperature environment of the module, the deformation of the power substrate and the power chip 4 remain consistent, reducing the risk of power chip 4 failure and improving power module reliability. Furthermore, the power substrate in this application utilizes a silicon wafer as its substrate, which offers low material cost and high thermal conductivity, contributing to a reduction in the size of the power chip 4 and the volume of the power module.

[0150] Compared to conventional power modules, the power module of this application eliminates the copper foil layer between the power substrate and the heat sink, significantly reducing the overall thermal resistance of the power module. Furthermore, the second metal layer 3, made of a metal that is fluid at high temperatures, exhibits excellent flexibility at high temperatures, further preventing failure of the power chip 4 due to inconsistent thermal expansion coefficients and improving the production yield of the power module. The power module of this application has a lightweight structure, eliminates multiple layers of metal and solder, and offers low cost and high reliability.

[0151] The power substrate of this application does not require arc design or micro-arc, and has a thin solder layer, good soldering quality, small residual stress, low leakage risk, and high reliability. This application reduces thermal resistance, and while reducing materials, the lateral heat dissipation capacity of the power module is increased by 1 to 10 times, and the heat dissipation performance is improved while ensuring reliability. The manufacturing process of this application has been greatly changed compared to the existing technology. By using a high-temperature and fluid metal layer, the production yield is improved, the void rate is reduced, and the product reliability is improved, making it suitable for industrial mass production applications.

[0152] The insulating layer 1 of the present application is made of the same silicon material as the power chip 4, which is conducive to synchronous thermal expansion consistency and can solve the problem of deformation caused by thermal stress during the welding process of the power chip 4, which leads to chip tearing. At the same temperature, the two have the same deformation and the error is not large, which avoids the deformation difference caused by the different thermal expansion coefficients of the power substrate during the welding process of the power chip 4, which leads to tearing and damage of the power chip 4. The solution provided by the present application greatly reduces the terminal application cost by 1 / 3, which is conducive to industrial and commercial mass production and application.

[0153] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0154] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0155] The above is a detailed introduction to a power substrate, a power module, and a method for preparing a power substrate provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only intended to help understand the method and core ideas of the present invention. It should be pointed out that, for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications may be made to the present invention, and such improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A power substrate, characterized in that: include: a first metal layer, an insulating layer, and a second metal layer; The insulating layer includes a top surface facing the power chip and a bottom surface away from the power chip, the first metal layer is located on the bottom surface of the insulating layer and covers a first area of the top surface of the insulating layer along at least one side surface of the insulating layer, the second metal layer is located in a second area of the top surface of the insulating layer, and the first metal layer and the second metal layer are isolated from each other on the top surface of the insulating layer; The insulating layer includes a main body layer made of the same material as the substrate of the power chip to be bonded, the main body layer is provided with an insulating film layer at least in the second area of the top surface, and the second metal layer is isolated from the main body layer by the insulating film layer.

2. The power substrate according to claim 1, wherein: The main layer includes a silicon wafer, and the insulating film layer includes an oxide layer.

3. The power substrate according to claim 2, wherein: The oxide layer at least covers the top surface of the silicon wafer.

4. The power substrate according to claim 1, wherein: The first metal layer covers all side surfaces of the insulating layer from the bottom surface of the insulating layer to the edge of the top surface of the insulating layer.

5. The power substrate according to any one of claims 1 to 4, characterized in that: The second metal layer is a metal layer having fluidity when fixing the power chip at a first temperature.

6. The power substrate according to any one of claims 1 to 4, characterized in that: A solder layer is provided on a surface of the second metal layer facing away from the insulating layer, and the solder layer is used to fix the power chip.

7. A power module, characterized in that: The invention comprises a power chip and the power substrate according to any one of claims 1 to 6, wherein the power chip is fixedly connected to the second metal layer.

8. A method for preparing a power substrate, characterized in that: include: Arranging a first metal layer covering the insulating layer on the surface of the insulating layer; The insulating layer is made of the same material as the substrate of the power chip to be bonded, the insulating layer includes a top surface facing the power chip and a bottom surface away from the power chip, the first metal layer is located on the bottom surface of the insulating layer and covers a first area of the top surface of the insulating layer along at least one side surface of the insulating layer; A second metal layer is arranged on the surface of the insulating layer covered with the first metal layer; the second metal layer is located in the second area of the top surface of the insulating layer, and the first metal layer and the second metal layer are isolated from each other on the top surface of the insulating layer; the insulating layer includes a main body layer made of the same material as the substrate in the power chip to be bonded, and the main body layer is provided with an insulating film layer at least in the second area of the top surface, and the second metal layer is isolated from the main body layer by the insulating film layer.

9. The method according to claim 8, characterized in that Providing a first metal layer covering the insulating layer on the surface of the insulating layer comprises: Place the insulation layer into the jig; A molten metal material is injected along the jig into the surface of the insulating layer to form a first metal layer covering the insulating layer.

10. The method according to claim 8, characterized in that Providing a second metal layer on the surface of the insulating layer coated with the first metal layer comprises: A patterned metal layer is provided on the surface of the insulating layer coated with the first metal layer as the second metal layer; the metal layer is a metal layer having fluidity when fixing the power chip at a first temperature.

Images