Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a lead frame, a chip and a plurality of spaced first leads. The lead frame comprises a base island and a first pin; the base island is provided with a first side edge and a second side edge which are opposite to each other along a first direction, and a third side edge and a fourth side edge which are opposite to each other along a second direction; the first pin is located on the side where the third side edge is located and is close to the second side edge. Wherein a non-zero included angle is formed between the first direction and the second direction; the chip is provided with a front surface and a back surface which are deviated from each other, and the front surface of the chip is provided with a first electrode and a control electrode; the chip is arranged on the base island, and the back surface of the chip faces the base island; the first electrode is closer to the second side edge relative to the control electrode; the geometric center of the chip is closer to the second side edge relative to the geometric center of the base island; a plurality of spaced first leads are connected with the first electrode and the first pin.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] On-resistance (Rdson) is a key parameter for metal oxide field-effect transistors (MOSFETs). For similar MOSFET devices, the lower the on-resistance, the lower the power loss during operation. Therefore, reducing a product's on-resistance is crucial for improving its power density.

[0003] In the related art, the method of improving the on-resistance of the package is mainly to reduce the on-resistance by increasing the frame area. This method of reducing the on-resistance by changing the frame size not only increases investment and significantly increases costs, but also takes a long time. Summary of the Invention

[0004] An embodiment of the present application provides a semiconductor structure, comprising:

[0005] A lead frame comprising a base island and a first lead; the base island having a first side and a second side opposite to each other along a first direction, and a third side and a fourth side opposite to each other along a second direction; the first lead being located on a side where the third side is located and close to the second side; wherein a non-zero angle is formed between the first direction and the second direction;

[0006] A chip having a front side and a back side facing away from each other, wherein the front side of the chip is provided with a first electrode and a control electrode; the chip is arranged on the base island, and the back side of the chip faces the base island; the first electrode is closer to the second side than the control electrode; and the geometric center of the chip is closer to the second side than the geometric center of the base island;

[0007] A plurality of spaced first lead lines connect the first electrode and the first pin.

[0008] In some embodiments, the orthographic projection of the chip on the plane of the front surface of the chip is located within the orthographic projection of the base island on the plane of the front surface of the chip, and the projection area of the chip is smaller than the projection area of the base island.

[0009] In some embodiments, a distance between an edge of the chip and the second side of the base island is greater than or equal to 400 μm.

[0010] In some embodiments, the first lead includes a bonding portion close to the base island and used for bonding the first lead, and a lead body located on a side of the bonding portion away from the base island, and the maximum width of the bonding portion in the first direction is greater than the maximum width of the lead body in the first direction;

[0011] In which, the bonding portion has a first bonding side and a second bonding side opposite to each other in the first direction, the position of each first lead farthest from the second side in the second direction is located on the side of the first bonding side close to the second side, and the position of each first lead closest to the second side in the second direction is located on the side of the second bonding side away from the second side.

[0012] In some embodiments, each of the first leads includes a first portion at least partially welded to the first electrode and a second portion connecting the first portion and the first pin; the first electrode has a group of first welding points and second welding points opposite to the first portion of each first lead, and the first portion of each first lead is welded to the corresponding group of first welding points and second welding points.

[0013] In some embodiments, the first welding points and the second welding points of the same group are arranged at intervals in a direction perpendicular to the first direction, and the second welding points are closer to the third side; the end of the first part of each first lead facing away from the second part is welded to the corresponding first welding point, and the end close to the second part is welded to the corresponding second welding point.

[0014] In some embodiments, the lead frame includes a second pin, the second pin is located on the side where the third side is located, is spaced apart from the first pin in the first direction, and is closer to the first side;

[0015] The semiconductor structure further includes a second lead connecting the control electrode and the second pin;

[0016] A second electrode is provided on the back side of the chip, and the second electrode is connected to the base island;

[0017] One of the first electrode and the second electrode is a source electrode, and the other is a drain electrode.

[0018] In some embodiments, the lead frame further includes a third pin, which is connected to the base island from a third side of the base island, and the orthographic projections of the first pin, the third pin and the second pin on the plane where the front side of the chip is located are spaced apart in the first direction.

[0019] The present invention further provides a method for preparing a semiconductor structure, the method comprising:

[0020] A lead frame is provided, the lead frame comprising a base island and a first lead; the base island having a first side and a second side opposite to each other along a first direction, and a third side and a fourth side opposite to each other along a second direction; the first lead is located on a side where the third side is located and is close to the second side; wherein a non-zero angle is formed between the first direction and the second direction;

[0021] A chip is placed on a base island of a lead frame, wherein the chip has a front side and a back side facing away from each other, the front side of the chip is provided with a first electrode and a control electrode; the back side of the chip faces the base island; the first electrode is closer to the second side than the control electrode; and the geometric center of the chip is closer to the second side than the geometric center of the base island;

[0022] A plurality of spaced first lead lines are provided, and the plurality of spaced first lead lines connect the first electrode and the first pin.

[0023] In some embodiments, each of the first leads includes a first portion at least partially welded to the first electrode and a second portion connecting the first portion and the first pin; the first electrode includes a group of first and second welding points opposite to the first portion of each first lead; wherein the first and second welding points in the same group are spaced apart in a direction perpendicular to the first direction, and the second welding points are closer to the third side, or a line connecting the first and second welding points in the same group has a non-perpendicular angle with the first direction, and the second welding points are closer to the second side and the third side;

[0024] The first lead lines provided with a plurality of intervals include:

[0025] The end of the first portion of each first lead facing away from the second portion is welded to the first welding point, and the end of the first portion of each first lead close to the second portion is welded to the second welding point.

[0026] The main technical effects achieved by the embodiments of the present application are:

[0027] The semiconductor structure and preparation method provided in the embodiments of the present application can effectively control the length of the bonding wire to be shorter by setting the geometric center of the chip closer to the second side relative to the geometric center of the base island, thereby reducing the on-resistance of the semiconductor structure. This solution can effectively control the length of the bonding wire by adjusting the chip mounting position to reduce the on-resistance of the semiconductor structure. Compared with the method of reducing the on-resistance by changing the frame size, it does not require additional investment in increasing the frame size, which is beneficial to cost control. There is no need to wait for a long time for the manufacture of a separate adapted frame, which is beneficial to ensuring the production efficiency of the product, and can adapt to a variety of different types of products, with a wider range of adaptability. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a three-dimensional structural diagram of a semiconductor structure provided by an exemplary embodiment of the present application;

[0029] Figure 2 It is along Figure 1 The cross-sectional view taken along the section line AA' is shown;

[0030] Figure 3 is a partial side view of a semiconductor structure provided by an exemplary embodiment of the present application;

[0031] Figure 4 is a partial side view of a semiconductor structure provided by an exemplary embodiment of the present application;

[0032] Figure 5 is a partial side view of another semiconductor structure provided by an exemplary embodiment of the present application;

[0033] Figure 6 is a flow chart of a method for preparing a semiconductor structure provided by an exemplary embodiment of the present application;

[0034] Figure 7 This is a partial structural diagram of a lead frame provided by an exemplary embodiment of the present application;

[0035] Figure 8 It is a first intermediate structure formed when a semiconductor structure is manufactured using a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0036] Figure 9 A second intermediate structure is formed when a semiconductor structure is manufactured using a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0037] Figure 10 A semiconductor structure is prepared by using a method for preparing a semiconductor structure provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0038] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0039] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0040] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0041] After research, the inventors found that in the related art, the chip in the metal oxide field effect transistor device is generally set in the center of the lead frame base island. Based on this, in order to reduce the on-resistance in the metal oxide field effect transistor device, the present application provides a semiconductor structure and a preparation method thereof. The semiconductor structure includes a lead frame, a chip and multiple spaced first leads. The lead frame includes a base island and a first lead; the base island has a first side and a second side opposite to each other along a first direction, and a third side and a fourth side opposite to each other along a second direction; the first lead is located on the side where the third side is located and is close to the second side; wherein the first direction and the second direction have a non-zero angle; the chip has a front and a back side that are opposite to each other, and the front side of the chip is provided with a first electrode and a control electrode; the chip is arranged on the base island, and the back side of the chip faces the base island; the first electrode is closer to the second side than the control electrode; and the geometric center of the chip is closer to the second side than the geometric center of the base island; multiple spaced first leads connect the first electrode and the first lead. By positioning the chip's geometric center closer to the second side relative to the base island's geometric center, the semiconductor structure can effectively shorten the bonding wire length, thereby reducing the semiconductor structure's on-resistance. This solution effectively controls the bonding wire length by adjusting the chip mounting position to reduce the semiconductor structure's on-resistance. Compared to reducing on-resistance by changing the frame size, this solution eliminates the need for additional investment in increasing the frame size, thus facilitating cost control. It eliminates the need for a long wait for the manufacture of a custom frame, facilitating efficient production and adapting to a wide range of product types.

[0042] The following is combined with Figures 1 to 10, some embodiments of the present application are described in detail. In the absence of conflict, the features of the following embodiments can be combined with each other.

[0043] Please refer to Figure 1 , and when necessary, combine Figures 2 to 5 As shown, the semiconductor structure 100 includes a lead frame 10 and a chip 20 disposed on the lead frame 10 .

[0044] The lead frame 10 includes a base island 11 and a plurality of leads 12. The plurality of leads 12 include a first lead 121. The base island 11 has a first side 1101 and a second side 1102 that are opposite each other along a first direction x, and a third side 1103 and a fourth side 1104 that are opposite each other along a second direction y. The first lead 121 is located on the side of the third side 1103 and is close to the second side 1102. The first direction x and the second direction y form a non-zero angle.

[0045] In some embodiments, the first direction x and the second direction y are perpendicular to each other. Here, the cross section of the base island 11 perpendicular to the third direction z can be as follows: Figure 3 It is understood that the cross-sectional shape of the base island perpendicular to the third direction z can also be other non-rectangular regular or irregular shapes.

[0046] In some other embodiments, the first direction x and the second direction y may also have other included angles.

[0047] Here, the base island 11 has a first surface S11 for mounting the chip 20, and a second surface S12 facing away from the first surface S11. The first pins 121 are spaced apart from the base island 11. In some embodiments, the projection of the first pins 121 along the third direction z onto the plane of the first surface S11 may partially fall within the first surface S11 of the base island 11. Of course, in other embodiments, the projection of the first pins along the third direction z onto the plane of the first surface may be completely offset from the first surface.

[0048] Here, the third direction z may be perpendicular to the plane defined by the first direction x and the second direction y, or may form other non-zero angles with the plane defined by the first direction x and the second direction y.

[0049] The chip 20 has a front side S21 and a back side S22 facing away from each other. The front side S21 of the chip 20 is provided with a first electrode 22 and a control electrode 21. The chip 20 is disposed on the base island 11, with the back side S22 of the chip 20 facing the base island 11. The first electrode 22 is closer to the second side 1102 than the control electrode 21. Furthermore, the geometric center O1 of the chip 20 is closer to the second side 1102 than the geometric center O2 of the base island 11.

[0050] When the semiconductor structure 100 is operating, the operating current of the first electrode 22 is greater than the operating current of the control electrode 21 .

[0051] Here, the chip 20 is described as having a rectangular cross-section perpendicular to the third direction z. The chip 20 may include two opposing sides in the first direction x and two opposing sides in the second direction y. In other words, the four sides of the chip 20 may be substantially parallel to the first side 1101, the third side 1103, the second side 1102, and the fourth side 1104 of the base island 11, respectively.

[0052] It is understandable that the cross-sectional shape of the chip perpendicular to the third direction z may also be other non-rectangular regular or irregular shapes.

[0053] The semiconductor structure 100 further includes a plurality of spaced first leads 31 connecting the first electrode 22 and the first pin 121 .

[0054] The first lead can be connected to the first electrode 22 and the first pin 121 by welding.

[0055] In some embodiments, the semiconductor structure is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) device.

[0056] In some embodiments, the orthographic projection of the chip 20 on the plane of the front surface S21 of the chip 20 is located within the orthographic projection of the base island 11 on the plane of the front surface S21 of the chip 20, and the projected area of the chip 20 is smaller than the projected area of the base island 11. In this case, compared to an embodiment in which the on-resistance is reduced by changing the size of the lead frame, the semiconductor structure does not affect the size of the product due to the increase in the size of the lead frame.

[0057] In some embodiments, the distance between the edge of the chip 20 and the second side 1102 of the base island 11 is greater than or equal to 400 μm to reserve sufficient space for solder and prevent the solder from overflowing from the edge of the base island and affecting product performance.

[0058] It is understandable that, if process conditions permit, the chip 20 is placed as close to the second side 1102 as possible to shorten the length of the bonding wire, ie, the first wire 31 , and to minimize the on-resistance of the semiconductor structure.

[0059] For example, the distance between the edge of the chip 20 and the second side 1102 of the base island 11 may be equal to 400 μm.

[0060] As Figure 3 As shown, the cross-sectional shape of the chip 20 and the base island 11 perpendicular to the third direction z is roughly rectangular, and the four sides of the two correspond to each other as an example. The distance between the side of the chip 20 close to the second side 1102 and the second side 1102 can be 400μm or slightly larger than 400μm.

[0061] Combine Figure 3 As shown, in some embodiments, the first pin 121 includes a bonding portion 1211 close to the base island 11 and used for bonding the first lead 31, and a pin body 1212 located on the side of the bonding portion 1211 away from the base island 11, and the maximum width of the bonding portion 1211 in the first direction x is greater than the maximum width of the pin body 1212 in the first direction x.

[0062] The bonding portion 1211 has a first bonding side 1201 and a second bonding side 1202 that are opposite to each other in a first direction x. The spanning region of each first lead 31 in the first direction x falls within the spanning region of the first bonding side 1201 and the second bonding side 1202 in the bonding portion 1211 in the first direction x. Preferably, the spanning region of each first lead 31 in the first direction x is aligned with the intermediate region between the first bonding side 1201 and the second bonding side 1202 in the bonding portion 1211.

[0063] It can be understood that the second bonding side 1202 can be substantially aligned with the second side 1102 .

[0064] In some embodiments, each first lead 31 includes a first portion 311 at least partially welded to the first electrode 22 and a second portion 312 connecting the first portion 311 and the first pin 121. The first electrode 22 has a group of first welding points 201 and second welding points 202 opposite to the first portion 311 of each first lead, and the first portion 311 of each first lead 31 is welded to the corresponding group of first welding points 201 and second welding points 202.

[0065] Here, the first electrode 22 is connected to the first lead 31 via two welding points, a first welding point 201 and a second welding point 202 , which can well ensure the current intensity.

[0066] like Figure 3 As shown, in some preferred embodiments, the first welding points 201 and the second welding points 202 of the same group are spaced apart in a direction perpendicular to the first direction x, and the second welding points 202 are closer to the third side 1103. The end of the first portion 311 facing away from the second portion 312 is welded to the corresponding first welding point 201, and the end close to the second portion 312 is welded to the second welding point 202.

[0067] It is understandable that the first electrode 22 may only have windows at the first solder joint 201 and the second solder joint 202, with a passivation layer or other film layer provided in other areas. Of course, windows may also be provided on the entire surface of the first electrode 22.

[0068] like Figure 5 As shown, in other embodiments, each of the first leads 31 includes a first portion 311 at least partially welded to the first electrode 22 and a second portion 312 connecting the first portion 311 and the first pin 121; the first electrode 22 has a group of first welding points 201 and second welding points 202 opposite to the first portion 311 of each first lead, and the line connecting the first welding points 201 and the second welding points 202 of the same group has a non-right angle α with the first direction x, and the second welding point 202 is closer to the second side 1102 and the third side 1103; at least one of the first portions 311 has an end facing away from the second portion 312 welded to the first welding point 201, and an end close to the second portion 312 welded to the second welding point 202.

[0069] Compared to Figure 5 For the embodiment shown, Figure 3 In the illustrated embodiment, the line connecting the first solder joint 201 and the second solder joint 202 is perpendicular to the first direction x, which can shorten the size of the first portion 311 and reduce the on-resistance of the semiconductor structure.

[0070] The inventors have found through research that the metal layer on the chip surface is usually an alloy, and the lead frame is pure metal. The resistivity of the alloy is greater than that of the pure metal. The first portion 311 of the first lead 31 has a greater impact on the on-resistance than the second portion 312. Based on this, the following is adopted: Figure 3 In the illustrated embodiment, the size of the first portion 311 is reduced, which can better reduce the on-resistance of the semiconductor structure.

[0071] In some embodiments, the lead frame 10 includes a second pin 122 , which is located on the side where the third side 1103 is located, spaced apart from the first pin 121 in the first direction x, and closer to the first side 1101 .

[0072] Correspondingly, the semiconductor structure 100 may further include a second lead 32 for connecting the control electrode 21 and the second pin 122 .

[0073] like Figure 3 As shown, the second pin 122 is similar to the first pin 121 and may also include a bonding portion 1221 for soldering the second lead 32, and a pin body 1222 located on a side of the bonding portion 1221 facing away from the base island 11. The width of the bonding portion 1221 in the first direction x may also be greater than the width of the pin body 1222 in the first direction x.

[0074] The second lead 122 has two opposite sides along the first direction x, wherein the side facing away from the first lead 121 can be substantially parallel to the first side 1011 .

[0075] In some embodiments, a second electrode (not shown) is provided on the back surface S22 of the chip 20 , and the second electrode is connected to the base island 11 .

[0076] like Figure 2 As shown, the second electrode of the chip 20 can be connected to the base island 11 through a conductive solder 50 .

[0077] One of the first electrode 22 and the second electrode is a source electrode, and the other is a drain electrode. For example, the first electrode 22 is a source electrode, and the second electrode is a drain electrode.

[0078] In some embodiments, the lead frame 10 also includes a third pin 123, which is connected to the base island 11 from the third side 1103 of the base island 11, and the first pin 121, the third pin 123 and the second pin 122 are spaced apart in the first direction x by their orthographic projections on the plane where the front side S21 of the chip 20 is located.

[0079] Combine Figure 3 As shown, the first pin 121, the second pin 122 and the third pin 123 are located on the same side of the base island 11, ie, on the side where the third side 1103 is located. The semiconductor structure 100 can be a TO series pin-type metal oxide field effect transistor.

[0080] It is understood that in other embodiments, the first pin, the second pin, and the third pin may also be distributed outside of at least two different sides, thereby forming other types of semiconductor structures. In other words, the arrangement provided in this application is applicable to a variety of different types of semiconductor structures.

[0081] In addition, the semiconductor structure 100 may further include a plastic package 40. The plastic package 40 encapsulates the leads, the chip 20, and a portion of the lead frame 10. The second surface S12 of the island 11 may be exposed from the plastic package 40 to facilitate heat dissipation.

[0082] like Figure 6 As shown, the present application further provides a method for preparing a semiconductor structure, which includes the following steps S101 to S105:

[0083] In step S101, a lead frame is provided, the lead frame including a base island and a first lead; the base island has a first side and a second side opposite to each other along a first direction, and a third side and a fourth side opposite to each other along a second direction; the first lead is located on a side where the third side is located and is close to the second side; wherein a non-zero angle is formed between the first direction and the second direction;

[0084] In step S103, a chip is placed on a base island of a lead frame, wherein the chip has a front side and a back side facing away from each other, wherein a first electrode and a control electrode are provided on the front side of the chip; the back side of the chip faces the base island; the first electrode is closer to the second side than the control electrode; and the geometric center of the chip is closer to the second side than the geometric center of the base island.

[0085] In step S105 , a plurality of spaced first lead lines are provided, wherein the plurality of spaced first lead lines connect the first electrode and the first pin.

[0086] The following combination Figures 7 to 10 The preparation method of the semiconductor structure is described.

[0087] like Figure 7 As shown, in step S101, a lead frame 10 is provided, and the lead frame 10 includes a base island 11 and a first pin 121; the base island 11 has a first side 1101 and a second side 1102 opposite to each other along a first direction x, and a third side 1103 and a fourth side 1104 opposite to each other along a second direction y; the first pin 121 is located on the side where the third side 1103 is located, and is close to the second side 1102; wherein, there is a non-zero angle between the first direction x and the second direction y.

[0088] like Figure 8 As shown, in step S103, the chip 20 is arranged on the base island 11 of the lead frame 10, and the chip 20 has a front side S21 and a back side S22 that are opposite to each other, and the front side S21 of the chip 20 is provided with a first electrode 22 and a control electrode 21; the back side S22 of the chip 20 faces the base island 11; the first electrode is closer to the second side 1102 relative to the control electrode 21; wherein, the geometric center of the chip 20 is closer to the second side 1102 relative to the geometric center of the base island 11.

[0089] like Figure 9As shown, in step S105 , a plurality of spaced first lead lines 31 are provided, and the plurality of spaced first lead lines 31 connect the first electrode 22 and the first pin 121 .

[0090] like Figure 9 As shown, in some embodiments, the lead frame 10 includes a second pin 122 , which is located on the side of the third side 1103 , spaced apart from the first pin 121 in the first direction x, and closer to the first side 1101 .

[0091] Accordingly, the semiconductor structure 100 may further include a second lead 32 for connecting the control electrode 21 and the second pin 122. During, before, or after the step S105 is performed, the second lead 32 may be provided.

[0092] In some embodiments, the first lead 31 includes a first portion 311 at least partially welded to the first electrode 22 and a second portion 312 connecting the first portion 311 and the first lead 121; the first electrode 22 has a group of first welding points 201 and second welding points 202 opposite to at least one of the first portions 311; wherein the first welding points 201 and second welding points 202 are spaced apart along the second direction y, and the second welding points 202 are closer to the third side 1103, or a line connecting the first welding points 201 and the second welding points 202 forms a non-zero angle with the second direction y, and the second welding points 202 are closer to the second side 1102 and the third side 1103;

[0093] Step S105 of providing a plurality of spaced first lead lines 31 may include:

[0094] An end of at least one first portion 311 facing away from the second portion 312 is welded to the first welding point 201 , and an end of at least one first portion 311 close to the second portion 312 is welded to the second welding point 202 .

[0095] The embodiment of the method for preparing the semiconductor structure provided in the embodiment of the present application and the embodiment of the semiconductor structure belong to the same inventive concept, and the description of the relevant details and beneficial effects can be referred to each other, and will not be repeated here.

[0096] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it may be the only layer between the two layers or elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0097] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0098] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: A lead frame comprising a base island and a first lead; the base island having a first side and a second side opposite to each other along a first direction, and a third side and a fourth side opposite to each other along a second direction; the first lead being located on a side where the third side is located and close to the second side; wherein a non-zero angle is formed between the first direction and the second direction; A chip having a front side and a back side facing away from each other, wherein the front side of the chip is provided with a first electrode and a control electrode; the chip is arranged on the base island, and the back side of the chip faces the base island; the first electrode is closer to the second side than the control electrode; and the geometric center of the chip is closer to the second side than the geometric center of the base island; A plurality of spaced first lead lines connect the first electrode and the first pin.

2. The semiconductor structure according to claim 1, wherein The orthographic projection of the chip on the plane of the front surface of the chip is located within the orthographic projection of the base island on the plane of the front surface of the chip, and the projection area of the chip is smaller than the projection area of the base island.

3. The semiconductor structure according to claim 2, wherein: A distance between an edge of the chip and the second side of the base island is greater than or equal to 400 μm.

4. The semiconductor structure according to claim 1, wherein: The first lead includes a bonding portion close to the base island and used for bonding the first lead, and a lead body located on a side of the bonding portion away from the base island, wherein the maximum width of the bonding portion in the first direction is greater than the maximum width of the lead body in the first direction; In which, the bonding portion has a first bonding side and a second bonding side opposite to each other in the first direction, the position of each first lead farthest from the second side in the second direction is located on the side of the first bonding side close to the second side, and the position of each first lead closest to the second side in the second direction is located on the side of the second bonding side away from the second side.

5. The semiconductor structure according to claim 1, wherein Each of the first leads includes a first portion that is at least partially welded to the first electrode and a second portion that connects the first portion and the first pin; the first electrode has a group of first welding points and second welding points opposite to the first portion of each of the first leads, and the first portion of each of the first leads is welded to the corresponding group of first welding points and second welding points.

6. The semiconductor structure according to claim 5, wherein: The first welding points and the second welding points of the same group are arranged at intervals in a direction perpendicular to the first direction, and the second welding points are closer to the third side; the end of the first part of each first lead facing away from the second part is welded to the corresponding first welding point, and the end close to the second part is welded to the corresponding second welding point.

7. The semiconductor structure according to claim 1, wherein: The lead frame includes a second pin, the second pin is located on the side where the third side is located, is spaced apart from the first pin in the first direction, and is closer to the first side; The semiconductor structure further includes a second lead connecting the control electrode and the second pin; A second electrode is provided on the back side of the chip, and the second electrode is connected to the base island; One of the first electrode and the second electrode is a source electrode, and the other is a drain electrode.

8. The semiconductor structure according to claim 7, wherein: The lead frame further includes a third pin connected to the base island from a third side of the base island, and the orthographic projections of the first pin, the third pin and the second pin on the plane where the front surface of the chip is located are spaced apart in a first direction.

9. A method for preparing a semiconductor structure, characterized in that: The method comprises: A lead frame is provided, the lead frame comprising a base island and a first lead; the base island having a first side and a second side opposite to each other along a first direction, and a third side and a fourth side opposite to each other along a second direction; the first lead is located on a side where the third side is located and is close to the second side; wherein a non-zero angle is formed between the first direction and the second direction; A chip is placed on a base island of a lead frame, wherein the chip has a front side and a back side facing away from each other, the front side of the chip is provided with a first electrode and a control electrode; the back side of the chip faces the base island; the first electrode is closer to the second side than the control electrode; and the geometric center of the chip is closer to the second side than the geometric center of the base island; A plurality of spaced first lead lines are provided, and the plurality of spaced first lead lines connect the first electrode and the first pin.

10. The method for preparing a semiconductor structure according to claim 9, wherein: Each of the first leads includes a first portion at least partially welded to the first electrode and a second portion connecting the first portion and the first pin; the first electrode has a group of first and second welding points opposite to the first portion of each first lead; wherein the first and second welding points in the same group are spaced apart in a direction perpendicular to the first direction, and the second welding points are closer to the third side, or a line connecting the first and second welding points in the same group forms a non-perpendicular angle with the first direction, and the second welding points are closer to the second side and the third side; The first lead lines provided with a plurality of intervals include: The end of the first portion of each first lead facing away from the second portion is welded to the first welding point, and the end of the first portion of each first lead close to the second portion is welded to the second welding point.

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