Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The method comprises the following steps: providing a substrate; a first intermetallic dielectric layer and a first metal layer structure located in the first metal dielectric layer are formed on the substrate, the first metal layer structure comprises a first metal layer, and the first intermetallic dielectric layer is exposed out of the surface of the first metal layer structure; etching a part of the first intermetallic dielectric layer around the first metal layer, and forming a first groove in the first intermetallic dielectric layer; a second intermetallic dielectric layer is formed in the first groove and on the first intermetallic dielectric layer and the first metal layer structure, a second metal layer structure is arranged in the second intermetallic dielectric layer, and the second metal layer structure comprises a plurality of conductive plugs and second metal layers located on the conductive plugs; and the plurality of conductive plugs are located on the surface of the first metal layer, so that the layering risk can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Metal interconnects are the process of connecting different devices together through conductive materials to form complete circuits and systems according to design requirements. They also transmit external electrical signals to different parts of the chip, thereby creating a chip with specific functions. With increasing integration, metal interconnect technology has evolved from simple to complex, and from single-layer to multi-layer.

[0003] In metal interconnect structures, large metal layers and densely packed vias are prone to significant via bottom delamination, severely impacting device performance. Therefore, existing metal interconnect processes require further improvement. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0005] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate; a first intermetallic dielectric layer located on the substrate and a first metal layer structure located within the first metal dielectric layer, the first metal layer structure comprising a first metal layer, the first intermetallic dielectric layer exposing the surface of the first metal layer structure; a first groove located within the first intermetallic dielectric layer around the first metal layer; a second intermetallic dielectric layer located within the first groove, on the first intermetallic dielectric layer and the first metal layer structure, the second intermetallic dielectric layer having a second metal layer structure, the second metal layer structure comprising a plurality of conductive plugs and a second metal layer located on the plurality of conductive plugs, the plurality of conductive plugs being located on the surface of the first metal layer.

[0006] Optionally, the second metal layer has a first projection area on the surface of the first metal layer, and the contact surface between each of the conductive plugs and the first metal layer is located within the first projection area; the contact surfaces between several of the conductive plugs and the first metal layer have a first total area, the first projection area has a second area, and the ratio of the first total area to the second area is greater than or equal to 8%.

[0007] Optionally, the first metal layer has a first thickness, the first groove has a first depth, and a ratio of the first depth to the first thickness ranges from 30% to 50%.

[0008] Optionally, the first groove exposes a portion of the sidewall of the first metal layer; and the first groove is arranged around the first metal layer.

[0009] Optionally, the first metal layer structure also includes: several third metal layers located around the first metal layer, and the several third metal layers are separated from the first metal layer; the first groove is located between the first metal layer and the several third metal layers; with the minimum spacing between the first metal layer and the several third metal layers as the critical value, the width of the first groove is greater than or equal to the critical value.

[0010] Optionally, the second intermetallic dielectric layer includes a second etch stop layer and a second dielectric layer located on the second etch stop layer, the second etch stop layer and the second dielectric layer are made of different materials, the second metal layer is located in the second dielectric layer, and the plurality of conductive plugs are located in the second dielectric layer and the second etch stop layer; the depth of the first groove is greater than or equal to the thickness of the second etch stop layer.

[0011] Optionally, the first intermetallic dielectric layer includes a first etch stop layer and a first dielectric layer located on the first etch stop layer.

[0012] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate; forming a first intermetallic dielectric layer and a first metal layer structure located in the first metal dielectric layer on the substrate, the first metal layer structure including a first metal layer, the first intermetallic dielectric layer exposing the surface of the first metal layer structure; etching a portion of the first intermetallic dielectric layer around the first metal layer to form a first groove in the first intermetallic dielectric layer; forming a second intermetallic dielectric layer in the first groove, on the first intermetallic dielectric layer and the first metal layer structure, the second intermetallic dielectric layer having a second metal layer structure, the second metal layer structure including a plurality of conductive plugs and a second metal layer located on the plurality of conductive plugs, the plurality of conductive plugs being located on the surface of the first metal layer.

[0013] Optionally, the first metal layer has a first thickness, the first groove has a first depth, and a ratio of the first depth to the first thickness ranges from 30% to 50%.

[0014] Optionally, the first groove exposes a portion of the sidewall of the first metal layer; and the first groove is arranged around the first metal layer.

[0015] Optionally, the first metal layer structure also includes: several third metal layers located around the first metal layer, and the several third metal layers are separated from the first metal layer; the first groove is located between the first metal layer and the several third metal layers; with the minimum spacing between the first metal layer and the several third metal layers as the critical value, the width of the first groove is greater than or equal to the critical value.

[0016] Optionally, the second intermetallic dielectric layer includes a second etch stop layer and a second dielectric layer located on the second etch stop layer, and the materials of the second etch stop layer and the second dielectric layer are different; the second metal layer is located in the second dielectric layer, and the plurality of conductive plugs are located in the second dielectric layer and the second etch stop layer.

[0017] Optionally, a process for forming the second intermetallic dielectric layer and the second metal layer structure includes a dual damascene process or a single damascene process.

[0018] Optionally, the method for forming the second intermetallic dielectric layer and the second metal layer structure includes: forming a second etch-stop layer in the first groove, on the first intermetallic dielectric layer and the first metal layer structure; forming a second dielectric layer on the second etch-stop layer; the depth of the first groove is greater than or equal to the thickness of the second etch-stop layer; etching a portion of the second dielectric layer until a portion of the second etch-stop layer on the surface of the first metal layer is exposed, thereby forming a plurality of initial through holes in the second dielectric layer; etching a portion of the second dielectric layer around the plurality of initial through holes to form a second groove; after forming the second groove, continuing to etch the second etch-stop layer exposed by the plurality of initial through holes until the surface of the first metal layer is exposed, thereby forming through holes with the initial through holes at the bottom of the second groove, wherein the projections of the plurality of through holes on the substrate surface are within the projection range of the second groove on the substrate surface; forming the plurality of conductive plugs in the plurality of through holes; and forming the second metal layer in the second groove.

[0019] Optionally, the method for forming the several initial through holes also includes: forming a hard mask layer and a first patterned layer located on the hard mask layer on a portion of the surface of the second dielectric layer; etching the second dielectric layer using the first patterned layer as a mask; after forming the several initial through holes, removing the first patterned layer; the material of the first patterned layer includes photoresist.

[0020] Optionally, the method for forming the second groove further includes: forming a protective layer in the several initial through holes and on the hard mask layer; forming a second patterned layer on a portion of the protective layer; using the second patterned layer as a mask, etching the hard mask layer and the second dielectric layer to form the second groove; the material of the protective layer includes an organic material, and the organic material includes a bottom anti-reflective coating material; after forming the second groove, removing the protective layer and the second patterned layer.

[0021] Optionally, the method for forming the second metal layer structure also includes: forming the second metal material layer in the second groove, in the several through holes, and on the surface of the hard mask layer; flattening the second metal material layer and the hard mask layer until the surface of the second dielectric layer is exposed, forming the several conductive plugs with the second metal material layer in the several through holes, and forming the second metal layer with the second metal material layer in the second groove.

[0022] Optionally, the second metal layer has a first projection area on the surface of the first metal layer, and the contact surface between each of the conductive plugs and the first metal layer is located within the first projection area; the contact surfaces between several of the conductive plugs and the first metal layer have a first total area, the first projection area has a second area, and the ratio of the first total area to the second area is greater than or equal to 8%.

[0023] Compared with the existing technology, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0024] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a portion of the first intermetallic dielectric layer surrounding the first metal layer is etched to form a first groove in the first intermetallic dielectric layer. A second intermetallic dielectric layer is formed in the first groove and on the surfaces of the first intermetallic dielectric layer and the first metal layer. This causes the interface between the first intermetallic dielectric layer and the second intermetallic dielectric layer in the first groove to be recessed relative to the interface between the surrounding first intermetallic dielectric layer and the second intermetallic dielectric layer. This causes the originally continuous interface to be discontinuous in the first groove, cutting off the stress release path and thus reducing the risk of delamination. Furthermore, the interface between the first intermetallic dielectric layer and the second intermetallic dielectric layer in the first groove is located on a different plane from the interface between the first metal layer and the plurality of conductive plugs, further reducing the risk of delamination.

[0025] Furthermore, the first groove exposes part of the sidewall of the first metal layer, so that the first intermetallic dielectric layer wraps the first metal layer and the conductive plugs, protecting the interface between the conductive plugs and the first metal layer, thereby reducing the risk of delamination.

[0026] Furthermore, the depth of the first groove is greater than or equal to the thickness of the second etch stop layer. The second etch stop layer wraps the first metal layer and the plurality of conductive plugs, protecting the interface between the plurality of conductive plugs and the first metal layer, thereby reducing the risk of delamination.

[0027] Furthermore, the first groove is located between the first metal layer and the third metal layer, and the interface between the first intermetallic dielectric layer and the second intermetallic dielectric layer in the first groove is lower than the interface between the first intermetallic dielectric layer and the second intermetallic dielectric layer outside the third metal layer. Stress is released in the first groove, thereby reducing the problem of stress extending to the interface between the first metal layer and the plurality of conductive plugs, which is beneficial to reducing the risk of delamination between the first metal layer and the plurality of conductive plugs.

[0028] In the semiconductor structure provided by the technical solution of the present invention, a first groove is defined within the first intermetallic dielectric layer surrounding the first metal layer. The interface between the first intermetallic dielectric layer and the second intermetallic dielectric layer within the first groove is recessed relative to the interface between the surrounding first intermetallic dielectric layer and the second intermetallic dielectric layer, causing a discontinuity within the first groove in the originally continuous interface, thereby cutting off the stress release path and reducing the risk of delamination. Furthermore, the interface between the first intermetallic dielectric layer and the second intermetallic dielectric layer within the first groove is located on a different plane from the interface between the first metal layer and the plurality of conductive plugs, further reducing the risk of delamination.

[0029] Furthermore, the first groove exposes part of the sidewall of the first metal layer, so that the first intermetallic dielectric layer wraps the first metal layer and the conductive plugs, protecting the interface between the conductive plugs and the first metal layer, thereby reducing the risk of delamination.

[0030] Furthermore, the depth of the first groove is greater than or equal to the thickness of the second etch stop layer. The second etch stop layer wraps the first metal layer and the plurality of conductive plugs, protecting the interface between the plurality of conductive plugs and the first metal layer, thereby reducing the risk of delamination.

[0031] Furthermore, the first groove is located between the first metal layer and the third metal layer; the first groove also exposes a portion of the third metal layer, and the interface between the first intermetallic dielectric layer and the second intermetallic dielectric layer in the first groove is lower than the interface between the first intermetallic dielectric layer and the second intermetallic dielectric layer outside the third metal layer. Stress is released at the first groove, reducing the problem of stress extending to the interface between the first metal layer and the plurality of conductive plugs, which is beneficial to reducing the risk of delamination between the first metal layer and the plurality of conductive plugs. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 and Figure 2 It is a cross-sectional schematic diagram of a semiconductor structure;

[0033] Figures 3 to 10 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0035] As described in the background art, the existing metal interconnection process needs to be further improved. This is now explained and analyzed in conjunction with a semiconductor structure.

[0036] Figure 1 and Figure 2 It is a cross-sectional diagram of a semiconductor structure.

[0037] Please refer to Figure 1 The semiconductor structure includes: a substrate 100 having a device layer (not shown in the figure); an interlayer dielectric layer 101 located on the substrate 100, the interlayer dielectric layer 101 having a contact layer 102 therein, the contact layer 102 being electrically connected to the device layer; a first intermetallic dielectric layer located on the interlayer dielectric layer 101, the first intermetallic dielectric layer including a first etch-stop layer 103 and a first dielectric layer 104 located on the first etch-stop layer 103, the first intermetallic dielectric layer having a first metal layer 105 therein, the first metal layer 105 also being located on a surface of the contact layer 102; a second intermetallic dielectric layer located on the first intermetallic dielectric layer, the second intermetallic dielectric layer including a second etch-stop layer 106 and a second dielectric layer 107 located on the second etch-stop layer 106, the second intermetallic dielectric layer having a conductive plug 109 therein and a second metal layer 108 located on the conductive plug 109, the conductive plug 109 also being located on a surface of the first metal layer 105.

[0038] In the above semiconductor structure, the first etch stop layer 103 and the second etch stop layer 106 are both made of nitrogen-doped silicon carbide (NDC), and the first dielectric layer 104 and the second dielectric layer 107 are both made of low dielectric constant materials such as black diamond (BD).

[0039] However, if Figure 2 As shown in the dashed area, due to the mismatch in material properties (such as thermal expansion coefficient, stress intensity, and elastic modulus) between the NDC, metal layer, and BD, coupled with external factors such as thermal balance and stress loss during the process, the interface properties are unstable and the adhesion between the interfaces is poor. This makes delamination prone to occur at the interface between the first and second intermetallic dielectric layers. In particular, the densely packed structure of conductive plugs 109 causes greater damage to this interface, resulting in more severe delamination.

[0040] In another embodiment, to overcome the above-mentioned delamination phenomenon, the deposition process of forming the first intermetallic dielectric layer and the second intermetallic dielectric layer is generally improved, and the opening of the second etch stop layer 106 is precisely controlled to optimize the process. However, the improvement effect is very limited.

[0041] To address the above-mentioned problems, the present invention provides a semiconductor structure and a method for forming the same. A portion of the first intermetallic dielectric layer surrounding the first metal layer is etched to form a first groove within the first intermetallic dielectric layer. A second intermetallic dielectric layer is formed within the first groove and on the surfaces of the first intermetallic dielectric layer and the first metal layer. This causes the interface between the first intermetallic dielectric layer and the second intermetallic dielectric layer within the first groove to be recessed relative to the interface between the surrounding first intermetallic dielectric layer and the second intermetallic dielectric layer. This causes a discontinuity within the first groove in the originally continuous interface, thereby cutting off a stress release path and reducing the risk of delamination. Furthermore, the interface between the first intermetallic dielectric layer and the second intermetallic dielectric layer within the first groove is located on a different plane from the interface between the first metal layer and the plurality of conductive plugs, further reducing the risk of delamination.

[0042] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0043] Figures 3 to 10 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0044] Please refer to Figure 3, providing a substrate; forming a first intermetallic dielectric layer 201 and a first metal layer structure located within the first metal dielectric layer 201 on the substrate, the first metal layer structure including a first metal layer 202, and the first intermetallic dielectric layer 201 exposing the surface of the first metal layer structure.

[0045] In this embodiment, the substrate includes a base 200 and an interlayer dielectric layer 203 located on the base 200. The base 200 includes a device layer (not shown in the figure). The interlayer dielectric layer 203 includes a plurality of contact layers 204. The first metal layer 202 is located on the surface of the plurality of contact layers 204. In other embodiments, the substrate may include a device layer and one or more metal interconnect layers located on the device layer, the metal interconnect layer being electrically connected to the device layer, and the first metal layer structure being electrically connected to the metal interconnect layer.

[0046] In this embodiment, the device layer includes several device structures, and the device structures may include transistors, diodes, triodes, capacitors, inductors or conductive structures.

[0047] In this embodiment, the first intermetallic dielectric layer 201 includes a first etch stop layer 201 a and a first dielectric layer 201 b located on the first etch stop layer 201 a .

[0048] The material of the first etch stop layer 201a includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon nitride oxide, aluminum oxide, aluminum nitride, nitrogen-doped silicon carbide and silicon nitride and carbon nitride oxide; the material of the first dielectric layer 201b includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon nitride oxide, aluminum oxide, aluminum nitride, nitrogen-doped silicon carbide and silicon nitride and carbon nitride oxide, and the materials of the first etch stop layer 201a and the first dielectric layer 201b are different.

[0049] In this embodiment, the material of the first etch stop layer 201a is nitrogen-doped silicon carbide; the material of the first dielectric layer 201b is black diamond (BD), that is, silicon oxycarbide material.

[0050] In this embodiment, the first metal layer structure further includes: a plurality of third metal layers 205 located around the first metal layer 202 , and the plurality of third metal layers 205 are separated from the first metal layer 202 .

[0051] Please refer to Figure 4 , etching a portion of the first intermetallic dielectric layer 201 around the first metal layer 202 to form a first groove 206 in the first intermetallic dielectric layer 201 .

[0052] In this embodiment, the first metal layer 202 has a first thickness, the first groove 206 has a first depth, and the ratio of the first depth to the first thickness ranges from 30% to 50%.

[0053] Subsequently, a second intermetallic dielectric layer is filled in the first groove 206 .

[0054] In this embodiment, the second intermetallic dielectric layer includes a second etch stop layer and a second dielectric layer located on the second etch stop layer, and the second etch stop layer and the second dielectric layer are made of different materials.

[0055] In this embodiment, the depth of the first groove 206 is greater than or equal to the thickness of the second etch-stop layer. That is, the second etch-stop layer is completely filled into the first groove 206. This is because, since the second etch-stop layer and the first dielectric layer 201b are made of different materials, the second etch-stop layer is completely filled into the first groove 206, thereby reducing delamination problems caused by interface stress introduced by the different materials.

[0056] In this embodiment, the first groove 206 exposes a portion of the sidewall of the first metal layer 202. In other embodiments, the first groove may not expose the sidewall of the first metal layer. Exposing a portion of the sidewall of the first metal layer 202 by the first groove 206 is more conducive to reducing the risk of delamination than not exposing the sidewall of the first metal layer 202.

[0057] In this embodiment, the first groove 206 is disposed around the first metal layer 202 .

[0058] In this embodiment, the first groove 206 is located between the first metal layer 202 and the plurality of third metal layers 205 .

[0059] In this embodiment, the minimum spacing between the first metal layer 202 and the plurality of third metal layers 202 is used as a critical value, and the width of the first groove 206 is greater than or equal to the critical value. The width refers to the dimension in a direction parallel to the substrate surface. This width range is selected because a too small width will hinder subsequent filling of the second intermetallic dielectric layer.

[0060] The method for forming the first groove 206 includes: forming a third patterned layer 207 on the first intermetallic dielectric layer 201 and the first metal layer structure, wherein the third patterned layer 207 exposes the surface of the first metal layer 202 and a portion of the first intermetallic dielectric layer 201 surrounding the first metal layer 202; etching the first intermetallic dielectric layer 201 using the third patterned layer 207 and the first metal layer 202 as a mask; and after forming the first groove 206, removing the third patterned layer 207. Specifically, the first dielectric layer 201b is etched using the third patterned layer 207 and the first metal layer 202 as a mask.

[0061] In this embodiment, the material of the third patterned layer 207 includes photoresist.

[0062] Subsequently, a second intermetallic dielectric layer is formed in the first groove 206, on the first intermetallic dielectric layer 201 and the first metal layer structure. The second intermetallic dielectric layer has a second metal layer structure. The second metal layer structure includes a plurality of conductive plugs and a second metal layer located on the plurality of conductive plugs. The plurality of conductive plugs are located on the surface of the first metal layer.

[0063] In this embodiment, the second metal layer is located in the second dielectric layer, and the plurality of conductive plugs are located in the second dielectric layer and the second etch stop layer.

[0064] The formation process of the second intermetallic dielectric layer and the second metal layer structure includes a dual damascene process or a single damascene process. In this embodiment, the formation process of the second intermetallic dielectric layer and the second metal layer structure is a dual damascene process. Specifically, the formation method of the second intermetallic dielectric layer and the second metal layer structure can be referred to Figures 5 to 9 .

[0065] Please refer to Figure 5 , in the first groove 206 (such as Figure 4 As shown in FIG, a second etch stop layer 208a is formed on the first intermetallic dielectric layer 201 and the first metal layer structure; and a second dielectric layer 208b is formed on the second etch stop layer 208a.

[0066] The second intermetallic dielectric layer 208 includes the second etch stop layer 208 a and the second dielectric layer 208 b .

[0067] Here, the interface between the first intermetallic dielectric layer 201 and the second intermetallic dielectric layer 208 in the first groove 206 is recessed relative to the surrounding interface between the first intermetallic dielectric layer 201 and the second intermetallic dielectric layer 208, so that the originally continuous interface is discontinuous in the first groove 206, cutting off the stress release path and helping to reduce the risk of delamination.

[0068] The material of the second etch stop layer 208a includes a dielectric material, which includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon nitride oxide, aluminum oxide, aluminum nitride, nitrogen-doped silicon carbide and silicon nitride and carbon nitride oxide; the material of the second dielectric layer 208b includes a dielectric material, which includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon nitride oxide, aluminum oxide, aluminum nitride, nitrogen-doped silicon carbide and silicon nitride and carbon nitride oxide, and the materials of the second dielectric layer 208b and the second etch stop layer 208a are different.

[0069] In this embodiment, the material of the second etch stop layer 208a is nitrogen-doped silicon carbide; the material of the second dielectric layer 208b is black diamond.

[0070] Please refer to Figure 6 , a portion of the second dielectric layer 208b is etched until a portion of the second etch stop layer 208a on the surface of the first metal layer 202 is exposed, and a plurality of initial through holes 209 are formed in the second dielectric layer 208b.

[0071] In this embodiment, the method for forming the plurality of initial through holes 209 further includes: forming a hard mask layer 210 and a first patterned layer 211 located on the hard mask layer 210 on a portion of the surface of the second dielectric layer 208b; and etching the second dielectric layer 208b using the first patterned layer 211 as a mask.

[0072] The material of the hard mask layer 210 is different from the material of the second dielectric layer 208b; the material of the hard mask layer 210 includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, nitrogen-doped silicon carbide and silicon oxycarbon nitride.

[0073] In this embodiment, after the initial through holes 209 are formed, the first patterned layer 211 is removed.

[0074] In this embodiment, the material of the first patterned layer 211 includes photoresist.

[0075] Please refer to Figure 7 , etching the initial through holes 209 (such as Figure 6The second dielectric layer 208b is partially cut around the second dielectric layer 208b to form a second groove 212.

[0076] In this embodiment, the method for forming the second groove 212 further includes: forming a protective layer 213 in the plurality of initial through holes 209 and on the hard mask layer 210; forming a second patterned layer 214 on a portion of the protective layer 213; and etching the hard mask layer 210 and the second dielectric layer 208b using the second patterned layer 214 as a mask to form the second groove 212.

[0077] In this embodiment, the material of the protective layer 213 includes an organic material, which includes a bottom anti-reflective coating material. The protective layer 213 has fluidity and can be easily filled into the initial through holes 209 to protect the initial through holes 209. In other embodiments, the material of the protective layer 213 can also be an organic material such as spin-on carbon.

[0078] In this embodiment, after the second groove 212 is formed, the protection layer 213 and the second patterned layer 214 are removed.

[0079] Please refer to Figure 8 After forming the second groove 212, continue etching the plurality of initial through holes 209 (eg Figure 6 The second etch stop layer 208a exposed by the etching process is etched until the surface of the first metal layer 202 is exposed, and the initial through holes 209 at the bottom of the second groove 212 form through holes 215, and the projections of the through holes 215 on the surface of the substrate 200 are within the projection range of the second groove 212 on the surface of the substrate 200.

[0080] Specifically, after removing the protection layer 213 and the second patterned layer 214 , the second etch stop layer 208 a exposed by the initial through holes 209 is continuously etched.

[0081] Subsequently, the conductive plugs are formed in the through holes 215; and the second metal layer is formed in the second groove 212. In this embodiment, the method for forming the second metal layer structure is described in detail. Figures 9 and 10 .

[0082] Please refer to Figure 9 The second metal material layer 216 is formed in the second groove 212 , in the plurality of through holes 215 , and on the surface of the hard mask layer 210 .

[0083] Please refer to Figure 10, planarize the second metal material layer 216 and the hard mask layer 210 until the surface of the second dielectric layer 208b is exposed, form the plurality of conductive plugs 217 with the second metal material layer 216 in the plurality of through holes 215, and form the second metal layer 218 with the second metal material layer 216 in the second groove 212.

[0084] Here, the first groove 206 (such as Figure 4 The interface between the first intermetallic dielectric layer 201 and the second intermetallic dielectric layer 208 and the interface between the first metal layer 202 and the plurality of conductive plugs 217 are located on different planes, further reducing the risk of delamination.

[0085] Furthermore, the first groove 206 exposes part of the sidewall of the first metal layer 202, so that the first intermetallic dielectric layer 201 wraps the first metal layer 202 and the plurality of conductive plugs 217, protecting the interface between the plurality of conductive plugs 217 and the first metal layer 202, thereby reducing the risk of delamination.

[0086] As can be seen from the above, the depth of the first groove 206 is greater than or equal to the thickness of the second etch stop layer 208a, so that the second etch stop layer 208a wraps the first metal layer 202 and the plurality of conductive plugs 217, protecting the interface between the plurality of conductive plugs 217 and the first metal layer 202, which helps to reduce the risk of delamination.

[0087] Furthermore, the first groove 206 is located between the first metal layer 202 and the third metal layer 205. The interface between the first intermetallic dielectric layer 201 and the second intermetallic dielectric layer 208 in the first groove 206 is lower than the interface between the first intermetallic dielectric layer 201 and the second intermetallic dielectric layer 208 outside the third metal layer 205. Stress is released in the first groove 206, reducing the problem of stress extending to the interface between the first metal layer 202 and the plurality of conductive plugs 217, which is beneficial to reducing the risk of delamination between the first metal layer 202 and the plurality of conductive plugs 217.

[0088] In this embodiment, the second metal layer 218 has a first projected area on the surface of the first metal layer 202, and the contact surface between each of the conductive plugs 217 and the first metal layer 202 is located within the first projected area. The contact surfaces between the conductive plugs 217 and the first metal layer 202 have a first total area, the first projected area has a second area, and the ratio of the first total area to the second area is greater than or equal to 8%. The ratio of the first total area to the second area defines the distribution density of the conductive plugs 217 on the surface of the first metal layer 202. A larger ratio of the first total area to the second area increases the risk of stress delamination. As mentioned above, the purpose of this embodiment is to reduce the risk of delamination. In another embodiment, the ratio of the first total area to the second area is not limited.

[0089] Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Figure 10 The semiconductor structure includes: a substrate; a first intermetallic dielectric layer 201 located on the substrate and a first metal layer structure located within the first metal dielectric layer 201, wherein the first metal layer structure includes a first metal layer 202, wherein the first intermetallic dielectric layer 201 exposes the surface of the first metal layer structure; a first groove 206 (such as Figure 4 as shown); a second intermetallic dielectric layer 208 located in the first groove 206, on the first intermetallic dielectric layer 201 and the first metal layer structure, wherein the second intermetallic dielectric layer 208 has a second metal layer structure, and the second metal layer structure includes a plurality of conductive plugs 217 and a second metal layer 218 located on the plurality of conductive plugs 217, and the plurality of conductive plugs 217 are located on the surface of the first metal layer 202.

[0090] Here, the first groove 206 (such as Figure 4 The interface between the first intermetallic dielectric layer 201 and the second intermetallic dielectric layer 208 and the interface between the first metal layer 202 and the plurality of conductive plugs 217 are located on different planes, further reducing the risk of delamination.

[0091] In this embodiment, the second metal layer 218 has a first projected area on the surface of the first metal layer 202, and the contact surface between each of the conductive plugs 217 and the first metal layer 202 is located within the first projected area. The contact surfaces between the conductive plugs 217 and the first metal layer 202 have a first total area, the first projected area has a second area, and the ratio of the first total area to the second area is greater than or equal to 8%. The ratio of the first total area to the second area defines the distribution density of the conductive plugs 217 on the surface of the first metal layer 202. A larger ratio of the first total area to the second area increases the risk of stress delamination. As mentioned above, the purpose of this embodiment is to reduce the risk of delamination. In another embodiment, the ratio of the first total area to the second area is not limited.

[0092] In this embodiment, the first metal layer 202 has a first thickness, the first groove 206 has a first depth, and the ratio of the first depth to the first thickness ranges from 30% to 50%.

[0093] In this embodiment, the first groove 206 exposes a portion of the sidewall of the first metal layer 202. The first intermetallic dielectric layer 201 wraps the first metal layer 202 and the conductive plugs 217, protecting the interface between the conductive plugs 217 and the first metal layer 202, thereby reducing the risk of delamination.

[0094] In this embodiment, the first groove 206 is disposed around the first metal layer 202 .

[0095] In this embodiment, the first metal layer structure further includes a plurality of third metal layers 205 located around the first metal layer 202 , and the plurality of third metal layers 205 are separate from the first metal layer 202 ; the first groove 206 is located between the first metal layer 202 and the plurality of third metal layers 205 .

[0096] In this embodiment, the minimum spacing between the first metal layer 202 and the plurality of third metal layers 205 is used as a critical value, and the width of the first groove 206 is greater than or equal to the critical value. The width refers to the dimension in a direction parallel to the substrate surface. This width range is selected because a too small width will hinder subsequent filling of the second intermetallic dielectric layer.

[0097] Here, the interface between the first intermetallic dielectric layer 201 and the second intermetallic dielectric layer 208 in the first groove 206 is lower than the interface between the first intermetallic dielectric layer 201 and the second intermetallic dielectric layer 208 outside the third metal layer 205. Stress is released in the first groove 206, thereby reducing the problem of stress extending to the interface between the first metal layer 202 and the plurality of conductive plugs 217, which helps to reduce the risk of delamination between the first metal layer 202 and the plurality of conductive plugs 217.

[0098] In this embodiment, the second intermetallic dielectric layer 208 includes a second etch stop layer 208a and a second dielectric layer 208b located on the second etch stop layer 208a, and the second etch stop layer 208a and the second dielectric layer 208b are made of different materials; the second metal layer 218 is located in the second dielectric layer 208b, and the plurality of conductive plugs 217 are located in the second dielectric layer 208b and the second etch stop layer 208a.

[0099] Specifically, the depth of the first groove 206 is greater than or equal to the thickness of the second etch stop layer 208a. The second etch stop layer 208a wraps around the first metal layer 202 and the plurality of conductive plugs 217, protecting the interface between the plurality of conductive plugs 217 and the first metal layer 202, thereby reducing the risk of delamination.

[0100] In this embodiment, the substrate includes a base 200 and an interlayer dielectric layer 203 located on the base 200. The base 200 includes a device layer (not shown in the figure). The interlayer dielectric layer 203 includes a plurality of contact layers 204. The first metal layer 202 is located on the surface of the plurality of contact layers 204. In other embodiments, the substrate may include a device layer and one or more metal interconnect layers located on the device layer, the metal interconnect layer being electrically connected to the device layer, and the first metal layer structure being electrically connected to the metal interconnect layer.

[0101] In this embodiment, the first intermetallic dielectric layer 201 includes a first etch stop layer 201 a and a first dielectric layer 201 b located on the first etch stop layer 201 a .

[0102] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: substrate; a first intermetallic dielectric layer located on the substrate and a first metal layer structure located within the first metal dielectric layer, wherein the first metal layer structure includes a first metal layer, and the first intermetallic dielectric layer exposes a surface of the first metal layer structure; a first groove in the first intermetallic dielectric layer surrounding the first metal layer; A second intermetallic dielectric layer is located in the first groove, on the first intermetallic dielectric layer and the first metal layer structure, wherein the second intermetallic dielectric layer has a second metal layer structure, and the second metal layer structure includes a plurality of conductive plugs and a second metal layer located on the plurality of conductive plugs, wherein the plurality of conductive plugs are located on the surface of the first metal layer.

2. The semiconductor structure according to claim 1, wherein The second metal layer has a first projected area on the surface of the first metal layer, and the contact surface of each conductive plug with the first metal layer is located within the first projected area; the contact surfaces of several conductive plugs with the first metal layer have a first total area, the first projected area has a second area, and the ratio of the first total area to the second area is greater than or equal to 8%.

3. The semiconductor structure according to claim 1, wherein: The first metal layer has a first thickness, the first groove has a first depth, and a ratio of the first depth to the first thickness ranges from 30% to 50%.

4. The semiconductor structure according to claim 1, wherein: The first groove exposes a portion of the sidewall of the first metal layer; the first groove is arranged around the first metal layer.

5. The semiconductor structure according to claim 1, wherein The first metal layer structure also includes: several third metal layers located around the first metal layer, and the several third metal layers are separated from the first metal layer; the first groove is located between the first metal layer and the several third metal layers; with the minimum spacing between the first metal layer and the several third metal layers as the critical value, the width of the first groove is greater than or equal to the critical value.

6. The semiconductor structure according to claim 1, wherein The second intermetallic dielectric layer includes a second etch stop layer and a second dielectric layer located on the second etch stop layer, the second etch stop layer and the second dielectric layer are made of different materials, the second metal layer is located in the second dielectric layer, and the plurality of conductive plugs are located in the second dielectric layer and the second etch stop layer; The depth of the first groove is greater than or equal to the thickness of the second etch stop layer.

7. The semiconductor structure according to claim 1, wherein: The first intermetallic dielectric layer includes a first etch stop layer and a first dielectric layer located on the first etch stop layer.

8. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a first intermetallic dielectric layer and a first metal layer structure located within the first metal dielectric layer on the substrate, wherein the first metal layer structure includes a first metal layer, and the first intermetallic dielectric layer exposes a surface of the first metal layer structure; Etching a portion of the first intermetallic dielectric layer around the first metal layer to form a first groove in the first intermetallic dielectric layer; A second intermetallic dielectric layer is formed in the first groove, on the first intermetallic dielectric layer and the first metal layer structure. The second intermetallic dielectric layer has a second metal layer structure. The second metal layer structure includes a plurality of conductive plugs and a second metal layer located on the plurality of conductive plugs. The plurality of conductive plugs are located on the surface of the first metal layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: The first metal layer has a first thickness, the first groove has a first depth, and a ratio of the first depth to the first thickness ranges from 30% to 50%.

10. The method for forming a semiconductor structure according to claim 8, wherein: The first groove exposes a portion of the sidewall of the first metal layer; the first groove is arranged around the first metal layer.

11. The method for forming a semiconductor structure according to claim 8, wherein: The first metal layer structure also includes: several third metal layers located around the first metal layer, and the several third metal layers are separated from the first metal layer; the first groove is located between the first metal layer and the several third metal layers; with the minimum spacing between the first metal layer and the several third metal layers as the critical value, the width of the first groove is greater than or equal to the critical value.

12. The method for forming a semiconductor structure according to claim 8, wherein: The second intermetallic dielectric layer includes a second etch stop layer and a second dielectric layer located on the second etch stop layer, and the second etch stop layer and the second dielectric layer are made of different materials; the second metal layer is located in the second dielectric layer, and the plurality of conductive plugs are located in the second dielectric layer and the second etch stop layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: The formation process of the second intermetallic dielectric layer and the second metal layer structure includes a dual damascene process or a single damascene process.

14. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming the second intermetallic dielectric layer and the second metal layer structure includes: forming a second etch stop layer in the first groove, on the first intermetallic dielectric layer and the first metal layer structure; the depth of the first groove is greater than or equal to the thickness of the second etch stop layer; forming a second dielectric layer on the second etch stop layer; etching a portion of the second dielectric layer until a portion of the second etch stop layer on the surface of the first metal layer is exposed, thereby forming a plurality of initial through holes in the second dielectric layer; etching a portion of the second dielectric layer around the plurality of initial through holes to form a second groove; after forming the second groove, continuing to etch the second etch stop layer exposed by the plurality of initial through holes until the surface of the first metal layer is exposed, thereby forming through holes with the initial through holes at the bottom of the second groove, wherein the projections of the plurality of through holes on the substrate surface are within the projection range of the second groove on the substrate surface; forming the plurality of conductive plugs in the plurality of through holes; and forming the second metal layer in the second groove.

15. The method for forming a semiconductor structure according to claim 14, wherein: The method for forming the plurality of initial through holes further includes: forming a hard mask layer and a first patterned layer located on the hard mask layer on a portion of the surface of the second dielectric layer; etching the second dielectric layer using the first patterned layer as a mask; and removing the first patterned layer after forming the plurality of initial through holes; the material of the first patterned layer includes photoresist.

16. The method for forming a semiconductor structure according to claim 15, wherein: The method for forming the second groove further includes: forming a protective layer within the plurality of initial through holes and on the hard mask layer; forming a second patterned layer on a portion of the protective layer; etching the hard mask layer and the second dielectric layer using the second patterned layer as a mask to form the second groove; the material of the protective layer includes an organic material, and the organic material includes a bottom anti-reflective coating material; and removing the protective layer and the second patterned layer after forming the second groove.

17. The method for forming a semiconductor structure according to claim 16, wherein: The method for forming the second metal layer structure also includes: forming the second metal material layer in the second groove, in the plurality of through holes, and on the surface of the hard mask layer; planarizing the second metal material layer and the hard mask layer until the surface of the second dielectric layer is exposed, forming the plurality of conductive plugs with the second metal material layer in the plurality of through holes, and forming the second metal layer with the second metal material layer in the second groove.

18. The method for forming a semiconductor structure according to claim 8, wherein: The second metal layer has a first projected area on the surface of the first metal layer, and the contact surface of each conductive plug with the first metal layer is located within the first projected area; the contact surfaces of several conductive plugs with the first metal layer have a first total area, the first projected area has a second area, and the ratio of the first total area to the second area is greater than or equal to 8%.

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