Semiconductor laser chip structure and method of manufacturing the same

Abstract

This application relates to the field of semiconductor laser manufacturing technology. Specifically, it relates to a semiconductor laser chip structure and its manufacturing method. The semiconductor laser chip structure manufactured by the method provided in this application includes: a laser chip substrate and a heavily doped stage; the length and width of the heavily doped stage are both smaller than the length and width of the laser chip substrate; an insulating layer covering a portion of the width of the heavily doped stage near its edge, the side portion of the heavily doped stage, and the laser chip substrate surface on the side portion of the heavily doped stage; and an ion implantation region located in the portion of the heavily doped stage and laser chip substrate below the insulating layer, which, together with the insulating layer, defines the width of the current injection window of the semiconductor laser chip. This application can solve the defects caused by using isolation trenches at the edge of the heavily doped stage to define the current injection window.

Description

Technical Field

[0001] This application relates to the field of semiconductor laser chip technology. Specifically, it relates to a semiconductor laser chip structure and its manufacturing method. Background Technology

[0002] Semiconductor lasers are widely used in various fields, including industrial production, lidar, military defense, optical communication, optical information storage, and medical aesthetics, due to their advantages such as compact structure, long lifespan, high reliability, high electro-optical conversion efficiency, fast modulation rate, wide wavelength range, and ease of integration. With technological advancements, higher demands are being placed on the power, efficiency, polarization degree, horizontal far-field divergence angle, and reliability of semiconductor lasers in multiple application areas.

[0003] Generally, semiconductor laser chip designs use wet etching along the cavity length to remove heavily doped ohmic contact layers and part of the highly doped upper confinement layer to form strip-shaped isolation trenches, thus defining the width of the optical surface. However, this method leads to several problems in subsequent processes: if a P-plane-down packaging method is used to form a COS device, it will affect the polarization degree (DOP); the insulation layer thickness required to define the current injection window is relatively thick, which will create significant stress and cause the semiconductor laser chip wafer warpage to exceed the threshold; it hinders lateral heat dissipation of the chip and creates reliability risks near the isolation trench area; and the isolation trench itself will affect the far-field horizontal divergence angle.

[0004] Therefore, a solution is needed to address the aforementioned drawbacks caused by defining the current injection window using isolation trenches at the edge of heavily doped tiers. Summary of the Invention

[0005] Therefore, this application provides a semiconductor laser chip structure and a method for manufacturing the same, to solve the above-mentioned defects caused by using isolation trenches at the edge of heavily doped slabs to define the current injection window.

[0006] In one aspect of this application: This application provides a semiconductor laser chip structure, comprising: a laser chip substrate, the laser chip substrate comprising, in sequence: a substrate layer, a buffer layer, a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, and a first upper confinement layer; a heavily doped stage disposed on the surface of the upper first upper confinement layer of the laser chip substrate facing away from the substrate layer, including a second upper confinement layer and an ohmic contact layer; the length and width of the heavily doped stage are both smaller than the length and width of the laser chip substrate; an insulating layer covering a portion of the width of the heavily doped stage near its edge, the side portion of the heavily doped stage, and the laser chip substrate surface of the side portion of the heavily doped stage; an ion implantation region located in the heavily doped stage and the laser chip substrate with a portion of its thickness below the insulating layer; the ion implantation region and the insulating layer together define the width of the current injection window of the semiconductor laser chip.

[0007] The semiconductor laser chip structure provided in this application modifies the laser chip structure through a partially thick doped stage located beneath the insulating layer and an ion-implanted region in the laser chip substrate. The remaining un-ion-implanted modified region is further defined by the insulating layer, and the remaining exposed region can serve as a current injection window. The unexposed portion is blocked by the insulating layer, making direct current injection difficult. Furthermore, the ion-implanted modification of the exposed region increases its resistance. Current injected through the P-side electrode on the top surface cannot pass through this ion-implanted region because the resistance of the corresponding region is much lower than that of the ion-implanted region. This achieves better lateral current expansion without causing additional photon loss, thus defining the current injection window and its width. This approach avoids defining the current injection window and width using isolation trenches of the heavily doped stage, preventing the associated stress problems. Therefore, it solves the related polarization, stress, reliability risks, and heat dissipation defects associated with defining the current injection window and width using isolation trenches of the heavily doped stage, and reduces the impact on the far-field divergence angle.

[0008] In some embodiments of this application, the depth of the ion implantation region does not exceed the upper surface of the quantum well active layer.

[0009] In the semiconductor laser chip structure provided in this application, the depth of the ion implantation region does not exceed the upper surface of the quantum well active layer, thus the quantum well active layer is not modified. Since the quantum well active region is the core region for electro-optical conversion of the laser, the solution in this application will not affect the electro-optical conversion capability of the laser.

[0010] In some embodiments of this application, the ion implantation region is located in the ohmic contact layer, the second upper confinement layer, the first upper confinement layer, and a partial thickness of the upper waveguide layer beneath the insulating layer.

[0011] In some embodiments of this application, the width of the insulating layer covering the edge of the heavily doped stage is greater than the width of the portion of the ion implantation region located on the heavily doped stage; the depth of the portion of the ion implantation region located on the heavily doped stage is shallower than the depth of the portion of the ion implantation region located on the laser chip substrate.

[0012] In the semiconductor laser chip structure provided in this application, the ion implantation region located in the heavily doped stage has a width smaller than the width of the insulating layer covering the heavily doped stage, and a depth shallower than the portion of the laser chip substrate located on the side of the heavily doped stage. This creates a transition region with less lattice damage, minimizing the adverse effects of this region on photon absorption and scattering. It avoids unnecessary photon scattering and absorption losses at the edge of the stripe, preventing reduced electro-optical conversion efficiency and potential reliability risks. Simultaneously, the deeper implantation depth in the portion of the laser chip substrate located on the side of the heavily doped stage better isolates the lateral spread of current, improving the device's electro-optical conversion efficiency.

[0013] In some embodiments of this application, the implanted ions in the ion implantation region are Si ions or H ions.

[0014] In some embodiments of this application, the insulating layer is made of SiO2 or SiN. x The thickness of the insulating layer is 50nm~100nm; the width of one side of the insulating layer covering the heavily doped stage is 10μm~25μm; the semiconductor laser chip structure also includes a front electrode layer covering the surface of the current injection window and the surface of the insulating layer and a back electrode layer covering the surface of the substrate layer facing away from the buffer layer; the material of the front electrode layer includes titanium, platinum, gold or their alloys; the material of the back electrode layer includes gold, germanium, nickel or their alloys.

[0015] In the semiconductor laser chip structure provided in this application, since the current injection window is not defined by the isolation trench at the edge of the heavily doped stage, the insulating layer does not need to be of a high thickness. Since increasing the thickness of the insulating layer often introduces more stress, it may cause semiconductor wafer warping and breakage during manufacturing. The insulating layer of this application is thinner, which can reduce the stress problem caused by the thickness of the insulating layer and improve the polarization degree of the semiconductor laser chip.

[0016] In another aspect of this application, a method for manufacturing a semiconductor laser chip structure is also provided, comprising the following steps: providing a laser chip substrate epitaxial structure, comprising, in sequence, a substrate layer, a buffer layer, a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, an upper confinement layer, and an ohmic contact layer; etching the laser chip epitaxial layer to form a laser chip substrate and heavily doped stations on its surface; wherein the portion of the upper confinement layer located on the laser chip substrate is a first upper confinement layer, and the portion located on the heavily doped stations is a second upper confinement layer; the laser chip substrate comprises, in sequence, a substrate layer, a buffer layer, a lower waveguide layer, a lower waveguide layer, a lower waveguide layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, an upper confinement layer, and an ohmic contact layer; the laser chip substrate comprises, in sequence, a substrate layer, a buffer layer, a lower waveguide ... and an ohmic contact layer; The system comprises a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, and a first upper confinement layer; a heavily doped stage including a second upper confinement layer and an ohmic contact layer; the length and width of the heavily doped stage are both smaller than the length and width of the laser chip substrate; an ion implantation region is formed in the width and thickness of the heavily doped stage near its edge and in the thickness of the laser chip substrate; an insulating layer is formed on the surface of the heavily doped stage near its edge, on the side surface of the heavily doped stage, and on the side surface of the laser chip substrate; together with the ion implantation region, the system defines the current injection window of the semiconductor laser chip.

[0017] The method for manufacturing a semiconductor laser chip structure provided in this application can produce the semiconductor laser chip structure provided in this application. The laser chip structure is modified by a partially thick heavily doped stage located beneath the insulating layer and an ion-implanted region in the laser chip substrate. The remaining un-ion-implanted modified region is further defined by the insulating layer, and the remaining exposed region can serve as a current injection window. The unexposed portion is blocked by the insulating layer, making direct current injection difficult. Furthermore, the exposed region's side is modified by ion implantation, increasing the resistance of this region. Current injected through the P-side electrode on the top surface cannot pass through this ion-implanted region, thus achieving better lateral current expansion without causing additional photon loss. This allows for the definition of the current injection window and its width. This method avoids using the isolation trench of the heavily doped stage for definition, preventing the various stress problems associated with it. Therefore, it solves the related polarization degree, stress, reliability risks, heat dissipation defects, and reduces the impact on the far-field divergence angle caused by using the isolation trench of the heavily doped stage to define the current injection window and width.

[0018] In some embodiments of this application, the step of forming an ion implantation region includes: forming an ion implantation protective layer that covers a portion of the surface near the edge of the heavily doped stage, a side surface of the heavily doped stage, and a laser chip substrate surface on the side of the heavily doped stage; forming a photoresist layer that covers the ohmic contact layer exposed by the ion implantation protective layer and covers a portion of the width of the ion implantation protective layer, spaced a distance from the edge of the heavily doped stage; performing ion implantation to form an initial ion implantation region in the heavily doped stage and laser chip substrate with a portion of the thickness below the ion implantation protective layer; removing the photoresist layer and the ion implantation protective layer; and annealing to repair ion implantation damage and activate the doped atoms in the initial ion implantation region to the correct lattice positions.

[0019] The method for manufacturing a semiconductor laser chip structure provided in this application involves first forming a thin ion implantation protective layer, and then covering a portion of it with photoresist. The photoresist completely blocks ion implantation in the covered area. Simultaneously, the presence of the ion implantation protective layer in the covered portion ensures a certain level of ion implantation while preventing excessive ion implantation and severe damage to the epitaxial structure of the laser substrate, thus avoiding performance degradation and potential reliability risks. Annealing repairs the lattice damage to the epitaxial structure of the laser chip substrate caused by ion implantation, while simultaneously activating doped atoms to the correct lattice positions, thereby ensuring the performance of the laser chip structure.

[0020] In some embodiments of this application, during the ion implantation step: the material of the ion implantation protective layer is SiO2 or SiN. x The thickness is 20nm~50nm; the overlap width between the photoresist layer and the ion implantation protective layer is 5μm~15μm, and the width distance between the photoresist layer and the edge of the insulating layer located on the heavily doped stage is 5μm~10μm.

[0021] In some embodiments of this application, the ion implantation step involves: implanting Si ions or H ions, performing the implantation in multiple steps, and gradually increasing the ion energy and / or gradually increasing the implantation dose, while keeping the tilt angle constant. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1This is a top view schematic diagram of a semiconductor laser chip structure;

[0024] Figure 2 This is a top view schematic diagram of a semiconductor laser chip structure according to an embodiment of this application;

[0025] Figure 3 for Figure 2 Schematic diagram of the cross section line in the middle MM section;

[0026] Figure 4 This is a schematic diagram of the formation of an ion implantation protective layer N during the formation of an ion implantation region in a method for manufacturing a semiconductor laser chip structure according to an embodiment of this application.

[0027] Figure 5 This is a schematic diagram of the formation of a photoresist layer P during the formation of an ion implantation region in a method for manufacturing a semiconductor laser chip structure according to an embodiment of this application.

[0028] Figure 6 This is a schematic diagram illustrating ion implantation during the formation of an ion implantation region in a method for manufacturing a semiconductor laser chip structure according to an embodiment of this application.

[0029] Figure 7 This is a schematic diagram showing the removal of the photoresist layer P and the ion implantation protective layer N during the formation of the ion implantation region in a method for manufacturing a semiconductor laser chip structure according to an embodiment of this application.

[0030] Figure 8 This is a schematic diagram illustrating the annealing repair of ion implantation damage during the formation of the ion implantation region in a method for manufacturing a semiconductor laser chip structure according to an embodiment of this application.

[0031] Figure 9 This is a schematic diagram of the formation of an insulating layer in a method for manufacturing a semiconductor laser chip structure according to an embodiment of this application.

[0032] Explanation of reference numerals in the attached figures:

[0033] 110 - Substrate layer; 120 - Buffer layer; 130 - Lower confinement layer; 140 - Lower waveguide layer; 150 - Quantum well active layer; 160 - Upper waveguide layer; 171 - First upper confinement layer; 172 - Second upper confinement layer; 180 - Ohmic contact layer; 200 - Insulating layer; A - Laser chip substrate; B - Heavily doped stage; C - Current injection window; D - Striped isolation trench; E - Overlapping portion of photoresist layer and ion implantation protection layer; F - Width distance from the edge of the photoresist layer to the edge of the insulating layer on the heavily doped stage; N - Ion implantation protection layer; P - Photoresist layer; W - Strip width. Detailed Implementation

[0034] refer to Figure 1 , Figure 1 This is a top view schematic diagram of a semiconductor laser chip structure. It includes a laser chip substrate A, which comprises, in sequence, a substrate layer, a buffer layer, a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, and an upper confinement layer. Figure 1 (This is a top view; the layers are not shown in detail, only the exposed surface is the upper confinement layer). A heavily doped stage B is disposed on the surface of the upper confinement layer of the laser chip substrate A facing away from the substrate layer, and includes at least an ohmic contact layer. The length and width of the heavily doped stage B are both smaller than the length and width of the laser chip substrate A. In this semiconductor laser chip design, a strip-shaped isolation groove D is formed in the cavity length direction by wet etching to remove the ohmic contact layer of the heavily doped stage B and part of the highly doped upper confinement layer, defining the width W of the light-emitting surface and constituting the current injection window C. The direction of the empty arrow in the figure indicates the direction of the light-emitting surface, that is, the direction from the rear cavity surface to the front cavity surface.

[0035] As mentioned above, this method has the following drawbacks: (1) When the P-down packaging method is used to form COS devices, the shear stress introduced by the packaging of the strip isolation groove will affect the polarization degree (DOP), which is not conducive to the high DOP requirement of subsequent polarization beam combining, especially in products with small strip width; (2) The method of defining the strip width W of the strip isolation groove D often requires the deposition of a thicker SiO2 / SiN. x An insulating layer (usually 100nm or more to 200nm) is needed to achieve good current isolation and form a non-current injection window (i.e., other areas outside the current injection window pattern). A thicker insulating layer often creates greater stress on the wafer surface, which can easily lead to warping exceeding the threshold or even chip breakage during manufacturing, thus affecting yield and increasing manufacturing costs; (3) Wet etching forms strip-shaped isolation trenches hundreds of nm deep, which will create a certain thermal path obstacle when the chip dissipates heat laterally, and the wet etching process itself makes the area near the strip-shaped isolation trench more prone to reliability risks; (4) The strip-shaped isolation trench itself will have a certain impact on the far-field horizontal divergence angle.

[0036] Therefore, this application provides a semiconductor laser chip structure and its manufacturing method to solve the above-mentioned defects caused by using the isolation trench at the edge of the heavily doped stage to define the current injection window.

[0037] This application provides a semiconductor laser chip structure, comprising: a laser chip substrate, the laser chip substrate including, in sequence: a substrate layer, a buffer layer, a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, and a first upper confinement layer; a heavily doped stage disposed on the surface of the first upper confinement layer facing away from the substrate layer, including a second upper confinement layer and an ohmic contact layer; the length and width of the heavily doped stage are both smaller than the length and width of the laser chip substrate; an insulating layer covering a portion of the width of the heavily doped stage near its edge, the side portion of the heavily doped stage, and the laser chip substrate surface of the side portion of the heavily doped stage; and an ion implantation region located in the heavily doped stage and the laser chip substrate within a portion of the thickness below the insulating layer; the ion implantation region and the insulating layer together define the current injection window of the semiconductor laser chip.

[0038] This application also provides a method for manufacturing a semiconductor laser chip structure, comprising the following steps: providing a laser chip substrate epitaxial structure, including: a substrate layer, a buffer layer, a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, an upper confinement layer, and an ohmic contact layer stacked sequentially; etching the laser chip epitaxial layer to form a laser chip substrate and heavily doped stations on its surface; wherein the portion of the upper confinement layer located on the laser chip substrate is a first upper confinement layer, and the portion located on the heavily doped stations is a second upper confinement layer; the laser chip substrate includes: a substrate layer, a buffer layer, a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, an upper confinement layer, and an ohmic contact layer stacked sequentially. The laser consists of a waveguide layer, a quantum well active layer, an upper waveguide layer, and a first upper confinement layer. A heavily doped stage includes a second upper confinement layer and an ohmic contact layer. The length and width of the heavily doped stage are both smaller than the length and width of the laser chip substrate. An ion implantation region is formed in the width and thickness of the heavily doped stage near its edge and in a portion of the thickness of the laser chip substrate. An insulating layer is formed on the surface of the heavily doped stage near its edge, on the side surface of the heavily doped stage, and on the side surface of the laser chip substrate. Together with the ion implantation region, an insulating layer defines the current injection window of the semiconductor laser chip.

[0039] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the description of this application, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0040] Example 1

[0041] refer to Figure 2 and Figure 3This embodiment provides a semiconductor laser chip structure, including:

[0042] Laser chip substrate A includes the following components stacked sequentially: substrate layer 110, buffer layer 120, lower confinement layer 130, lower waveguide layer 140, quantum well active layer 150, upper waveguide layer 160, and first upper confinement layer 171.

[0043] The heavily doped stage B is disposed on the surface of the first upper confinement layer 171 on the side opposite to the substrate layer on the laser chip substrate A, and includes a second upper confinement layer 172 and an ohmic contact layer 180; the length and width of the heavily doped stage B are both smaller than the length and width of the laser chip substrate A.

[0044] An insulating layer 200 covers a portion of the width of the heavily doped stage B near its edge, the side portion of the heavily doped stage B, and the surface of the laser chip substrate A on the side portion of the heavily doped stage B.

[0045] Ion implantation region ( Figure 3 The dense dot matrix region is located in the heavily doped stage B, which is a portion of the thickness below the insulating layer 200, and in the laser chip substrate A; the ion implantation region and the insulating layer 200 together define the stripe width W of the current injection window C of the semiconductor laser chip.

[0046] It should be noted that, Figure 2 The central part is displayed transparently to show the heavily doped stage B covered by the insulating layer 200; only the border is shown, not the entire area. Figure 2 Insulation layer 200 and Figure 3 The insulation layer 200 is different. Furthermore, it should be noted that... Figure 3 The dots only represent implanted ions and do not indicate that these ions have formed visible granular objects. In fact, because the size of the implanted ions is extremely small, and the corresponding lattice size is also extremely small, they are difficult to discern with the naked eye on a macroscopic scale.

[0047] In this embodiment, the semiconductor laser chip structure is modified by a heavily doped stage B located below the insulating layer 200 and an ion-implanted region in the laser chip substrate A. The remaining un-ion-implanted modified region is further defined by the insulating layer 200, and the remaining exposed region can serve as the current injection window C. The unexposed portion is blocked by the insulating layer 200, making direct current injection difficult. Furthermore, the ion-implanted modification of the exposed region increases its resistance. Current injected through the P-side electrode on the top surface cannot pass through the ion-implanted region because the resistance of the region corresponding to the current injection window C is much lower than that of the ion-implanted region. This achieves good lateral current expansion without causing additional photon loss, thus defining the current injection window and its width W. This approach avoids using the isolation trench of the heavily doped stage B for definition, preventing the stress problems associated with it. Therefore, it solves the related polarization, stress, reliability risks, heat dissipation defects, and reduces the impact on the far-field divergence angle that arise from using the isolation trench of the heavily doped stage B to define the current injection window and width.

[0048] Furthermore, in some embodiments, the depth of the ion implantation region does not exceed the upper surface of the quantum well active layer.

[0049] In the semiconductor laser chip structure of this embodiment, the depth of the ion implantation region does not exceed the upper surface of the quantum well active layer 150, therefore the quantum well active layer 150 is not modified. Since the quantum well active layer is the core region for electro-optical conversion of the laser, the solution in this application will not affect the electro-optical conversion capability of the laser.

[0050] Specifically, in some embodiments, the ion implantation region is located in the ohmic contact layer 180, the second upper confinement layer 172, the first upper confinement layer 171, and the upper waveguide layer 160 of a certain thickness below the insulating layer 200.

[0051] Furthermore, in some embodiments, the width of the insulating layer 200 covering the edge of the heavily doped stage B is greater than the width of the portion of the ion implantation region located in the heavily doped stage B; the depth of the portion of the ion implantation region located in the heavily doped stage B is shallower than the depth of the portion of the ion implantation region located in the laser chip substrate A.

[0052] In the semiconductor laser chip structure of this embodiment, the ion implantation region located in the heavily doped stage B has a width smaller than the width of the insulating layer 200 covering the heavily doped stage B, and a depth shallower than the portion of the laser chip substrate A located on the side of the heavily doped stage B, thereby forming a transition region. This portion exhibits less lattice damage, minimizing the adverse effects of photon absorption and scattering on this region, avoiding unnecessary photon scattering and absorption losses at the edge of the stripe width W, thus reducing electro-optical conversion efficiency and potential reliability risks. Simultaneously, the deeper implantation depth in the portion of the laser chip substrate A located on the side of the heavily doped stage B better isolates the lateral spread of current, improving the device's electro-optical conversion efficiency.

[0053] In some embodiments of this application, the implanted ions in the ion implantation region are Si ions or H ions.

[0054] Specifically, in some embodiments, the insulating layer is made of SiO2 or SiN. x The thickness of the insulating layer is 50nm~100nm;

[0055] The width of one side of the insulating layer covering the heavily doped stage is 10μm~25μm;

[0056] The semiconductor laser chip structure also includes a front electrode layer (P-side electrode, not shown in the figure) covering the surface of the current injection window C and the surface of the insulating layer 200, and a back electrode layer (N-side electrode, not shown in the figure) covering the surface of the substrate layer facing away from the buffer layer.

[0057] The materials for the front electrode layer include titanium (Ti), platinum (Pt), gold (Au), or their alloys; the materials for the back electrode layer include gold (Au), germanium (Ge), nickel (Ni), or their alloys.

[0058] Example 2

[0059] This embodiment provides a method for manufacturing a semiconductor laser chip structure, including the following steps:

[0060] A laser chip substrate epitaxial structure is provided, comprising the following layers stacked sequentially: a substrate layer, a buffer layer, a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, an upper confinement layer, and an ohmic contact layer;

[0061] The epitaxial layer of the laser chip is etched to form a laser chip substrate and heavily doped stations on its surface; wherein the portion of the upper confinement layer located on the laser chip substrate is the first upper confinement layer, and the portion located on the heavily doped stations is the second upper confinement layer;

[0062] The laser chip substrate comprises, in sequence, a substrate layer, a buffer layer, a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, and a first upper confinement layer; the heavily doped stage comprises a second upper confinement layer and an ohmic contact layer; the length and width of the heavily doped stage are both smaller than the length and width of the laser chip substrate;

[0063] An ion implantation region is formed in the width and thickness of the heavily doped stage near the edge and in the thickness of the laser chip substrate.

[0064] An insulating layer is formed on the surface of the heavily doped stage near the edge, the side surface of the heavily doped stage, and the laser chip substrate surface on the side of the heavily doped stage; together with the ion implantation region, it defines the current injection window of the semiconductor laser chip.

[0065] The method for manufacturing a semiconductor laser chip structure provided in this embodiment can manufacture the semiconductor laser chip structure provided in this application. The laser chip structure is modified by a heavily doped stage of a partial thickness located below the insulating layer and an ion-implanted region in the laser chip substrate. The remaining un-ion-implanted modified region is further defined by the insulating layer, and the remaining exposed region can serve as a current injection window. The unexposed portion is blocked by the insulating layer, making direct current injection difficult. Furthermore, the exposed region's side is modified by ion implantation, increasing the resistance of that region. Current injected through the P-side electrode on the top surface cannot pass through this ion-implanted region because the resistance of the region corresponding to the current injection window is much smaller than that of the ion-implanted region. This achieves better lateral current expansion without causing additional photon loss, thus defining the current injection window and its width. This method avoids using the isolation trench of the heavily doped stage for definition, preventing the various stress problems associated with it. Therefore, it solves the related polarization degree, stress, reliability risks, heat dissipation defects, and reduces the impact on the far-field divergence angle caused by using the isolation trench of the heavily doped stage to define the current injection window and width.

[0066] Further reference Figures 4-8 ,by Figure 2 Taking a cross-sectional view of the MM section line location as an example, in some embodiments, the step of forming the ion implantation region includes:

[0067] refer to Figure 4 An ion implantation protective layer N is formed, which covers a portion of the surface of the heavily doped stage B near the edge, the side surface of the heavily doped stage B, and the laser chip substrate A surface on the side of the heavily doped stage B.

[0068] refer to Figure 5A photoresist layer P is formed, which covers the ohmic contact layer 180 exposed by the ion implantation protective layer N and covers a portion of the width of the ion implantation protective layer, and is spaced a distance from the edge of the heavily doped stage.

[0069] refer to Figure 6 Ion implantation is performed to form an initial ion implantation region in the heavily doped stage B and the laser chip substrate A, which are a portion of the thickness below the ion implantation protective layer N.

[0070] refer to Figure 7 Remove the photoresist layer P and the ion implantation protective layer N;

[0071] refer to Figure 8 Annealing repairs ion implantation damage and activates the doped atoms in the initial ion implantation region to the correct lattice positions.

[0072] Following this, the step of forming insulating layer 200 is performed. (See reference) Figure 9 An insulating layer 200 is formed on the surface of the heavily doped stage B near its edge, on the side surface of the heavily doped stage B, and on the surface of the laser chip substrate A on the side of the heavily doped stage B. The ion implantation region covered by the insulating layer 200 is an ion implantation region that has been annealed and repaired.

[0073] It should be noted that the P-side electrode and N-side electrode in the aforementioned embodiments refer to the electrodes located on the P-side and N-side when the semiconductor laser chip performs electro-optic conversion, and do not refer to the electrodes on the surface of the photoresist layer P and the electrodes on the surface of the ion implantation protective layer N.

[0074] The semiconductor laser chip structure manufacturing method of this embodiment first forms a thin ion implantation protective layer N, and then covers a portion of it with a photoresist layer P. The photoresist layer P can completely block ion implantation in the covered area. Simultaneously, in the portion covered only by the ion implantation protective layer N, the presence of the ion implantation protective layer N can, under certain ion implantation conditions, block the implanted ions to a certain extent, preventing excessive ion implantation and serious damage to the epitaxial structure of the laser substrate, thus avoiding performance degradation and potential reliability risks. Annealing repairs the lattice damage to the epitaxial structure of the laser chip substrate caused by ion implantation, and simultaneously activates the doped atoms to the correct lattice positions, thereby ensuring the performance of the laser chip structure.

[0075] Specifically, in some embodiments, the ion implantation step includes:

[0076] The material of the ion implantation protective layer is SiO2 or SiN. x The thickness is 20nm~50nm;

[0077] The overlap E between the photoresist layer and the ion implantation protective layer is 5 μm to 15 μm wide, and the width F between the photoresist layer and the edge of the insulating layer located on the heavily doped stage is 5 μm to 10 μm. The ion implantation region corresponding to region F has more layers and a shallower ion implantation depth because the underlying film still retains a complete epitaxial structure, forming a transition region. This prevents excessive lateral expansion of ion implantation at the boundary of the stripe width W (the junction of W and E). This avoids unnecessary photon scattering and absorption losses at the edge of the stripe width W, reducing electro-optical conversion efficiency and potential reliability risks.

[0078] The aforementioned thinner ion-implanted protective layer SiO2 or SiN x This can avoid directly bombarding the surface of the epitaxial structure during ion implantation, thus avoiding unnecessary surface damage, which could lead to device performance degradation and potential reliability risks.

[0079] Specifically, in some embodiments, the ion implantation step includes:

[0080] The implanted ions are Si ions or H ions, and the implantation is carried out in multiple steps, with the ion energy and / or the implantation dose gradually increasing, while the tilt angle remains unchanged.

[0081] Multi-step ion implantation, with progressively increasing ion energy, ensures sufficient implantation depth and quantity. The consistent tilt angle prevents the implantation region from exceeding the expected range and allows for deeper implantation within the previously defined area. It also prevents excessively deep implantation at once, thus avoiding damage to the quantum well's active layer.

[0082] In some embodiments, Si ion implantation is employed, involving a three-step implantation process:

[0083] The first Si ion implantation was performed at an ion energy of 20 keV and an implantation dose of 3.0E+12 cm⁻¹. -2 Inclination angle 7°;

[0084] The second Si ion implantation was performed at an ion energy of 100 keV and an implantation dose of 3.0E+12 cm⁻¹. -2 Inclination angle 7°;

[0085] The third Si ion implantation was performed at an ion energy of 180 keV and an implantation dose of 3.0E+12 cm⁻¹. -2 Inclination angle 7°;

[0086] Specifically, in some embodiments, the ion implantation step includes:

[0087] In some embodiments, H ion implantation is employed, and a two-step implantation process is performed:

[0088] The first H ion implantation was performed at an ion energy of 30 keV and an implantation dose of 5.0E+14 cm⁻¹. -2 Inclination angle 7°;

[0089] The second H ion implantation was performed at an ion energy of 120 keV and an implantation dose of 5.0E+15 cm⁻¹. -2 The tilt angle is 7°.

[0090] Furthermore, the method for manufacturing the semiconductor laser chip structure provided in this embodiment also includes:

[0091] A front electrode layer is formed on the top surface of the laser chip substrate A and the heavily doped stage B, covering the surface of the current injection window C and the surface of the insulating layer 200; a back electrode layer is formed on the bottom surface of the laser chip substrate A, covering the surface of the substrate layer 110 facing away from the buffer layer 120.

[0092] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A semiconductor laser chip structure, characterized in that, The semiconductor laser chip structure includes: A laser chip substrate, comprising, in sequence, a substrate layer, a buffer layer, a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, and a first upper confinement layer; A heavily doped stage is disposed on the surface of the first upper confinement layer facing away from the substrate layer on the laser chip substrate, and includes a second upper confinement layer and an ohmic contact layer; the length and width of the heavily doped stage are both smaller than the length and width of the laser chip substrate; An insulating layer covers a portion of the width of the heavily doped stage near its edge, the side portion of the heavily doped stage, and the laser chip substrate surface on the side portion of the heavily doped stage; An ion-implanted region is located within a portion of the thickness of the heavily doped stage and the laser chip substrate beneath the insulating layer; the resistance of the ion-implanted region is greater than the resistance of the un-ion-implanted areas of the heavily doped stage and the laser chip substrate surrounding the ion-implanted region; the ion-implanted region and the insulating layer together define the width of the current injection window of the semiconductor laser chip.

2. The semiconductor laser chip structure according to claim 1, characterized in that, The depth of the ion implantation region does not exceed the upper surface of the quantum well active layer.

3. The semiconductor laser chip structure according to claim 2, characterized in that, The ion implantation region is located in the ohmic contact layer, the second upper confinement layer, the first upper confinement layer, and a portion of the thickness of the upper waveguide layer beneath the insulating layer.

4. The semiconductor laser chip structure according to claim 1, characterized in that, The width of the insulating layer covering the edge of the heavily doped stage is greater than the width of the portion of the ion implantation region located on the heavily doped stage; The depth of the ion implantation region located in the heavily doped stage is shallower than the depth of the ion implantation region located in the laser chip substrate.

5. The semiconductor laser chip structure according to claim 1, characterized in that, The implanted ions in the ion implantation region are Si ions or H ions.

6. The semiconductor laser chip structure according to claim 1, characterized in that, The insulating layer is made of SiO2 or SiN. x The thickness of the insulating layer is 50nm~100nm; The insulating layer covers a single side of the heavily doped stage with a width of 10 μm to 25 μm; The semiconductor laser chip structure further includes a front electrode layer covering the surface of the current injection window and the surface of the insulating layer, and a back electrode layer covering the surface of the substrate layer facing away from the buffer layer. The material of the front electrode layer includes titanium, platinum, gold, or alloys thereof; The material of the back electrode layer includes gold, germanium, nickel, or alloys thereof.

7. A method for manufacturing a semiconductor laser chip structure, characterized in that, Includes the following steps: A laser chip substrate epitaxial structure is provided, comprising the following layers stacked sequentially: a substrate layer, a buffer layer, a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, an upper confinement layer, and an ohmic contact layer; The epitaxial structure of the laser chip substrate is etched to form a laser chip substrate and a heavily doped stage on its surface; wherein the portion of the upper confinement layer located on the laser chip substrate is the first upper confinement layer, and the portion located on the heavily doped stage is the second upper confinement layer; The laser chip substrate comprises, in sequence, a substrate layer, a buffer layer, a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, and a first upper confinement layer; The heavily doped stage includes a second upper confinement layer and an ohmic contact layer; the length and width of the heavily doped stage are both smaller than the length and width of the laser chip substrate; An ion implantation region is formed in a portion of the width and thickness of the heavily doped stage near its edge and in a portion of the thickness of the laser chip substrate, such that the resistance of the ion implantation region is greater than the resistance of the un-ion-implanted regions of the heavily doped stage and the laser chip substrate surrounding the ion implantation region. An insulating layer is formed on the surface of the heavily doped stage near the edge, on the side surface of the heavily doped stage, and on the laser chip substrate surface on the side of the heavily doped stage; the insulating layer and the ion implantation region together define the current injection window of the semiconductor laser chip.

8. The method for manufacturing a semiconductor laser chip structure according to claim 7, characterized in that, The step of forming the ion implantation region includes: An ion implantation protective layer is formed, which covers a portion of the surface of the heavily doped stage near its edge, the side surface of the heavily doped stage, and the laser chip substrate surface on the side of the heavily doped stage. A photoresist layer is formed, which covers the ohmic contact layer exposed by the ion implantation protective layer and covers a portion of the width of the ion implantation protective layer, and is spaced apart from the edge of the heavily doped stage by a certain distance; Ion implantation is performed to form an initial ion implantation region in the heavily doped stage and the laser chip substrate, which are a portion of the thickness below the ion implantation protective layer. Remove the photoresist layer and the ion implantation protective layer; Annealing repairs ion implantation damage and activates the doped atoms in the initial ion implantation region to the correct lattice positions.

9. The method for manufacturing a semiconductor laser chip structure according to claim 8, characterized in that, In the step of performing ion implantation: The material of the ion implantation protective layer is SiO2 or SiN. x The thickness is 20nm~50nm; The overlap between the photoresist layer and the ion implantation protective layer is 5 μm to 15 μm wide, and the width distance from the photoresist layer to the edge of the insulating layer located on the heavily doped stage is 5 μm to 10 μm.

10. The method for manufacturing a semiconductor laser chip structure according to claim 8, characterized in that, In the step of performing ion implantation: The implanted ions are Si ions or H ions, and the implantation is carried out in multiple steps, with the ion energy and / or the implantation dose gradually increasing, while the tilt angle remains unchanged.

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