Signal processor and radar sensor including same

Abstract

A signal processor and a radar sensor including the same are provided. The signal processor includes: a first filter circuit configured to generate an output signal based on an input signal and a feedback signal, the first filter circuit including a first resistor and a first capacitor, a filtering frequency range of the signal processor being set based on a first resistance of the first resistor and a first capacitance of the first capacitor; a second filter circuit connected to a feedback path of the first filter circuit, the second filter circuit configured to generate an intermediate signal based on the output signal; and an offset cancellation circuit connected to the feedback path of the first filter circuit, the offset cancellation circuit configured to generate a feedback signal based on the intermediate signal.

Description

[0001] This application is based on and claims the benefit of Korean Patent Application No. 10-2024-0018397 filed on February 6, 2024, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2024-0079096 filed on June 18, 2024, in the Korean Intellectual Property Office, the disclosure of each of which is incorporated herein in its entirety by reference. Technical Field

[0002] The inventive concept relates to a signal processor which can be designed relatively simply. Background Art

[0003] An electronic device may include a radar sensor for detecting the distance to an object and the speed of the object. The radar sensor may transmit a transmission signal (such as a frequency modulated continuous waveform (FMCW) signal) to the object and estimate the distance to the object and the speed of the object based on the reflected signal reflected by the object.

[0004] The radar sensor may perform signal processing on the reflected signal before estimating the distance to the object and the speed of the object. For example, the radar sensor may filter the reflected signal into a signal with a desired gain and a desired frequency band by passing the reflected signal through a signal processor including a high-pass filter, a low-pass filter, a variable gain amplifier, etc.

[0005] Here, when designing a signal processor with a structure in which a high-pass filter, a low-pass filter, a variable gain amplifier, etc. are connected in cascade, there may be difficulties in designing the circuit when the respective circuits have different operating points. In addition, there may be loss due to impedance between the circuits connected in cascade. Summary of the Invention

[0006] The inventive concept provides a signal processor that can be designed relatively simply. The embodiments provide a signal processor that can be designed more simply even when performing the same operation (or similar operation).

[0007] According to one aspect of the inventive concept, a signal processor is provided, comprising: a first filter circuit configured to generate an output signal based on an input signal and a feedback signal, the first filter circuit comprising a first resistor and a first capacitor, a filtering frequency range of the signal processor being set based on a first resistance of the first resistor and a first capacitance of the first capacitor; a second filter circuit connected to a feedback path of the first filter circuit, the second filter circuit being configured to generate an intermediate signal based on the output signal; and an offset cancellation circuit connected to the feedback path of the first filter circuit, the offset cancellation circuit being configured to generate a feedback signal based on the intermediate signal.

[0008] According to one aspect of the inventive concept, a signal processor is provided, comprising: a first filter circuit configured to generate an output signal based on an input signal and a feedback signal, the gain of the signal processor being set based on a first resistance of a first resistor in the first filter circuit; a second filter circuit connected to a feedback path of the first filter circuit, the second filter circuit being configured to generate an intermediate signal based on the output signal; and an offset cancellation circuit connected to the feedback path of the first filter circuit, the offset cancellation circuit being configured to generate a feedback signal based on the intermediate signal.

[0009] According to one aspect of the inventive concept, a radar sensor is provided, comprising: a processing circuit system configured to generate a transmission signal, amplify the transmission signal to obtain an amplified transmission signal, transmit the amplified transmission signal via a transmission antenna, receive the reception signal via a reception antenna, and generate an input signal by amplifying the reception signal, wherein the reception signal corresponds to a reflection signal generated by reflection of the transmission signal by an object; and a signal processor comprising a first filter circuit, a second filter circuit, and an offset cancellation circuit, the first filter circuit being configured to generate an output signal based on the input signal and a feedback signal, the first filter circuit comprising a resistor and a capacitor, a filtering frequency range of the signal processor being set based on the resistance of the resistor and the capacitance of the capacitor, the second filter circuit being connected to a feedback path of the first filter circuit, the second filter circuit being configured to generate an intermediate signal based on the output signal, and the offset cancellation circuit being connected to the feedback path of the first filter circuit, the offset cancellation circuit being configured to generate the feedback signal based on the intermediate signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figure 1 is a block diagram illustrating a radar sensor according to an embodiment.

[0012] Figure 2 is a block diagram illustrating a signal processor included in a radar sensor according to a comparative technique.

[0013] Figure 3 is a block diagram illustrating a signal processor included in a radar sensor according to an embodiment.

[0014] Figure 4 is a circuit diagram showing an example of a first filter circuit of a signal processor according to an embodiment.

[0015] Figure 5 : is a circuit diagram showing respective examples of a second filter circuit and an offset cancellation circuit of a signal processor according to an embodiment.

[0016] Figure 6 is a diagram illustrating a graph of frequency response characteristics of a signal processor according to an embodiment.

[0017] Figure 7 is a circuit diagram showing another example of the first filter circuit of the signal processor according to the embodiment.

[0018] Figure 8 : is a circuit diagram showing other corresponding examples of the second filter circuit and the offset cancellation circuit of the signal processor according to the embodiment.

[0019] Figure 9 is a block diagram illustrating a computing device including a radar sensor according to an embodiment.

[0020] Figure 10 is a block diagram illustrating an autonomous driving system including a radar sensor according to an embodiment. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0022] Figure 1 is a block diagram illustrating a radar sensor according to an embodiment.

[0023] Reference Figure 1 , the radar sensor 100 according to an embodiment may include a processor 110, a signal generator 115, a signal distributor 125, a transmitting amplifier 130, a transmitting antenna 135, a receiving antenna 140, a receiving amplifier 145, a receiving frequency converter 150 and / or a signal processor 160.

[0024] The radar sensor 100 may detect the distance to an object outside the radar sensor 100 and / or the speed of the object. The radar sensor 100 may generate and transmit a signal to the outside of the radar sensor 100, may receive a reflected signal generated by the reflected signal from the object, and may predict the distance to the object and / or the speed of the object based on the reflected signal.

[0025] The processor 110 may control all operations of the radar sensor 100. The processor 110 may transmit a control signal for generating a transmission signal to the signal generator 115, and may predict a distance to an object and / or a speed of the object based on a signal output from the signal processor 160.

[0026] Signal generator 115 may generate a transmit signal based on a control signal received from processor 110. In an embodiment, the transmit signal may be a frequency modulated continuous waveform (FMCW) signal generated based on a preset (or, alternatively, a given) frequency modulation pattern. The FMCW signal generated by signal generator 115 may have a waveform in which the carrier frequency gradually increases in some time periods and gradually decreases in other time periods.

[0027] The signal generator 115 may include a voltage controlled oscillator (VCO) circuit for generating various oscillation frequencies and a phase locked loop (PLL) circuit for improving stability of an output frequency of the VCO circuit.

[0028] The signal distributor 125 may receive the transmission signal generated by the signal generator 115. The signal distributor 125 may divide the transmission signal and transfer the transmission signal to the transmission amplifier 130 and the reception frequency converter 150.

[0029] The transmission amplifier 130 may amplify the transmission signal received from the signal distributor 125. The transmission amplifier 130 may amplify the transmission signal and transmit the transmission signal (eg, the amplified transmission signal) to the transmission antenna 135.

[0030] The transmission antenna 135 may transmit the amplified transmission signal received from the transmission amplifier 130. Figure 1 Although an example is shown in which the radar sensor 100 includes one transmitting antenna 135 (e.g., only one transmitting antenna 135), the inventive concept is not limited thereto, and the radar sensor 100 may include one or more transmitting antennas 135. According to a time division method, the one or more transmitting antennas 135 may each transmit a transmission signal in a time period for which each transmitting antenna 135 is responsible (e.g., a corresponding time period allocated to each transmitting antenna 135).

[0031] The receiving antenna 140 may receive a reflected signal generated by a return of the transmitted transmission signal reflected by an object as a received signal. Figure 1 An example is shown in which the radar sensor 100 includes one receiving antenna 140 (eg, only one receiving antenna 140 ), but the inventive concept is not limited thereto, and the radar sensor 100 may include one or more receiving antennas 140 .

[0032] The reception amplifier 145 may amplify a reception signal received via the reception antenna 140 . The reception amplifier 145 may amplify the reception signal and transmit the reception signal (eg, the amplified reception signal) to the reception frequency converter 150 .

[0033] The reception frequency converter 150 may receive the reception signal amplified by the reception amplifier 145 and the transmission signal distributed by the signal distributor 125. The reception frequency converter 150 may modulate the reception signal into a baseband signal by multiplying the reception signal by the transmission signal received from the signal distributor 125. The reception frequency converter 150 may transmit the modulated reception signal to the signal processor 160.

[0034] The signal processor 160 may perform signal processing on the modulated reception signal received via the reception frequency converter 150. The signal processor 160 may perform processing (such as high-pass filtering, low-pass filtering, variable gain amplification, or offset cancellation) on the reception signal (eg, the modulated reception signal).

[0035] In an embodiment, the signal processor 160 may include a first filter circuit, a second filter circuit connected to a feedback path of the first filter circuit, and / or an offset cancellation circuit connected to the feedback path of the first filter circuit.

[0036] Here, the filtering frequency range of the signal processor 160 can be set based on the resistance of the resistor included in the first filter circuit and the capacitance of the capacitor included in the first filter circuit. In addition, the gain of the signal processor 160 can be set based on the resistance of the resistor of the first filter circuit.

[0037] The following reference Figure 3 and Figure 3 The following figures describe the more detailed structure and operation of the signal processor 160 .

[0038] Figure 2 is a block diagram illustrating a signal processor included in a radar sensor according to a comparative technique.

[0039] Reference Figure 2 , the signal processor 160 included in the radar sensor 100 according to the comparative technology may include a high-pass filter 161 , a low-pass filter 162 , and an amplification circuit 165 .

[0040] The high pass filter 161 may receive the reception signal amplified by the reception amplifier 145 and modulated by the reception frequency converter 150. The high pass filter 161 may pass a frequency component equal to or greater than a preset (or alternatively, given) cutoff frequency in the signal input to the high pass filter 161.

[0041] The low-pass filter 162 may receive the signal that has passed through the high-pass filter 161. The low-pass filter 162 may pass frequency components of the received signal that are equal to or less than a preset (or alternatively, a given) cutoff frequency. The cutoff frequency of the low-pass filter 162 may be greater than the cutoff frequency of the high-pass filter 161.

[0042] Amplification circuit 165 may include a variable gain amplifier 163 and an offset cancellation circuit 164 (also referred to herein as offset removal circuit 164). Because offset cancellation circuit 164 of amplification circuit 165 is connected to the feedback path of variable gain amplifier 163, variable gain amplifier 163 and offset cancellation circuit 164 can be designed simultaneously. For example, relevant parameters of components included in variable gain amplifier 163 and offset cancellation circuit 164 (e.g., the resistance of a resistor, the capacitance of a capacitor, etc.) can be set (or defined, configured, etc.) together (e.g., at a single point in time).

[0043] The variable gain amplifier 163 may receive the signal having passed through the low pass filter 162. The variable gain amplifier 163 may amplify the signal having passed through the low pass filter 162 so that the signal has a target signal strength.

[0044] The offset cancellation circuit 164 may receive the signal that has passed through the variable gain amplifier 163. The offset cancellation circuit 164 may be located on a feedback path of the variable gain amplifier 163. The offset cancellation circuit 164 may remove a direct current (DC) offset caused by an error in an oscillator, a switching device, etc. in the radar sensor 100 from the signal that has passed through the variable gain amplifier 163.

[0045] When high-pass filter 161, low-pass filter 162, and amplifier circuit 165 are connected in a cascade configuration as in signal processor 160 according to the comparative technique, high-pass filter 161, low-pass filter 162, and amplifier circuit 165 can be individually designed, and signal processor 160 can be constructed by connecting the individually designed high-pass filter 161, low-pass filter 162, and amplifier circuit 165 to one another. For example, the relevant parameters of the components included in each of high-pass filter 161, low-pass filter 162, and amplifier circuit 165 (e.g., the resistance of a resistor, the capacitance of a capacitor, etc.) can be initially set (or defined, configured, etc.) separately. Subsequently, the relevant parameters of the components initially set for each of high-pass filter 161, low-pass filter 162, and amplifier circuit 165 (e.g., the resistance of a resistor, the capacitance of a capacitor, etc.) can be adjusted (or corrected, refined, etc.) for the combination of high-pass filter 161, low-pass filter 162, and amplifier circuit 165. Here, because high-pass filter 161, low-pass filter 162, and amplifier circuit 165 are designed separately, the operating points of each circuit need to (or should) be consistent with each other, which may cause difficulties in circuit design. In addition, there may be loss due to impedance between high-pass filter 161, low-pass filter 162, and amplifier circuit 165 connected in cascade.

[0046] Figure 3is a block diagram illustrating a signal processor included in a radar sensor according to an embodiment.

[0047] Reference Figure 3 , the signal processor 200 according to the embodiment may include a first filter circuit 210, a second filter circuit 220 and / or an offset cancellation circuit 230. Here, Figure 3 The signal processor 200 can be used as Figure 1 signal processor 160.

[0048] The signal processor 200 may receive an input signal V in Input signal V in It may be a signal input to the signal processor 160 of the radar sensor 100, and may be a received signal amplified by the receiving amplifier 145 and modulated by the receiving frequency converter 150. The signal processor 200 may generate an input signal V based on the received signal. in Perform signal processing to generate the output signal V out .

[0049] The first filter circuit 210 can receive an input signal V in In addition, the first filter circuit 210 can receive the feedback signal I f Feedback signal I f It can be a signal generated by the second filter circuit 220 and the offset cancellation circuit 230. In an embodiment, the first filter circuit 210 can be based on the input signal V in and feedback signal I f To generate the output signal V out .

[0050] The first filter circuit 210 may include a bandpass filter that passes a signal within a specific frequency range. The first filter circuit 210 may pass the input signal V in The signal in a specific frequency range is used to generate the output signal V out . Please refer to Figure 4 An example of the first filter circuit 210 is described in more detail.

[0051] Figure 4 is a circuit diagram showing an example of a first filter circuit of a signal processor according to an embodiment.

[0052] Reference Figure 4 In an embodiment, the first filter circuit 210a may include a first capacitor 211, a first resistor 213, an amplifier 215a, a second capacitor 216 and / or a second resistor 218. Figure 4 In the example of FIG. 5 , the first filter circuit 210 a may be a circuit designed in single mode (eg, not differential mode).

[0053] The first capacitor 211 can receive an input signal V in That is, the first capacitor 211 can receive the input signal V via one end of the first capacitor 211. in The first capacitor 211 may have a first capacitance C1.

[0054] The first resistor 213 may be connected in series to the first capacitor 211. Here, one end of the first resistor 213 may be connected to the other end of the first capacitor 211. The first resistor 213 may have a first resistance R1.

[0055] The amplifier 215a may be connected to the first resistor 213 via an input terminal of the amplifier 215a. Here, the first input terminal of the amplifier 215a may be connected to the other end of the first resistor 213. The second input terminal of the amplifier 215a may be connected to a ground terminal. The amplifier 215a may output a signal V out Output.

[0056] The second capacitor 216 may be connected in parallel to the amplifier 215a. Here, one end (eg, a first end) of the second capacitor 216 may be connected to the first input terminal of the amplifier 215a, and the other end (eg, a second end) of the second capacitor 216 may be connected to the output terminal of the amplifier 215a.

[0057] The second capacitor 216 can receive the feedback signal I f That is, the second capacitor 216 may receive the feedback signal I via one end (eg, the first end) of the second capacitor 216. f The second capacitor 216 may have a second capacitance C2.

[0058] The second resistor 218 may be connected in parallel to the amplifier 215a. Here, one end (e.g., a first end) of the second resistor 218 may be connected to the first input terminal of the amplifier 215a, and the other end (e.g., a second end) of the second resistor 218 may be connected to the output terminal of the amplifier 215a.

[0059] The second resistor 218 can receive the feedback signal I f Here, the second resistor 218 may receive the feedback signal I via one end (eg, the first end) of the second resistor 218. f The second resistor 218 may have a second resistance R2.

[0060] When the first filter circuit 210a has Figure 4 When the structure shown in FIG. 1 is used, by applying Kirchhoff's law around the first input terminal of the amplifier 215 a of the first filter circuit 210 a , Equation 1 shown below can be derived.

[0061] [Equation 1]

[0062] In Equation 1, v i (s) can be the input signal V in The result of the Laplace transform, v o (s) can be the output signal V out The result of the Laplace transform, i f (s) can be the feedback signal I f The result of the Laplace transform, and s can be a Laplace variable.

[0063] Refer again Figure 3 , the second filter circuit 220 may be connected to the feedback path of the first filter circuit 210. Here, the second filter circuit 220 may constitute the feedback path of the first filter circuit 210 together with the offset cancellation circuit 230. The second filter circuit 220 may be connected to the output terminal of the first filter circuit 210. The second filter circuit 220 may receive the output signal V out .

[0064] The second filter circuit 220 may include a low-pass filter that passes a signal having a specific frequency or less. In an embodiment, the second filter circuit 220 may be based on the output signal V out To generate the intermediate signal V m For example, the second filter circuit 220 can be configured to filter the output signal V out A signal with a specific frequency or less in the middle is generated by m .

[0065] The offset cancellation circuit 230 may be connected to the feedback path of the first filter circuit 210. Here, the offset cancellation circuit 230 may constitute the feedback path of the first filter circuit 210 together with the second filter circuit 220. The offset cancellation circuit 230 may be connected to the output terminal of the second filter circuit 220. The offset cancellation circuit 230 may receive the intermediate signal V m In an embodiment, the offset cancellation circuit 230 may be based on the intermediate signal V m To generate the feedback signal I f .

[0066] The offset cancellation circuit 230 may remove a DC offset from the signal having passed through the second filter circuit 220 .

[0067] Please refer to Figure 5 Corresponding examples of the second filter circuit 220 and the offset cancellation circuit 230 are described in further detail.

[0068] Figure 5 : is a circuit diagram showing respective examples of a second filter circuit and an offset cancellation circuit of a signal processor according to an embodiment.

[0069] Reference Figure 5 In an embodiment, the second filter circuit 220a may include a third resistor 221 and / or a third capacitor 223, and the offset cancellation circuit 230a may include a voltage-current converter 231a. Figure 5 In the example of FIG. 1 , the second filter circuit 220 a and the offset cancellation circuit 230 a may each be a circuit designed as a single mode circuit and may be used in conjunction with the circuit shown in FIG. Figure 4 As in the example of FIG. 1 , the first filter circuit 210 a designed in a single mode is used together.

[0070] The third resistor 221 can receive the output signal V out That is, the third resistor 221 can receive the output signal V via one end of the third resistor 221. out The third resistor 221 may have a third resistance R3.

[0071] The third capacitor 223 may be connected to the third resistor 221. Here, one end of the third capacitor 223 may be connected to the other end of the third resistor 221. The other end of the third capacitor 223 may be connected to a ground terminal. The third capacitor 223 may have a third capacitance C3.

[0072] Here, the intermediate signal V m The voltage may be outputted via a terminal between the third resistor 221 and the third capacitor 223 .

[0073] When the second filter circuit 220a has Figure 5 When the structure shown in FIG. 1 is used, by applying Kirchhoff's law around the terminals between the third resistor 221 and the third capacitor 223 , Equation 2 shown below can be obtained.

[0074] [Equation 2]

[0075] In Equation 2, v m (s) can be the intermediate signal V m The result of the Laplace transform.

[0076] The input terminal of the voltage-current converter 231a may be connected to a terminal between the third resistor 221 and the third capacitor 223. Here, the voltage-current converter 231a may receive the intermediate signal V m The voltage-current converter 231a can output a feedback signal I through the output terminal of the voltage-current converter 231a. f.

[0077] When the offset cancellation circuit 230a has Figure 5 In the structure shown in FIG, the feedback signal I f With the intermediate signal V m The relationship between can be expressed by Equation 3 shown below.

[0078] [Equation 3]

[0079] In Equation 3, g m It can be the gain of the voltage-to-current converter 231a.

[0080] Refer again Figure 3 , when the first filter circuit 210 of the signal processor 200 has Figure 4 The structure shown in FIG and the second filter circuit 220 and the offset cancellation circuit 230 of the signal processor 200 have Figure 5 When the structure shown in , the transfer function of the signal processor 200 obtained by combining Equations 1 to 3 can be expressed by Equation 4 shown below.

[0081] [Equation 4]

[0082] In Equation 4, H(s) may be a result of Laplace transform of a transfer function of the signal processor 200 .

[0083] In this way, the signal processor 200 may have two zero points and three poles. Here, in order to make the signal processor 200 have a desired filtering frequency range, the following setting may be performed.

[0084] First, the signal processor 200 can be configured so that the gain g of the second resistor R2 and the offset cancellation circuit 230a is m The product of is as large as a first reference multiple (e.g., 100 times) or a larger multiple of the reference gain (e.g., 1). According to an embodiment, the reference multiple and / or reference gain used herein may represent an integer value. That is, the signal processor 200 may be configured to satisfy Inequality 5 shown below.

[0085] [Inequality 5]

[0086] By using Inequality 5, Equation 4 can be approximated as Equation 6 shown below.

[0087] [Equation 6]

[0088] That is, the constant term of the quadratic expression in the denominator in Equation 4 can be simplified as in Equation 6.

[0089] Next, the signal processor 200 may be configured so that the gain g of the offset cancellation circuit 230a is adjusted by combining the second resistor R2 with the gain g of the offset cancellation circuit 230a. m The value obtained by dividing the product of the third resistor R3 and the third capacitor C3 by the product of the third resistor R3 and the third capacitor C3 is approximately equal to (or can be set to be equal to) the inverse of the product of the first resistor R1 and the first capacitor C1. That is, by combining the second resistor R2 with the gain g of the offset cancellation circuit 230a, m The difference between the value obtained by dividing the product of the third resistor R3 and the third capacitor C3 and the inverse of the product of the first resistor R1 and the first capacitor C1 may be within a predetermined error range. That is, the signal processor 200 may be configured to satisfy Equation 7 shown below.

[0090] [Equation 7]

[0091] By using Equation 7, Equation 6 can be approximated as Equation 8 shown below.

[0092] [Equation 8]

[0093] That is, the constant term of the quadratic expression in the denominator in Equation 6 can be further simplified as in Equation 8.

[0094] Next, to determine the positions of the zero and pole points, the signal processor 200 may be configured such that the reciprocal of the product of the second resistor R2 and the second capacitor C2 is a second reference multiple (e.g., 100 times) or greater of the reciprocal of the product of the first resistor R1 and the first capacitor C1, and the reciprocal of the product of the first resistor R1 and the first capacitor C1 is a third reference multiple (e.g., 100 times) or greater of the reciprocal of the product of the third resistor R3 and the third capacitor C3. That is, the signal processor 200 may be configured to satisfy Inequality 9 shown below.

[0095] [Inequality 9]

[0096] By using inequality 9, equation 8 can be approximated as equation 10 shown below.

[0097] [Equation 10]

[0098] Here, a graph of the frequency response characteristics of the signal processor 200 satisfying Equation 10 may be shown as Figure 6 As shown in .

[0099] Figure 6 is a diagram illustrating a graph of frequency response characteristics of a signal processor according to an embodiment.

[0100] Reference Figure 6 , a graph showing the frequency response characteristics of the signal processor 200 satisfying Equation 10 can be checked. Since the positions of the zero point and the pole are determined as in Inequality 9, the gain of the signal processor 200 may first increase from a point at a frequency of 0 (e.g., +20 decibels / decade), may secondly increase from a point at a frequency of 1 / (2πR3C3) (e.g., +40 dB / decade), may have a constant value from a point at a frequency of 1 / (2πR1C1), and may first decrease from a point at a frequency of 1 / (2πR2C2) (e.g., -20 dB / decade).

[0101] Reference Figure 6 According to the graph and Equation 10, the filtering frequency range of the signal processor 200 may be within a range from a frequency corresponding to the inverse of the product of the first resistor R1 and the first capacitor C1 to a frequency corresponding to the inverse of the product of the second resistor R2 and the second capacitor C2. That is, the filtering frequency range of the signal processor 200 may be set based on the respective resistances R1 and R2 (e.g., first resistor R1 and second resistor R2) of the resistors 213 and 218 (e.g., first resistor 213 and second resistor 218) of the first filter circuit 210a, and the respective capacitances C1 and C2 (e.g., first capacitance C1 and second capacitance C2) of the capacitors 211 and 216 (e.g., first capacitor 211 and second capacitor 216) of the first filter circuit 210a. In an embodiment, if the first filter circuit 210a includes the first capacitor 211 and the first resistor 213, the filtering frequency range of the signal processor 200 may be set based on the first capacitance C1 of the first capacitor 211 and the first resistance R1 of the first resistor 213.

[0102] Furthermore, the gain of the signal processor 200 may be derived from Equation 10 as Equation 11 shown below.

[0103] [Equation 11]

[0104] In Equation 11, It can be any (or alternatively, a given) frequency within the filtering frequency range of the signal processor 200 .

[0105] Reference Figure 6According to the graph and Equation 11, the gain of the signal processor 200 can be set to be inversely proportional to the first resistance R1 and proportional to the second resistance R2 (e.g., directly proportional to the second resistance R2). The gain of the signal processor 200 can be set based on the respective resistances R1 and R2 of the resistors 213 and 218 of the first filter circuit 210a. In an embodiment, when the first filter circuit 210a includes the first capacitor 211 and the first resistor 213, the gain of the signal processor 200 can be set based on the first resistance R1 of the first resistor 213.

[0106] Refer again Figure 3 The signal processor 200 according to the embodiment can be implemented by the first filter circuit 210, the second filter circuit 220, and the offset cancellation circuit 230 included in one feedback loop. Therefore, the signal processor 200 can have a relatively simple structure. Therefore, since the entire signal processor 200 can be designed at once, the signal processor 200 can be designed more simply.

[0107] In addition, since the filtering frequency range of the signal processor 200 according to the embodiment can be set based on the corresponding resistances R1 and R2 of the resistors 213 and 218 of the first filter circuit 210a and the corresponding capacitances C1 and C2 of the capacitors 211 and 216 of the first filter circuit 210a, the frequency band of the signal that has passed through the signal processor 200 can be simply adjusted.

[0108] Furthermore, since the gain of the signal processor 200 according to the embodiment can be set based on the respective resistances R1 and R2 of the resistors 213 and 218 of the first filter circuit 210 a , the gain of the signal processor 200 can be simply adjusted.

[0109] Figure 7 is a circuit diagram showing another example of the first filter circuit of the signal processor according to the embodiment.

[0110] Reference Figure 7 In an embodiment, the first filter circuit 210b may include a pair of first capacitors 211 and 212, a pair of first resistors 213 and 214, an amplifier 215b, a pair of second capacitors 216 and 217, and / or a pair of second resistors 218 and 219. Figure 7 In the example of FIG. 5 , the first filter circuit 210 b may be a circuit designed in a differential mode.

[0111] The pair of first capacitors 211 and 212 can respectively receive a pair of input signals (eg, a pair of differential input signals) V in + and V inThat is, the pair of first capacitors 211 and 212 can receive a pair of input signals V respectively via the ends (eg, first ends) of one side of the pair of first capacitors 211 and 212. in + and V in The pair of first capacitors 211 and 212 may each have a first capacitance C1.

[0112] The pair of first resistors 213 and 214 may be connected in series to the pair of first capacitors 211 and 212, respectively. Here, one end (e.g., first end) of the pair of first resistors 213 and 214 may be connected to the other end (e.g., second end) of the pair of first capacitors 211 and 212, respectively. The pair of first resistors 213 and 214 may each have a first resistance R1.

[0113] The amplifier 215b may be connected to the pair of first resistors 213 and 214 via a pair of input terminals of the amplifier 215b. Here, the pair of input terminals of the amplifier 215b may be connected to the other ends (e.g., second ends) of the pair of first resistors 213 and 214. The amplifier 215b may output a pair of output signals (e.g., a pair of differential output signals) V via a pair of output terminals. out + and V out -.

[0114] The pair of second capacitors 216 and 217 may each be connected in parallel to the amplifier 215 b. Here, one end (e.g., first end) of the pair of second capacitors 216 and 217 may be connected to a pair of input terminals of the amplifier 215 b, and the other end (e.g., second end) of the pair of second capacitors 216 and 217 may be connected to a pair of output terminals of the amplifier 215 b.

[0115] A pair of second capacitors 216 and 217 can respectively receive a pair of feedback signals I f -andI f That is, the pair of second capacitors 216 and 217 can receive a pair of feedback signals I respectively via the ends (eg, first ends) of one side of the pair of second capacitors 216 and 217. f -andI f The pair of second capacitors 216 and 217 may each have a second capacitance C2.

[0116] The pair of second resistors 218 and 219 may each be connected in parallel to the amplifier 215 b. Here, one end (e.g., first end) of the pair of second resistors 218 and 219 may be connected to a pair of input terminals of the amplifier 215 b, and the other end (e.g., second end) of the pair of second resistors 218 and 219 may be connected to a pair of output terminals of the amplifier 215 b.

[0117] A pair of second resistors 218 and 219 can respectively receive a pair of feedback signals I f -andI f Here, the pair of second resistors 218 and 219 may receive a pair of feedback signals I respectively via ends (eg, first ends) of one side of the pair of second resistors 218 and 219. f -andI f The pair of second resistors 218 and 219 may each have a second resistance R2.

[0118] Also for Figure 7 The first filter circuit 210b shown in FIG. 1 yields Equation 1, and here, by filtering a pair of input signals V in + and V in - the difference between (i.e., (V in +)-(V in -)) Perform Laplace transform to obtain v i (s), and can be output by a pair of output signals V out + and V out - the difference between (i.e., (V out +)-(V out -)) Perform Laplace transform to obtain v o (s).

[0119] Figure 8 : is a circuit diagram showing other corresponding examples of the second filter circuit and the offset cancellation circuit of the signal processor according to the embodiment.

[0120] Reference Figure 8 In an embodiment, the second filter circuit 220b may include a pair of third resistors 221 and 222 and / or a pair of third capacitors 223 and 224, and the offset cancellation circuit 230b may include a voltage-current converter 231b. Figure 8 In the example of FIG. 1 , the second filter circuit 220 b and the offset cancellation circuit 230 b may each be a circuit designed in a differential mode and may be used in conjunction with FIG. Figure 7 As in the example of FIG. 1 , the first filter circuit 210 b designed in differential mode is used together with the first filter circuit 210 b.

[0121] A pair of third resistors 221 and 222 can respectively receive a pair of output signals V out + and V out That is, the pair of third resistors 221 and 222 can receive a pair of output signals V respectively via the ends (eg, first ends) of one side of the pair of third resistors 221 and 222. out + and V out The pair of third resistors 221 and 222 may each have a third resistance R3.

[0122] The pair of third capacitors 223 and 224 may be connected to the pair of third resistors 221 and 222, respectively. Here, one end (e.g., first end) of the pair of third capacitors 223 and 224 may be connected to the other end (e.g., second end) of the pair of third resistors 221 and 222, respectively. The other end (e.g., second end) of the pair of third capacitors 223 and 224 may be connected to each other. The pair of third capacitors 223 and 224 may each have a third capacitance C3.

[0123] Here, a pair of intermediate signals V m + and V m - may be output via terminals between the pair of third resistors 221 and 222 and the pair of third capacitors 223 and 224, respectively.

[0124] Also for Figure 8 The second filter circuit 220b shown in FIG. 1 yields Equation 2, and here, by filtering a pair of intermediate signals V m + and V m - the difference between (i.e., (V m +)-(V m -)) Perform Laplace transform to obtain v m (s).

[0125] A pair of input terminals of the voltage-current converter 231b may be connected to terminals between the pair of third resistors 221 and 222 and the pair of third capacitors 223 and 224, respectively. Here, the voltage-current converter 231b may receive a pair of intermediate signals V m + and V m The voltage-current converter 231b can output a pair of feedback signals I through a pair of output terminals of the voltage-current converter 231b. f + and I f -.

[0126] Also for Figure 8 The offset cancellation circuit 230b shown in FIG. 3 yields Equation 3, and here, the pair of feedback signals I f + and I f - the difference between (i.e., (I f +)-(I f -)) Perform Laplace transform to obtain i f (s).

[0127] Figure 9 is a block diagram illustrating a computing device including a radar sensor according to an embodiment.

[0128] Reference Figure 9 The computing device 900 may perform operations and functions for detecting the distance to an object outside the computing device 900 and / or the speed of the object. The computing device 900 may be used in an autonomous driving system, a flight radar system, a driver assistance system, an object recognition system, a surveillance / security system, and the like. The computing device 900 may operate while being installed in, for example, an image processing device, a radar device, a smartphone, a wearable device, a tablet computer, a netbook computer, a laptop computer, a desktop computer, a head-mounted display (HMD), an autonomous vehicle, a smart vehicle, and the like.

[0129] The computing device 900 may include a processor 910, a storage device 920, a sensor 930, an input device 940, an output device 950, and / or a network device 960. The processor 910, the storage device 920, the sensor 930, the input device 940, the output device 950, and / or the network device 960 may communicate with each other via a communication bus 970.

[0130] The processor 910 executes functions and instructions to be executed in the computing device 900. For example, the processor 910 may process instructions stored in the storage device 920.

[0131] The storage device 920 stores information or data required for (or used for) processing operations performed by the processor 910. The storage device 920 may store instructions to be executed by the processor 910. The storage device 920 may include a non-transitory computer-readable storage medium (e.g., random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), a magnetic hard disk, an optical disk, a flash memory, an erasable programmable read-only memory (EPROM), or other types of non-transitory computer-readable storage media known in the art).

[0132] The sensor 930 may include one or more sensors. The sensor 930 may include a radar sensor, an image sensor, etc. Here, the radar sensor included in the sensor 930 may be referred to as Figures 1 to 8 The radar sensor 100 according to the exemplary embodiment is described as being implemented.

[0133] The input device 940 may receive input from the user via tactile input, video input, audio input, touch input, etc. The input device 940 may include a keyboard, a mouse, a touch screen, a microphone, or any other device capable of detecting input from the user and transmitting the detected input.

[0134] The output device 950 may provide the output of the computing device 900 to the user in a visual, auditory, and / or tactile manner. For example, the output device 950 may include a liquid crystal display, a light-emitting diode (LED) display, a touch screen, a speaker, a vibration-generating device, or any other device capable of providing an output to the user. In embodiments, the output device 950 may provide a result reflecting the position information (and / or velocity information) of the object estimated by the processor 910 by using one or more of visual information, auditory information, and / or tactile information.

[0135] The network device 960 may communicate with external devices via a wired network or a wireless network. For example, the network device 960 may communicate with external devices via a wired communication method or a wireless communication method such as Bluetooth, WiFi, 3G, or LTE.

[0136] Figure 10 is a block diagram illustrating an autonomous driving system including a radar sensor according to an embodiment.

[0137] Reference Figure 10 , the autonomous driving device 1000 may include a sensor 1010, a memory 1020, a processor 1030, a RAM 1040, a main processor 1050, a driver 1060 and / or a communication interface (I / F) 1070, and these components of the autonomous driving device 1000 may be communicatively connected to each other through a bus.

[0138] The sensor 1010 may include a plurality of sensors that generate information about the surrounding environment of the autonomous driving device 1000. For example, the sensor 1010 may include a plurality of sensors that receive image signals about the surrounding environment of the autonomous driving device 1000 and output the received image signals as images. The sensor 1010 may include an image sensor 1011 (such as a charge coupled device (CCD) and / or a complementary metal oxide semiconductor (CMOS)), a radar sensor 1013, and the like. In an embodiment, the image sensor 1011 may generate a front side image of the autonomous driving device 1000 and provide the front side image to the processor 1030. In an embodiment, the radar sensor 1013 may detect the distance to an object outside the radar sensor 1013 and / or the speed of the object. Here, the radar sensor 1013 may be referred to as Figures 1 to 8 The radar sensor 100 according to the exemplary embodiment is described as being implemented.

[0139] The memory 1020 is a storage location for storing data, and may store, for example, various data generated in a process of performing calculations by the main processor 1050 and / or the processor 1030 .

[0140] The processor 1030 may process various calculations related to the sensor 1010 .

[0141] The main processor 1050 may control all operations of the autonomous driving device 1000. For example, the main processor 1050 may control the functions of the processor 1030 by executing a program stored in the RAM 1040. The RAM 1040 may temporarily store programs, data, applications, and / or instructions.

[0142] In addition, the main processor 1050 may control the operation of the automatic driving device 1000 based on the calculation results of the processor 1030. In an embodiment, the main processor 1050 may receive information about the position and / or speed of the target from the processor 1030, and may control the operation of the driver 1060 based on the received information about the position and speed of the target.

[0143] Driver 1060 is a component for driving autonomous driving device 1000 and may include an engine and motor 1061, a steering unit 1063, and a brake unit 1065. In embodiments, driver 1060 may adjust the propulsion, braking, speed, direction, and the like of autonomous driving device 1000 by using engine and motor 1061, steering unit 1063, and / or brake unit 1065 under the control of processor 1030. Depending on embodiments, each of engine and motor 1061, steering unit 1063, and / or brake unit 1065 may include a corresponding actuator configured to adjust, for example, the power output by engine and motor 1061, the steering angle of steering unit 1063, the braking force of the brake unit, and the like. Depending on embodiments, processor 1030 and / or main processor 1050 may use radar sensor 100 to detect objects external to autonomous driving device 1000. For example, the objects may represent obstacles, targets, and the like of autonomous driving device 1000. According to an embodiment, the processor 1030 and / or the main processor 1050 may control corresponding actuators of the engine and motor 1061, the steering unit 1063, and / or the brake unit 1065 based on the detected object (e.g., to avoid an obstacle, move toward a target, etc.). For example, the corresponding actuators may move one or more supporting structures (e.g., wheels, rotors, etc.) of the autonomous driving device 1000 (e.g., to increase, decrease, or maintain speed, adjust the steering angle, etc.) under the control of the processor 1030 and / or the main processor 1050.

[0144] The communication interface 1070 may communicate with an external device via a wired communication method or a wireless communication method. For example, the communication interface 1070 may communicate via a wired communication method such as Ethernet or a wireless communication method such as WiFi or Bluetooth.

[0145] Conventional devices and methods for processing received radar signals (e.g., radar signals reflected from an object) involve a high-pass filter, a low-pass filter, and a variable-gain amplifier connected in cascade. The circuits used to implement these filters and amplifiers are initially designed separately (e.g., the relevant parameters and operating points of the components are set separately) and subsequently adjusted relative to each other (or redesigned). This complexity in circuit design leads to excessive difficulty and corresponding costs (e.g., manufacturing costs, delays, etc.) when designing the circuits. Furthermore, this complexity increases the difficulty and corresponding costs (e.g., manufacturing costs, delays, etc.) of adjusting the filtering frequency range of the circuits (e.g., circuits implementing the high-pass and low-pass filters) and / or the gain of the circuits (e.g., circuits implementing the variable-gain amplifier). Furthermore, the cascaded arrangement of the circuits results in excessive impedance and corresponding power consumption.

[0146] However, according to embodiments, improved devices and methods are provided for processing received radar signals (e.g., radar signals reflected from an object). For example, the improved devices and methods may involve the first filter circuit, the second filter circuit, and the offset cancellation circuit in a single feedback loop. This single feedback loop enables the circuits to be designed together (e.g., related parameters, operating points, etc. of the components to be set together) simultaneously (or concurrently), thereby reducing the difficulty and / or cost (e.g., manufacturing costs, delays, etc.) associated with designing and / or adjusting (or redesigning) the filtering frequency range of circuits (e.g., circuits implementing high-pass and low-pass filters) and / or the gain of circuits (e.g., circuits implementing variable-gain amplifiers). Furthermore, the single feedback loop reduces impedance and corresponding power consumption. Thus, the improved devices and methods overcome the shortcomings of conventional devices and methods, at least reducing difficulty, cost, and / or power consumption.

[0147] According to an embodiment, the operations described herein as being performed by the radar sensor 100, the processor 110, the signal generator 115, the signal distributor 125, the transmit amplifier 130, the receive amplifier 145, the receive frequency converter 150, the signal processor 160, the signal processor 200, the first filter circuit 210, the second filter circuit 220, the offset cancellation circuit 230, the first filter circuit 210a, the amplifier 215a, the second filter circuit 220a, the offset cancellation circuit 230a, the voltage-to-current converter 231a, the first filter circuit 210b, the amplifier 215b, the second filter circuit 220b, the offset cancellation circuit 230b, the voltage-to-current converter 231b, the computing device 900, the processor 910, the sensor 930, the network device 960, the autonomous driving device 1000, the sensor 1010, the processor 1030, the main processor 1050, the driver 1060, and / or the communication interface 1070 may be performed by a processing circuit system. As used in this disclosure, the term "processing circuitry" may refer to, for example, hardware including logic circuits; a hardware / software combination (such as a processor that executes software); or a combination thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), and the like.

[0148] The various operations of the methods described above may be performed by any suitable device capable of performing the operations (such as the processing circuitry discussed above). For example, as discussed above, the operations of the methods described above may be performed by various hardware and / or software implemented in some form of hardware (e.g., a processor, an ASIC, etc.).

[0149] The software may include an ordered listing of executable instructions for implementing logical functions and may be embodied in any "processor-readable medium" for use by or in conjunction with an instruction execution system, device, or apparatus (such as a single-core processor or a multi-core processor or a system including a processor).

[0150] The blocks or operations of the methods, algorithms, and functions described in conjunction with the embodiments disclosed herein may be embodied directly in hardware, in software modules executed by a processor, or in a combination of both. If implemented in software, the functions may be stored as one or more instructions or codes on or transmitted through a tangible, non-transitory computer-readable medium (e.g., storage device 920, memory 1020, RAM 1040, etc.). The software modules may reside in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CDROM, or any other form of storage medium known in the art.

[0151] Although the terms "first" or "second" can be used to explain various components, components are not limited to terms. These terms should only be used to distinguish one component from another. For example, the "first" component may be referred to as the "second" component, or similarly, the "second" component may be referred to as the "first" component. Expressions such as "at least one of..." modify the entire column of elements when following a column of elements, rather than modifying the individual elements in the column. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, all a, b, and c, or any variation of the foregoing examples. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0152] The terms "exterior" and / or "outside" refer to an area beyond the outermost boundaries of a physical object (e.g., radar sensor 100, computing device 900, autonomous driving device 1000, etc.). The term "interior" indicates that at least a portion of the area is partially contained within the boundaries formed by the object.

[0153] Any of the arrows and lines interconnecting the components in the drawings may represent a physical data path, a logical data path, or both. For example, a physical data path may include a data bus or a transmission line. A logical data path may represent communications or data messages between software programs, software modules, subroutines, or other software components or components. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or intervening elements may be present.

[0154] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A signal processor comprising: a first filter circuit configured to generate an output signal based on an input signal and a feedback signal, the first filter circuit comprising a first resistor and a first capacitor, wherein a filtering frequency range of the signal processor is set based on a first resistance of the first resistor and a first capacitance of the first capacitor; a second filter circuit connected to a feedback path of the first filter circuit, the second filter circuit configured to generate an intermediate signal based on the output signal; as well as The offset cancellation circuit is connected to the feedback path of the first filter circuit, and is configured to generate a feedback signal based on the intermediate signal.

2. The signal processor according to claim 1, wherein The gain of the signal processor is set based on the first resistor.

3. The signal processor according to claim 1, wherein The first capacitor is configured to receive an input signal, The first resistor is connected in series to the first capacitor, and The first filter circuit further includes: an amplifier connected to the first resistor via an input terminal of the amplifier; a second capacitor connected in parallel to the amplifier, the second capacitor being configured to receive a feedback signal and having a second capacitance; and a second resistor connected in parallel to the amplifier, the second resistor being configured to receive the feedback signal and having a second resistance.

4. The signal processor according to claim 3, wherein: The gain of the signal processor is set to be inversely proportional to the first resistance and directly proportional to the second resistance.

5. The signal processor according to claim 3, wherein The second filter circuit comprises: a third resistor configured to receive the output signal, the third resistor having a third resistance; and A third capacitor is connected to the third resistor, and has a third capacitance. The signal processor according to claim 5 , wherein: A product of the second resistance and the gain of the offset cancel circuit is set to be as large as a first reference multiple of the reference gain or more.

7. The signal processor according to claim 5, wherein The first value is set to approximately the inverse of a product of the first resistance and the first capacitance, and is obtained by dividing a product of the second resistance and the gain of the offset cancellation circuit by a product of the third resistance and the third capacitance.

8. The signal processor according to claim 5, wherein The reciprocal of the product of the second resistance and the second capacitance is set to be as large as a second reference multiple or greater of the reciprocal of the product of the first resistance and the first capacitance; and The reciprocal of the product of the first resistance and the first capacitance is set to be as large as a third reference multiple or more of the reciprocal of the product of the third resistance and the third capacitance.

9. The signal processor according to claim 5, wherein: The signal processor has a filtering frequency range from a first frequency to a second frequency, the first frequency corresponding to a reciprocal of a product of a first resistor and a first capacitor, and the second frequency corresponding to a reciprocal of a product of a second resistor and a second capacitor.

10. A signal processor comprising: a first filter circuit configured to generate an output signal based on an input signal and a feedback signal, a gain of the signal processor being set based on a first resistance of a first resistor in the first filter circuit; a second filter circuit connected to a feedback path of the first filter circuit, the second filter circuit configured to generate an intermediate signal based on the output signal; as well as The offset cancellation circuit is connected to the feedback path of the first filter circuit, and is configured to generate a feedback signal based on the intermediate signal.

11. The signal processor according to claim 10, wherein: A filtering frequency range of the signal processor is set based on a first resistor and a first capacitance of a first capacitor in a first filter circuit.

12. The signal processor according to claim 10, wherein The first filter circuit comprises: a pair of first capacitors, each configured to receive a pair of differential input signals, and each of the pair of first capacitors has a first capacitance; a pair of first resistors connected in series to the pair of first capacitors, respectively, the pair of first resistors including a first resistor, and each of the pair of first resistors having a first resistance; an amplifier connected to the pair of first resistors via input terminals of the amplifier, respectively; a pair of second capacitors, each connected in parallel to the amplifier, and each of the pair of second capacitors being configured to receive a feedback signal, each of the pair of second capacitors having a second capacitance; and A pair of second resistors are each connected in parallel to the amplifier, each of the pair of second resistors is configured to receive a feedback signal, and each of the pair of second resistors has a second resistance.

13. The signal processor according to claim 12, wherein: The gain of the signal processor is set to be inversely proportional to the first resistance and directly proportional to the second resistance.

14. The signal processor according to claim 12, wherein: The second filter circuit comprises: a pair of third resistors, each configured to receive a pair of differential output signals, each of the pair of third resistors having a third resistance; and A pair of third capacitors are connected in series between the pair of third resistors, and each of the pair of third capacitors has a third capacitance.

15. The signal processor according to claim 14, wherein A product of the second resistance and the gain of the offset cancel circuit is set to be as large as a first reference multiple of the reference gain or more.

16. The signal processor according to claim 14, wherein The first value is set to approximately the inverse of a product of the first resistance and the first capacitance, and is obtained by dividing a product of the second resistance and the gain of the offset cancellation circuit by a product of the third resistance and the third capacitance.

17. The signal processor according to claim 14, wherein The reciprocal of the product of the second resistance and the second capacitance is set to be as large as a second reference multiple or greater of the reciprocal of the product of the first resistance and the first capacitance; and The reciprocal of the product of the first resistance and the first capacitance is set to be as large as a third reference multiple or more of the reciprocal of the product of the third resistance and the third capacitance.

18. The signal processor according to claim 14, wherein The signal processor has a filtering frequency range from a first frequency to a second frequency, the first frequency corresponding to a reciprocal of a product of a first resistor and a first capacitor, and the second frequency corresponding to a reciprocal of a product of a second resistor and a second capacitor.

19. A radar sensor comprising: A processing circuit system is configured to: Generate a send signal, amplifying the transmission signal to obtain an amplified transmission signal, The amplified signal is transmitted through the transmitting antenna. receiving a reception signal via a reception antenna, the reception signal corresponding to a reflection signal generated by the transmission signal being reflected by an object, and generating an input signal by amplifying the received signal; as well as Signal processor, including: a first filter circuit configured to generate an output signal based on an input signal and a feedback signal, the first filter circuit including a resistor and a capacitor, a filtering frequency range of the signal processor being set based on the resistance of the resistor and the capacitance of the capacitor, a second filter circuit connected to a feedback path of the first filter circuit, the second filter circuit being configured to generate an intermediate signal based on the output signal, and The offset cancellation circuit is connected to the feedback path of the first filter circuit, and is configured to generate a feedback signal based on the intermediate signal.

20. The radar sensor according to claim 19, wherein: The gain of the signal processor is set based on the resistance.

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