Bootstrap switch
By alternately using two sets of capacitors as bootstrap capacitors, the problem of limited operating frequency of bootstrap switches is solved, continuous operation and frequency improvement of bootstrap switches are achieved, and the overall performance of the circuit is improved.
Patent Information
- Application Number
- CN202410170779.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-06
- Publication Date
- 2025-08-08
AI Technical Summary
The operating frequency of the bootstrap switch is limited by the charging time of the bootstrap capacitor, resulting in a degradation of the overall circuit performance.
Two sets of capacitors are used alternately as bootstrap capacitors, and the switch is turned on and off through the clock signal to realize alternating charging of capacitors and ensure continuous operation of bootstrap switches.
It improves the operating frequency of the bootstrap switch and improves the overall performance and accuracy of the circuit.
Smart Images
Figure CN120454698A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a bootstrapped switch, and more particularly to a bootstrapped switch that operates continuously. Background Art
[0002] Figure 1 The following is a circuit diagram of a conventional bootstrap switch. Bootstrap switch 100 includes switch 101, switch 102, switch 103, switch 104, switch 105, an N-channel Metal-Oxide-Semiconductor Field-Effect Transistor (NMOS) 106, and a bootstrap capacitor 107. The input terminal VI and output terminal VO of bootstrap switch 100 are coupled to the source and drain of NMOS transistor 106, respectively. The gate of NMOS transistor 106 is coupled to voltage source V3 via switch 105 and to one end of bootstrap capacitor 107 and one end of switch 101 via switch 104. The other end of switch 101 is coupled to voltage source V1. The other end of bootstrap capacitor 107 is coupled to voltage source V2 via switch 102, and to the source of NMOS transistor 106 and input terminal V1 of bootstrap switch 100 via switch 103. Voltage source V1 is the power supply voltage VDD, while voltage sources V2 and V3 are ground. The operation of bootstrap switch 100 is well known to those skilled in the art and will not be described in detail.
[0003] Since the bootstrap capacitor 107 needs to be charged, the operating frequency of the bootstrap switch 100 is limited, resulting in the bootstrap switch 100 degrading the performance of the entire circuit. Summary of the Invention
[0004] In view of the deficiencies of the prior art, one object of the present invention is to provide a bootstrap switch to improve the deficiencies of the prior art.
[0005] One embodiment of the present invention provides a bootstrap switch. The bootstrap switch has an input terminal and an output terminal, and includes: a first switch, a second switch, a third switch, a fourth switch, and a bootstrap capacitor switching circuit. The first switch has a first terminal, a second terminal, and a first control terminal, wherein the first terminal is coupled to the input terminal, and the second terminal is coupled to the output terminal. The second switch has a third terminal, a fourth terminal, and a second control terminal, wherein the third terminal is coupled to the input terminal, the fourth terminal is coupled to a first node, and the second control terminal is coupled to the first control terminal. The third switch has a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is coupled to a second node, the sixth terminal is coupled to the first control terminal, and the third control terminal receives a first clock. The fourth switch has a seventh terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is coupled to the first control terminal, the eighth terminal is coupled to a first reference voltage, and the fourth control terminal receives the first clock. The bootstrap capacitor switching circuit is coupled to the first node and the second node and includes a first capacitor and a second capacitor. When the first capacitor is charged, the second capacitor is coupled between the first node and the second node, and when the second capacitor is charged, the first capacitor is coupled between the first node and the second node.
[0006] Another embodiment of the present invention provides a bootstrap switch. The bootstrap switch has an input terminal and an output terminal, and includes: a first switch, a second switch, a third switch, a fourth switch, a first capacitor, a second capacitor, and a switch group. The first switch has a first terminal, a second terminal, and a first control terminal, wherein the first terminal is coupled to the input terminal, and the second terminal is coupled to the output terminal. The second switch has a third terminal, a fourth terminal, and a second control terminal, wherein the third terminal is coupled to the input terminal, the fourth terminal is coupled to a first node, and the second control terminal is coupled to the first control terminal. The third switch has a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is coupled to a second node, the sixth terminal is coupled to the first control terminal, and the third control terminal receives a first clock. The fourth switch has a seventh terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is coupled to the first control terminal, the eighth terminal is coupled to a first reference voltage, and the fourth control terminal receives the first clock. The switch group is coupled to the first capacitor and the second capacitor, and is used to couple the first capacitor or the second capacitor to the first node and the second node according to a second clock and a third clock.
[0007] The technical means embodied in the embodiments of the present invention can improve at least one of the shortcomings of the prior art. Therefore, the present invention can increase the operating frequency of the bootstrap switch compared to the prior art.
[0008] The features, implementation and effects of the present invention are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Figure 1 A circuit diagram of an existing bootstrap switch;
[0010] Figure 2 is a circuit diagram of one embodiment of a bootstrap switch of the present invention;
[0011] Figure 3 is a circuit diagram of one embodiment of a bootstrap capacitor switching circuit of the present invention;
[0012] Figure 4 is a waveform diagram of one embodiment of a clock of the present invention;
[0013] Figure 5 is a circuit diagram of another embodiment of a bootstrap switch of the present invention;
[0014] Figure 6 is a circuit diagram of another embodiment of the bootstrap switch of the present invention; and
[0015] Figure 7 FIG. 4 is a circuit diagram of another embodiment of the bootstrap switch of the present invention. DETAILED DESCRIPTION
[0016] The technical terms used in the following descriptions refer to the customary terms in the technical field. If this specification provides explanations or definitions for some terms, the interpretation of those terms shall be based on the explanations or definitions in this specification.
[0017] The present invention includes a bootstrap switch. Since some components of the bootstrap switch may be known components, details of known components will be omitted in the following description without affecting the full disclosure and feasibility of the present invention.
[0018] In the following description, each transistor has a first terminal, a second terminal, and a control terminal. When the transistor is used as a switch, the first terminal and the second terminal of the transistor are the two terminals of the switch, and the control terminal controls whether the switch is conductive (the transistor is on) or non-conductive (the transistor is off). For a metal-oxide-semiconductor field-effect transistor (MOSFET), the first terminal can be one of the source and drain, the second terminal is the other of the source and drain, and the control terminal is the gate. For a bipolar junction transistor (BJT), the first terminal can be one of the collector and emitter, the second terminal is the other of the collector and emitter, and the control terminal is the base.
[0019] See also Figure 2 , Figure 2 FIG2 is a circuit diagram of an embodiment of a bootstrap switch according to the present invention. Bootstrap switch 200 includes a bootstrap capacitor switching circuit 205, switches 210, 220, 230, 240, 250, and 260. The input and output of bootstrap switch 200 are input terminal VI and output terminal VO, respectively.
[0020] The switch 210 is implemented by an NMOS transistor M1. One terminal (source) of the switch 210 is coupled or electrically connected to the input terminal VI; the other terminal (drain) of the switch 210 is coupled or electrically connected to the output terminal VO; and the control terminal of the switch 210 is the gate of the NMOS transistor M1.
[0021] The switch 220 is implemented by an NMOS transistor M2. One terminal (source) of the switch 220 is coupled or electrically connected to the input terminal VI; the other terminal (drain) of the switch 220 is coupled or electrically connected to the node N1; and the control terminal (gate) of the switch 220 is coupled or electrically connected to the control terminal of the switch 210.
[0022] The switch 230 is implemented by an NMOS transistor M3. One terminal (source) of the switch 230 is coupled or electrically connected to a reference voltage GND (e.g., ground level); the other terminal (drain) of the switch 230 is coupled or electrically connected to the node N1; and the control terminal (gate) of the switch 230 receives a clock Φ1b.
[0023] Switch 240 is implemented using a P-channel Metal-Oxide-Semiconductor Field-Effect Transistor (PMOS) M4. One terminal (source) of switch 240 is coupled to or electrically connected to a reference voltage VDD (e.g., a power supply voltage); the other terminal (drain) of switch 240 is coupled to or electrically connected to node N2; and the control terminal (gate) of switch 240 is coupled to or electrically connected to the control terminal of switch 210.
[0024] The switch 250 is implemented by a PMOS transistor M5. One terminal (source) of the switch 250 is coupled or electrically connected to the node N2. The other terminal (drain) of the switch 250 is coupled or electrically connected to the control terminal of the switch 210. The control terminal (gate) of the switch 250 receives the clock Φ1b.
[0025] The switch 260 is implemented by an NMOS transistor M6. One terminal (source) of the switch 260 is coupled or electrically connected to the control terminal of the switch 210. The other terminal (drain) of the switch 260 is coupled or electrically connected to the reference voltage GND. The control terminal (gate) of the switch 260 receives the clock Φ1b.
[0026] Bootstrap switch 200 operates according to clock Φ1b. More specifically, when clock Φ1b is at a first level (e.g., a high level), switches 230, 240, and 260 are conductive, and switches 210, 220, and 250 are non-conductive. When clock Φ1b is at a second level (e.g., a low level), switches 230, 240, and 260 are non-conductive, and switches 210, 220, and 250 are conductive.
[0027] See also Figure 3 , Figure 3 This is a circuit diagram of one embodiment of the bootstrap capacitor switching circuit 205 of the present invention. The bootstrap capacitor switching circuit 205 includes a capacitor Cb1, a capacitor Cb2, and a switch group 300. Capacitor Cb1 has two terminals connected to nodes N3 and N4, respectively. Capacitor Cb2 has two terminals connected to nodes N5 and N6, respectively. Switch group 300 includes switches SW1, SW2, SW3, SW4, SW5, SW6, SW7, and SW8. Switch group 300 couples or electrically connects capacitor Cb1 or capacitor Cb2 to nodes N1 and N2 based on clock Φ2 and / or clock Φ2b.
[0028] One end of the switch SW1 is coupled to or electrically connected to the node N3 ; the other end of the switch SW1 is coupled to or electrically connected to the voltage VH.
[0029] One end of the switch SW2 is coupled to or electrically connected to the node N4 ; the other end of the switch SW2 is coupled to or electrically connected to the voltage VL.
[0030] One end of the switch SW3 is coupled to or electrically connected to the node N2 ; the other end of the switch SW3 is coupled to or electrically connected to the node N3 .
[0031] One end of the switch SW4 is coupled or electrically connected to the node N1 ; the other end of the switch SW4 is coupled or electrically connected to the node N4 .
[0032] One end of the switch SW5 is coupled to or electrically connected to the node N5 ; the other end of the switch SW5 is coupled to or electrically connected to the voltage VH.
[0033] One end of the switch SW6 is coupled to or electrically connected to the node N6 ; the other end of the switch SW6 is coupled to or electrically connected to the voltage VL.
[0034] One end of the switch SW7 is coupled or electrically connected to the node N2 ; the other end of the switch SW7 is coupled or electrically connected to the node N5 .
[0035] One end of the switch SW8 is coupled or electrically connected to the node N1 ; the other end of the switch SW8 is coupled or electrically connected to the node N6 .
[0036] Switches SW1 through SW8 operate based on clock Φ2 and / or clock Φ2b. More specifically, when clock Φ2 is at a first level, switches SW1, SW2, SW7, and SW8 are conductive. When clock Φ2 is at a second level, switches SW1, SW2, SW7, and SW8 are non-conductive. When clock Φ2b is at a first level, switches SW3, SW4, SW5, and SW6 are conductive. When clock Φ2b is at a second level, switches SW3, SW4, SW5, and SW6 are non-conductive.
[0037] See also Figure 4 , Figure 4 This is a waveform diagram of one embodiment of the clock of the present invention. Figure 4 In the embodiment, clock Φ1 and clock Φ1b are inverted signals. More specifically, when clock Φ1 is at the first level (the second level), clock Φ1b is at the second level (the first level). When clock Φ1 is at the first level, bootstrap switch 200 is conductive (i.e., the voltage at output terminal VO is substantially equal to the voltage at input terminal VI). When clock Φ1 is at the second level, bootstrap switch 200 is non-conductive.
[0038] Clock Φ2 and clock Φ2b are not simultaneously at the first level. In other words, capacitors Cb1 and Cb2 are not simultaneously electrically connected to nodes N1 and N2. More specifically, nodes N3 and N5 are not simultaneously electrically connected to node N2, and nodes N4 and N6 are not simultaneously electrically connected to node N1. When two nodes are electrically connected, they are essentially the same node; that is, there is no component between them.
[0039] The periods of the clock Φ2 and the clock Φ2b are substantially equal, and the periods of the clock Φ2 and the clock Φ2b are twice the periods of the clock Φ1 and the clock Φ1b.
[0040] Please also see Figure 3 and Figure 4 During phase Ph1 (clock Φ1, clock Φ1b, clock Φ2, and clock Φ2b are at the first level, the second level, the second level, and the first level, respectively), capacitor Cb1 is electrically connected to node N1 and node N2, respectively (i.e., it is functioning as a bootstrap capacitor), while capacitor Cb2 is electrically connected to voltage VH and voltage VL, respectively (i.e., it is being charged). During phase Ph2 (clock Φ1, clock Φ1b, clock Φ2, and clock Φ2b are at the first level, the second level, the first level, and the second level, respectively), capacitor Cb1 is electrically connected to voltage VH and voltage VL, respectively (i.e., it is being charged), while capacitor Cb2 is electrically connected to node N1 and node N2, respectively (i.e., it is functioning as a bootstrap capacitor).
[0041] Continuing from the previous paragraph, capacitor Cb1 and capacitor Cb2 alternately serve as the bootstrap capacitors of bootstrap switch 200, namely, they are alternately coupled between node N1 and node N2. More specifically, during one cycle of clock Φ2 or clock Φ2b (e.g., between time t1 and time t5), the bootstrap capacitors of bootstrap switch 200 are sequentially capacitor Cb1 (e.g., between time t2 and time t3) and capacitor Cb2 (e.g., between time t4 and time t5). Therefore, bootstrap switch 200 can operate continuously without waiting for the bootstrap capacitors to charge, significantly increasing the operating frequency of bootstrap switch 200.
[0042] like Figure 4 As shown, the bootstrap switch 200 can be reset during the phase Phs (when the clock Φ1, the clock Φ1b, the clock Φ2, and the clock Φ2b are respectively at the second level, the first level, the second level, and the first level, or respectively at the second level, the first level, the first level, and the second level) to improve the accuracy of the bootstrap switch 200. Resetting the bootstrap switch 200 is well known to those skilled in the art and will not be described in detail herein.
[0043] In some embodiments, the length of the phase Phs may approach zero.
[0044] Voltage VH is not equal to voltage VL. Voltage VH may be equal to or different from reference voltage VDD. Voltage VL may be equal to or different from reference voltage GND. In some embodiments, voltage VH is equal to reference voltage VDD, and voltage VL is equal to reference voltage GND to simplify circuit design.
[0045] See also Figure 5 , Figure 5 This is a circuit diagram of another embodiment of the bootstrap switch of the present invention. The bootstrap switch 500 is similar to the bootstrap switch 200. The difference is that Figure 5 In the embodiment, the control terminal of the switch 240 is not coupled to or electrically connected to the control terminal of the switch 210, but receives the clock Φ1.
[0046] See also Figure 6 , Figure 6 2 is a circuit diagram of another embodiment of the bootstrap switch of the present invention. The bootstrap switch 600 is similar to the bootstrap switch 200 , except that the bootstrap switch 600 further includes a switch 270 , a switch 280 , a switch 290 , and a switch 295 .
[0047] Switch 270 is implemented by an NMOS transistor M7. One terminal (source) of switch 270 is coupled or electrically connected to the control terminal of switch 210. The other terminal (drain) of switch 270 is coupled or electrically connected to the source of NMOS transistor M6. The control terminal (gate) of switch 270 is coupled or electrically connected to reference voltage VDD.
[0048] The switch 280 is implemented by a PMOS transistor M8. One terminal (source) of the switch 280 is coupled or electrically connected to the reference voltage VDD. The other terminal (drain) of the switch 280 is coupled or electrically connected to the control terminal of the switch 250. The control terminal (gate) of the switch 280 receives the clock Φ1.
[0049] The switch 290 is implemented by an NMOS transistor M9. One terminal (source) of the switch 290 is coupled or electrically connected to the node N1. The other terminal (drain) of the switch 290 is coupled or electrically connected to the control terminal of the switch 250. The control terminal (gate) of the switch 290 receives the clock Φ1.
[0050] Switch 295 is implemented by an NMOS transistor M10. One terminal (source) of switch 295 is coupled or electrically connected to the control terminal of switch 250; the other terminal (drain) of switch 295 is coupled or electrically connected to node N1; and the control terminal (gate) of switch 295 is coupled or electrically connected to the control terminal of switch 210.
[0051] The switches 270 , 280 , 290 and 295 serve as protection elements for the bootstrap switch 600 . The operating principles of these protection elements are well known to those skilled in the art and will not be further described.
[0052] See also Figure 7 , Figure 7 This is a circuit diagram of another embodiment of the bootstrap switch of the present invention. The bootstrap switch 700 is similar to the bootstrap switch 600, except that Figure 7 In the embodiment, the control terminal of the switch 240 is not coupled to or electrically connected to the control terminal of the switch 210, but receives the clock Φ1.
[0053] In some embodiments, switches 230 and 240 in bootstrap switches 200 , 500 , 600 , and 700 may be omitted because capacitor Cb1 is coupled to voltage VH and voltage VL through switches SW1 and SW2 , respectively, and capacitor Cb2 is coupled to voltage VH and voltage VL through switches SW5 and SW6 , respectively.
[0054] In other embodiments, the PMOS transistor and NMOS transistor in the aforementioned embodiments may be replaced by NMOS transistors and PMOS transistors, respectively. A person skilled in the art would know how to adjust the clock and reference voltage accordingly to implement the aforementioned implementation.
[0055] Please note that in the above figures, the shapes, sizes and proportions of the components are merely illustrative and are provided to help those skilled in the art understand the present invention, and are not intended to limit the present invention.
[0056] Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. Those skilled in the art may modify the technical features of the present invention based on the explicit or implicit content of the present invention. All such modifications may fall within the scope of the patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the scope of the patent application defined in this specification.
[0057]
Explanation of symbols
[0058] 100,200,500,600,700: Bootstrap switch
[0059] 101,102,103,104,105,210,220,230,240,250,260,SW1,SW2,SW3,SW4,SW 5,SW6,SW7,SW8,270,280,290,295: switch
[0060] 106, M1, M2, M3, M6, M10, M7, M9: NMOS transistors
[0061] 107: Bootstrap capacitor
[0062] V1, V2, V3: voltage source
[0063] VI: Input
[0064] VO: output terminal
[0065] 205: Bootstrap capacitor switching circuit
[0066] GND, VDD: reference voltage
[0067] M4, M5, M8: PMOS transistors
[0068] N1, N2, N3, N4, N5, N6: nodes
[0069] Φ1b,Φ2,Φ2b,Φ1: clock
[0070] 300: switch group
[0071] Cb1, Cb2: capacitors
[0072] VH, VL: voltage
[0073] Ph1, Ph2, Phs: Phase
[0074] t1, t2, t3, t4, t5: time points.
Claims
1. A bootstrap switch having an input terminal and an output terminal, comprising: A first switch has a first terminal, a second terminal and a first control terminal, wherein The first end is coupled to the input end, and the second end is coupled to the output end; a second switch having a third terminal, a fourth terminal, and a second control terminal, wherein the third terminal is coupled to the input terminal, the fourth terminal is coupled to a first node, and the second control terminal is coupled to the first control terminal; a third switch having a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is coupled to a second node, the sixth terminal is coupled to the first control terminal, and the third control terminal receives a first clock; a fourth switch having a seventh terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is coupled to the first control terminal, the eighth terminal is coupled to a first reference voltage, and the fourth control terminal receives the first clock; and a bootstrap capacitor switching circuit coupled to the first node and the second node, comprising a first capacitor and a second capacitor; When the first capacitor is charged, the second capacitor is coupled between the first node and the second node, and when the second capacitor is charged, the first capacitor is coupled between the first node and the second node.
2. The bootstrap switch according to claim 1, wherein: When the first clock is at a first level, the bootstrap switch is not turned on, and when the first clock is at a second level, the bootstrap switch is turned on.
3. The bootstrap switch according to claim 2, wherein: The first capacitor and the second capacitor are alternately coupled between the first node and the second node.
4. The bootstrap switch of claim 1 , further comprising: a fifth switch having a ninth terminal, a tenth terminal, and a fifth control terminal, wherein: The ninth terminal is coupled to the first control terminal, the tenth terminal is coupled to the seventh terminal, and the fifth control terminal is coupled to a second reference voltage; a sixth switch having an eleventh terminal, a twelfth terminal, and a sixth control terminal, wherein the eleventh terminal is coupled to the second reference voltage, the twelfth terminal is coupled to the third control terminal, and the sixth control terminal receives a second clock; a seventh switch having a thirteenth terminal, a fourteenth terminal, and a seventh control terminal, wherein the thirteenth terminal is coupled to the first node, the fourteenth terminal is coupled to the third control terminal, and the seventh control terminal receives the second clock; and An eighth switch has a fifteenth terminal, a sixteenth terminal, and an eighth control terminal, wherein the fifteenth terminal is coupled to the third control terminal, the sixteenth terminal is coupled to the first node, and the eighth control terminal is coupled to the first control terminal.
5. The bootstrap switch according to claim 1, wherein: The two ends of the first capacitor are respectively a third node and a fourth node, the two ends of the second capacitor are respectively a fifth node and a sixth node, and the bootstrap capacitor switching circuit further includes: a fifth switch coupled between the third node and a first voltage; a sixth switch coupled between the fourth node and a second voltage; a seventh switch coupled between the third node and the second node; an eighth switch coupled between the fourth node and the first node; a ninth switch coupled between the fifth node and the first voltage; a tenth switch coupled between the sixth node and the second voltage; an eleventh switch coupled between the fifth node and the second node; and A twelfth switch is coupled between the sixth node and the first node.
6. The bootstrap switch according to claim 5, wherein: When a second clock is at a first level, the fifth switch, the sixth switch, the eleventh switch, and the twelfth switch are turned on; when the second clock is at a second level, the fifth switch, the sixth switch, the eleventh switch, and the twelfth switch are turned off; when a third clock is at the first level, the seventh switch, the eighth switch, the ninth switch, and the tenth switch are turned on; and when the third clock is at the second level, the seventh switch, the eighth switch, the ninth switch, and the tenth switch are turned off; the second clock and the third clock are not at the first level at the same time.
7. The bootstrap switch of claim 5 , further comprising: a thirteenth switch having a ninth terminal, a tenth terminal, and a fifth control terminal, wherein: The ninth terminal is coupled to the first reference voltage, the tenth terminal is coupled to the first node, and the fifth control terminal receives the first clock; and A fourteenth switch has an eleventh terminal, a twelfth terminal and a sixth control terminal, wherein the eleventh terminal is coupled to a second reference voltage, the twelfth terminal is coupled to the second node, and the sixth control terminal is coupled to the first control terminal or receives a second clock.
8. The bootstrap switch according to claim 7, wherein: The first voltage is not equal to the second voltage, the first voltage is equal to the second reference voltage, and the second voltage is equal to the first reference voltage.
9. A bootstrap switch having an input terminal and an output terminal, comprising: A first switch has a first terminal, a second terminal and a first control terminal, wherein The first end is coupled to the input end, and the second end is coupled to the output end; a second switch having a third terminal, a fourth terminal, and a second control terminal, wherein the third terminal is coupled to the input terminal, the fourth terminal is coupled to a first node, and the second control terminal is coupled to the first control terminal; a third switch having a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is coupled to a second node, the sixth terminal is coupled to the first control terminal, and the third control terminal receives a first clock; a fourth switch having a seventh terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is coupled to the first control terminal, the eighth terminal is coupled to a first reference voltage, and the fourth control terminal receives the first clock; a first capacitor; a second capacitor; and A switch group is coupled to the first capacitor and the second capacitor, and is used to couple the first capacitor or the second capacitor to the first node and the second node according to a second clock and a third clock.
10. The bootstrap switch according to claim 9, wherein The first capacitor and the second capacitor are not electrically connected to the first node and the second node at the same time.