Phase-locked loop circuit, chip and electronic equipment

Abstract

The invention discloses a phase-locked loop circuit, a chip and electronic equipment. The phase-locked loop circuit comprises a phase discrimination unit used for receiving a reference signal and a feedback signal and outputting an error signal according to the phase difference between the reference signal and the feedback signal; the loop filtering unit is used for receiving the error signal, filtering the error signal and outputting a control signal; a signal generating unit and a signal adjusting unit, the signal generating unit is used for generating an input clock signal with a preset frequency, and the signal adjusting unit is used for receiving the control signal and the input clock signal, and performing frequency division or frequency multiplication processing on the input clock signal according to the control signal to generate an output clock signal; and the feedback unit is used for receiving the output clock signal and performing frequency division or frequency multiplication processing on the output clock signal to generate a feedback signal. According to the invention, a frequency division or frequency multiplication technology is adopted to replace a crystal-based voltage-controlled oscillator, so that the problems of high cost of a crystal device, crystal aging and high complexity of a control algorithm in a phase-locked loop circuit are solved.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a phase-locked loop circuit, chip, and electronic equipment. Background Art

[0002] In traditional phase-locked loops (PLLs), the voltage-controlled oscillator (VCO) is a key component for controlling the output frequency. It typically uses a temperature-compensated crystal oscillator (TCO) or an oven-controlled crystal oscillator (OCC). However, these crystal-based VCOs present several challenges. First, the high cost of the crystal itself limits their application in cost-sensitive scenarios. Second, the crystal ages over time, and this aging becomes increasingly pronounced, affecting frequency stability. Furthermore, controlling these VCOs requires precise digital-to-analog conversion, placing higher demands on linear parameters and corresponding algorithms, increasing the complexity of system design. Summary of the Invention

[0003] In view of the above problems, the present application provides a phase-locked loop circuit, chip and electronic device to solve the above technical problems.

[0004] In a first aspect, the present application provides a phase-locked loop circuit, comprising:

[0005] a phase detector unit, configured to receive a reference signal and a feedback signal, and output an error signal according to a phase difference between the reference signal and the feedback signal;

[0006] a loop filtering unit, configured to receive the error signal, filter the error signal, and output a control signal;

[0007] a signal generating unit and a signal conditioning unit, wherein the signal generating unit is used to generate an input clock signal of a preset frequency, and the signal conditioning unit is used to receive the control signal and the input clock signal, and perform frequency division or frequency multiplication processing on the input clock signal according to the control signal to generate an output clock signal;

[0008] The feedback unit is configured to receive the output clock signal and perform frequency division or frequency multiplication processing on the output clock signal to generate the feedback signal.

[0009] In a second aspect, the present application also provides a chip comprising the phase-locked loop circuit of the first aspect.

[0010] In a third aspect, the present application also provides an electronic device comprising the chip according to the second aspect.

[0011] The phase-locked loop circuit, chip and electronic device provided by the present application, the phase-locked loop circuit uses a signal generating unit to generate an input clock signal of a preset frequency, and the signal adjustment unit divides or multiplies the input clock signal to generate an output clock signal, thereby realizing the use of dynamic frequency division or multiplication technology to replace the crystal-based voltage-controlled oscillator in the traditional phase-locked loop circuit, and using the signal adjustment unit to flexibly adjust the frequency of the input clock signal, thereby solving the problems of high cost of crystal devices in the phase-locked loop circuit, decreased stability due to crystal aging, and high complexity of the digital-to-analog conversion control algorithm, significantly reducing the cost of the phase-locked loop system and improving the accuracy of the output signal of the phase-locked loop circuit.

[0012] These and other aspects of the present application will become more readily apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A schematic diagram of a phase-locked loop circuit provided in an embodiment of the present application is shown.

[0015] Figure 2 Another schematic diagram of a phase-locked loop circuit provided in an embodiment of the present application is shown.

[0016] Figure 3 Another schematic diagram of a phase-locked loop circuit provided in an embodiment of the present application is shown.

[0017] Figure 4 Another schematic diagram of a phase-locked loop circuit provided in an embodiment of the present application is shown.

[0018] Figure 5 Another schematic diagram of a phase-locked loop circuit provided in an embodiment of the present application is shown.

[0019] Figure 6 Another schematic diagram of a phase-locked loop circuit provided in an embodiment of the present application is shown.

[0020] Figure 7 Another schematic diagram of a phase-locked loop circuit provided in an embodiment of the present application is shown.

[0021] Figure 8 A schematic diagram of a chip provided in an embodiment of the present application is shown.

[0022] Figure 9A schematic diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0024] In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second, etc., are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0025] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0026] The embodiment of the present application provides a phase-locked loop circuit, Figure 1 Schematic diagram of a phase-locked loop circuit provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the phase-locked loop circuit includes a phase detection unit, a loop filtering unit, a signal generating unit, a signal regulating unit and a feedback unit.

[0027] The phase detection unit is used to receive a reference signal and a feedback signal, and output an error signal according to the phase difference between the reference signal and the feedback signal. Optionally, the phase detection unit compares the phase difference between the reference signal and the feedback signal, thereby generating an error signal that is linearly related to the phase difference. The error signal is used to indicate the frequency offset that needs to be adjusted by the phase-locked loop circuit, thereby ensuring that the frequency clock of the output signal of the phase-locked loop circuit is synchronized with the reference signal.

[0028] It can be understood that the phase-locked loop circuit provided in the embodiment of the present application does not limit the specific structure of the phase detection unit. For example, the phase detection unit can be set to a phase detector such as an analog phase detector, a digital phase detector, a charge pump phase detector, a delay locked loop (DLL) phase detector, etc. to compare the phases of the reference signal and the feedback signal and output an error signal.

[0029] The loop filter unit is used to receive the error signal, filter the error signal and output a control signal. Optionally, the loop filter unit suppresses the high-frequency noise components in the error signal and only retains the low-frequency error signal related to the frequency deviation, thereby generating a control signal in the form of a smooth DC voltage or current.

[0030] It can be understood that the phase-locked loop circuit provided in the embodiment of the present application does not limit the specific structure of the loop filtering unit. For example, the loop filtering unit can be set to a filter such as a passive filter, an active filter, a composite filter including a bandpass filter and an integrator, etc. to implement filtering processing of the error signal to output a control signal.

[0031] The signal generation unit is configured to generate an input clock signal of a preset frequency. Optionally, the signal generation unit generates an input clock signal with a fixed frequency characteristic based on the requirements of the phase-locked loop system or external configuration. This input clock signal serves as the reference clock source for the phase-locked loop. For example, the input clock signal of the preset frequency can be determined by an external oscillator, a clock network, or any other clock source, ensuring that its frequency stability meets the requirements of the phase-locked loop system.

[0032] The signal conditioning unit is configured to receive a control signal and an input clock signal and, based on the control signal, divide or multiply the input clock signal to generate an output clock signal. Optionally, the signal conditioning unit dynamically adjusts the division or multiplication factor using the control signal, thereby programmably adjusting the frequency of the input clock signal. For example, when the control signal indicates a need to increase the output frequency, the signal conditioning unit increases the frequency of the generated output clock signal by reducing the division factor or increasing the multiplication factor; conversely, the signal conditioning unit decreases the frequency of the output clock signal by increasing the division factor or decreasing the multiplication factor.

[0033] The feedback unit is used to receive the output clock signal, divide or multiply the output clock signal to generate a feedback signal. Optionally, the feedback unit converts the frequency of the output clock signal to a target value that matches the reference signal frequency by adjusting the frequency division or multiplication coefficient. The target value is the reference signal, thereby forming a closed-loop control path for the phase-locked loop circuit. For example, if the frequency of the reference signal is 1MHz and the frequency of the output clock signal is 10MHz, the feedback unit generates a feedback signal with a frequency of 1MHz by setting the frequency division coefficient to 100, so that it is aligned with the frequency of the reference signal. The setting of the frequency division coefficient or the frequency multiplication coefficient can be set according to the requirements of the phase-locked loop system or dynamically adjusted to ensure that the feedback signal is always consistent with the frequency of the reference signal.

[0034] It can be understood that in the embodiment of the present application, the signal conditioning unit is configured to perform frequency division or frequency multiplication processing on the input clock signal. Similarly, the feedback unit is also configured to perform frequency division or frequency multiplication processing on the output clock signal. The frequency division or frequency multiplication selection of the signal conditioning unit and the feedback unit are based on the specific application scenario requirements of the phase-locked loop circuit, and the frequency division or frequency multiplication selection of the signal conditioning unit is intended to directly control the final frequency of the output clock signal, and its configuration is determined by the output frequency requirements of the phase-locked loop circuit, while the frequency division or frequency multiplication selection of the feedback unit is intended to convert the output clock signal into a feedback signal that matches the reference signal frequency, and its configuration is determined by the ratio of the reference signal frequency to the output clock frequency. The configurations of the two are independent of each other and there is no direct correlation.

[0035] The phase-locked loop circuit provided in the embodiment of the present application uses a signal generating unit to generate an input clock signal of a preset frequency, and a signal regulating unit divides or multiplies the input clock signal to generate an output clock signal, thereby realizing the use of dynamic frequency division or multiplication technology to replace the crystal-based voltage-controlled oscillator in the traditional phase-locked loop circuit, and using the signal regulating unit to flexibly adjust the frequency of the input clock signal, thereby solving the problems of high cost of crystal devices in the phase-locked loop circuit, decreased stability due to crystal aging, and high complexity of the digital-to-analog conversion control algorithm, significantly reducing the cost of the phase-locked loop system and improving the accuracy of the output signal of the phase-locked loop circuit.

[0036] In some embodiments, Figure 2 Another schematic diagram of a phase-locked loop circuit provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, in the phase-locked loop circuit provided in the embodiment of the present application, the signal generating unit includes:

[0037] A Synchronous Ethernet (SyncE) clock source is used to generate an input clock signal and, based on this input clock signal, output an Ethernet link stream containing the input clock signal information. Optionally, the input clock signal generated by the SyncE clock source is a high-precision clock signal. By encoding the high-precision input clock signal into the Ethernet link stream, the generated Ethernet link stream implicitly contains the clock phase information of the sender (i.e., the SyncE clock source).

[0038] A physical layer (PHY) chip is connected to a synchronous Ethernet clock source via an Ethernet link, and is used to receive the Ethernet link data stream, recover the input clock signal from the Ethernet link data stream, and output the input clock signal to the signal conditioning unit. Optionally, the physical layer chip parses the Ethernet link data stream, extracts a local recovered clock that is strictly synchronized with the synchronous Ethernet clock source, and transmits it as a stable input clock signal to the signal conditioning unit to drive the phase-locked loop circuit output.

[0039] The phase-locked loop circuit provided in the embodiment of the present application uses a synchronous Ethernet clock source, a physical layer chip, and a signal conditioning unit to replace the voltage-controlled oscillator in the traditional phase-locked loop circuit. The synchronous Ethernet clock source is an additional product of the network system and can support multiple devices simultaneously, so it does not bring additional cost overhead to the phase-locked loop circuit. Therefore, the cost of the phase-locked loop circuit based on this synchronous Ethernet clock source is low. On the other hand, the use of a synchronous Ethernet clock source, a physical layer chip, and a signal conditioning unit to replace the voltage-controlled oscillator in the traditional phase-locked loop circuit does not require a crystal, so there is no need to design the phase-locked loop circuit and there is no need to consider the problem of crystal aging. The clock accuracy of the synchronous Ethernet clock source far exceeds that of ordinary high-precision crystals, further improving the output accuracy of the phase-locked loop circuit. In addition, using a synchronous Ethernet clock source, a physical layer chip, and a signal conditioning unit to replace the voltage-controlled oscillator in the traditional phase-locked loop circuit only requires dynamically adjusting the frequency division or multiplication coefficient of the signal conditioning unit to divide or multiply the input clock signal. Compared to the complex algorithm requirements required by the voltage-controlled oscillator, the embodiment of the present application greatly simplifies the algorithm requirements of the phase-locked loop circuit and reduces the complexity of the phase-locked loop system design.

[0040] As an implementation method, in the phase-locked loop circuit provided in the embodiment of the present application, the synchronous Ethernet clock source and the physical layer chip are directly connected to solve the problem of frequency error accumulation of the input clock signal generated by the synchronous Ethernet clock source.

[0041] In some embodiments, Figure 3 Another schematic diagram of a phase-locked loop circuit provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, in the phase-locked loop circuit provided in the embodiment of the present application, the signal generating unit includes:

[0042] An oscillator is configured to generate an input clock signal having a preset frequency and output the input clock signal to the signal conditioning unit. Optionally, the input clock signal generated by the oscillator has a fixed frequency, which is much more stable than a dynamic frequency modulation scheme of a voltage-controlled oscillator.

[0043] The embodiment of the present application uses an uncontrolled oscillator and a signal conditioning unit that can generate a fixed frequency to replace the voltage-controlled oscillator in the traditional phase-locked loop circuit. There is no need to design a complex voltage-controlled oscillator circuit and a tuning network corresponding to the voltage-controlled oscillator circuit, which simplifies the hardware structure of the phase-locked loop circuit. In addition, the frequency of the oscillator does not depend on the control signal output by the loop filter unit. The control signal only needs to control the frequency division or multiplication coefficient of the signal conditioning unit, thereby avoiding the frequency jitter problem caused by the control signal noise. In addition, the phase-locked loop circuit based on the oscillator only needs to divide or multiply the input clock signal by dynamically adjusting the frequency division or multiplication coefficient of the signal conditioning unit. Compared with the complex algorithm requirements required by the voltage-controlled oscillator, the embodiment of the present application greatly simplifies the algorithm requirements of the phase-locked loop circuit and reduces the complexity of the phase-locked loop system design.

[0044] In some embodiments, Figure 4 and Figure 5 Two more schematic diagrams of the phase-locked loop circuit provided in the embodiments of the present application are shown, such as Figure 4 and Figure 5 As shown, in the phase-locked loop circuit provided in the embodiment of the present application, the signal conditioning unit includes:

[0045] The first frequency divider is used to receive a control signal and an input clock signal, and adjust a frequency division coefficient according to the control signal to perform frequency division processing on the input clock signal according to the frequency division coefficient to generate an output clock signal.

[0046] or a first frequency multiplier, configured to receive a control signal and an input clock signal, and adjust a frequency multiplication factor according to the control signal to multiply the input clock signal according to the frequency multiplication factor to generate an output clock signal.

[0047] Optionally, in an embodiment of the present application, when the phase-locked loop circuit needs to perform frequency division processing on the input clock signal, the frequency division processing is achieved by setting a controllable frequency divider, i.e., a first frequency divider. When the phase-locked loop circuit needs to perform frequency multiplication processing on the input clock signal, the frequency multiplication processing is achieved by setting a controllable frequency multiplier, i.e., a first frequency multiplier. The control signal output by the loop filter unit is used to control the frequency division coefficient of the first frequency divider or the frequency multiplication coefficient of the first frequency multiplier. In this way, the control signal in the traditional phase-locked loop circuit becomes a control signal for controlling the frequency division or frequency multiplication coefficient, thereby simplifying the algorithm requirements of the phase-locked loop circuit.

[0048] As an implementation method, when the phase-locked loop circuit provided in the embodiment of the present application is applied to an FPGA (Field-Programmable Gate Array, programmable logic device), the function of the above-mentioned first frequency divider or first frequency multiplier can be implemented through FPGA programming. It should be clear that the purpose of the embodiment of the present application is to replace the voltage-controlled oscillator in the traditional phase-locked loop circuit with a signal generating unit and a signal conditioning unit, and the implementation method of the controllable frequency divider or frequency multiplier is a known technology in the circuit field. Therefore, the embodiment of the present application does not limit the implementation method of the frequency division coefficient control function of the first frequency divider or the first frequency multiplier. It is only used here to illustrate an implementation method of the first frequency divider or the first frequency multiplier when applied to an FPGA.

[0049] In some embodiments, the embodiments of the present application provide a phase-locked loop circuit, in which, when the phase-locked loop circuit needs to perform frequency division processing on the input clock signal, the frequency division coefficient of the first frequency divider is configured to be linearly related to the control signal, and when the phase-locked loop circuit needs to perform frequency division processing on the input clock signal, the frequency multiplication coefficient of the first frequency multiplier is configured to be linearly related to the control signal. Optionally, assuming that the current frequency division / multiplication coefficient of the first frequency divider / first frequency multiplier is δ1, the dynamic setting period of the frequency division / multiplication coefficient of the first frequency divider / first frequency multiplier is T, the control signal represents the phase difference between the reference signal and the feedback signal, which is ΔT, the input clock frequency generated by the signal generating unit is F, and the frequency difference between the reference signal and the feedback signal is ΔF, then in the phase-locked loop circuit, the adjusted frequency division / multiplication coefficient δ satisfies: It can be seen from this that the frequency division / multiplication coefficient δ is linearly related to the control signal ΔT.

[0050] In some embodiments, the phase-locked loop circuit provided by the embodiments of the present application, when the phase-locked loop is in an initial state and needs to perform frequency division processing on the input clock signal, the first frequency divider is configured to perform frequency division processing on the input clock signal to generate an output clock signal with the same frequency as the reference signal; when the phase-locked loop is in an initial state and needs to perform frequency multiplication processing on the input clock signal, the first frequency multiplier is configured to perform frequency multiplication processing on the input clock signal to generate an output clock signal with the same frequency as the reference signal. Optionally, when the reference signal frequency is known in advance, the embodiments of the present application can set the first frequency divider or the first frequency multiplier so that the frequency of the output clock signal in the initial state is the same as the frequency of the reference signal, so that the frequency of the output clock signal can be directly consistent with the frequency of the reference signal, and then the frequency of the feedback signal obtained after the feedback unit performs frequency division or frequency multiplication processing on the output clock signal is consistent with the frequency of the reference signal, thereby achieving a faster phase-locked loop circuit reaching a locked state, avoiding the problem that the first frequency divider or the first frequency multiplier needs to gradually adjust the division or multiplication coefficient multiple times to reach a locked state, and accelerating the adjustment speed of the phase-locked loop circuit.

[0051] In some embodiments, Figure 6 and Figure 7 Two more schematic diagrams of the phase-locked loop circuit provided in the embodiments of the present application are shown, such as Figure 6 and Figure 7 As shown, in the phase-locked loop circuit provided in the embodiment of the present application, the feedback unit includes a second frequency divider or a second frequency multiplier.

[0052] When the phase-locked loop needs to perform frequency division processing on the input clock signal, the feedback unit includes a second frequency divider to receive the output clock signal and divide the output clock signal according to a preset frequency division coefficient to generate a feedback signal. When the phase-locked loop needs to perform frequency multiplication processing on the input clock signal, the feedback unit includes a second frequency multiplier to receive the output clock signal and divide the output clock signal according to a preset frequency multiplication coefficient to generate a feedback signal.

[0053] It is understandable that the specific value of the preset frequency division coefficient or the preset frequency multiplication coefficient is set according to the requirements of the phase-locked loop circuit, and the embodiment of the present application does not limit the specific value of the preset frequency division coefficient or the frequency multiplication coefficient.

[0054] In specific implementations, the modules / units included in the various devices and products described in the above embodiments may be software modules / units, hardware modules / units, or partly software modules / units and partly hardware modules / units.

[0055] For example, for each device or product applied to or integrated in a chip, each module / unit contained therein may be implemented in the form of hardware such as circuits, or at least some of the modules / units may be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules / units may be implemented in the form of hardware such as circuits; for each device or product applied to or integrated in a chip module, each module / unit contained therein may be implemented in the form of hardware such as circuits, and different modules / units may be located in the same component (such as a chip, circuit module, etc.) or different components of the chip module, or at least some of the modules / units may be implemented in the form of software programs. The unit can be implemented in the form of a software program, which runs on the processor integrated inside the chip module, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in the terminal, the various modules / units contained therein can all be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or different components in the terminal, or, at least some modules / units can be implemented in the form of a software program, which runs on the processor integrated inside the terminal, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits.

[0056] The embodiment of the present application further provides a chip 80, Figure 8 A schematic diagram of a chip provided in an embodiment of the present application is shown, wherein the chip 80 includes the aforementioned phase-locked loop circuit. An integrated circuit (IC) is also referred to as an integrated circuit. Such chips include, but are not limited to, SOC (System on Chip), SIP (System in Package), and FPGA (Field-Programmable Gate Array). FPGAs, as programmable logic devices, can implement user-customized logic functions through hardware description languages and are widely used in communications, industry, data centers, and other fields.

[0057] The embodiment of the present application also provides an electronic device, Figure 9 A schematic diagram of an electronic device provided in an embodiment of the present application is shown, and the electronic device includes a device body 90 and a chip 80 as described above, which is provided in the device body. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control screen, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smart phones, laptops, tablet computers, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights.

[0058] The above content is a further detailed description of the present application in conjunction with specific implementation methods, and the specific implementation of the present application cannot be considered to be limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, they can make several simple deductions or substitutions without departing from the concept of the present application, which should be considered as the scope of protection of the present application.

Claims

1. A phase-locked loop circuit, characterized in that: include: a phase detector unit, configured to receive a reference signal and a feedback signal, and output an error signal according to a phase difference between the reference signal and the feedback signal; a loop filtering unit, configured to receive the error signal, filter the error signal, and output a control signal; a signal generating unit and a signal conditioning unit, wherein the signal generating unit is used to generate an input clock signal of a preset frequency, and the signal conditioning unit is used to receive the control signal and the input clock signal, and perform frequency division or frequency multiplication processing on the input clock signal according to the control signal to generate an output clock signal; The feedback unit is configured to receive the output clock signal and perform frequency division or frequency multiplication processing on the output clock signal to generate the feedback signal.

2. The phase-locked loop circuit according to claim 1, wherein: The signal generating unit includes: a synchronous Ethernet clock source, configured to generate the input clock signal and output an Ethernet link code stream containing information of the input clock signal based on the input clock signal; A physical layer chip is connected to the synchronous Ethernet clock source via an Ethernet link, and is used to receive the Ethernet link code stream, recover the input clock signal from the Ethernet link code stream, and output the input clock signal to the signal conditioning unit.

3. The phase-locked loop circuit according to claim 1, wherein: The signal generating unit includes: An oscillator is configured to generate the input clock signal having the preset frequency and output the input clock signal to the signal conditioning unit.

4. The phase-locked loop circuit according to claim 1, wherein: The signal conditioning unit comprises: a first frequency divider, configured to receive the control signal and the input clock signal, and adjust a frequency division coefficient according to the control signal to divide the input clock signal by the frequency division coefficient to generate the output clock signal; or a first frequency multiplier, configured to receive the control signal and the input clock signal, and adjust a frequency multiplication factor according to the control signal to multiply the input clock signal according to the frequency multiplication factor to generate an output clock signal.

5. The phase-locked loop circuit according to claim 4, wherein: The frequency division coefficient of the first frequency divider is configured to be in a linear relationship with the control signal; or the frequency multiplication coefficient of the first frequency multiplier is configured to be in a linear relationship with the control signal.

6. The phase-locked loop circuit according to claim 4, wherein: The first frequency divider is configured to: in the initial state of the phase-locked loop circuit, divide the input clock signal to generate an output clock signal with the same frequency as the reference signal; or the first frequency multiplier is configured to: multiply the input clock signal to generate an output clock signal with the same frequency as the reference signal.

7. The phase-locked loop circuit according to claim 1, wherein: The feedback unit includes: a second frequency divider, configured to receive the output clock signal and perform frequency division processing on the output clock signal according to a preset frequency division coefficient to generate the feedback signal; or a second frequency multiplier, configured to receive the output clock signal and perform frequency division processing on the output clock signal according to a preset frequency multiplication factor to generate the feedback signal.

8. A chip, characterized in that: The phase-locked loop circuit comprises the phase-locked loop circuit according to any one of claims 1 to 7.

9. An electronic device, characterized in that: The device comprises a device body and the chip according to claim 8 arranged in the device body.

Images