Radio frequency module and electronic equipment

Abstract

The invention relates to the technical field of communication, in particular to a radio frequency module and electronic equipment. The radio frequency module comprises a first path and a second path which are selectively coupled to an antenna port; the first path is configured to process an input first uplink signal and output the processed first uplink signal to the antenna port; the second path is configured to process and output a first downlink signal of the antenna port; the third path and the fourth path are coupled to the antenna port in a switchable manner through the first switch; the third path is configured to process an input second uplink signal and output the processed signal to the antenna port; the fourth path is configured to output an input third uplink signal to the antenna port; wherein the power levels of the first uplink signal and the second uplink signal are different, and the power levels of the first downlink signal and the third uplink signal are different. According to the radio frequency module and the electronic equipment provided by the invention, the insertion loss can be reduced while the overall size is reduced, and the signal transmission efficiency of the radio frequency module is improved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a radio frequency module and electronic equipment. Background Art

[0002] With the advancement of communication technology, users are increasingly demanding the communication capabilities of electronic devices. RF modules are the front-end circuits in the communication systems of electronic devices, used to transmit and receive communication signals. The performance and efficiency of RF modules directly impact the communication capabilities of electronic devices.

[0003] To improve RF module performance, multiple pathways are often integrated within the module to enhance signal reception sensitivity. This increases the overall size of the module, conflicting with the demand for miniaturized electronic devices. Currently, achieving miniaturization while simultaneously improving RF module performance is a challenge in the design of RF modules and electronic devices. Summary of the Invention

[0004] In order to solve the above problems, the present application provides a radio frequency module and electronic equipment that can reduce the overall size while reducing insertion loss, improving the signal transmission efficiency of the radio frequency module, and improving the signal receiving sensitivity.

[0005] In order to achieve the above-mentioned objectives, in a first aspect, the present application provides a radio frequency module, comprising: an antenna port, a first switch, a first path, a second path, a third path and a fourth path; the first path and the second path are selectively coupled to the antenna port; the first path is configured to: process the input first uplink signal and output it to the antenna port; the second path is configured to: process and output the first downlink signal of the antenna port; the third path and the fourth path are switchably coupled to the antenna port through the first switch; the third path is configured to: process the input second uplink signal and output it to the antenna port; the fourth path is configured to: output the input third uplink signal to the antenna port; wherein the power levels of the first uplink signal and the second uplink signal are different, and the power levels of the first downlink signal and the third uplink signal are different.

[0006] In the embodiments provided herein, by coupling a second uplink signal having a different power level from the first uplink signal and a third uplink signal having a different power level from the first downlink signal to the same first switch, the structural complexity of other switches in the RF module can be reduced. This can reduce the overall size of other switches in the RF module, thereby facilitating a miniaturized design of the RF module, reducing signal loss, improving the signal transmission efficiency of the RF module, and improving the signal reception sensitivity.

[0007] In one optional embodiment, the first path is configured to sequentially amplify and filter an input first uplink signal and output it to the antenna port; the third path is configured to sequentially amplify and filter an input second uplink signal and output it to the antenna port; wherein the first uplink signal is in the first network mode, the second uplink signal is in the second network mode, and the signal power level of the second network mode is greater than the signal power level of the first network mode. In this way, the second uplink signal with a higher power level can be transmitted separately from the first uplink signal with a relatively lower power level, thereby simplifying the switch structure coupled to the first path.

[0008] In an optional embodiment, along the signal transmission direction of the first uplink signal, the first path includes a first power amplification module, a second switch, a first filtering module, and a third switch coupled in sequence; the first filtering module includes multiple first filters of different frequency bands; the first power amplification module is configured to: amplify the input signal of the first uplink signal to obtain a first amplified signal, and output the first uplink signal input signal to the second switch; the second switch is configured to: input the first amplified signal to the first filter of the corresponding frequency band; the first filter is configured to: filter the first amplified signal to obtain the output signal of the first uplink signal (the output signal of the first uplink signal), and output it to the third switch; the third switch is configured to: output the output signal of the first uplink signal (the output signal of the first uplink signal) to the antenna port. In this way, it is convenient to implement amplification and filtering processing of the first uplink signal.

[0009] In an optional embodiment, the fifth path is configured to process and output a second downlink signal from the antenna port; the network mode of the second downlink signal includes a first network mode and a second network mode, and the power level of the second downlink signal is the same as the power level of the first uplink signal. In this way, the fifth path can be used to receive the second downlink signal, thereby implementing a dual receive path within the RF module and improving the RF module's signal reception sensitivity.

[0010] In an optional embodiment, along the signal transmission direction of the second downlink signal, the fifth path includes a third filtering module, a fourth switch, and a first low-noise amplifier module coupled in sequence; the third filtering module includes multiple third filters of frequency bands corresponding to the frequency bands of the first filter, each third filter coupled between the fourth switch and the third switch; the third switch is configured to input the input signal of the second downlink signal input from the antenna port to the output signal of the first uplink signal of the third filter of the corresponding frequency band; the third filter is configured to filter the input signal of the second downlink signal to obtain a first filtered signal, and output it to the fourth switch; the fourth switch is configured to output the first filtered signal to the first low-noise amplifier module; and the first low-noise amplifier module is configured to amplify the first filtered signal to obtain an output signal of the second downlink signal, and output it. In this way, filtering and amplification of the second downlink signal can be facilitated.

[0011] In one optional embodiment, along the signal transmission direction of the second uplink signal, the third path includes a second power amplification module, a third filtering module, and a first switch coupled in sequence. The second power amplification module is configured to amplify the input signal of the second uplink signal to obtain a second amplified signal, and output it to the third filtering module. The third filtering module is configured to filter the second amplified signal to obtain an output signal of the second uplink signal, and output it to the first switch. The first switch is configured to output the output signal of the second uplink signal to the antenna port. This facilitates amplification and filtering of the second uplink signal.

[0012] In one optional embodiment, the second path is configured to filter and amplify the first downlink signal from the antenna port before outputting it. The fourth path is configured to output a third uplink signal to the antenna port, or output a third downlink signal from the antenna port. The third uplink signal is an externally processed signal, and the third downlink signal is output by the fourth path for external processing. This allows the fourth path to be used to add an external common terminal to the RF module, thereby increasing the module's flexibility.

[0013] In an optional embodiment, along the signal transmission direction of the first downlink signal, the second path includes a fifth switch, a fourth filtering module, a sixth switch, and a second low-noise amplifier module coupled in sequence; the fourth filtering module includes a plurality of fourth filters of different frequency bands; the fifth switch is configured to input the input signal of the first downlink signal input from the antenna port into the output signal of the first uplink signal of the fourth filter of the corresponding frequency band; the fourth filter is configured to filter the first downlink signal to obtain a second filtered signal, and output it to the sixth switch; the sixth switch is configured to output the second filtered signal to the second low-noise amplifier module; and the second low-noise amplifier module is configured to amplify the second filtered signal to obtain an output signal of the first downlink signal, and output it. In this way, filtering and amplifying the first downlink signal can be easily implemented.

[0014] In an optional embodiment, the RF module further includes a sixth path coupled to the third switch; the sixth path is configured to output a fourth uplink signal input to the antenna port, or to output a fourth downlink signal input from the antenna port; the power level of the fourth uplink signal is the same as the power level of the third uplink signal; the fourth uplink signal is an externally processed signal, and the fourth downlink signal is output by the sixth path for external processing. In this way, the sixth path can be used to add an external common terminal to the RF module, thereby increasing the flexibility of the RF module.

[0015] In an optional embodiment, a first coupling module is coupled between the third switch and the antenna port and is configured to detect and output the power of the first uplink signal and the fourth uplink signal transmitted to the antenna port via the third switch. In this way, the first coupling module can be used to detect the power of the first uplink signal and the fourth uplink signal, thereby facilitating power calibration of the first uplink signal and the fourth uplink signal.

[0016] In an optional embodiment, the RF module further includes a sixth path coupled to the fifth switch; the sixth path is configured to: output a fourth uplink signal input to the antenna port, or output a fourth downlink signal input from the antenna port; the power level of the fourth uplink signal is the same as the power level of the third uplink signal; wherein the fourth uplink signal is an externally processed signal, and the fourth downlink signal is output by the sixth path for external processing. In this way, the sixth path can be used to add an external common terminal to the RF module, thereby increasing the flexibility of the RF module.

[0017] In an optional embodiment, a second coupling module is coupled between the fifth switch and the antenna port and is configured to detect and output the power of the third uplink signal transmitted to the antenna port via the fifth switch. In this way, the second coupling module can be used to detect the power of the third uplink signal, thereby facilitating power calibration of the third uplink signal.

[0018] In an optional embodiment, the fourth path is configured to: output the input third uplink signal to the antenna port, or output the third downlink signal input to the antenna port; wherein the third uplink signal is a signal that has been externally processed, and the third downlink signal is transmitted by the fourth path to the external processing; the RF module also includes a sixth path, and the sixth path is coupled to the first switch; the sixth path is configured to: output the input fourth uplink signal to the antenna port, or output the fourth downlink signal input to the antenna port; the power level of the fourth uplink signal is the same as the power level of the third uplink signal; wherein the fourth uplink signal is a signal that has been externally processed, and the fourth downlink signal is transmitted by the sixth path to the external processing. In this way, the external common end of the RF module can be coupled to the same switch to simplify the structure of other switches and reduce the power loss and overall size of other switches.

[0019] In an optional embodiment, a third coupling module is coupled between the first switch and the antenna port and is configured to detect and output the power of the second uplink signal, the third uplink signal, or the fourth uplink signal transmitted to the antenna port via the first switch. In this way, the third coupling module can be used to detect the power of the second uplink signal, the third uplink signal, or the fourth uplink signal, thereby facilitating power calibration of the second uplink signal, the third uplink signal, or the fourth uplink signal.

[0020] In an optional embodiment, the RF module further includes a seventh switch; the first path, the second path, and the first switch are selectively coupled to the antenna port via the seventh switch. Thus, the seventh switch can be used to selectively couple the first path, the second path, and the first switch to the antenna port, thereby facilitating switching of the path coupled to the antenna port.

[0021] In an optional embodiment, the antenna ports include a first antenna port and a second antenna port; the first antenna port and the second antenna port are coupled to a seventh switch; and the first path, the second path, and the first switch are selectively coupled to the first antenna port or the second antenna port via the seventh switch. This allows for dual-path signal transmission using the two antenna ports, improving signal transmission efficiency.

[0022] In an optional embodiment, the first network mode is a 4G communication network mode with a low bandwidth frequency band or a 5G communication network mode with a low bandwidth frequency band; and the second network mode is a 2G communication network mode with a low bandwidth frequency band. In this way, the communication performance of the low bandwidth frequency band signal can be improved.

[0023] In order to achieve the above-mentioned purpose, in a second aspect, the present application provides an electronic device, including an antenna, and a radio frequency module as described in the first aspect above; the antenna is coupled to the antenna port.

[0024] It is understandable that the beneficial effects of the technical solution of the second aspect have been described in the first aspect and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0026] Figure 1 is a schematic structural diagram of the first radio frequency module provided in this embodiment;

[0027] Figure 2 is a schematic structural diagram of the second radio frequency module provided in this embodiment;

[0028] Figure 3 is a structural diagram of the first RF module provided in this embodiment;

[0029] Figure 4 is a schematic structural diagram of the second RF module provided in this embodiment;

[0030] Figure 5 This is a basic structural diagram of a single-pole multi-throw switch provided in this embodiment;

[0031] Figure 6 This embodiment provides Figure 4 A schematic structural diagram of the third switch in FIG.

[0032] Figure 7 This embodiment provides Figure 4 A schematic structural diagram of the fifth switch in FIG.

[0033] Figure 8 This embodiment provides Figure 4 A schematic structural diagram of the seventh switch in FIG.

[0034] Figure 9 is a schematic structural diagram of the third RF module provided in this embodiment;

[0035] Figure 10This embodiment provides Figure 9 A schematic structural diagram of the third switch in FIG.

[0036] Figure 11 This embodiment provides Figure 9 A schematic structural diagram of the fifth switch in FIG.

[0037] Figure 12 This embodiment provides Figure 9 A schematic structural diagram of the first switch in FIG.

[0038] Figure 13 This embodiment provides Figure 9 A schematic structural diagram of the seventh switch in FIG.

[0039] Figure 14 2 is a schematic structural diagram of the fourth radio frequency module provided in this embodiment;

[0040] Figure 15 2 is a schematic structural diagram of the fifth radio frequency module provided in this embodiment;

[0041] Figure 16 This embodiment provides Figure 15 A schematic structural diagram of the third switch in FIG.

[0042] Figure 17 This embodiment provides Figure 15 A schematic structural diagram of the fifth switch in FIG.

[0043] Figure 18 This embodiment provides Figure 15 A schematic structural diagram of the first switch in FIG.

[0044] Figure 19 This is a schematic structural diagram of an electronic device provided by this embodiment. DETAILED DESCRIPTION

[0045] The following will clearly describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments of the present application, other embodiments obtained by ordinary technicians in this field without making any creative work are all within the scope of protection of this application.

[0046] Hereinafter, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature qualified as "first," "second," etc. may explicitly or implicitly include one or more of such features. Throughout the description of this application, "plurality" means two or more unless otherwise specified.

[0047] In addition, in this application, directional terms such as "upper", "lower", "inner" and "outer" are defined relative to the orientation of the components in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they can change accordingly according to changes in the orientation of the components in the drawings.

[0048] With the development of 4G / 5G communications, people have higher and higher requirements for the communication functions of electronic devices. A processor, a radio frequency module, and an antenna module that are interconnected can be set in an electronic device to realize the wireless communication function of the electronic device. Among them, the processor can be used to perform digital domain processing of the signal, and the radio frequency module can be used to perform analog domain processing of the signal. The antenna module can be used to convert the analog signal into an electromagnetic wave for transmission to realize the transmission function. Alternatively, the antenna module can be used to convert the electromagnetic wave into an analog signal and transmit it to the radio frequency module to realize the receiving function. Among them, the antenna module can be considered as a part of the radio frequency module. For the sake of convenience of explanation, in this embodiment, the radio frequency module does not include the antenna module.

[0049] In some embodiments, the RF module can receive RF signals through an antenna and process the RF signals, such as amplifying and filtering. The RF module can also process RF signals from the baseband subsystem and transmit the RF signals through an antenna.

[0050] In electronic devices, the signal received by the RF module from the baseband subsystem is obtained by the baseband subsystem performing modulation and demodulation on the baseband signal.

[0051] Specifically, the baseband subsystem can implement signal processing operations such as modulation and demodulation, encoding and decoding. Different wireless access technologies, such as 5G New Radio and 4G long-term evolution (LTE), often have different baseband signal processing operations. Since the radio frequency signal is an analog signal, the signal processed by the baseband subsystem is mainly a digital signal, and the electronic device also needs an analog-to-digital converter. The analog-to-digital converter includes an analog-to-digital converter (ADC) that converts analog signals into digital signals, and a digital-to-analog converter (DAC) that converts digital signals into analog signals.

[0052] In one example, the analog-to-digital conversion device may be provided in a baseband subsystem.

[0053] The baseband subsystem can be implemented as a standalone chip, which can be called a modem chip. The hardware components of the baseband subsystem can be manufactured and sold as a unit of a modem chip. Modem chips are sometimes also called baseband chips or baseband processors. Furthermore, the baseband subsystem can be further integrated into a system-on-chip (SOC), manufactured and sold as a unit of SOC. The software components of the baseband subsystem can be built into the chip's hardware components before the chip leaves the factory, imported from other non-volatile memory into the chip's hardware components after the chip leaves the factory, or downloaded and updated online via the network. Furthermore, the application subsystem may also include driver software related to other subsystems (such as the baseband subsystem). The baseband subsystem may also include one or more processing cores, as well as hardware accelerators (HACs), caches, and other components.

[0054] To improve the communication performance of electronic devices, the algorithms of their baseband subsystems can be optimized, or the computing power of their core processors can be increased. Furthermore, improvements in the transmission and reception performance of radio signal groups can be made to enhance communication performance, thereby increasing the competitiveness of electronic devices.

[0055] When improving the transmission and reception performance of RF signals, the RF front-end circuit can be integrated into a system consisting of discrete components. This allows the RF front-end circuit to move towards a more integrated and modular design. In this way, the RF module can not only achieve high performance, but also achieve high integration and miniaturization. This can further reduce the space required to install the individual discrete components of the RF front-end circuit within the electronic device, thus meeting the miniaturization requirements of the electronic device.

[0056] Figure 1 This is a schematic structural diagram of the first radio frequency module provided in this embodiment.

[0057] like Figure 1 As shown, the structure of a radio frequency module of a sub-3 GHz low frequency (Sub-3G Low Band, Sub3G LB) radio frequency module is taken as an example for description.

[0058] The Sub3G LB RF module covers the low-frequency bands (850 / 900 MHz) of the Global System for Mobile Communications (GSM), the low-frequency bands (800-900 MHz) of the third-generation mobile communications technology, and the low-frequency bands (617-960 MHz) of the fourth-generation mobile communications technology (Long-Term Evolution, LTE) or the fifth-generation mobile communications technology (New Radio, NR). GSM is a second-generation mobile communications technology, referred to as 2G. The third-generation mobile communications technology is referred to as 3G, the fourth-generation mobile communications technology is referred to as 4G, and the fifth-generation mobile communications technology is referred to as 5G.

[0059] The radio frequency module includes a first terminal P1 , a second terminal P2 , a third terminal P3 , a fourth terminal P4 , a fifth terminal P5 , a sixth terminal P6 , a seventh terminal P7 , a first switch S1 , a first coupler and a first processing module A.

[0060] The sixth end P6 is an antenna port, and the number of antenna ports may be one, two, three or more, which is not limited in this embodiment.

[0061] The first terminal P1 , the second terminal P2 , the third terminal P3 and the first switch S1 are coupled to the first processing module A.

[0062] The fourth terminal P4 and the sixth terminal P6 are coupled to the first switch S1 .

[0063] The first coupler is coupled between the first switch S1 and the sixth terminal P6 and is coupled to the fifth terminal P5. The first coupler is used to detect the power of the RF signal output from the first switch S1 to the sixth terminal P6 to facilitate calibration of the output power of the RF signal.

[0064] The seventh terminal P7 is coupled to the sixth terminal P6.

[0065] The LTE / NR transmission signal is output to the first processing module A through the first terminal P1. The first processing module A amplifies and filters the LTE / NR transmission signal and then outputs it to the sixth terminal P6 through the first switching switch S1.

[0066] The GSM transmission signal is output to the first processing module A through the second terminal P2. The first processing module A amplifies and filters the GSM transmission signal and then outputs it to the sixth terminal P6 through the first switch S1.

[0067] The sixth terminal P6 receives the LTE / NR RF signal or the GSM RF signal and outputs it to the first processing module A through the first switching switch S1. The first processing module A filters and amplifies the LTE / NR RF signal or the GSM RF signal and then outputs it to the third terminal P3.

[0068] The fourth terminal P4 can be an external common port. In this case, the fourth terminal P4 can output a radio frequency signal and output it to the sixth terminal P6 through the first switch S1. Alternatively, the sixth terminal P6 can receive a radio frequency signal and switch it to the fourth terminal P4 through the first switch S1 to output the radio frequency signal.

[0069] In the RF module, the above structure can form a master set to implement a one-transmit-one-receive (1T1R) system function. To improve the receiving sensitivity of the Sub3G LB RF module, a one-transmit-two-receive (1T2R) system function can be adopted. In this case, the seventh terminal P7 can be coupled to an external diversity to implement the 1T2R function.

[0070] Figure 2 2 is a schematic structural diagram of the second RF module provided in this embodiment.

[0071] like Figure 2 As shown, in order to further improve the integration of the RF module, diversity can be integrated into the RF module.

[0072] For example, a second switch S2 and a second processing module B can be coupled between the seventh terminal P7 and the sixth terminal P6. In this case, the sixth terminal P6 receives an LTE / NR RF signal or a GSM RF signal, which can be output to the second processing module B via the second switching circuit. The second processing module B filters and amplifies the LTE / NR RF signal or the GSM RF signal before outputting it to the seventh terminal P7. In this way, simultaneous dual-path reception can be achieved at the seventh terminal P7 and the third terminal P3, thereby improving sensitivity to RF signals outside the electronic device.

[0073] Meanwhile, in order to further improve the flexibility of the RF module, the RF module may further include an eighth terminal P8 , where the eighth terminal P8 is coupled to the second switch S2 .

[0074] The eighth terminal P8 can be an external common port. In this case, the eighth terminal P8 can output a radio frequency signal and transmit it to the sixth terminal P6 through the second switch S2. Alternatively, the sixth terminal P6 can receive a radio frequency signal and transmit it to the eighth terminal P8 through the second switch S2 to output the radio frequency signal.

[0075] Optionally, the RF module may further include a second coupler coupled between the second switch S2 and the sixth terminal P6, and the second coupler is coupled to the ninth terminal P9. The second coupler is configured to detect the power of the RF signal output by the second switch S2 to the sixth terminal P6, thereby calibrating the output power of the RF signal.

[0076] Depend on Figure 2 As can be seen, both LTE / NR and GSM transmission signals currently need to pass through the first switch S1 to be transmitted to the sixth terminal P6. The power level of GSM transmission signals is much higher than that of LTE / NR transmission signals. To ensure that the first switch S1 can meet the power level of GSM transmission signals, a larger number of transistors must be included in the first switch S1 to meet circuit requirements. This results in a larger size for the first switch S1 and a higher insertion loss, which affects signal transmission efficiency and the miniaturization of electronic devices.

[0077] Furthermore, for the second switch S2, the power level of the RF signal output from the external common port is significantly higher than the power level of the received signal for LTE / NR or GSM. To ensure that the second switch S2 can meet the power level of the transmitted signal from the external common port, a larger number of transistors must be included within the second switch S2 to meet circuit requirements. This results in a larger size for the second switch S2 and a higher insertion loss, impacting signal transmission efficiency and miniaturization of electronic devices.

[0078] From the above description, it can be seen that Figure 1 and Figure 2 In the circuit structure shown, the circuit structure of the connection between the first switching switch S1 and the second switching switch S2 is unreasonable, resulting in a large area of the first switching switch S1 and the second switching switch S2. At the same time, the insertion loss generated by the first switching switch S1 and the second switching switch S2 is also large, affecting the signal transmission efficiency.

[0079] In order to solve the above problems, the present application provides a radio frequency module that can reduce the overall size while reducing the insertion loss and improving the signal transmission efficiency of the radio frequency module.

[0080] Figure 3 This is a schematic structural diagram of the first radio frequency module provided in this embodiment.

[0081] like Figure 3 As shown, the structure of a radio frequency module of a sub-3 GHz low frequency (Sub-3G Low Band, Sub3G LB) radio frequency module is taken as an example for description.

[0082] For example, the Sub3G LB RF module integrates a power amplifier module, a low-noise power amplifier module, a switch, a filter, and a coupler into the module to achieve the integration of the transmit path and the receive path.

[0083] The radio frequency module includes an antenna port, a first path, a third path, and a fifth path, all of which are coupled to the antenna port.

[0084] The first path is configured to process the input signal of the input first uplink signal and output it to the antenna port. In other words, the first path is configured to amplify and filter the input signal of the input first uplink signal to obtain an output signal of the first uplink signal and output it to the antenna port.

[0085] It is worth noting that the input signal of the first uplink signal and the output signal of the first uplink signal are both RF signals. At the same time, the output signal of the first uplink signal is a signal after amplification and filtering, and the power level of the output signal of the first uplink signal is greater than the power level of the input signal of the first uplink signal.

[0086] The first uplink signal may be a low-frequency LTE / NR transmission signal. In this case, the first uplink signal may be a radio frequency signal. The first network mode may be a low-frequency 4G communication network mode or a low-frequency 5G communication network mode, hereinafter referred to as the LTE / NR transmission signal. It is understood that in other radio frequency modules, the first uplink signal may also be a signal of another network mode or a radio frequency signal of another frequency band.

[0087] Optionally, the input end of the first path can be coupled to a first input port IN1. The first input port IN1 is configured to input the input signal of the first uplink signal into the first path. Exemplarily, along the signal transmission direction of the first uplink signal, the first path includes a first power amplifier module PA1, a second switch SW2, a first filter module, and a third switch SW3 coupled in sequence.

[0088] The first input port IN1 is configured to input the input signal of the first uplink signal to the input end of the first power amplification module PA1.

[0089] Specifically, the first power amplifier module PA1 may include one or more power amplifiers. If there is one power amplifier, the power amplifier is a high-bandwidth power amplifier, thereby being able to achieve full coverage of the low-frequency band of the LTE / NR transmission signal, so as to facilitate amplification of the low-frequency band LTE / NR transmission signal.

[0090] The first power amplifier module PA1 is configured to amplify the input signal of the first uplink signal to obtain a first amplified signal, and output the first amplified signal to the second switch SW2.

[0091] The second switch SW2 is configured to output the first amplified signal to the first filtering module.

[0092] Furthermore, the first filtering module may include a plurality of first filters F1 of different frequency bands.

[0093] Optionally, the first filter F1 may be a bandpass filter. The frequency bands of the first filter F1 may include B5 / B26, B8, and B12.

[0094] It is worth noting that in Figure 3 The first filters F1 of all frequency bands are not shown in the figure. The number and frequency band types of the first filters F1 can be selected according to the actual transmitted signals and are not limited in this embodiment.

[0095] When there are multiple first filters F1, the second switch SW2 may be a single-pole multi-throw switch, so that the first amplified signal input through the single-port side of the second switch SW2 can be switched to the first filter F1 corresponding to the frequency band through the multi-port side.

[0096] The first filter F1 is configured to filter the first amplified signal to obtain an output signal of the first uplink signal, and output the output signal to the third switch SW3 .

[0097] The third switch SW3 is configured to output the output signal of the first uplink signal to the antenna port.

[0098] Accordingly, the third switch SW3 may also be a single-pole, multi-throw switch, so that the multiple ports of the third switch SW3 can be coupled to multiple first filters F1. The first filter F1 can couple the output signal of the first uplink signal to a single port via one of the multiple ports, thereby allowing the output signal of the first uplink signal to be output to the antenna port via the single port of the third switch SW3.

[0099] In summary, for the uplink path (transmission path) of the first uplink signal, the first input port IN1 can transmit an input signal of the first uplink signal and output it to the first power amplifier module PA1. At this time, the first power amplifier module PA1 can amplify the input signal of the first uplink signal to obtain a first amplified signal. The first amplified signal is switched to the first filter F1 of the corresponding frequency band through the second switch SW2. Afterwards, the first filter F1 can filter the first amplified signal to obtain the output signal of the first uplink signal. In this way, the output signal of the first uplink signal can be output to the antenna port through the third switch SW3. Finally, the output signal of the first uplink signal can be radiated to the outside of the electronic device through the antenna to complete the signal transmission process.

[0100] It is worth noting that the input signal of the first uplink signal, the first amplified signal and the processed output signal of the first uplink signal can be collectively referred to as the first uplink signal input by the first input port IN1 and output via the antenna port.

[0101] The third path is configured to process the input signal of the second uplink signal and output it to the antenna port. In other words, the third path is configured to amplify and filter the input signal of the second uplink signal to obtain an output signal of the second uplink signal and output it to the antenna port.

[0102] It is worth noting that the input signal of the second uplink signal and the output signal of the second uplink signal are both RF signals. At the same time, the output signal of the second uplink signal is a signal after amplification and filtering. The power level of the output signal of the second uplink signal is greater than the power level of the input signal of the second uplink signal.

[0103] The power level of the second uplink signal is different from the power level of the first uplink signal. The second uplink signal may be a low-frequency GSM transmission signal. In this case, the second uplink signal may be a radio frequency signal. The second network mode may be a low-frequency 2G communication network mode, hereinafter referred to as the GSM transmission signal. It is understood that in other radio frequency modules, the second uplink signal may also be a signal of another network mode or a radio frequency signal of another frequency band.

[0104] At this time, the signal power level of the second network mode is greater than the signal power level of the first network mode.

[0105] Optionally, the input end of the third path may be coupled to the second input port IN2. The second input port IN2 is configured to input the input signal of the second uplink signal to the third path.

[0106] Exemplarily, along the signal transmission direction of the second uplink signal, the third path includes a second power amplifier module PA2, a second filter module and a third switch SW3 coupled in sequence. The second input port IN2 is configured to input the input signal of the second uplink signal to the input end of the second power amplifier module PA2.

[0107] Specifically, the second power amplifier module PA2 may include one or more power amplifiers. If there is one power amplifier, the power amplifier is a high-bandwidth power amplifier, thereby being able to achieve full coverage of the low-frequency band of the GSM transmission signal, so as to facilitate amplification of the low-frequency band GSM transmission signal.

[0108] The second power amplification module PA2 is configured to amplify the input signal of the second uplink signal to obtain a second amplified signal, and output the second amplified signal to the second filtering module.

[0109] Furthermore, the second filtering module may include a second filter F2.

[0110] Optionally, since the frequency band of the GSM transmission signal is 850 / 900 MHz, the second filter F2 may be a low-pass filter.

[0111] It is worth noting that the number and frequency band types of the second filters F2 can be selected according to the actual transmitted signal and are not limited in this embodiment.

[0112] The second filter F2 is configured to filter the second amplified signal to obtain an output signal of a second uplink signal, and output the output signal to the third switch SW3.

[0113] The third switch SW3 is configured to output the output signal of the second uplink signal to the antenna port.

[0114] Accordingly, the third switch SW3 may also be a single-pole, multi-throw switch. Thus, the multiple ports of the third switch SW3 can be coupled to multiple first filters F1 and can also be coupled to the second filter F2. The second filter F2 can couple the output signal of the second uplink signal to a single port via one of the multiple ports, thereby allowing the output signal of the second uplink signal to be output to the antenna port via the single port of the third switch SW3.

[0115] In summary, for the uplink path (transmission path) of the second uplink signal, the second input port IN2 can transmit an input signal of the second uplink signal and output it to the second power amplifier module PA2. At this time, the second power amplifier module PA2 can amplify the input signal of the second uplink signal to obtain a second amplified signal. The second amplified signal is transmitted to the second filter F2. Thereafter, the second filter F2 can filter the second amplified signal to obtain the output signal of the second uplink signal. In this way, the output signal of the second uplink signal can be output to the antenna port through the third switch SW3. Finally, the output signal of the second uplink signal can be radiated to the outside of the electronic device through the antenna to complete the signal transmission process.

[0116] It is worth noting that the second uplink signal input signal, the second amplified signal, and the processed second uplink signal output signal can be collectively referred to as the second uplink signal input by the second input port IN2 and output via the antenna port.

[0117] The fifth path is configured to process and output the second downlink signal of the antenna port. In other words, the fifth path is configured to amplify and filter the input signal of the second downlink signal of the antenna port to obtain and output the output signal of the second downlink signal.

[0118] It is worth noting that the input signal of the second downlink signal and the output signal of the second downlink signal are both RF signals. At the same time, the output signal of the second downlink signal is a signal after amplification and filtering. The power level of the output signal of the second downlink signal is greater than the power level of the input signal of the second downlink signal.

[0119] It should be understood that both the output signal of the uplink signal and the input signal of the downlink signal pass through the antenna port, wherein the output signal of the uplink signal is output via the antenna port, and the input signal of the downlink signal is input via the antenna port.

[0120] Optionally, the output end of the fifth path may be coupled to the first output port OUT1. The first output port OUT1 is configured to output the output signal of the second downlink signal.

[0121] The power level of the second downlink signal is the same as the power level of the first uplink signal. The second downlink signal can be a low-frequency GSM reception signal or a low-frequency LTE / NR reception signal. In this case, the second downlink signal can be a radio frequency signal of the first network mode or the second network mode from the antenna. It is understandable that in other radio frequency modules, the second downlink signal can also be a signal of other network modes or a radio frequency signal of other frequency bands.

[0122] Optionally, the second downlink signal includes a radio frequency signal of the first network mode and / or a radio frequency signal of the second network mode received by the antenna port.

[0123] Exemplarily, along the signal transmission direction of the second downlink signal, the fifth path includes a third filtering module, a fourth switch SW4 and a first low noise amplifier module LNA1 coupled in sequence.

[0124] The antenna port is configured to output the input signal of the second downlink signal to the third switch SW3.

[0125] The third switch SW3 is configured to output the input signal of the second downlink signal to the third filtering module.

[0126] Specifically, the third filtering module may include a plurality of third filters F3 of different frequency bands.

[0127] Optionally, the third filter F3 may be a bandpass filter. The frequency bands of the first filter F1 may include frequency bands such as n5 / n26, n8 and n12.

[0128] It is worth noting that in Figure 3 The third filters F3 of all frequency bands are not shown in the figure. The number and frequency band types of the third filters F3 can be selected according to the actual transmitted signals and are not limited in this embodiment.

[0129] The third filter F3 with the same frequency band can form a duplexer with the first filter F1, so that the third filter F3 and the first filter F1 can share the same port of the third switch SW3, thereby simplifying the structure of the third switch SW3.

[0130] The third filter F3 is configured to perform filtering processing on the input signal of the second downlink signal, thereby obtaining a first filtered signal.

[0131] The fourth switch SW4 is configured to transmit the first filtered signal to the input end of the first low noise amplifier module LNA1.

[0132] Accordingly, the fourth switch SW4 can be a single-pole, multi-throw switch. The multiple ports of the fourth switch SW4 can be coupled to the outputs of the third filter F3 in different frequency bands, thereby transmitting the first filtered signal. A single port of the fourth switch SW4 is coupled to the input of the first low-noise amplifier module LNA1 to output the first filtered signal to the first low-noise amplifier module LNA1.

[0133] Furthermore, the first low-noise amplifier module LNA1 may include one or more low-noise amplifiers. If there is one low-noise amplifier, the low-noise amplifier is a high-bandwidth low-noise amplifier, thereby being able to achieve full coverage of the low-frequency bands of GSM receive signals and LTE / NR receive signals, thereby facilitating amplification of low-frequency band GSM receive signals and LTE / NR receive signals.

[0134] The first low noise amplifier module LNA1 is configured to amplify the first filtered signal to obtain an output signal of the first network mode or the second downlink signal, and output the output signal to the first output port OUT1.

[0135] It is understood that when the second downlink signal is a radio frequency signal of the first network, the first low-noise amplifier module LNA1 amplifies the first filtered signal to obtain an amplified radio frequency signal of the first network mode. When the second downlink signal is a radio frequency signal of the second network, the first low-noise amplifier module LNA1 amplifies the first filtered signal to obtain an amplified radio frequency signal of the second network mode.

[0136] In summary, for the downlink path (receive path) of the second downlink signal, the antenna port can receive an input signal of the second downlink signal and transmit it to the third switch SW3. The third switch SW3 switches the input signal of the second downlink signal to the corresponding third filter F3. At this time, the third filter F3 can filter the input signal of the second downlink signal to obtain a first filtered signal, which is output to the fourth switch SW4. In this way, the first filtered signal can be output to the first low-noise amplifier module LNA1 through the fourth switch SW4. The first low-noise amplifier module LNA1 amplifies the first filtered signal to obtain the output signal of the second downlink signal, completing the signal reception process.

[0137] It is worth noting that the input signal of the second downlink signal received by the antenna port, the first filtered signal and the processed output signal of the second downlink signal can be collectively referred to as the second downlink signal received by the antenna port and output by the first output port OUT1.

[0138] like Figure 3 As shown, the RF module further includes a first coupling module C1, which is coupled between the third switch SW3 and the antenna port. The first coupling module C1 is configured to detect the power of the first uplink signal transmitted to the antenna port through the third switch SW3 and output it.

[0139] The first coupling module C1 may include a coupler and a first coupling port CPL1. The coupler is coupled between the third switch SW3 and the antenna port to detect the power of the first uplink signal. The first coupling port CPL1 is coupled to the coupler so that data detected by the coupler can be transmitted to a calibration system to facilitate power correction of the first uplink signal.

[0140] Furthermore, the RF module includes a sixth path coupled to the multi-port side of the third switch SW3. The sixth path is configured to output a fourth uplink signal input to the antenna port, or to output a fourth downlink signal input to the antenna port. The power level of the fourth uplink signal is greater than the power level of the first uplink signal, and the power level of the fourth uplink signal is less than the power level of the second uplink signal.

[0141] Among them, the fourth uplink signal is a signal that has been externally processed, and the fourth downlink signal is also externally processed. The RF module does not process the fourth uplink signal and the fourth downlink signal.

[0142] Optionally, the sixth path may be coupled to the external common port TRX. The external common port TRX is configured to input the fourth upstream signal to the sixth path, or receive the fourth downstream signal from the sixth path.

[0143] In this way, the sixth path can be utilized to provide a universal path for connecting to other external devices or systems. The external common port can support different types of communication interfaces and functions, such as external antennas, sensors, expansion modules, etc., thereby providing flexibility and scalability for the module, meeting different application requirements and interacting and communicating with other devices or systems. It can be understood that the fourth uplink signal via the external common port TRX is a radio frequency signal processed by the external structure, and the fourth downlink signal via the external common port TRX will be processed by the external structure to obtain a corresponding radio frequency signal.

[0144] In the first RF module solution, the module can implement a one-transmit-one-receive (1T1R) system. To improve the RF module's receiving sensitivity, a one-transmit-two-receive (1T2R) system can be adopted. In this case, the first, third, fifth, and sixth channels form the main set within the module. By adding a diversity channel within the RF module, the 1T2R function can be implemented.

[0145] like Figure 3 As shown, the antenna port is further coupled to a DRX port, which is configured to connect to an external discrete device or module such as a low noise amplifier to serve as a diversity receiving part.

[0146] At the same time, in order to facilitate dual-path reception, the antenna port may include a first antenna port ANT1 and a second antenna port ANT2, and the radio frequency module may further include a seventh switch SW7.

[0147] Optionally, the seventh switch SW7 may be a double-pole double-throw switch. In this case, the first path and the DRX port may be selectively coupled to the first antenna port ANT1 or the second antenna port ANT2.

[0148] Figure 4 This is a schematic diagram of the structure of the second radio frequency module provided in this embodiment.

[0149] like Figure 4 As shown, in order to further improve the integration of the module, the diversity and main set connected to the DRX port can be integrated to realize the 1T2R system function.

[0150] Combine Figure 3 and Figure 4 In the RF module, the structure of the main set remains basically unchanged. At this time, the sixth path is coupled to the first external common port TRX1.

[0151] A second receiving path is added to the radio frequency module to achieve diversity by utilizing the added second receiving path.

[0152] The second radio frequency module includes a second path, which can replace the DRX port in the first radio frequency module to form a second receiving path using the second path.

[0153] Exemplarily, the second path is configured to process and output the first downlink signal of the antenna port. In other words, the second path is configured to amplify and filter the input signal of the first downlink signal of the antenna port to obtain and output the output signal of the first downlink signal.

[0154] It is worth noting that the input signal of the first downlink signal and the output signal of the first downlink signal are both RF signals. At the same time, the output signal of the first downlink signal is a signal after amplification and filtering, and the power level of the output signal of the first downlink signal is greater than the power level of the input signal of the first downlink signal.

[0155] Optionally, the output end of the second path can be coupled to the second output port OUT2. The second output port OUT2 is configured to output the output signal of the first downlink signal. The power level of the first downlink signal is the same as the power level of the first uplink signal. The first downlink signal can be a low-frequency GSM reception signal or a low-frequency LTE / NR reception signal. At this time, the first downlink signal can be a radio frequency signal of the first network mode or the second network mode from the antenna port. It can be understood that in other radio frequency modules, the first downlink signal can also be a signal of other network modes or a radio frequency signal of other frequency bands.

[0156] Optionally, the second downlink signal includes a radio frequency signal of the first network mode and / or a radio frequency signal of the second network mode received by the antenna port.

[0157] Exemplarily, along the signal transmission direction of the first downlink signal, the second path includes a fifth switch SW5 , a fourth filtering module, a sixth switch SW6 , and a second low noise amplifier module LNA2 , which are coupled in sequence.

[0158] The first antenna port ANT1 or the second antenna port ANT2 is configured to output the input signal of the first downlink signal to the seventh switch SW7 .

[0159] The seventh switch SW7 is configured to output the input signal of the first downlink signal to the fifth switch SW5 .

[0160] The fifth switch SW5 is configured to output the input signal of the first downlink signal to the fourth filtering module.

[0161] Specifically, the fourth filtering module may include a plurality of fourth filters F4 of different frequency bands.

[0162] Optionally, the fourth filter F4 may be a bandpass filter. The frequency bands of the fourth filter F4 may include frequency bands such as n5 / n26, n8, and n12.

[0163] It is worth noting that in Figure 4 The fourth filters F4 of all frequency bands are not shown in the figure. The number and frequency band types of the fourth filters F4 can be selected according to the actual transmitted signals and are not limited in this embodiment.

[0164] The number and frequency bands of the fourth filters F4 can correspond to the number and frequency bands of the third filters F3. In this way, the second path and the fifth path can receive downlink signals at the same time to improve the sensitivity of the RF module.

[0165] The fourth filter F4 is configured to filter the input signal of the first downlink signal to obtain a second filtered signal. The sixth switch SW6 is configured to transmit the second filtered signal to the input end of the second low noise amplifier module LNA2.

[0166] Accordingly, the sixth switch SW6 can be a single-pole, multi-throw switch. The multiple ports of the sixth switch SW6 can be coupled to the outputs of the fourth filter F4 in different frequency bands, thereby transmitting the second filtered signal. A single port of the sixth switch SW6 is coupled to the input of the second low-noise amplifier module LNA2 to output the second filtered signal to the second low-noise amplifier module LNA2.

[0167] Furthermore, the second low-noise amplifier module LNA2 may include one or more low-noise amplifiers. If there is one low-noise amplifier, the low-noise amplifier is a high-bandwidth low-noise amplifier, thereby being able to achieve full coverage of the low-frequency bands of GSM receive signals and LTE / NR receive signals, thereby facilitating amplification of low-frequency band GSM receive signals and LTE / NR receive signals.

[0168] The second low noise amplifier module LNA2 is configured to amplify the second filtered signal to obtain an output signal of the first downlink signal, and output the output signal to the second output port OUT2.

[0169] It is understood that when the first downlink signal is a radio frequency signal of the first network, the second low-noise amplifier module LNA2 amplifies the second filtered signal to obtain a radio frequency signal of the first network mode. When the first downlink signal is a radio frequency signal of the second network, the second low-noise amplifier module LNA2 amplifies the first filtered signal to obtain a radio frequency signal of the second network mode.

[0170] In summary, for the downlink path (receive path) of the first downlink signal, the antenna port can receive an input signal of the first downlink signal and transmit it to the fifth switch SW5. The fifth switch SW5 switches the input signal of the first downlink signal to the corresponding fourth filter F4. At this time, the fourth filter F4 can filter the input signal of the first downlink signal to obtain a second filtered signal, which is output to the sixth switch SW6. In this way, the second filtered signal can be output to the second low-noise amplifier module LNA2 through the sixth switch SW6. The second low-noise amplifier module LNA2 amplifies the second filtered signal to obtain the output signal of the first downlink signal, completing the signal reception process.

[0171] It is worth noting that the input signal of the first downlink signal received by the antenna port, the second filtered signal and the processed output signal of the first downlink signal can be collectively referred to as the first downlink signal received by the antenna port and output by the second output port OUT2.

[0172] In order to further improve the flexibility of the RF module, the RF module also includes a fourth path.

[0173] The fourth path is coupled to the multi-port side of the fifth switch SW5 and is configured to output the third uplink signal input to the antenna port, or output the third downlink signal input to the antenna port.

[0174] The power level of the third uplink signal is greater than the power level of the first uplink signal, and the power level of the third uplink signal is less than the power level of the second uplink signal. The power level of the third uplink signal is equal to the power level of the fourth uplink signal. The power level of the third uplink signal is much greater than the power level of the first downlink signal.

[0175] Among them, the third uplink signal is a signal that has been externally processed, and the third downlink signal is also externally processed. The RF module does not process the third uplink signal and the third downlink signal.

[0176] Optionally, the fourth path may be coupled to the second external common port TRX2. The second external common port TRX2 is configured to input the third uplink signal to the fourth path, or receive the third downlink signal of the fourth path.

[0177] This allows the fourth path to be used as a universal path for connecting to other external devices or systems. The external common port can support different types of communication interfaces and functions, such as external antennas, sensors, and expansion modules, providing flexibility and scalability for the module to meet diverse application requirements and interact and communicate with other devices or systems.

[0178] It can be understood that the third uplink signal via the second external common port TRX2 is a radio frequency signal processed by an external structure, and the third downlink signal via the second external common port TRX2 will be processed by the external structure to obtain a corresponding radio frequency signal.

[0179] The RF module further includes a second coupling module C2 coupled between the fifth switch SW5 and the antenna port. The second coupling module C2 is configured to detect and output the power of the third uplink signal transmitted to the antenna port through the fifth switch SW5.

[0180] The second coupling module C2 may include a coupler and a second coupling port CPL2. The coupler is coupled between the fifth switch SW5 and the antenna port to detect the power of the third uplink signal. The second coupling port CPL2 is coupled to the coupler so that data detected by the coupler can be transmitted to a calibration system to facilitate power correction of the third uplink signal.

[0181] At this time, the second type of RF module includes two public external paths, one main channel, one diversity channel and two coupling modules.

[0182] In the radio frequency module, the second switch SW2 , the third switch SW3 , the fourth switch SW4 , the fifth switch SW5 , and the sixth switch SW6 are all single-pole multi-throw switches.

[0183] Figure 5 This is a basic structural diagram of a single-pole multi-throw switch provided in this embodiment.

[0184] like Figure 5 As shown, for a single-pole multi-throw switch, its basic structure includes multiple paths, each of which includes a series transistor branch and a parallel transistor branch. The series transistor branch and the parallel transistor branch are both formed by connecting several stages of active transistors in sequence.

[0185] For example, consider a single-pole, multi-throw switch (SPMT) with a single-port side as the input and a multi-port side as the output. The SPMT switch includes one switch input and X switch outputs. A series transistor branch and a parallel transistor branch are provided between the switch input and each switch output. The series transistor branch has two ends coupled to the switch input and the switch output, respectively. The parallel transistor branch has one end coupled to the switch output and the other end grounded.

[0186] It is understandable that when the transmission direction of the signal changes, the single-port side may also be the output end, and the multi-port side may also be the input end, but the conduction mode of the branch is the same.

[0187] For example, the path between the switch input terminal and the switch output terminal 1 is a working path, and the other paths are non-working paths.

[0188] In the working path, the series transistor branch 1 is turned on and the parallel transistor branch 1 is turned off, so that the signal at the switch input end can be transmitted to the switch output port 1 via the series transistor branch 1 .

[0189] To prevent signal transmission to other paths, the non-operating path's series transistor branch 2 to series transistor branch X is disconnected, while the parallel transistor branch 2 to parallel transistor branch X is connected. In other words, except for the operating path, the series branches of all non-operating paths are disconnected, while the parallel branches are connected. This allows the non-operating paths to be protected by the parallel transistor branches. If the series transistor branch that should have been disconnected breaks down, the signal can be grounded through the parallel transistor branch, thus preventing any impact on the signal transmission path.

[0190] In a single-pole, multi-throw (SPMT) switch, whether it's a series transistor branch or a parallel transistor branch, the number of transistor stages within it is limited. Consequently, in the open state, the voltage swing that the branches can withstand is limited. If the signal power passing through the SPMT switch is high, and the voltage swing that the branches can withstand is lower than the signal power requirement, breakdown can occur, causing the branch that should have been open to become open, thus affecting the signal transmission path.

[0191] Specifically, for the working path, series transistor branch 1 is on, while shunt transistor branch 1 is off. If the voltage swing that shunt transistor branch 1 can withstand is less than the power requirement of the signal, shunt transistor branch 1 will break down, causing shunt transistor branch 1 to turn on. In this case, the signal will directly pass through shunt transistor branch 1 to ground, and will not be able to be transmitted to the designated structure.

[0192] Therefore, for the working path, the parallel transistor branch cannot be broken down and needs to be able to meet the power level requirement of the signal being conducted.

[0193] For example, in a non-operating path, series transistor branch 2 is open, while shunt transistor branch 2 is conducting. If the voltage swing that series transistor branch 2 can withstand is less than the power requirement of the signal, series transistor branch 2 will break down, causing series transistor branch 2 to conduct. In this case, the signal will directly transmit through series transistor branch 2 in the non-operating path to shunt transistor branch 2 and then to ground, rather than being transmitted to the designated structure.

[0194] Therefore, for the non-working path, the series transistor branch cannot be broken down, which needs to be able to meet the power level requirement of the signal being conducted.

[0195] It can be seen that both active and non-active circuits need to withstand signal power requirements. Regardless of whether it is a series transistor branch or a parallel transistor branch, as long as the number of active transistors is sufficient, the voltage swing it can withstand is larger, and thus it can withstand greater signal power.

[0196] However, since the number of active transistors increases, the size of the switch increases, resulting in a corresponding increase in the size of the entire module, affecting the integration and miniaturization design of the module.

[0197] Furthermore, SPMT switches introduce insertion loss into the signal. Specifically, when the series transistor branch is conducting, the signal passes through each of the series active transistors. This process incurs additional signal loss, known as insertion loss.

[0198] Insertion loss can affect the RF performance of the RF module, such as insufficient transmitted RF signal power.

[0199] When operating in the uplink, insertion loss causes a certain degree of signal power reduction, reducing efficiency and thus increasing transmit power consumption. When operating in the downlink, insertion loss deteriorates the signal's noise figure, resulting in a decrease in signal reception sensitivity.

[0200] In this case, one approach is to reduce the number of active transistors to lower insertion loss. Another approach is to increase the gate width of the active transistors to reduce the on-resistance and thus improve insertion loss, given a fixed number of active transistors in the SPMT switch.

[0201] In the second method mentioned above, the gate width of the series transistor is much larger than that of the parallel transistor, which means that the insertion loss of the series transistor is smaller than that of the parallel transistor. This also means that the area of the series transistor is much larger than that of the parallel transistor. Therefore, if you want to increase the gate width by adding series transistors, the overall size of the SPMT switch will increase. If you want to reduce the size by reducing the number of series transistors, the overall insertion loss of the SPMT switch will increase. In this case, for the SPMT switch, considering both the overall size and insertion loss will make the switch structure design difficult.

[0202] More importantly, for a single-pole, multi-throw switch, the more paths it can switch, the greater the risk of energy leakage in the conducting branches within the switch. For branches containing the same number of series transistors, the more paths the switch can switch, the greater the insertion loss caused by the series transistors.

[0203] In this embodiment, the multi-port side of the second switch SW2, the fourth switch SW4, and the sixth switch SW6 is coupled only to the filter. In this case, only the first uplink signal passes through the second switch SW2, only the second downlink signal passes through the fourth switch SW4, and only the first downlink signal passes through the sixth switch SW6. Furthermore, the power levels of the first uplink signal, the first downlink signal, and the second downlink signal are all relatively low. This reduces the power levels required to be handled by the second switch SW2, the fourth switch SW4, and the sixth switch SW6, resulting in a relatively simple structure and smaller overall size, while also minimizing signal power loss.

[0204] The third switch SW3 is responsible for transmitting the first, second, second, fourth, and fourth uplink signals. Furthermore, because the power level of the second uplink signal is greater than that of the fourth uplink signal, the power level of the fourth uplink signal is greater than that of the first and second downlink signals. Therefore, the structural design of the third switch SW3 must be able to handle the power levels of the second and fourth uplink signals. This results in a more complex structure, larger size, and greater power loss than the second switch SW2.

[0205] The first downlink signal, the third uplink signal, and the third downlink signal all pass through the fifth switch SW5. Furthermore, because the power level of the third uplink signal is greater than the power levels of the first and third downlink signals, the structural design of the fifth switch SW5 must be able to handle the power level of the third uplink signal. This makes the structure of the fifth switch SW5 more complex and larger than that of the second switch SW2, resulting in greater power loss.

[0206] From the above description, it can be seen that the benefits brought by adjusting the structures of the third switch SW3 and the fifth switch SW5 should be significantly greater than those of the second switch SW2 , the fourth switch SW4 and the sixth switch SW6 .

[0207] The number of transistor stages and insertion loss of the third switch SW3 and the fifth switch SW5 are analyzed below.

[0208] Specifically, the following takes the case where the number of duplexers formed by the first filter F1 and the second filter F2 is N and the number of fourth filters F4 is N as an example, where N is a positive integer, to calculate the number of active transistor stages and insertion loss of the third switch SW3 and the fifth switch SW5.

[0209] The power of the second uplink signal is relatively high and can be set to level H (High), where the value range of H is 13 to 15.

[0210] The power of the first uplink signal is medium, and can be set to level M (Middle), where the value range of M is 9 to 11.

[0211] The power of the third uplink signal and the fourth uplink signal is medium and can be set to M level.

[0212] The power of the first downlink signal, the second downlink signal, the third downlink signal, and the fourth downlink signal is relatively low and can be set to level L (Low). The value range of L is 3 to 5 levels.

[0213] Among them, H>M>L.

[0214] Figure 6 This embodiment provides Figure 4 Schematic diagram of the structure of the third switch in .

[0215] Combine Figure 4 and Figure 6As shown, the third switch SW3 includes a first port a, a second port b, N third ports c, and a fourth port d. The first port a is coupled to the seventh switch SW7, the second port b is coupled to the sixth path, each of the N third ports c is coupled to a duplexer, and the fourth port d is coupled to the output of the second filter F2. In this case, the third switch SW3 is a single-pole (N+2) throw switch.

[0216] Because the second and fourth uplink signals have higher power levels among the signals passing through the third switch SW3, the power level requirements of the second and fourth uplink signals should be considered first in the design of the third switch SW3. In the subsequent description, the structure of the third switch SW3 will be analyzed based solely on the power level requirements of the second and fourth uplink signals.

[0217] When the first port a and the second port b are conductive, the third switch SW3 can be used to transmit a fourth uplink signal or a fourth downlink signal. In this case, the series transistor branch between the first port a and the second port b needs to be conductive, the parallel transistor branch connected to the second port b needs to be disconnected, and the series transistor branches between the first port a and the N third ports c and the fourth port d are all disconnected, while the parallel transistor branches are all conductive.

[0218] From the above analysis of the basic structure of a single-pole, multi-throw switch, it can be seen that when the first port a and the second port b are conducting, the parallel transistor branch coupled to the second port b must meet the power level of the fourth uplink signal. In this case, the power level of the fourth uplink signal is M, and the parallel transistor level between the first port a and the second port b is also M to prevent the parallel transistor branch from breaking down. The number of levels of the series transistor branch between the first port a and the second port b needs to take into account the power level of the signals passing through other ports. For the fourth uplink signal, it is sufficient that the series transistor branch between the first port a and the second port b can be conducting.

[0219] When the first port a and the second port b are conducting, the series transistor branches between the first port a and the remaining ports must be disconnected, and the parallel transistor branches must be open. To prevent breakdown of the series transistor branches between the first port a and the remaining ports, the series transistors between the first port a and the remaining ports must be at least Class M.

[0220] When the first port a and the fourth port d are conductive, the third switch SW3 can be used to transmit the second uplink signal. In this case, the series transistor branch between the first port a and the fourth port d needs to be conductive, the parallel transistor branch connected to the fourth port d needs to be disconnected, and the series transistor branches between the first port a and the N third ports c and the second port b are all disconnected, while the parallel transistor branches are all conductive.

[0221] From the above analysis of the basic structure of a single-pole, multi-throw switch, it can be seen that when the first port a and the fourth port d are conductive, the parallel transistor branch coupled to the fourth port d must meet the power level of the second uplink signal. In this case, the power level of the second uplink signal is H, and the parallel transistor branch between the first port a and the fourth port d is also H to prevent breakdown of the parallel transistor branch. The number of stages of the series transistor branch between the first port a and the fourth port d needs to take into account the power level of the signals passing through other ports. For the second uplink signal, it is sufficient that the series transistor branch between the first port a and the fourth port d can be conductive.

[0222] When the first port a and the fourth port d are conducting, the series transistor branches between the first port a and the remaining ports must be disconnected, and the parallel transistor branches must be open. To prevent breakdown of the series transistor branches between the first port a and the remaining ports, the series transistors between the first port a and the remaining ports must be at least Class H. Since H is greater than M, the series transistors between the first port a and the remaining ports can be determined to be Class H.

[0223] As can be seen from the above description, for the third switch SW3, the series transistors between the first port a and the fourth port d are of M class, and the parallel transistors are of H class. The series transistors between the first port a and the N third ports c and the second port b are all of H class, and the parallel transistors are all of M class.

[0224] At this time, the total number of series-connected transistors in the third switch SW3 is M+(N+1)*H, and the total number of parallel-connected transistors is H+(N+1)*M.

[0225] The insertion loss performance can be evaluated by counting the number of stages of each series transistor. The insertion loss of the third switch SW3 for each signal is shown in Table 1 below:

[0226] Table 1

[0227]

[0228] Figure 7 This embodiment provides Figure 4 Schematic diagram of the structure of the fifth switch in .

[0229] Combine Figure 4 and Figure 7As shown, the fifth switch SW5 includes a fifth port e, a sixth port f, and N seventh ports g. The fifth port e is coupled to the seventh switch SW7, the sixth port f is coupled to the sixth path, and each of the N seventh ports g is coupled to a fourth filter F4. In this case, the fifth switch SW5 is a single-pole (N+1) throw switch.

[0230] Because the third uplink signal has a higher power level among the signals passing through the fifth switch SW5, the third downlink signal and the first downlink signal have the same power level. When designing the fifth switch SW5, the power level requirements of the third uplink signal and the first downlink signal can be considered first. In the subsequent description, the structure of the fifth switch SW5 will be analyzed based solely on the power level requirements of the third uplink signal and the first downlink signal.

[0231] When the fifth port e and the sixth port f are conductive, the fifth switch SW5 can be used to transmit a third uplink signal or a third downlink signal. In this case, the series transistor branch between the fifth port e and the sixth port f needs to be conductive, and the parallel transistor branch connected to the sixth port f needs to be disconnected. Simultaneously, the series transistor branches between the fifth port e and the N seventh ports g are all disconnected, and the parallel transistor branches are all conductive.

[0232] From the above analysis of the basic structure of a single-pole, multi-throw switch, it can be seen that when the fifth port e and the sixth port f are conducting, the parallel transistor branch coupled to the sixth port f must meet the power level of the third uplink signal. In this case, the power level of the third uplink signal is Class M, and the parallel transistor branch between the fifth port e and the sixth port f is also Class M to prevent breakdown of the parallel transistor branch. The number of levels of the series transistor branch between the fifth port e and the sixth port f needs to take into account the power level of the signals passing through other ports. For the third uplink signal, it is sufficient that the series transistor branch between the fifth port e and the sixth port f can be conducting.

[0233] When the fifth port e and the sixth port f are conducting, the series transistor branches between the fifth port e and the remaining ports must be disconnected, and the parallel transistor branches must be open. To prevent breakdown of the series transistor branches between the fifth port e and the remaining ports, the series transistors between the fifth port e and the remaining ports must be of at least Class M.

[0234] When the fifth port e and one of the seventh ports g are conductive, the fifth switch SW5 can be used to transmit the first downlink signal. In this case, the series transistor branch between the fifth port e and the seventh port g needs to be conductive, the parallel transistor branch connected to the seventh port g needs to be disconnected, and the series transistor branches between the fifth port e and the sixth port f and the remaining seventh ports g are all disconnected, while the parallel transistor branches are all conductive.

[0235] From the above analysis of the basic structure of a single-pole, multi-throw switch, it can be seen that when the fifth port e and one of the seventh ports g are conducting, the parallel transistor branch coupled to the seventh port g must meet the power level of the first downstream signal. In this case, the power level of the first downstream signal is L, and the parallel transistor branch between the fifth port e and the seventh port g is also L to prevent breakdown of the parallel transistor branch. The number of stages of the series transistor branch between the fifth port e and the seventh port g must take into account the power level of the signals passing through other ports. For the first downstream signal, the series transistor branch between the fifth port e and the seventh port g only needs to be able to conduct.

[0236] When the fifth port e and the seventh port g are conducting, the series transistor branches between the fifth port e and the remaining ports must be disconnected, and the parallel transistor branches must be open. To prevent breakdown of the series transistor branches between the fifth port e and the remaining ports, the series transistor level between the fifth port e and the remaining ports must be at least L. Since M is greater than L, the series transistor level between the fifth port e and the remaining ports can be determined to be M.

[0237] As can be seen from the above description, for the fifth switch SW5, the series transistors between the fifth port e and the sixth port f are L-class, and the parallel transistors are M-class. The series transistors between the fifth port e and the N seventh ports g are all M-class, and the parallel transistors are all L-class.

[0238] At this time, the total number of series-connected transistors in the fifth switch SW5 is L+NM, and the total number of parallel-connected transistors is NL+M.

[0239] The insertion loss performance can be evaluated by counting the number of stages of each series transistor. The insertion loss of the fifth switch SW5 for each signal is shown in Table 2 below:

[0240] Table 2

[0241]

[0242] In the RF module, in addition to the third switch SW3 and the fifth switch SW5 passing many signals, the seventh switch SW7 coupled to the antenna port needs to transmit even more signals.

[0243] The number of transistor stages and insertion loss of the seventh switch SW7 are analyzed below.

[0244] exist Figure 4 In the RF module shown, the seventh switch SW7 is a double-pole double-throw switch.

[0245] Figure 8 This embodiment provides Figure 4 Schematic diagram of the structure of the seventh switch in .

[0246] Combine Figure 4 and Figure 8 As shown, the seventh switch SW7 includes an eighth port h, a ninth port i, a tenth port j, and an eleventh port k. The eighth port h and the ninth port i are coupled to the first antenna port ANT1 and the second antenna port ANT2, respectively. The tenth port j is coupled to the first port a. The eleventh port is coupled to the fifth port e.

[0247] The eighth port h can be selectively connected to the tenth port j and the eleventh port k, and the ninth port can be selectively connected to the tenth port j and the eleventh port k.

[0248] Specifically, when the eighth port h and the tenth port j are conductive, the third switch SW3 may output the first uplink signal to the first antenna port ANT1, or the third switch SW3 may output the second uplink signal to the first antenna port ANT1, or the third switch SW3 may output the fourth uplink signal to the first antenna port ANT1. Furthermore, the first antenna port ANT1 may output the second downlink signal to the third switch SW3, or the first antenna port ANT1 may output the fourth downlink signal to the third switch SW3.

[0249] Among the signals passing between the eighth port h and the tenth port j, the second uplink signal has the highest power level. In this case, the number of transistor stages between the eighth port h and the tenth port j can give priority to the second uplink signal.

[0250] When the eighth port h and the tenth port j are conductive, the second upstream signal can reach the eighth port h from the tenth port j through point y, the q branch, and point u in sequence. In this case, the series transistor branch through which the second upstream signal passes is the series transistor branch of the q branch. The parallel transistor branches through which the second upstream signal passes include the parallel transistor branch between the tenth port j and point y, and the parallel transistor branch between the eighth port h and point u.

[0251] At this time, the parallel transistor branch through which the second uplink signal passes should be open circuited to meet the power level of the second uplink signal. Therefore, the level of the parallel transistor branch between the tenth port j and point y is H, and the level of the parallel transistor branch between the eighth port h and point u is also H.

[0252] The series transistor branch through which the second uplink signal passes is the q-branch, and the level of the series transistor branch needs to be determined according to other signals.

[0253] When the second uplink signal is output from the tenth port j and reaches point y, branch o is disconnected and branch q is connected. At this time, the series transistor of branch o is of class H to prevent branch o from being broken down and affecting the transmission of the second uplink signal.

[0254] When the second uplink signal reaches point u from point y via branch q, branch p is disconnected, and the parallel transistor branch between point u and the eighth port h is disconnected, and the second uplink signal is directly output to the first antenna port ANT1. At this time, branch p is connected to the eleventh port k.

[0255] In order to prevent the second uplink signal from being conducted from the p branch to the eleventh port k, the p branch needs to be ensured not to be broken down, thereby avoiding affecting the fifth switch SW5. At this time, the series transistor level of the p branch is H level.

[0256] In order to prevent the second uplink signal from being grounded through the parallel transistor branch between point u and the eighth port h, the parallel transistor branch needs to be ensured not to be broken down, thereby avoiding affecting the second uplink signal.

[0257] When the ninth port i is connected to the tenth port j, the situation is similar to the above situation and will not be described in detail here.

[0258] Specifically, when the eighth port h and the eleventh port k are conductive, the fifth switch SW5 may output the third uplink signal to the first antenna port ANT1. Alternatively, the first antenna port ANT1 may output the first downlink signal to the fifth switch SW5, or the first antenna port ANT1 may output the third downlink signal to the fifth switch SW5.

[0259] Among the signals passing between the eighth port h and the eleventh port k, the third uplink signal has the highest power level. In this case, the number of transistor stages between the eighth port h and the eleventh port k can give priority to the third uplink signal.

[0260] When the eighth port h and the eleventh port k are conductive, the third uplink signal can travel from the eleventh port k through point v, the p branch, and then to point u, reaching the eighth port h. In this case, the series transistor branch through which the third uplink signal travels is the series transistor branch of the r branch. The parallel transistor branches through which the third uplink signal travels include the parallel transistor branch between the eleventh port k and point v, and the parallel transistor branch between the eighth port h and point u.

[0261] At this point, the parallel transistor branch through which the third uplink signal passes should be open circuited and must meet the power level of the third uplink signal. Therefore, the level of the parallel transistor branch between the eleventh port k and point v is M, and the level of the parallel transistor branch between the eighth port h and point u has been determined based on the second uplink signal.

[0262] The series transistor branch through which the third uplink signal passes is a p-branch, and the level of the series transistor branch has been determined according to the second uplink signal.

[0263] It is understandable that when designing the seventh switch SW7 , the insertion loss of the second uplink signal needs to be considered first, and the signals of the other ports can be adaptively adjusted.

[0264] When the ninth port i is connected to the eleventh port k, the situation is similar to the above situation and will not be described in detail here.

[0265] At this time, the total number of series-connected transistors in the seventh switch SW7 is 4H, and the total number of parallel-connected transistors is 3H+M.

[0266] The insertion loss performance can be evaluated by counting the number of stages of each series transistor. The insertion loss of the seventh switch SW7 for each signal is shown in Table 3 below:

[0267] Table 3

[0268]

[0269] According to the above description, the total number of transistors in series of the third switch SW3, the fifth switch SW5, and the seventh switch SW7 is: (N+5)*H+(N+1)*M+L, and the total number of transistors in parallel of the third switch SW3, the fifth switch SW5, and the seventh switch SW7 is: (N+3)*M+4H+NL

[0270] As can be seen from the above description, the number of switchable paths, the number of series transistors, and the number of parallel transistors in the third, fifth, and seventh switches SW3, SW5, and SW7 all affect switch size and insertion loss. Therefore, by properly designing the connection methods for each path within the RF module, and thus the structure of each switch, insertion loss can be reduced while also reducing switch size.

[0271] In order to achieve the above objectives, this embodiment provides a third radio frequency module.

[0272] Figure 9 This is a schematic structural diagram of the third RF module provided in this embodiment.

[0273] Combine Figure 4 and Figure 9 It can be seen that the comparison Figure 4 In the third RF module, a first switch SW1 is added. Since the signals passing through the third and fourth paths have higher power levels, they can be coupled to the first switch SW1. This allows the higher-power second uplink signal from the third switch SW3 to be separated, while the higher-power third uplink signal from the fifth switch SW5 to be separated. At this point, the third downlink signal also follows the transformation of the fourth path.

[0274] At this time, the uplink path of the second uplink signal is as follows: it is input from the second input port IN, amplified by the second power amplifier module, filtered by the second filter, transmitted through the first switch SW1 to the seventh switch SW7, and then transmitted to the antenna port. The uplink path of the third uplink signal is as follows: it is input from the second external port TRX2, transmitted through the first switch SW1 to the seventh switch SW7, and then transmitted to the antenna port. The downlink path of the third downlink signal is as follows: it is input from the antenna port, transmitted through the seventh switch SW7 to the first switch SW1, and then output from the second external port TRX2.

[0275] In this way, the first switch SW1 can be used to separate the signals with higher power levels in the third switch SW3 and the fifth switch SW5, thereby simplifying the structure of the third switch SW3 and the fifth switch SW5, reducing the size of the third switch SW3 and the fifth switch SW5, reducing the insertion loss of the third switch SW3 and the fifth switch SW5, and improving the transmission efficiency of the RF module.

[0276] Furthermore, by switching the fourth path from the fifth switch SW5 to the first switch SW1, the second coupling module C2 can be removed, and a third coupling module C3 can be provided between the first switch SW1 and the seventh switch SW7. The third coupling module C3 is coupled between the first switch SW1 and the antenna port. The third coupling module C3 is configured to detect the power of the second uplink signal and the third uplink signal transmitted to the antenna port via the first switch SW1.

[0277] The third coupling module C3 may include a coupler and a third coupling port CPL3. The coupler is coupled between the third switch SW3 and the antenna port to detect the power of the second and third uplink signals. The third coupling port CPL3 is coupled to the coupler so that data detected by the coupler can be transmitted to a calibration system to facilitate power calibration of the second and third uplink signals.

[0278] Furthermore, in the radio frequency module, not only is a first switch SW1 added, but the structures of the third switch SW3 , the fifth switch SW5 , and the seventh switch SW7 will also change accordingly.

[0279] Figure 4 The third switch SW3 is a single-pole (N+2) throw switch. Figure 9 The third switch SW3 is a single-pole (N+1) throw switch, which reduces one path. Figure 4 The fifth switch SW5 is a single-pole (N+1) throw switch. Figure 9 The fifth switch SW5 is a single-pole N-throw switch, which reduces one path.

[0280] For the third and fifth switches SW3 and SW5, after splitting the higher-power signals, firstly, the number of paths in the third and fifth switches SW3 and SW5 is reduced, reducing their overall size and lowering the risk of signal leakage. Secondly, the power level that the third and fifth switches SW3 and SW5 need to withstand is reduced. This reduces the number of transistor stages within the third and fifth switches SW3 and SW5, reducing their overall size and insertion loss.

[0281] The following Figure 9 The number of transistor stages and insertion losses of the first switch SW1, the third switch SW3, the fifth switch SW5, and the seventh switch SW7 are analyzed.

[0282] Figure 10 This embodiment provides Figure 9 Schematic diagram of the structure of the third switch in .

[0283] Combine Figure 9 and Figure 10 The third switch SW3 includes a first port a, a second port b, and N third ports c. The first port a is coupled to the seventh switch SW7, and the second port b is coupled to the sixth path. Each of the N third ports c is coupled to a duplexer. In this case, the third switch SW3 is a single-pole (N+1) throw switch.

[0284] The signals passing through the third switch SW3 include a first uplink signal, a second downlink signal, a fourth uplink signal and a fourth downlink signal. The power levels of the first uplink signal and the fourth uplink signal are at most M, and the power levels of the other signals are L.

[0285] Through Figure 4 From the analysis of the basic structure of the third switch SW3 shown in FIG, it can be seen that Figure 9 In the third switch SW3, the series transistors between the first port a and the second port b and the N third ports c are all M-level, and the parallel transistors are all M-level.

[0286] At this time, the total number of series-connected transistors in the third switch SW3 is (N+1)*M, and the total number of parallel-connected transistors is (N+1)*M.

[0287] The evaluation of insertion loss performance can be characterized by counting the number of stages of each series transistor. Figure 9 The insertion loss of the third switch SW3 for each signal is shown in Table 4:

[0288] Table 4

[0289]

[0290] Figure 11This embodiment provides Figure 9 Schematic diagram of the structure of the fifth switch in .

[0291] Combine Figure 9 and Figure 11 As shown, the fifth switch SW5 includes a fourth port d and N fifth ports e. The fourth port d is coupled to the seventh switch SW7, and each of the N fifth ports e is coupled to a fourth filter F4. In this case, the fifth switch SW5 is a single-pole, N-throw switch.

[0292] The signal passing through the fifth switch SW5 is only the first downlink signal, which has a low power level, namely, level L.

[0293] Through Figure 4 From the analysis of the basic structure of the fifth switch SW5 shown in FIG, it can be seen that Figure 9 In the fifth switch SW5, the series transistors between the fourth port d and each fifth port e are all L-level, and the parallel transistors are also all L-level.

[0294] At this time, the total number of series-connected transistors in the fifth switch SW5 is NL, and the total number of parallel-connected transistors is NL.

[0295] The insertion loss performance can be evaluated by counting the number of stages of each series transistor. The insertion loss of the fifth switch SW5 for each signal is shown in Table 5 below:

[0296] Table 5

[0297] Signal name First downlink signal Insertion loss / level L

[0298] exist Figure 9 In the solution, in addition to the changes in the structures of the third switch SW3 and the fifth switch SW5, a first switch SW1 is added.

[0299] The following Figure 9 The number of transistor stages and insertion loss of the first switch SW1 in FIG.

[0300] Figure 12 This embodiment provides Figure 9 Schematic diagram of the structure of the first switch in .

[0301] Combine Figure 9 and Figure 12 As shown, the first switch SW1 is a single-pole double-throw switch, including a sixth port f, a seventh port g, and an eighth port h. The sixth port f is coupled to the seventh switch SW7, the seventh port g is coupled to the output of the second filter F2, and the eighth port h is coupled to the fourth path.

[0302] When the sixth port f and the seventh port g are conductive, the second uplink signal can be transmitted to the seventh switch SW7 via the first switch SW1. When the sixth port f and the eighth port h are conductive, the third uplink signal can be transmitted to the seventh switch SW7 via the first switch SW1, or the third downlink signal in the seventh switch SW7 is transmitted to the first switch SW1.

[0303] Since the power level of the second uplink signal is H, the power level of the third uplink signal is M, and the power level of the third downlink signal is L, the structural design of the first switch SW1 gives priority to the second uplink signal and the third uplink signal.

[0304] Based on the structural principle of the above-described single-pole multi-throw switch, in the first switch SW1, the series transistor between the sixth port f and the seventh port g is of class M, and the parallel transistor is of class H. The series transistor between the sixth port f and the eighth port h is of class H, and the parallel transistor is of class M.

[0305] At this time, the total number of series-connected transistors in the first switch SW1 is M+H, and the total number of parallel-connected transistors is M+H.

[0306] The insertion loss performance can be evaluated by counting the number of stages of each series transistor. The insertion loss of the first switch SW1 for each signal is shown in Table 6 below:

[0307] Table 6

[0308] Signal name Second uplink signal Third uplink signal / third downlink signal Insertion loss / level M H

[0309] besides, Figure 4 The seventh switch SW7 is a double-pole double-throw switch. Figure 9 The seventh switch SW7 is a double-pole triple-throw switch.

[0310] The following Figure 9 The number of transistor stages and insertion loss of the seventh switch SW7 are analyzed.

[0311] Figure 13 This embodiment provides Figure 9 Schematic diagram of the structure of the seventh switch in .

[0312] Combine Figure 9 and Figure 13 As shown, the seventh switch SW7 includes a ninth port i, a tenth port j, an eleventh port k, a twelfth port l, and a thirteenth port m. The ninth port i and the tenth port j are coupled to the first antenna port ANT1 and the second antenna port ANT2, respectively. The eleventh port k is coupled to the first port a. The twelfth port l is coupled to the fourth port d. The thirteenth port m is coupled to the sixth port f.

[0313] The ninth port i can be selectively connected to the eleventh port k, the twelfth port l and the thirteenth port m, and the tenth port j can be selectively connected to the eleventh port k, the twelfth port l and the thirteenth port m.

[0314] Specifically, when the ninth port i is selectively connected to the eleventh port k, the third switch SW3 may output the first uplink signal to the first antenna port ANT1, or the third switch SW3 may output the fourth uplink signal to the first antenna port ANT1. In addition, the first antenna port ANT1 may output the second downlink signal to the third switch SW3, or the first antenna port ANT1 may output the fourth downlink signal to the third switch SW3.

[0315] When the ninth port i is selectively connected to the twelfth port l, the first antenna port ANT1 may output the first downlink signal to the fifth switch SW5.

[0316] When the ninth port i is selectively connected to the thirteenth port m, the first switch SW1 may output the second uplink signal to the first antenna port ANT1, or the first switch SW1 may output the third uplink signal to the first antenna port ANT1. In addition, the first antenna port ANT1 may output the third downlink signal to the first switch SW1.

[0317] When the tenth port j is selectively connected to the eleventh port k, the twelfth port l, and the thirteenth port m, reference may be made to the above description of the ninth port i, which will not be repeated here.

[0318] Furthermore, the design of the transistor level of each branch of the first switch SW1 can refer to Figure 4 The design description of the seventh switch SW7 in FIG is not repeated here.

[0319] At this time, Figure 9 The total number of series transistors in the seventh switch SW7 is 6H, and the total number of parallel transistors is 3H+2M.

[0320] The insertion loss performance can be evaluated by counting the number of stages of each series transistor. The insertion loss of the seventh switch SW7 for each signal is shown in Table 7 below:

[0321] Table 7

[0322]

[0323] According to the above description, Figure 9, the total number of series-connected transistors of the first switch SW1, the third switch SW3, the fifth switch SW5, and the seventh switch SW7 is: 7H+(N+2)*M+NL, and the total number of parallel-connected transistors of the first switch SW1, the third switch SW3, the fifth switch SW5, and the seventh switch SW7 is: (N+4)*M+4H+NL.

[0324] At this time Figure 4 The total number of series and parallel transistors of the third switch SW3, the fifth switch SW5 and the seventh switch SW7 in the RF module is Figure 9 The comparison of the total number of series and parallel transistors of the first switch SW1, the third switch SW3, the fifth switch SW5, and the seventh switch SW7 in the RF module is shown in Table 8 below:

[0325] Table 8

[0326] Total number of transistors in series Total number of parallel transistors Figure 4 RF modules in (N+5)*H+(N+1)*M+L (N+3)*M+4H+NL Figure 9 RF modules in 7H+(N+2)*M+NL (N+4)*M+4H+NL

[0327] As can be seen from Table 8 above, for the total number of series transistors, when N ≥ 3, the H level decreases, the M level increases, and the L level increases. Since H>M>L, when H, M, and L take their respective ranges of values, the total number of series transistors decreases, while the total number of parallel transistors increases by M. However, since the area of each series transistor is much larger than the area of each parallel transistor, in this case, Figure 9 The RF module in the Figure 4 The RF module in the system is reduced in area size, and the larger the N value is, the more obvious the benefit is.

[0328] Below, when N is equal to 5, L is equal to 6, M is equal to 10, and H is equal to 14, the above Table 8 can be specifically calculated as Table 9:

[0329] Table 9

[0330] Total number of transistors in series Total number of parallel transistors Figure 4 RF modules in 206 166 Figure 9 RF modules in 198 176

[0331] From the comparison in Table 9 above, it can be seen that the total number of series transistors is reduced by 8 levels, and the total number of parallel transistors is increased by 10 levels. However, since the area of each series transistor is much larger than the area of the parallel transistor, Figure 9 The total area of each switch in the RF module is smaller, and the larger the N value, the more obvious the benefit. A larger N value means more filtering frequency bands.

[0332] Figure 4 The third switch SW3, the fifth switch SW5 and the seventh switch SW7 in the RF module have different insertion losses for each signal. Figure 9 The insertion loss comparison of the first switch SW1, the third switch SW3, the fifth switch SW5 and the seventh switch SW7 in the RF module for each signal is shown in Table 10 below:

[0333] Table 10

[0334]

[0335] In Table 10, SP2T is a single-pole double-throw switch, SP(N+1)T is a single-pole N+1 throw switch, SP(N+2)T is a single-pole N+2 throw switch, DPDT is a double-pole double-throw switch, and DP3T is a double-pole triple-throw switch.

[0336] Taking the second uplink signal as an example, Figure 9 and Figure 4 The insertion loss level of the RF modules in the Figure 9 The number of paths through which the second uplink signal passes through the switch is 5. Figure 4 The number of paths through which the second uplink signal passes through the switch is N+4. When N≥2, Figure 9 The number of paths in is less than Figure 4 The number of pathways in Figure 4 , Figure 9 The insertion loss will be smaller.

[0337] The specific insertion loss analysis process of the remaining signals is the same as that of the second uplink signal and will not be repeated here.

[0338] In Table 10, except for the increased insertion loss of the third uplink / downlink signal, the insertion loss of all other signals decreased, maintaining the overall trend of decreasing insertion loss. Furthermore, the third uplink / downlink signal only has one frequency band, which is fewer than the first uplink signal. When the insertion loss of the third uplink / downlink signal increases, it only affects signals in one frequency band. Therefore, the increased insertion loss of the third uplink / downlink signal has minimal impact on the entire RF module.

[0339] In addition, from the comparison in Table 10, we can see that when N is larger, Figure 9 In other words, the more frequency channels a filter has, the greater the insertion loss benefit.

[0340] Figure 14 This is a schematic structural diagram of the fourth RF module provided in this embodiment.

[0341] Combine Figure 9 and Figure 14 It can be seen that Figure 14 and Figure 9 The difference is that the sixth path is coupled to the fifth switch SW5 instead of the third switch SW3.

[0342] In this case, the uplink path of the fourth uplink signal is: input from the first external port TRX1, transmitted through the fifth switch SW5 to the seventh switch SW7, and then transmitted to the antenna port. The downlink path of the fourth downlink signal is: input from the antenna port, transmitted through the seventh switch SW7 to the fifth switch SW5, and then output from the first external port TRX1. Optionally, a second coupling module C2 can be provided between the fifth switch SW5 and the seventh switch SW7 to implement power detection of the fourth uplink signal output by the fifth switch SW5.

[0343] Figure 14 The solution in Figure 9 The third switch SW3 and the fifth switch SW5 in the circuit are swapped. Figure 14 The number of transistor stages and insertion loss of the first switch SW1, the third switch SW3, the fifth switch SW5 and the seventh switch SW7 are the same as those of the first switch SW1, the third switch SW3, the fifth switch SW5 and the seventh switch SW7. Figure 9 The solution is the same as in , so I will not repeat it here.

[0344] Figure 15 This is a schematic structural diagram of the fifth RF module provided in this embodiment.

[0345] Combine Figure 9 and Figure 15 It can be seen that Figure 15 The RF module in the embodiment changes the sixth path from being coupled to the third switch SW3 to being coupled to the first switch SW1. In this case, the first switch SW1 is a single-pole triple-throw switch, the third switch SW3 and the fifth switch SW5 are both single-pole N-throw switches, and the structure of the seventh switch SW7 remains unchanged.

[0346] At this time, the uplink path of the fourth uplink signal is: input from the first external port TRX1, transmitted through the first switch SW1 to the seventh switch SW7, and then transmitted to the antenna port. The downlink path of the fourth downlink signal is: input from the antenna port, transmitted through the seventh switch SW7 to the first switch SW1, and then output from the first external port TRX1.

[0347] Figure 16 This embodiment provides Figure 15 Schematic diagram of the structure of the third switch in .

[0348] Combine Figure 15 and Figure 16 As shown, the third switch SW3 includes a first port a and N second ports b. The first port a is coupled to the seventh switch SW7. Each of the N second ports b is coupled to a duplexer. In this case, the third switch SW3 is a single-pole, N-throw switch.

[0349] The signal passing through the third switch SW3 includes a first uplink signal and a second downlink signal, wherein the power level of the first uplink signal is at most M, and the power levels of the other signals are L.

[0350] Through Figure 4 From the analysis of the basic structure of the third switch SW3 shown in FIG, it can be seen that Figure 15 In the third switch SW3, the series transistors between the first port a and the N second ports b are all of M level, and the parallel transistors are all of M level.

[0351] At this time, the total number of series-connected transistors in the third switch SW3 is NM, and the total number of parallel-connected transistors is NM.

[0352] The evaluation of insertion loss performance can be characterized by counting the number of stages of each series transistor. Figure 15 The insertion loss of the third switch SW3 for each signal is shown in Table 11:

[0353] Table 11

[0354] Signal name First uplink signal Second downlink signal Insertion loss / level M M

[0355] Figure 17 This embodiment provides Figure 15 Schematic diagram of the structure of the fifth switch in .

[0356] Combine Figure 15 and Figure 17 As shown, the fifth switch SW5 includes a third port c and N fourth ports d. The third port c is coupled to the seventh switch SW7, and each of the N fourth ports d is coupled to a fourth filter F4. In this case, the fifth switch SW5 is a single-pole, N-throw switch.

[0357] The signal passing through the fifth switch SW5 is only the first downlink signal, which has a low power level of L.

[0358] Through Figure 4 From the analysis of the basic structure of the fifth switch SW5 shown in FIG, it can be seen that Figure 15 In the fifth switch SW5, the series transistors between the third port c and each fourth port d are all L-level, and the parallel transistors are also all L-level.

[0359] At this time, the total number of series-connected transistors in the fifth switch SW5 is NL, and the total number of parallel-connected transistors is NL.

[0360] The insertion loss performance can be evaluated by counting the number of stages of each series transistor. The insertion loss of the fifth switch SW5 for each signal is shown in Table 12 below:

[0361] Table 12

[0362] Signal name First downlink signal Insertion loss / level L

[0363] Figure 18 This embodiment provides Figure 15 Schematic diagram of the structure of the first switch in .

[0364] Combine Figure 15 and Figure 18 As shown, the first switch SW1 is a single-pole triple-throw switch, including a fifth port e, a sixth port f, a seventh port g, and an eighth port h. The fifth port e is coupled to the seventh switch SW7, the sixth port f is coupled to the output of the second filter F2, the seventh port g is coupled to the fourth path, and the eighth port h is coupled to the sixth path.

[0365] When the fifth port e and the sixth port f are conductive, the second uplink signal can be transmitted to the seventh switch SW7 via the first switch SW1. When the fifth port e and the seventh port g are conductive, the third uplink signal can be transmitted to the seventh switch SW7 via the first switch SW1, or the third downlink signal in the seventh switch SW7 is transmitted to the first switch SW1. When the fifth port e and the eighth port h are conductive, the fourth uplink signal can be transmitted to the seventh switch SW7 via the first switch SW1, or the fourth downlink signal in the seventh switch SW7 is transmitted to the first switch SW1.

[0366] Since the power level of the second uplink signal is H, the power level of the third uplink signal is M, and the power level of the third downlink signal is L, the structural design of the first switch SW1 gives priority to the second uplink signal and the third uplink signal.

[0367] Based on the structural principle of the above-described single-pole multi-throw switch, in the first switch SW1, the series transistor between the fifth port e and the sixth port f is of class M, and the parallel transistor is of class H. The series transistors between the fifth port e and the seventh port g, and between the fifth port e and the eighth port h, are of class H, and the parallel transistors are of class M.

[0368] At this time, the total number of series-connected transistors in the first switch SW1 is M+2H, and the total number of parallel-connected transistors is 2M+H.

[0369] The insertion loss performance can be evaluated by counting the number of stages of each series transistor. The insertion loss of the first switch SW1 for each signal is shown in Table 13 below:

[0370] Table 13

[0371]

[0372] besides, Figure 15The seventh switch SW7 in Figure 9 The seventh switch SW7 is a double-pole triple-throw switch. Figure 15 The transistor grade and insertion loss of the seventh switch SW7 are consistent with those in Table 7 and are not described again here.

[0373] According to the above description, Figure 15 , the total number of series-connected transistors of the first switch SW1, the third switch SW3, the fifth switch SW5, and the seventh switch SW7 is: 8H+(N+1)*M+NL, and the total number of parallel-connected transistors of the first switch SW1, the third switch SW3, the fifth switch SW5, and the seventh switch SW7 is: (N+4)*M+4H+NL.

[0374] At this time Figure 4 The total number of series and parallel transistors of the third switch SW3, the fifth switch SW5 and the seventh switch SW7 in the RF module is Figure 15 The comparison of the total number of series and parallel transistors of the first switch SW1, the third switch SW3, the fifth switch SW5, and the seventh switch SW7 in the RF module is shown in Table 14 below:

[0375] Table 14

[0376] Total number of transistors in series Total number of parallel transistors Figure 4 RF modules in (N+5)*H+(N+1)*M+L (N+3)*M+4H+NL Figure 15 RF modules in 8H+(N+1)*M+NL (N+4)*M+4H+NL

[0377] As can be seen from Table 14 above, for the total number of series transistors, when N ≥ 4, the number of H levels decreases and the number of L levels increases. Since H>M>L, when H, M, and L take their respective ranges of values, the total number of series transistors decreases, while the total number of parallel transistors increases by M. However, since the area of each series transistor is much larger than the area of each parallel transistor, in this case, Figure 15 The RF module in the Figure 4 The RF module in the system is reduced in area size, and the larger the N value is, the more obvious the benefit is.

[0378] Below, when N is equal to 5, L is equal to 6, M is equal to 10, and H is equal to 14, the above Table 14 can be specifically calculated as Table 15:

[0379] Table 15

[0380] Total number of transistors in series Total number of parallel transistors Figure 4 RF modules in 206 166 Figure 15 RF modules in 202 176

[0381] From the comparison in Table 15 above, it can be seen that the total number of series transistors is reduced by 4, and the total number of parallel transistors is increased by 10. However, since the area of each series transistor is much larger than the area of the parallel transistor, Figure 15 The total area of each switch in the RF module is smaller, and the larger the N value, the more obvious the benefit.

[0382] Figure 4The third switch SW3, the fifth switch SW5 and the seventh switch SW7 in the RF module have different insertion losses for each signal. Figure 15 The insertion loss comparison of the first switch SW1, the third switch SW3, the fifth switch SW5 and the seventh switch SW7 in the RF module for each signal is shown in Table 16 below:

[0383] Table 16

[0384]

[0385] In Table 16, SP3T is a single-pole three-throw switch, SPNT is a single-pole N-throw switch, SP(N+1)T is a single-pole N+1-throw switch, SP(N+2)T is a single-pole N+2-throw switch, DPDT is a double-pole double-throw switch, and DP3T is a double-pole three-throw switch.

[0386] Taking the second uplink signal as an example, Figure 15 The insertion loss level of the RF module is M+M. Figure 4 The insertion loss level of the RF module is M+H level. Figure 15 The insertion loss level is reduced. Figure 9 The number of paths through which the second uplink signal passes through the switch is 6. Figure 4 The number of paths through which the second uplink signal passes through the switch is N+4. When N≥2, Figure 15 The number of paths in is less than Figure 4 The number of pathways in Figure 4 , Figure 15 The insertion loss will be further reduced.

[0387] The specific insertion loss analysis process of the remaining signals is the same as that of the second uplink signal and will not be repeated here.

[0388] In Table 16, except for the increased insertion loss of the third uplink / downlink signal, the insertion loss of all other signals decreased, maintaining the overall trend of decreasing insertion loss. Furthermore, the third uplink / downlink signal only has one frequency band, which is fewer than the first uplink signal. When the insertion loss of the third uplink / downlink signal increases, it only affects signals in one frequency band. In this case, the increased insertion loss of the third uplink / downlink signal has minimal impact on the entire RF module.

[0389] In addition, from the comparison in Table 16, we can see that when N is larger, Figure 15 In other words, the more frequency channels a filter has, the greater the insertion loss benefit.

[0390] Figure 19 This is a schematic structural diagram of an electronic device provided by this embodiment.

[0391] like Figure 19 As shown, the electronic device 200 provided in this embodiment includes an antenna 210 and the above-mentioned RF module 100, wherein the antenna 210 is coupled to the antenna port. The electronic device with the above-mentioned RF module has higher communication efficiency and is more convenient to realize miniaturization design.

[0392] Optionally, the electronic device may include one or more antennas. When there are multiple antennas, the number of antenna ports may correspond to the number of antennas. Multiple antennas may be used to receive radio frequency signals of different frequency bands, or multiple antennas may be used to receive different types of signals, which is not limited in this embodiment.

[0393] It should be noted that those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered merely as exemplary, and the true scope of this application is indicated by the claims.

[0394] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A radio frequency module, characterized in that: include: an antenna port, a first switch, a first path, a second path, a third path, and a fourth path; The first path and the second path are selectively coupled to the antenna port; The first path is configured to: process the input first uplink signal and output it to the antenna port; The second path is configured to: process and output the first downlink signal of the antenna port; The third path and the fourth path are switchably coupled to the antenna port via the first switch; The third path is configured to: process the input second uplink signal and output it to the antenna port; The fourth path is configured to: output the input third uplink signal to the antenna port; The power levels of the first uplink signal and the second uplink signal are different, and the power levels of the first downlink signal and the third uplink signal are different.

2. The radio frequency module according to claim 1, wherein: Also includes: The first path is configured to: sequentially amplify and filter the input first uplink signal, and output the signal to the antenna port; The third path is configured to: sequentially amplify and filter the input second uplink signal, and output the signal to the antenna port; The first uplink signal is in a first network mode, the second uplink signal is in a second network mode, and the signal power level of the second network mode is greater than the signal power level of the first network mode.

3. The radio frequency module according to claim 2, wherein: Along the signal transmission direction of the first uplink signal, the first path includes a first power amplification module, a second switch, a first filtering module, and a third switch coupled in sequence; The first filtering module includes a plurality of first filters in different frequency bands; The first power amplifier module is configured to: amplify the input signal of the first uplink signal to obtain a first amplified signal, and output the first amplified signal to the second switch; The second switch is configured to: input the first amplified signal to the first filter of the corresponding frequency band; The first filter is configured to: filter the first amplified signal to obtain an output signal of the first uplink signal, and output the output signal to the third switch; The third switch is configured to output the output signal of the first uplink signal to the antenna port.

4. The radio frequency module according to claim 3, wherein: Also includes: a fifth path, configured to: process and output the second downlink signal of the antenna port; The network mode of the second downlink signal includes the first network mode and the second network mode, and the power level of the second downlink signal is the same as the power level of the first uplink signal.

5. The radio frequency module according to claim 4, characterized in that: Along the signal transmission direction of the second downlink signal, the fifth path includes a third filtering module, a fourth switch and a first low-noise amplifier module coupled in sequence; The third filtering module includes a plurality of third filters having a frequency band corresponding to the frequency band of the first filter, and each of the third filters is coupled between the fourth switch and the third switch; The third switch is configured to: input the input signal of the second downlink signal input from the antenna port to the third filter of the corresponding frequency band; The third filter is configured to: filter the input signal of the second downlink signal to obtain a first filtered signal, and output the first filtered signal to the fourth switch; The fourth switch is configured to: output the first filtered signal to the first low-noise amplification module; The first low-noise amplification module is configured to: amplify the first filtered signal to obtain an output signal of the second downlink signal, and output the output signal.

6. The radio frequency module according to claim 2, wherein: Along the signal transmission direction of the second uplink signal, the third path includes a second power amplification module, a third filtering module, and the first switch coupled in sequence; The second power amplification module is configured to: amplify the input signal of the second uplink signal to obtain a second amplified signal, and output the second amplified signal to the third filtering module; The third filtering module is configured to: filter the second amplified signal to obtain an output signal of the second uplink signal, and output the output signal to the first switch; The first switch is configured to output the output signal of the second uplink signal to the antenna port.

7. The radio frequency module according to claim 3, wherein: The second path is configured to: filter and amplify the first downlink signal of the antenna port in sequence and then output it; The fourth path is configured to: output the input third uplink signal to the antenna port, or output the third downlink signal input to the antenna port; The third uplink signal is a signal processed externally, and the third downlink signal is outputted to the external device through the fourth path for external processing.

8. The radio frequency module according to claim 7, wherein: Along the signal transmission direction of the first downlink signal, the second path includes a fifth switch, a fourth filtering module, a sixth switch and a second low-noise amplifier module coupled in sequence; The fourth filtering module includes a plurality of fourth filters of different frequency bands; The fifth switch is configured to: input the input signal of the first downlink signal input from the antenna port to the fourth filter of the corresponding frequency band; The fourth filter is configured to: filter the input signal of the first downlink signal to obtain a second filtered signal, and output the second filtered signal to the sixth switch; The sixth switch is configured to: output the second filtered signal to the second low-noise amplification module; The second low-noise amplification module is configured to: amplify the second filtered signal to obtain an output signal of the first downlink signal, and output the output signal.

9. The radio frequency module according to claim 8, characterized in that: The radio frequency module further includes a sixth path coupled to the third switch; The sixth path is configured to: output the input fourth uplink signal to the antenna port, or output the fourth downlink signal input to the antenna port; The power level of the fourth uplink signal is the same as the power level of the third uplink signal; The fourth uplink signal is a signal processed externally, and the fourth downlink signal is outputted through the sixth path to be processed externally.

10. The radio frequency module according to claim 9, characterized in that: Also includes: a first coupling module, wherein the first coupling module is coupled between the third switch and the antenna port; The first coupling module is configured to detect and output power of the first uplink signal and the fourth uplink signal transmitted to the antenna port through the third switch.

11. The radio frequency module according to claim 8, wherein: The radio frequency module further includes a sixth path coupled to the fifth switch; The sixth path is configured to: output the input fourth uplink signal to the antenna port, or output the fourth downlink signal input to the antenna port; The power level of the fourth uplink signal is the same as the power level of the third uplink signal; The fourth uplink signal is a signal processed externally, and the fourth downlink signal is outputted through the sixth path to be processed externally.

12. The radio frequency module according to claim 11, wherein: Also includes: a second coupling module, the second coupling module being coupled between the fifth switch and the antenna port; The second coupling module is configured to detect and output the power of the third uplink signal transmitted to the antenna port through the fifth switch.

13. The radio frequency module according to claim 2, wherein: The fourth path is configured to: output the input third uplink signal to the antenna port, or output the third downlink signal input to the antenna port; Wherein, the third uplink signal is a signal that has been processed externally, and the third downlink signal is outputted to the external device for processing via the fourth path; The radio frequency module further includes a sixth path, wherein the sixth path is coupled to the first switch; The sixth path is configured to: output the input fourth uplink signal to the antenna port, or output the fourth downlink signal input to the antenna port; The power level of the fourth uplink signal is the same as the power level of the third uplink signal; The fourth uplink signal is a signal processed externally, and the fourth downlink signal is outputted through the sixth path to be processed externally.

14. The radio frequency module according to claim 13, wherein: Also includes: a third coupling module, the third coupling module being coupled between the first switch and the antenna port; The third coupling module is configured to detect and output the power of the second uplink signal, the third uplink signal, or the fourth uplink signal transmitted to the antenna port through the first switch.

15. The radio frequency module according to claim 1, wherein: The radio frequency module further includes a seventh switch; The first path, the second path, and the first switch are selectively coupled to the antenna port through the seventh switch.

16. The radio frequency module according to claim 15, characterized in that: The antenna port includes a first antenna port and a second antenna port; The first antenna port and the second antenna port are coupled to the seventh switch; The first path, the second path, and the first switch are selectively coupled to the first antenna port or the second antenna port through the seventh switch.

17. The radio frequency module according to any one of claims 2 to 14, characterized in that: The first network mode is a 4G communication network mode of a low-bandwidth frequency band or a 5G communication network mode of a low-bandwidth frequency band; The second network mode is a 2G communication network with a low bandwidth frequency band.

18. An electronic device, characterized in that: Comprising an antenna and a radio frequency module according to any one of claims 1 to 17; The antenna is coupled to the antenna port.

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