Power consumption and temperature data acquisition method for SmartNic network card

Abstract

The invention provides a method for collecting power consumption and temperature data of a SmartNic network card, and belongs to the technical field of collection methods. Through a plurality of high-performance multi-channel ADC chips, differential voltage at the two ends of a precision resistor of a power supply channel is collected, the differential voltage passes through an operational amplifier and then is sent to an ADC to obtain current data, and the differential voltage at the two ends of the power supply channel is collected to obtain power consumption and temperature data of the SmartNic network card. The data are sent to Fpga for sampling processing operation, the FPGA can be interconnected and communicated through an MCU, and aiming at the problem that the cost is high when an oscilloscope is used for collection in a traditional method, bus single-end voltage signals, chip core power source single-end voltage signals, chip function voltage single-end voltage signals and the like are collected, so that the collection cost is high. The single-ended signal and a ground signal can form a common-mode differential signal, so that an oscilloscope is not used, and the acquisition cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of collection methods, and in particular to a method for collecting power consumption and temperature data of a SmartNIC network card. Background Art

[0002] Currently, no commercially available data collection solutions can simultaneously collect power consumption data for more than 30 power paths, and the maximum sampling rate for a single channel can reach 23k / s. This invention uses an FPGA to process data sampled by multiple high-precision ADCs, which is then uploaded to an MCU for host computer visualization. Finally, a graphical GUI is used to collect real-time power consumption data for the SmartNic board, DPU chip, and temperature, and output the collected data curves.

[0003] Nowadays, AI servers usually install one or more smart network cards for training data network transmission according to the usage scenario, and the smart network card itself also needs to report its own power consumption and temperature to the BMC. Therefore, the normal design of the network card requires the collection of the power consumption and maximum temperature of the entire board. At the same time, for complex scenarios, the smart network card requires the ASIC to change the ASIC operating state in real time according to its own power consumption or temperature under external pressure, such as dynamic adjustment such as core voltage overvoltage and overfrequency at room temperature and voltage and frequency reduction at high temperature. In addition, for the ASIC or DPU processor of the self-developed smart network card, it is also necessary to collect the chip power consumption in various scenarios, and even the power consumption and temperature data of chips with different process corners on the production line. Therefore, the ability to accurately and real-time sample the power consumption of multiple channels is a necessary step in the research and development process.

[0004] Currently, the most common acquisition method is to weld a high-precision current probe to the location where the test is required and capture the relevant test values using a real-time oscilloscope. Alternatively, a third-party power consumption acquisition tool can be used to collect data through its DAQ acquisition card, and the host computer software can display and analyze the data in real time.

[0005] In addition, there is a self-developed plug-in acquisition card, which collects differential voltage signal ends through the acquisition interface, classifies them according to voltage types, and sends them to the ADC for sampling after passing through a multiplexer. The sampled data is sent to the CPLD or MCU for processing, and the MCU uploads the information to the cloud server via USB or Ethernet.

[0006] The existing collection methods have the following problems: 1. Oscilloscope acquisition costs are high and testing is not convenient. The disadvantages of third-party acquisition tools are fixed interfaces, poor scalability, and high supporting software costs. 2. Different from simultaneous multi-channel data collection, the feasibility and real-time performance of data collection and processing are poor. The present invention proposes a method for collecting power consumption and temperature data of SmartNIC network card to solve the above problems. Summary of the Invention

[0007] The present invention is flexible in use, capable of simultaneously reporting 32 power consumption channels through up to eight ADC chips, with the sampling rate adjustable in real time. This allows for high-speed acquisition of power consumption and temperature in various scenarios, making it easier to accurately determine temperature and power reduction decisions in various scenarios, thus overcoming the aforementioned problems in the background art.

[0008] Based on the above technical ideas, the technical solution adopted by the present invention is: A method for collecting power consumption and temperature data of a SmartNIC network card includes the following steps: S1 system initialization configuration step, which includes hardware deployment and signal grouping configuration; S2 data acquisition step, which includes differential current signal acquisition, voltage signal acquisition and temperature signal acquisition; S3 data processing and transmission step, which includes FPGA data integration and dynamic sampling rate adjustment; S4 data reporting and visualization step, which includes MCU data processing and host computer real-time monitoring.

[0009] To further limit the above technical solution, the S1 system initialization configuration step, the hardware deployment link in this step includes connecting a precision resistor in series with the power path of the SmartNic network card as a current sampling point; deploying multiple ADC chips, each supporting 8-channel acquisition, with a maximum expansion of 8 chips; connecting operational amplifiers, FPGAs, MCUs and temperature sensors, and docking the board under test through a high-density matrix connector or a custom interface.

[0010] Further limiting the above technical solution, the signal grouping configuration step includes dividing the current signal into two groups: High current differential group, the chip core power supply is equipped with an op amp with high frequency differential mode suppression function; Low current differential group, IO power domain performs standard op amp processing, voltage signal, single-ended voltage and ground signal form differential pair input.

[0011] Further limiting the above technical solution, the S2 data acquisition step, in which the differential current signal acquisition link includes: S21 collects the differential voltage across the precision resistor; The S22 signal is sent to the corresponding op amp group through the MUX selection path: The high current group transmits the current signal to the differential mode suppression operational amplifier, which suppresses the current signal and then transmits it to the 16-bit digital-to-analog converter. The high current group transmits the current signal to the standard operational amplifier, which transmits the current signal to the digital-to-analog converter. The S23ADC converts the analog voltage signal into a digital current value.

[0012] To further limit the above technical solution, the voltage signal acquisition step includes: S24 collects the single-ended voltage signal of the power path to the ground; S25 and the reference ground signal form a differential signal, which is sent to the ADC through the MUX; The ADC outputs a digital voltage value.

[0013] Further limiting the above technical solution, the S3 data processing and transmission step, the FPGA data integration link in this step includes the FPGA polling multiple ADCs through the SPI interface, generating chip select and clock signals to control data reading, sorting the ADC raw data, calculating power consumption according to the power domain, and buffering the data in the FIFO queue to ensure timing synchronization before outputting it to the MCU.

[0014] Further limitation of the above technical solution is the S4 data reporting and visualization step. In this step, the MCU data processing link includes receiving the FPGA power consumption data and temperature sensor data, and uploading them to the host computer or cloud server through the USB interface.

[0015] To further limit the above technical solution, the temperature signal acquisition step includes: S27 obtains differential current signals through the DPU chip edge die or external Tdiode; The S28 signal is sent to the temperature sensor after being filtered by the capacitor; The S29ADC outputs digital temperature values.

[0016] To further limit the above technical solution, the dynamic sampling rate adjustment link includes the MCU modifying the FPGA's SPI clock frequency through PLL configuration, and selecting multi-channel mode or high-speed mode according to needs. Among them, the multi-channel mode enables all 32 channels and evenly distributes the sampling rates; the high-speed mode shuts down some channels and increases the single-channel sampling rate.

[0017] To further limit the above technical solution, the real-time monitoring link of the host computer includes a GUI interface that displays the real-time power consumption and real-time temperature of each channel in a table form, generates dynamic curves, supports historical data comparison, and triggers a decision-making mechanism.

[0018] Compared with the prior art, the present invention has the following beneficial effects: Currently, low-cost solutions on the market have fewer acquisition channels. In order to meet the multi-channel power consumption and temperature requirements, separate acquisition is required. This acquisition method first cannot synchronize the collected data in real time, and the data reliability is poor; the acquisition cost is also high, and subsequent processing is inconvenient. In addition, the sampling rate is also linked to the cost. It is common to use a sampling frequency of several kilohertz to more than ten kilohertz in general scenarios, while higher frequencies are expensive. The present invention can achieve a balance by reducing the number of channels and increasing the sampling rate. In addition, the acquisition interface can be customized to adapt to a wider range of usage scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 A schematic diagram of a current differential signal group in a method for collecting power consumption and temperature data of a SmartNic network card according to the present invention; Figure 2 The present invention is a schematic diagram of a signal acquisition interface in a method for collecting power consumption and temperature data of a SmartNIC network card. DETAILED DESCRIPTION

[0021] The following is combined with Figure 1-Figure 2 The present invention is described in further detail.

[0022] Example 1: This example provides a method for collecting power consumption and temperature data of a SmartNic network card. Figure 1-Figure 2 As shown, the following steps are included: S1 system initialization configuration step, which includes hardware deployment and signal grouping configuration; S2 data acquisition step, which includes differential current signal acquisition, voltage signal acquisition and temperature signal acquisition; S3 data processing and transmission step, which includes FPGA data integration and dynamic sampling rate adjustment; S4 data reporting and visualization step, which includes MCU data processing and host computer real-time monitoring.

[0023] The S1 system initialization configuration step includes the hardware deployment link in this step, which includes connecting a precision resistor in series with the power path of the SmartNic network card as a current sampling point; deploying multiple ADC chips, each supporting 8-channel acquisition, and expanding to a maximum of 8; connecting the operational amplifier, FPGA, MCU and temperature sensor, and docking the board under test through a high-density matrix connector or a custom interface.

[0024] The signal grouping configuration step includes dividing the current signal into two groups: High current differential group, the chip core power supply is equipped with an op amp with high frequency differential mode suppression function; Low current differential group, IO power domain performs standard op amp processing, voltage signal, single-ended voltage and ground signal form differential pair input.

[0025] The S2 data acquisition step includes the following steps: S21 collects the differential voltage across the precision resistor; The S22 signal is sent to the corresponding op amp group through the MUX selection path: The high current group transmits the current signal to the differential mode suppression operational amplifier, which suppresses the current signal and then transmits it to the 16-bit digital-to-analog converter. The high current group transmits the current signal to the standard operational amplifier, which transmits the current signal to the digital-to-analog converter. The S23ADC converts the analog voltage signal into a digital current value.

[0026] The voltage signal acquisition link includes: S24 collects the single-ended voltage signal of the power path to the ground; S25 and the reference ground signal form a differential signal, which is sent to the ADC through the MUX; S26ADC outputs digital voltage value.

[0027] The S3 data processing and transmission step includes the FPGA data integration link, which includes the FPGA polling multiple ADCs through the SPI interface, generating chip select and clock signals to control data reading, sorting the ADC raw data, calculating power consumption by power domain, and buffering the data in the FIFO queue to ensure timing synchronization before outputting it to the MCU.

[0028] S4 data reporting and visualization step: The MCU data processing link in this step includes receiving the FPGA power consumption data and temperature sensor data, and uploading it to the host computer or cloud server through the USB interface.

[0029] The temperature signal acquisition link includes: S27 obtains differential current signals through the DPU chip edge die or external Tdiode; The S28 signal is sent to the temperature sensor after being filtered by the capacitor; The S29ADC outputs digital temperature values.

[0030] The dynamic sampling rate adjustment link includes the MCU modifying the FPGA's SPI clock frequency through PLL configuration, and selecting multi-channel mode or high-speed mode according to demand. Among them, the multi-channel mode enables all 32 channels and evenly distributes the sampling rates; the high-speed mode shuts down some channels and increases the single-channel sampling rate.

[0031] The host computer real-time monitoring link includes a GUI interface that displays the real-time power consumption and real-time temperature of each channel in a table format, generates dynamic curves, supports historical data comparison, and triggers a decision-making mechanism.

[0032] This invention defines the number of acquisition channels based on the number of ADC chips. This solution is not limited to the number of ADCs, but only provides a method and ideas. Furthermore, the ADC chip model is not limited. This solution uses the ADS1158, but alternatives are possible. This acquisition interface uses a high-density matrix connector, but multi-pin connection solutions such as MXM or MiniSAS can be used to define the connection relationship. These alternatives are also possible.

[0033] Example 2: This example provides a method for collecting power consumption and temperature data of a SmartNic network card. Figure 1-Figure 2 As shown, it also includes 1. collecting differential voltage signals at both ends of the bus precision resistor, differential voltage signals at both ends of the chip core power precision resistor, differential voltage signals at both ends of the chip functional power precision resistor, etc., wherein the chip functional power may include digital power and analog power required by multiple modules; 2. By collecting the bus single-ended voltage signal, the chip core power supply single-ended voltage signal, the chip functional voltage separate voltage signal, etc., the above single-ended signals can be combined with the ground signal to form a common-mode differential signal; 3. By collecting the differential current signal at both ends of the Tdiode on the chip side die or the external Tdiode; The power domain signals to be collected in step 1 can be divided into high-current differential signal groups and low-current differential signal groups based on current magnitude. Each differential power domain is then processed using a different operational amplifier circuit configuration according to the grouping, and then fed into the ADC for processing. For example, the high-current differential signal group includes the chip core power supply and SerDes core power supply. Each differential signal within the group is muted, then amplified by an op amp, and then fed into a 16-bit ADC for processing. The differential swing of the high-current power supply within the chip typically fluctuates significantly, requiring high-frequency differential mode suppression during the op amp. Similarly, the low-current differential signal group includes chip functional power supplies, such as the IO power domain and DDR analog circuits. After being selected by the mux, it is amplified by an op amp and fed into the ADC.

[0034] The single-ended power supply signal collected from the bus single-ended voltage signal, the chip core power supply single-ended voltage signal and the chip functional voltage separate voltage signal is combined with the ground signal as a reference to form a differential signal, which is sent to the ADC for collection after passing through the mux.

[0035] This method collects power consumption for the DPU chip and smart network card by multiplying the current ADC value obtained in each power domain in step 1 by the voltage ADC value obtained from the power domains that collect the busbar single-ended voltage signal, the chip core power supply single-ended voltage signal, and the chip functional voltage individual voltage signal. The ADC used in this solution is the ADS1158, which includes a set of multiplexers capable of collecting up to 8 channels of power data. Two OPA2365 operational amplifiers are used to mirror and amplify the differential P and N signals after the multiplexing process. This solution can utilize multiple ADCs connected in parallel on the acquisition card based on the chip power design. This design utilizes 8 ADCs to form 32 power acquisition channels to collect power from the chip and board separately.

[0036] The temperature differential signal collected by the differential current signal at both ends of the Tdiode on the die side of the acquisition chip is sent to the ADC for acquisition after capacitor filtering. The temperature sensor used in this solution is EMC1412.

[0037] The power consumption data collected by these multiple ADCs is sent to the FPGA via SPI communication signals for collection and calculation. The FPGA enables the data received from the multiple ADSs, queues them in a FIFO, and outputs them. The FPGA provides the system clock to the ADC chips and generates the CS and SCLK clock signals for reading ADC data. Furthermore, the FPGA controls the internal SPI MUX selector to select each ADC chip, ultimately sending the FIFO data to the upper-level MCU. The FPGA's I / O configuration can be selected based on the number of ADCs.

[0038] Finally, the MCU processes the collected power consumption FIFO data and temperature sensor data. The cloud or host computer communicates with the MCU via a USB interface. The MCU can also modify the ADC sampling frequency and the FPGA SPI tap clock based on the PLL configuration. Based on its own power consumption data, it can reduce the number of acquisition paths and achieve a higher sampling frequency.

[0039] The acquisition interface can use a standardized connector as a standard component, adapting to a variety of different board designs. Based on the required number of pins, a high-density matrix connector with a larger number than the sampling number can be selected for board-to-board connection. Alternatively, by redefining the GENZ interface, power consumption testing requirements for different generations of Smart NICs can be met. The above contents are further detailed descriptions of the present invention in conjunction with specific preferred embodiments, so as to facilitate those skilled in the art to understand and apply the present invention. It should not be considered that the specific implementation of the present invention is limited to these descriptions.

Claims

1. A method for collecting power consumption and temperature data of a SmartNic network card, characterized in that: The following steps are involved: S1 system initialization configuration step, which includes hardware deployment and signal grouping configuration; S2 data acquisition step, which includes differential current signal acquisition, voltage signal acquisition and temperature signal acquisition; S3 data processing and transmission step, which includes FPGA data integration and dynamic sampling rate adjustment; S4 data reporting and visualization step, which includes MCU data processing and host computer real-time monitoring.

2. The method for collecting power consumption and temperature data of a SmartNIC network card according to claim 1, characterized in that: The S1 system initialization configuration step includes the hardware deployment link in which a precision resistor is connected in series with the power path of the SmartNic network card as a current sampling point; Deploy multiple ADC chips, each supporting 8-channel acquisition, with a maximum expansion of 8 chips; connect operational amplifiers, FPGAs, MCUs, and temperature sensors, and dock with the boards under test through high-density matrix connectors or custom interfaces.

3. The method for collecting power consumption and temperature data of a SmartNIC network card according to claim 2, characterized in that: The signal grouping configuration step includes dividing the current signal into two groups: High current differential group, the chip core power supply is equipped with an op amp with high frequency differential mode suppression function; Low current differential group, IO power domain performs standard op amp processing, voltage signal, single-ended voltage and ground signal form differential pair input.

4. The method for collecting power consumption and temperature data of a SmartNic network card according to claim 3, characterized in that: The S2 data acquisition step includes the following steps: S21 collects the differential voltage across the precision resistor; The S22 signal is sent to the corresponding op amp group through the MUX selection path: The high current group transmits the current signal to the differential mode suppression operational amplifier, which suppresses the current signal and then transmits it to the 16-bit digital-to-analog converter. The high current group transmits the current signal to the standard operational amplifier, which transmits the current signal to the digital-to-analog converter. The S23ADC converts the analog voltage signal into a digital current value.

5. The method for collecting power consumption and temperature data of a SmartNic network card according to claim 4, characterized in that: The voltage signal acquisition link includes: S24 collects the single-ended voltage signal of the power path to the ground; S25 and the reference ground signal form a differential signal, which is sent to the ADC through the MUX; S26ADC outputs digital voltage value.

6. The method for collecting power consumption and temperature data of a SmartNIC network card according to claim 5, characterized in that: The temperature signal acquisition link includes: S27 obtains differential current signals through the DPU chip edge die or external Tdiode; The S28 signal is sent to the temperature sensor after being filtered by the capacitor; The S29ADC outputs digital temperature values.

7. The method for collecting power consumption and temperature data of a SmartNIC network card according to claim 6, characterized in that: The S3 data processing and transmission step includes the FPGA data integration link, which includes the FPGA polling multiple ADCs through the SPI interface, generating chip select and clock signals to control data reading, sorting the ADC raw data, calculating power consumption by power domain, and buffering the data in the FIFO queue to ensure timing synchronization before outputting it to the MCU.

8. The method for collecting power consumption and temperature data of a SmartNic network card according to claim 7, characterized in that: S4 data reporting and visualization step: The MCU data processing link in this step includes receiving the FPGA power consumption data and temperature sensor data, and uploading it to the host computer or cloud server through the USB interface.

9. The method for collecting power consumption and temperature data of a SmartNIC network card according to claim 8, characterized in that: The dynamic sampling rate adjustment link includes the MCU modifying the FPGA's SPI clock frequency through PLL configuration, and selecting multi-channel mode or high-speed mode according to demand. Among them, the multi-channel mode enables all 32 channels and evenly distributes the sampling rates; the high-speed mode shuts down some channels and increases the single-channel sampling rate.

10. The method for collecting power consumption and temperature data of a SmartNIC network card according to claim 9, characterized in that: The host computer real-time monitoring link includes a GUI interface that displays the real-time power consumption and real-time temperature of each channel in a table format, generates dynamic curves, supports historical data comparison, and triggers a decision-making mechanism.

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