Soft forwarding buffer management method and application
By managing buffer memory addresses and first-in-first-out queues, the performance bottlenecks in soft forwarding buffer management are solved, efficient buffer resource allocation and CPU resource optimization are achieved, and the forwarding performance of network switching technology is improved.
Patent Information
- Application Number
- CN202510738395.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-04
- Publication Date
- 2025-08-08
AI Technical Summary
In the existing network switching technology, soft forwarding buffer management is limited by software bottlenecks, and the CPU interacts frequently with DDR, resulting in poor read and write performance and affecting forwarding performance.
By batch applying for buffer memory addresses by switching chips and using first-in, first-out queue management, the switching chip directly responds to CPU or DMA cache requests, avoids software management bottlenecks, and configures different storage units to adapt to regular and burst traffic.
It improves the performance of soft forwarding buffer management, reduces CPU resource usage, improves the system's forwarding efficiency and adaptability, and avoids congestion during soft forwarding.
Smart Images
Figure CN120455419A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of Ethernet data forwarding, and in particular relates to a soft forwarding buffer management method and application. Background Art
[0002] There are many network products on the market, which can be roughly divided into two categories. One category uses dedicated forwarding chips to guide message forwarding, such as routers and switches, which we simply call hard forwarding; the other category uses general-purpose platforms such as x86 architecture, purely using the CPU to guide message forwarding, which we simply call soft forwarding.
[0003] With the development of network technology, software-based packet forwarding, as a key technology in SDN and NFV, has received widespread attention and recognition. Routers, as a crucial component of network infrastructure, are currently under intense research interest in leveraging software to ensure high forwarding performance on common platforms. However, the fundamental performance bottleneck lies in the processing of packets sent to and from the CPU—in other words, the performance of the interaction between the CPU and hardware in processing packets—which severely impacts forwarding performance.
[0004] In existing network switching technologies, buffer management relies entirely on software. This is limited by software bottlenecks, and the frequent interaction between the CPU and DDR results in poor read and write performance, which prevents the overall performance of soft forwarding from being improved.
[0005] Therefore, in order to solve the above technical problems, it is necessary to provide a new soft forwarding buffer management method and application.
[0006] The information disclosed in this background technology section is only intended to enhance understanding of the overall background of the invention and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the Invention
[0007] The purpose of the present invention is to provide a soft forwarding buffer management method and application, which can realize hardware management of soft forwarding buffer and significantly improve the performance of soft forwarding buffer compared with the existing technology.
[0008] In order to achieve the above object, a specific embodiment of the present invention provides the following technical solutions:
[0009] In a first aspect, the present invention provides a soft forwarding buffer management method, which includes:
[0010] The switching chip applies for memory addresses corresponding to a plurality of available first buffers, stores the memory addresses corresponding to the plurality of available first buffers in a first first-in first-out queue, applies for memory addresses corresponding to a plurality of available second buffers, and stores the memory addresses corresponding to the plurality of available second buffers in a second first-in first-out queue;
[0011] In response to a cache request from a central processing unit or a DMA, iterating through the number of available first buffers;
[0012] Based on the number of available first buffers, a memory address is returned from the first FIFO queue or the second FIFO queue; and the data to be cached is written into the buffer corresponding to the returned memory address.
[0013] In one or more embodiments of the present invention, the method further comprises:
[0014] The first buffer is configured in the first storage unit, and the second buffer is configured in the second storage unit;
[0015] A first cache pointer pool is also configured in the first storage unit, and the first cache pointer pool stores memory addresses corresponding to each first buffer zone. A second cache pointer pool is also configured in the second storage unit, and the second cache pointer pool stores memory addresses corresponding to each second buffer zone.
[0016] In one or more embodiments of the present invention, the access delay of the first storage unit is less than or equal to the access delay of the second storage unit;
[0017] The storage capacity of the second storage unit is greater than or equal to the storage capacity of the first storage unit.
[0018] In one or more embodiments of the present invention, the first storage unit is an SRAM; the second storage unit is a DDR.
[0019] In one or more embodiments of the present invention, the method further comprises:
[0020] Recording the number of memory addresses in the first first-in-first-out queue and the second first-in-first-out queue;
[0021] If the number of memory addresses in the first FIFO queue / second FIFO queue is greater than a preset first threshold, the preset number of memory addresses in the first FIFO queue / second FIFO queue are returned to the first cache pointer pool / second cache pointer pool.
[0022] In one or more embodiments of the present invention, returning a memory address from the first first-in-first-out queue or the second first-in-first-out queue based on the number of available first buffers includes:
[0023] If the first cache pointer pool does not support a global shared buffer and the remaining memory addresses in the first first-in-first-out queue are not 0, then based on the order in which the memory addresses in the first first-in-first-out queue are stored, a memory address in the first first-in-first-out queue is returned;
[0024] If the first cache pointer pool does not support global shared buffers and the remaining memory address in the first first-in-first-out queue is 0, this cache request fails.
[0025] In one or more embodiments of the present invention, returning a memory address from the first first-in-first-out queue or the second first-in-first-out queue based on the number of available first buffers further includes:
[0026] If the number of memory addresses in the first cache pointer pool is greater than or equal to a preset second threshold, returning a memory address in the first first-in-first-out queue based on the order in which the memory addresses in the first first-in-first-out queue are stored;
[0027] If the number of memory addresses in the first cache pointer pool is less than a preset second threshold and the first cache pointer pool supports a global shared buffer, a memory address in the second first-in-first-out queue is returned based on the storage order of the memory addresses in the second first-in-first-out queue.
[0028] In a second aspect, the present invention provides a soft forwarding buffer management method, which includes:
[0029] In response to a cache release request from the central processing unit / DMA, the memory of the buffer corresponding to the memory address to be released is released, and the memory address corresponding to the released buffer is returned to the first cache pointer pool or the second cache pointer pool;
[0030] Based on the memory address application of the switching chip, the memory addresses corresponding to the multiple first buffers are sent to the first first-in-first-out queue of the switching chip, and the memory addresses corresponding to the multiple second buffers are sent to the second first-in-first-out queue of the switching chip.
[0031] In a third aspect, the present invention provides a soft forwarding buffer management system, which includes:
[0032] a first storage unit, the first storage unit comprising a first cache pointer pool and a plurality of first buffer zones, each of the first buffer zones corresponding to a memory address in the first cache pointer pool;
[0033] a second storage unit, the second storage unit comprising a second cache pointer pool and a plurality of second buffers, each of the second buffers corresponding to a memory address in the second cache pointer pool;
[0034] A switching chip, wherein the switching chip maintains a first first-in-first-out queue and a second first-in-first-out queue, wherein the first first-in-first-out queue is used to store memory addresses applied for in the first cache pointer pool, and the second first-in-first-out queue is used to store memory addresses applied for in the second cache pointer pool.
[0035] In a fourth aspect, the present invention provides a computer device comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, computer instructions are stored in the memory, and the processor executes the soft forwarding buffer management method by executing the computer instructions.
[0036] Compared to the prior art, the soft forwarding buffer management method provided by the present invention implements soft forwarding buffer management through hardware such as switching chips, thereby avoiding the problem of poor read and write capabilities of the central processing unit and improving forwarding performance. At the same time, by providing a first buffer and a second buffer, the system's ability to handle burst traffic is improved, avoiding congestion during the soft forwarding process. Specifically, the first storage unit configured in the first buffer focuses on meeting low-latency communication requirements, while the second storage unit configured in the second buffer focuses on meeting burst traffic requirements. The combination of the two further improves the performance of buffer management during the soft forwarding process and the adaptability of the system. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0038] Figure 1 1 is a schematic diagram of the architecture of a soft forwarding buffer management system according to one embodiment of the present invention;
[0039] Figure 2 1 is a flow chart of a soft forwarding buffer management method according to an embodiment of the present invention;
[0040] Figure 3 This is a flow chart of a soft forwarding buffer management method in another embodiment of the present invention.
[0041] Figure 4It is a structural block diagram of an electronic device in one embodiment of the present invention. DETAILED DESCRIPTION
[0042] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.
[0043] Unless expressly stated otherwise, throughout the specification and claims, the term "comprise" or variations such as "include" or "comprising", etc., will be understood to include the stated elements or components but not to exclude other elements or other components.
[0044] Existing technical solutions include methods for buffer management during forwarding. Specifically, software pre-allocates a memory address for each descriptor and inserts it into the descriptor. When receiving a packet, the chip reads the descriptor and stores the message in its corresponding memory address. After the CPU reads the message, the software then allocates a new memory address and attaches it to the descriptor. When sending a packet, the CPU writes the message to be sent to memory. After the chip completes the packet transmission, the software must promptly release the corresponding memory address.
[0045] In the above technical solution, buffer management is entirely done by software, which is limited by software bottlenecks. This inevitably leads to a low soft forwarding rate due to poor read and write performance. At the same time, due to the reliance on software forwarding, the CPU needs to interact frequently with the storage unit, which not only consumes a large amount of processor resources, but also makes it difficult to improve the performance of soft forwarding.
[0046] The inventors of this invention identified the major shortcomings of the existing technology and proposed a novel technical implementation based on these shortcomings: a switching chip batches requests and stores the memory addresses of each buffer. When the CPU or DMA requests a cache, the switching chip returns an available memory address, and data is stored in the buffer corresponding to the returned address. This decouples buffer management from the software side, avoiding the problems of inefficient forwarding and CPU resource occupation caused by software read and write operations.
[0047] Furthermore, by configuring multiple storage units and corresponding first-in-first-out queues in the switching chip, different storage units produce different technical effects based on different characteristics. Together, they improve the system's forwarding efficiency and adaptability to different environments during the soft forwarding process.
[0048] Please refer to Figure 1 , which shows a schematic diagram of the soft forwarding buffer management system architecture provided by the present invention under one embodiment, the scenario specifically includes: a first storage unit (first level: SRAM), a second storage unit (second level: DDR) and a switching chip (chip).
[0049] Specifically, a first storage unit, the first storage unit includes a first cache pointer pool and multiple first buffers, each first buffer corresponds to a memory address in the first cache pointer pool; a second storage unit, the second storage unit includes a second cache pointer pool and multiple second buffers, each second buffer corresponds to a memory address in the second cache pointer pool; a switching chip, the switching chip maintains a first first-in-first-out queue and a second first-in-first-out queue, the first first-in-first-out queue is used to store the memory address applied for the first cache pointer pool, and the second first-in-first-out queue is used to store the memory address applied for the second cache pointer pool.
[0050] It should be noted that a communication connection is provided between the first storage unit, the second storage unit, and the switching chip. The communication network extended by the above communication connection can include various connection types, including but not limited to: wired connection, wireless connection, or fiber optic cable connection. Based on the above communication connection relationship, the switching chip can batch request the memory addresses of its corresponding buffers from the first storage unit and / or the second storage unit, and store the memory addresses in the first first-in-first-out queue and / or the second first-in-first-out queue on the switching chip.
[0051] It should also be noted that one or more registers are further configured in the switching chip for monitoring the number of memory addresses in the first FIFO queue, the second FIFO queue, the first cache pointer pool, and the second cache pointer pool.
[0052] Please refer to Figure 2 FIG. 1 is a flow chart of a soft forwarding buffer management method according to an embodiment of the present invention. The soft forwarding buffer management method specifically includes the following steps:
[0053] S201: The switching chip applies for memory addresses corresponding to a plurality of available first buffers, stores the memory addresses corresponding to the plurality of available first buffers in a first first-in-first-out queue, applies for memory addresses corresponding to a plurality of available second buffers, and stores the memory addresses corresponding to the plurality of available second buffers in a second first-in-first-out queue;
[0054] It should be noted that the buffer is a memory area added to the computer storage program for temporary storage of data, which is often used in scenarios such as network transmission, data storage and IO operations. It plays a role in coordinating data transmission between components of different speeds or different priorities. Secondly, the memory address corresponding to the buffer, that is, the position of the buffer in the corresponding storage unit. Based on the memory address, the location of the corresponding writable buffer can be pointed to, and the data to be cached can be stored in the cache area. Finally, the first-in-first-out queue is a data structure. The data in the first-in-first-out queue is arranged in the order of data arrival, and the first one to enter leaves first. It is used to control the orderly arrangement of system processes so that network data packets can be transmitted in sequence.
[0055] The difference between the first buffer and the second buffer of the present invention lies in the different cache media they reside in. Specifically, the first buffer is configured in a first storage unit, while the second buffer is configured in a second storage unit. Specifically, to implement storage of cached data in the first and second buffers, a first cache pointer pool is configured in the first storage unit, storing memory addresses corresponding to each first buffer; and a second cache pointer pool is configured in the second storage unit, storing memory addresses corresponding to each second buffer.
[0056] The switching chip, which serves as the core of the soft forwarding buffer management of the present invention, needs to respond to the request after the DMA or central processing unit issues a cache request, and return the memory address corresponding to the writable buffer. In order to ensure response efficiency, the switching chip of the present invention is configured with a first first-in-first-out queue corresponding to the first buffer and a second first-in-first-out queue corresponding to the second buffer. The first first-in-first-out queue is used to store the memory addresses corresponding to each of the first buffers, and the second first-in-first-out queue is used to store the memory addresses corresponding to each of the second buffers. Based on the setting of the first-in-first-out queue, the corresponding memory address can be directly allocated by the switching chip after the CPU or DMA issues a cache request, without having to request the storage unit again, thereby reducing the time required for response.
[0057] It should be noted that, in order to further improve the management performance of the subsequent soft forwarding buffer, it is preferred that the switching chip apply for the first buffer memory address and the second buffer memory address in batches. To avoid the situation where the number of memory addresses obtained after batch application is greater than the number of memory addresses that can be accommodated by the first first-in-first-out queue / the second first-in-first-out queue, one or more registers can be configured in the switching chip to dynamically record the number of memory addresses in the first first-in-first-out queue and the second first-in-first-out queue.
[0058] It should also be noted that, in one embodiment, the batch application may be periodic; in another embodiment, the batch application is issued based on the remaining number of memory addresses in the first-in-first-out queue and the remaining number of memory addresses in the current cache pointer pool. The present invention does not impose any specific restrictions on the application strategy.
[0059] In particular, batch applications can certainly speed up the efficiency of applications, but if the space of the first-in-first-out queue is limited, it may cause the memory address of the application to overflow, so the soft forwarding buffer management method includes: recording the number of memory addresses in the first first-in-first-out queue and the second first-in-first-out queue; if the number of memory addresses in the first first-in-first-out queue or the second first-in-first-out queue is greater than a preset first threshold, then the preset number of available memory addresses in the first first-in-first-out queue or the second first-in-first-out queue is returned to the first cache pointer pool or the second cache pointer pool. Among them, the first threshold can be dynamically adjusted based on the capacity of the first-in-first-out queue in the actual application scenario. On the basis that the first threshold is less than or equal to the maximum value of the memory address that can be stored in its corresponding first-in-first-out queue, the embodiment of the present invention does not make a specific limitation on the value of the first threshold.
[0060] S202: In response to a cache request from a central processing unit or a DMA, traverse the number of available first buffers;
[0061] As previously described, in one embodiment of the present invention, a corresponding register can be configured in the switching chip to record the number of memory addresses in the cache pointer pool. When the CPU or DMA issues a cache request, the switching chip responds by providing a memory address corresponding to a writable cache area. Optionally, the number of available memory addresses in the first cache pointer pool can be directly obtained by reading the corresponding register of the first cache pointer pool, i.e., the number of available first buffers.
[0062] It should be noted that in existing technologies, the selection and configuration of storage media must be dynamically adjusted based on different application scenarios. This adjustment process not only leads to frequent changes in the system architecture, but also carries the risk of data loss and prevents effective and adaptive management of the soft forwarding buffer. In an embodiment of the present invention, to improve the system's adaptability during the soft forwarding process, a hierarchical buffering mechanism is constructed, achieving intelligent scheduling of storage resources through differentiated design.
[0063] Specifically, the present invention is provided with two storage units with complementary functions, namely a low-latency storage unit corresponding to the first buffer and a large-capacity storage unit corresponding to the second buffer. When processing regular traffic, the first buffer configured on the low-latency storage unit is preferentially used for data temporary storage, realizing high-speed caching and rapid release of data, so as to improve the caching / release speed and ensure basic forwarding efficiency. Since low-latency storage units often have physical limitations such as bandwidth limitations and capacity thresholds, when the buffer of the low-latency storage unit is consumed in large quantities in the face of sudden traffic impact, the storage medium switching mechanism is automatically triggered to seamlessly migrate the overflow data to the second buffer on another large-capacity storage unit for data processing, providing the system with reliable elastic buffer space and avoiding problems such as data loss. That is, in one embodiment, it is preferred to set the access delay of the first storage unit to be less than or equal to the access delay of the second storage unit; and the storage capacity of the second storage unit to be greater than or equal to the first storage unit. This asymmetric resource allocation strategy achieves the best balance between delay and capacity at the hardware level.
[0064] Among existing storage media, SRAM has low access latency and high tolerance to voltage fluctuations and electromagnetic interference, so it can achieve low-latency data processing in various implementation scenarios. At the same time, since the static storage structure does not require dynamic refresh, its power consumption is reduced and the response speed is stable, which is suitable for processing data under normal network traffic conditions. Therefore, in a specific embodiment of the present invention, SRAM is preferably used as the first storage unit. In contrast, DDR has the advantage of high storage density. Through multi-channel and high-frequency design, it can provide extremely high data transmission bandwidth, which is suitable for scenarios that require large-capacity cache or batch data processing. The above characteristics make DDR have extremely high burst transmission efficiency, which can cope with a large amount of burst traffic that occurs in a short period of time. Therefore, in a specific embodiment of the present invention, DDR is preferably used as the second storage unit.
[0065] S203: Based on the number of available first buffers, return a memory address from the first FIFO queue or the second FIFO queue; and write the data to be cached into the buffer corresponding to the returned memory address.
[0066] In an exemplary embodiment, returning an available memory address includes: if the first cache pointer pool does not support a global shared buffer, and the remaining available memory addresses in the first first-in-first-out queue are not 0, then based on the storage order of the memory addresses in the first first-in-first-out queue, returning an available memory address in the first first-in-first-out queue; if the first cache pointer pool does not support a global shared buffer, and the remaining available memory addresses in the first first-in-first-out queue are 0, then this cache request fails.
[0067] It should be noted that the global shared buffer refers to a computer system or application in which multiple components support shared access to and use of the same memory area for temporary storage and transfer of data. In an embodiment of the present invention, if the first cache pointer pool supports the global shared buffer, it means that the system can apply for resources from the second cache pointer pool, that is, call the memory address in the second first-in-first-out queue for data temporary storage; if the first cache pointer pool does not support the global shared buffer, it means that the system can only apply for resources from the first cache pointer pool, that is, can only temporarily store data based on the memory address in the first first-in-first-out queue.
[0068] In another exemplary embodiment, returning an available memory address also includes: if the number of available memory addresses in the first cache pointer pool is greater than or equal to a preset second threshold, then based on the storage order of the memory addresses in the first first-in-first-out queue, returning an available memory address in the first first-in-first-out queue; if the number of available memory addresses in the first cache pointer pool is less than the preset second threshold and the first cache pointer pool supports a global shared buffer, then based on the storage order of the memory addresses in the second first-in-first-out queue, returning an available memory address in the second first-in-first-out queue.
[0069] In this embodiment, a second threshold is set to measure the number of available buffers in the first storage unit. Since the application and release of memory addresses corresponding to the buffers are interactive during the soft forwarding process, the memory addresses in the first cache pointer pool will not be continuously less than the threshold in the forwarding process of regular traffic. Only when burst traffic occurs will the memory in the first cache pointer pool be consumed in large quantities in a short period of time. That is, if the number of memory addresses in the first first-in-first-out queue is less than the second threshold, it is considered that burst traffic is currently being processed.
[0070] As previously described, in an embodiment of the present invention, under the premise of satisfying global buffer sharing, when the first buffer is heavily consumed, that is, when the available memory addresses in the first cache pointer pool are reduced to less than the second threshold, a storage medium switching mechanism is automatically triggered to seamlessly migrate overflow data to the second buffer pointed to by the memory address in the second cache pointer pool for data processing, thereby providing the system with reliable and elastic buffer space and avoiding problems such as data loss. In other words, at this time, a memory address needs to be returned based on the second first-in, first-out queue.
[0071] Please refer to Figure 3 FIG. 1 is a flow chart of a soft forwarding buffer management method according to an embodiment of the present invention. The soft forwarding buffer management method specifically includes the following steps:
[0072] S301: In response to a cache release request from a CPU / DMA, releasing a memory buffer corresponding to a memory address to be released, and returning the memory address corresponding to the released buffer to the first cache pointer pool or the second cache pointer pool;
[0073] It is understandable that the first buffer and / or the second buffer only serve as temporary data storage during the soft forwarding process. Therefore, after caching the data, there must be a corresponding process of releasing the buffer containing the data. The released buffer can be used again to write the data to be cached, so its corresponding memory address is returned to the cache pointer pool. If the released cache area is a cache area within the first storage unit, its memory address is returned to the first cache pointer pool; if the released cache area is a cache area within the second storage unit, its memory address is returned to the second cache pointer pool.
[0074] S302: Based on the memory address application of the switching chip, the memory addresses corresponding to the multiple first buffers are sent to the first first-in-first-out queue of the switching chip, and the memory addresses corresponding to the multiple second buffers are sent to the second first-in-first-out queue of the switching chip.
[0075] As previously mentioned, in order to further improve the management performance of the subsequent soft forwarding buffer, it is preferred that the switching chip batch-process the memory addresses of the first buffer and the second buffer. Similarly, if the CPU / DMA needs to release memory addresses after processing the message, they are also batch-processed and sent to the corresponding first-in-first-out queue of the switching chip. When the memory addresses stored in the first-in-first-out queue are about to overflow, the memory addresses in the first-in-first-out queue are batch-returned to the corresponding storage unit.
[0076] Please refer to Figure 4 As shown, an embodiment of the present invention further provides an electronic device 400, which includes at least one processor 401, a memory 402 (e.g., a non-volatile memory), a storage 403, and a communication interface 404, and the at least one processor 401, the memory 402, the storage 403, and the communication interface 404 are connected together via an internal bus 405. The at least one processor 401 is configured to call at least one program instruction stored or encoded in the memory 402, so that the at least one processor 401 performs various operations and functions of the soft forwarding buffer management method described in various embodiments of this specification.
[0077] In the embodiments of the present specification, the electronic device 400 may include but is not limited to: a personal computer, a server computer, a workstation, a desktop computer, a laptop computer, a notebook computer, a mobile electronic device, a smart phone, a tablet computer, a cellular phone, a personal digital assistant (PDA), a handheld device, a messaging device, a wearable electronic device, a consumer electronic device, and the like.
[0078] An embodiment of the present invention further provides a computer-readable medium carrying computer-executable instructions. When the computer-executable instructions are executed by a processor, they can be used to implement the various operations and functions of the soft forwarding buffer management method described in various embodiments of this specification.
[0079] The computer-readable medium in the present invention can be a computer-readable signal medium or a computer-readable storage medium or any combination of the two. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or component, or any combination of the above. More specific examples of computer-readable storage media can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present invention, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device.
[0080] In the present invention, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may transmit, propagate, or transfer a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination thereof.
[0081] It will be understood by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0082] The present invention is described with reference to flowcharts and / or block diagrams of methods, apparatuses, systems, and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0083] The foregoing descriptions of specific exemplary embodiments of the present invention are for purposes of illustration and description. These descriptions are not intended to limit the invention to the precise forms disclosed, and it is apparent that many variations and modifications are possible in light of the foregoing teachings. The exemplary embodiments have been selected and described for the purpose of explaining the specific principles of the invention and their practical application, thereby enabling those skilled in the art to realize and utilize a variety of exemplary embodiments of the invention and various options and modifications. The scope of the invention is intended to be defined by the claims and their equivalents.
[0084] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.
[0085] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.
Claims
1. A soft forwarding buffer management method, characterized in that: include: The switching chip applies for memory addresses corresponding to a plurality of available first buffers, stores the memory addresses corresponding to the plurality of available first buffers in a first first-in first-out queue, applies for memory addresses corresponding to a plurality of available second buffers, and stores the memory addresses corresponding to the plurality of available second buffers in a second first-in first-out queue; In response to a cache request from a central processing unit or a DMA, iterating through the number of available first buffers; Returning a memory address from the first FIFO queue or the second FIFO queue based on the number of available first buffers; And write the data to be cached into the buffer corresponding to the returned memory address.
2. The soft forwarding buffer management method according to claim 1, wherein: The method further comprises: The first buffer is configured in the first storage unit, and the second buffer is configured in the second storage unit; A first cache pointer pool is also configured in the first storage unit, and the first cache pointer pool stores memory addresses corresponding to each first buffer zone. A second cache pointer pool is also configured in the second storage unit, and the second cache pointer pool stores memory addresses corresponding to each second buffer zone.
3. The soft forwarding buffer management method according to claim 2, wherein: An access delay of the first storage unit is less than or equal to an access delay of the second storage unit; The storage capacity of the second storage unit is greater than or equal to the storage capacity of the first storage unit.
4. The soft forwarding buffer management method according to claim 2, wherein: The first storage unit is SRAM; the second storage unit is DDR.
5. The soft forwarding buffer management method according to claim 2, wherein: The method further comprises: Recording the number of memory addresses in the first first-in-first-out queue and the second first-in-first-out queue; If the number of memory addresses in the first FIFO queue / second FIFO queue is greater than a preset first threshold, the preset number of memory addresses in the first FIFO queue / second FIFO queue are returned to the first cache pointer pool / second cache pointer pool.
6. The soft forwarding buffer management method according to claim 2, characterized in that: Returning a memory address from the first first-in-first-out queue or the second first-in-first-out queue based on the number of available first buffers includes: If the first cache pointer pool does not support a global shared buffer and the remaining memory addresses in the first first-in-first-out queue are not 0, then based on the order in which the memory addresses in the first first-in-first-out queue are stored, a memory address in the first first-in-first-out queue is returned; If the first cache pointer pool does not support global shared buffers and the remaining memory address in the first first-in-first-out queue is 0, this cache request fails.
7. The soft forwarding buffer management method according to claim 1, wherein: Returning a memory address from the first first-in-first-out queue or the second first-in-first-out queue based on the number of available first buffers, further comprising: If the number of memory addresses in the first cache pointer pool is greater than or equal to a preset second threshold, returning a memory address in the first first-in-first-out queue based on the order in which the memory addresses in the first first-in-first-out queue are stored; If the number of memory addresses in the first cache pointer pool is less than a preset second threshold and the first cache pointer pool supports a global shared buffer, a memory address in the second first-in-first-out queue is returned based on the storage order of the memory addresses in the second first-in-first-out queue.
8. A soft forwarding buffer management method, characterized in that: include: In response to a cache release request from the central processing unit / DMA, the memory of the buffer corresponding to the memory address to be released is released, and the memory address corresponding to the released buffer is returned to the first cache pointer pool or the second cache pointer pool; Based on the memory address application of the switching chip, the memory addresses corresponding to the multiple first buffers are sent to the first first-in-first-out queue of the switching chip, and the memory addresses corresponding to the multiple second buffers are sent to the second first-in-first-out queue of the switching chip.
9. A soft forwarding buffer management system, characterized in that: include: a first storage unit, the first storage unit comprising a first cache pointer pool and a plurality of first buffer zones, each of the first buffer zones corresponding to a memory address in the first cache pointer pool; a second storage unit, the second storage unit comprising a second cache pointer pool and a plurality of second buffers, each of the second buffers corresponding to a memory address in the second cache pointer pool; A switching chip, wherein the switching chip maintains a first first-in-first-out queue and a second first-in-first-out queue, wherein the first first-in-first-out queue is used to store memory addresses applied for in the first cache pointer pool, and the second first-in-first-out queue is used to store memory addresses applied for in the second cache pointer pool.
10. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the soft forwarding buffer management method according to any one of claims 1 to 7 by executing the computer instructions.