Manufacturing method of 8-tube 2-port static random access memory

Abstract

The invention discloses a manufacturing method of an eight-tube two-port static random access memory, which is characterized in that an N LDD process of six transistors in a chip memory area uses an original storage unit N LDD photomask and a storage unit P LDD photomask, an N transistor of a read port is separated from the original storage unit N LDD photomask, and the original storage unit N LDD photomask is not used for N ion implantation; the method comprises the following steps: switching to use a logic device N field effect transistor threshold voltage adjusting photomask, opening a source drain region of an N transistor of a read port to carry out ion implantation while LDD of a logic device in a chip logic region is carried out, and completing an N LDD process of the N transistor of the read port so as to adjust the threshold voltage Vt and the source drain conduction current Ids of the N transistor of the read port; therefore, the reading current and the reading speed of the reading port can be adjusted, the reading and writing balance of the 6TSRAM in the storage unit cannot be influenced, a photomask does not need to be additionally added, and processing steps do not need to be added.

Description

Technical Field

[0001] The present invention relates to semiconductor circuit design technology, and in particular to a method for manufacturing an 8-tube 2-port static random access memory (8T2P SRAM). Background Art

[0002] In the past 20 to 30 years, with the rapid development of microelectronics technology, components have been miniaturized rapidly, chip density has increased, and computing performance has increased. Semiconductor memory is also developing in a significant direction. Among volatile memories, SRAM (Static Random Access Memory) has the characteristics of low power consumption and high performance, while DRAM (Dynamic Random Access Memory) has the characteristics of low cost and large storage capacity.

[0003] To improve system performance, various memories, particularly SRAM (static random access memory), are embedded in current SOCs (system on a chip) to improve system performance. Because SRAM circuits are compatible with current CMOS processes and are typically used in the L1 / L2 cache (first-level / second-level high-speed cache) of computing chips, they naturally become the preferred embedded memory. Therefore, SRAM plays a significant role in the functions and applications of digital chips.

[0004] An SRAM (Static Random Access Memory) chip includes a storage area and a logic area. Peripheral logic devices are formed in the logic area, and a memory cell array is formed in the storage area.

[0005] 8-tube 2-port static random access memory (8T2P SRAM) circuit Figure 1 As shown, an SRAM consists of eight transistors (Tr) and has two ports. Six transistors in the memory area function as write / read ports, operating at moderate speeds and maintaining a strong read / write balance. Nodes n1 and n2 store data. When the A-word line AWL = 1, turning on the third and fourth N-transistors PG1 and PG2, the first and second bit lines BL1 and BL2 are used for writing or reading. These two lines form a single port. The two transistors in the external logic area serve as read ports, operating at a relatively high speed and exhibiting slightly higher leakage current. When the B-word line BWL = 1, turning on the fifth N-transistor RP PG, the read port, the read port bit line RP BL is used for reading data.

[0006] The eight transistors (including the first N-transistor PD1, the second N-transistor PD2, the third N-transistor PG1, the fourth N-transistor PG2, the first P-transistor PU1, the second P-transistor PU2, the fifth N-transistor RP PG and the sixth N-transistor RP PD) of the 8-transistor 2-port static random access memory (8T2P SRAM) are shown in the planar layout diagram. Figure 2 shown.

[0007] The conventional planar transistor process of 8-transistor 2-port static random access memory (8T2P SRAM) is as follows Figure 3 First, the N-type lightly doped drain (N LDD) process is simultaneously performed on six N-transistors (including the first N-transistor PD1, the second N-transistor PD2, the third N-transistor PG1, the fourth N-transistor PG2, the fifth N-transistor RP PG, and the sixth N-transistor RP PD); then the P-type lightly doped drain (PLDD) process is simultaneously performed on two P-transistors (the first P-transistor PU1 and the second P-transistor PU2); then, the HVT (high V threshold, high voltage threshold) N-type lightly doped drain (NLDD) process / HVT (high V threshold, high voltage threshold) P-type lightly doped drain (PLDD) process / LVT (low V threshold, low voltage threshold) N-type lightly doped drain (N LDD) process / LVT (low V threshold, low voltage threshold) P-type lightly doped drain (PLDD) process / SVT (standard V threshold, standard voltage threshold) N-type lightly doped drain (NLDD) process / SVT (standard V threshold, standard voltage threshold) P-type lightly doped drain (P LDD) / UHVT (Ultrahigh V threshold, ultra-high voltage threshold) N-type lightly doped drain (N LDD) process / UHVT (Ultra high Vthreshold, ultra-high voltage threshold) P-type lightly doped drain (P LDD) process / ULVT (Ultra Low V threshold, ultra-low voltage threshold) N-type lightly doped drain (N LDD) process / ULVT (Ultra Low V threshold, ultra-low voltage threshold) P-type lightly doped drain (P LDD) process.

[0008] Lower threshold voltages result in lower saturation current, leading to higher speed performance. However, this also increases leakage current, resulting in lower power consumption. The speed ranking, from fastest to slowest, is ULVT, LVT, SVT, HVT, and UHVT. The power consumption, however, is the opposite.

[0009] Logic devices in the logic area using the ULVT (Ultra Low V threshold) lightly doped drain (LDD) process have the highest doping concentration, the lowest threshold voltage, the lowest saturation current, the highest speed performance, the highest leakage current, and the highest leakage power consumption.

[0010] In a conventional 8-transistor, 2-port static random access memory (8T2P SRAM) fabricated using a flat transistor process, each cell PFET device shares a cell P-type lightly doped drain mask (Cell PLDD mask) to adjust the threshold voltage Vt. Each cell NFET device shares a cell N-type lightly doped drain mask (Cell N LDD mask) to adjust the threshold voltage Vt and its on-state current Ids. Because each cell NFET device uses only a cell N-type lightly doped drain mask (Cell N LDD mask), the electrical properties of the two external N-type transistors (fifth N-transistor RP PG and sixth N-transistor RP PD) serving as the read port must match those of the two internal N-type transistors (second N-transistor PD2 and fourth N-transistor PG2). To maintain SRAM read / write balance (Read / Write Balance), the SRAM must be fabricated with a 1 / 4-th N-type transistor (Cell N LDD mask). To ensure a balanced read / write state, the leakage current cannot be too high and the speed cannot be too slow. Therefore, the threshold voltage Vt and the conduction current Ids of the 6 transistors (6T Device) inside the SRAM memory cell are specially adjusted to a certain potential. As a result, the read port operation speed is limited. The corresponding results of the conduction current Ids of each N-type / P-type field effect transistor of the memory cell (Cell N / PFET IDS) are as follows: Figure 4 shown. Summary of the Invention

[0011] The technical problem to be solved by the present invention is to provide a manufacturing method for an 8-transistor 2-port static random access memory, which can adjust the read current Iread and read speed of the B port (read port) without affecting the read / write balance (Read / Write Balance) of the 6T SRAM inside the memory cell, without requiring additional masks or process steps.

[0012] To solve the above technical problems, the present invention provides a method for manufacturing an 8-tube 2-port static random access memory, which includes the following steps:

[0013] S1. First, simultaneously perform the N LDD process of the first N transistor PD1, the second N transistor PD2, the third N transistor PG1, and the fourth N transistor PG2 in the chip memory area;

[0014] S2. Then simultaneously perform the P LDD process of the first P transistor PU1 and the second P transistor PU2 in the chip memory area;

[0015] S3. Then, when performing the LDD process for the logic devices in the chip logic area, select an ion implantation mask for an NFET logic device, open the source and drain regions of the fifth N transistor RP PG and the sixth N transistor RP PD for ion implantation, and complete the N LDD process for the fifth N transistor RP PG and the sixth N transistor RP PD.

[0016] Preferably, in step S3, the ion implantation mask is an ion implantation mask for an HVT N LDD process, an LVT N LDD process, an SVT N LDD process, an UHVT N LDD process or an ULVT N LDD process of an NFET in the logic region of the chip.

[0017] Preferably, in step S3, the ion implantation mask is an ion implantation mask for an LVT N LDD process, an SVT N LDD process or an ULVT N LDD process of an NFET in the logic region of the chip.

[0018] Preferably, in step S3, the ion implantation mask is an ion implantation mask for a HVT N LDD process, a UHVT N LDD process, or a SVT N LDD process of an NFET in the logic region of the chip.

[0019] Preferably, the 8-transistor 2-port static random access memory includes a first N-transistor PD1, a second N-transistor PD2, a third N-transistor PG1, a fourth N-transistor PG2, a first P-transistor PU1, a second P-transistor PU2, a fifth N-transistor RPPG and a sixth N-transistor RPPD;

[0020] The source terminals of the first P-transistor PU1 and the second P-transistor PU2 are connected to the operating voltage Vdd;

[0021] The gate terminal of the first P-transistor PU1, the drain terminal of the second P-transistor PU2, the gate terminal of the first N-transistor PD1, the drain terminal of the second N-transistor PD2 and the gate terminal of the fifth N-transistor RP PG are all connected to the second node n2;

[0022] The gate terminal of the second P-transistor PU2, the drain terminal of the first P-transistor PU1, the gate terminal of the second N-transistor PD2 and the drain terminal of the first N-transistor PD1 are all connected to the first node n1;

[0023] The gate terminals of the third N transistor PG1 and the fourth N transistor PG2 are connected to the A word line A-WL;

[0024] The source and drain of the third N-transistor PG1 are connected to the first node n1 and the first bit line BL1 respectively;

[0025] The source and drain of the fourth N-transistor PG2 are connected to the second node n2 and the second bit line BL2 respectively;

[0026] The fifth N-transistor RP PG has a gate terminal connected to the B word line B-WL, and a source and drain terminal connected to the drain terminal of the sixth N-transistor RP PD and the B port bit line B-BL respectively;

[0027] The source terminal of the first N-transistor PD1, the source terminal of the second N-transistor PD2 and the source terminal of the sixth N-transistor RP PD are connected to the common ground Vss;

[0028] The A-word line A-WL, the first bit line BL1 and the second bit line BL2 belong to the A port;

[0029] The B word line B-WL and the B port bit line belong to the B port;

[0030] A first N-transistor PD1 , a second N-transistor PD2 , a third N-transistor PG1 , a fourth N-transistor PG2 , a first P-transistor PU1 , and a second P-transistor PU2 are disposed in a memory area.

[0031] Preferably, the fifth N-transistor RP PG and the sixth N-transistor RP PD are disposed in the memory area or the external logic area.

[0032] Preferably, the fifth N-transistor RP PG and the sixth N-transistor RP PD are JFETs or MOSFETs.

[0033] Preferably, the first P transistor PU1 and the second P transistor PU2 are PMOS transistors;

[0034] The first N-transistor PD1 , the second N-transistor PD2 , the third N-transistor PG1 , and the fourth N-transistor PG2 are NMOS transistors.

[0035] Preferably, the chip plane layout structure of the 8-tube 2-port static random access memory is:

[0036] The first P-transistor PU1 is located on the left side of the second P-transistor PU2;

[0037] The first N-transistor PD1 and the third N-transistor PG1 are located on the left side of the first P-transistor PU1, and the first P-transistor PU1 is located in front of the third N-transistor PG1;

[0038] The second N-transistor PD2 and the fourth N-transistor PG2 are located to the right of the second P-transistor PU2, and the second N-transistor PD2 is located behind the fourth N-transistor PG2;

[0039] The fifth N-transistor RP PG and the sixth N-transistor RP PD are located on the right side of the second N-transistor PD2 and the fourth N-transistor PG2 , and the sixth N-transistor RP PD is located behind the fifth N-transistor RP PG.

[0040] Preferably, the left-right center lines of the gate polysilicon of the first P-transistor PU1, the first N-transistor PD1, the fourth N-transistor PG2 and the fifth N-transistor RP PG are on the same straight line;

[0041] The left-right center lines of the gate polysilicon layers of the second P-transistor PU2 , the third N-transistor PG1 , the second N-transistor PD2 , and the sixth N-transistor RP PD are on the same straight line.

[0042] The present invention relates to a method for manufacturing an 8-transistor 2-port static random access memory (8T2P SRAM). The lightly doped drain (N LDD) process for six transistors (a first N-transistor PD1, a second N-transistor PD2, a third N-transistor PG1, a fourth N-transistor PG2, a first P-transistor PU1, and a second P-transistor PU2) within the memory area of the chip uses the original cell N lightly doped drain mask (Cell N LDD mask) PG PD and the cell P lightly doped drain mask (Cell P LDD mask) PU. The fifth N-transistor RP PG and the sixth N-transistor RP PD of the B port (read port) are separated from the original cell N lightly doped drain mask (Cell N LDD mask). The original cell N lightly doped drain mask (Cell N LDD mask) PG PD is not used for N ion implantation. Instead, a logic device N field effect transistor threshold voltage adjustment mask (Logic device NFETVt mask) is used. Simultaneously with the lightly doped drain (LDD) process for the logic devices within the logic area of the chip, the N Rvt / N Lvt / N An ion implantation mask of Hvt / N uHvt / N uLvt is selected to open the source and drain regions of the fifth N-type transistor RP PG and the sixth N-type transistor RP PD for ion implantation, completing the N-type lightly doped drain (NLDD) process of the fifth N-type transistor RP PG and the sixth N-type transistor RP PD. This is used to adjust the threshold voltage Vt and source-drain conduction current Ids of the fifth N-type transistor RP PG and the sixth N-type transistor RP PD, thereby adjusting the read current Iread of the B port (read port) and the read speed, as shown in FIG. Figure 6This method does not affect the read / write balance of the 6T SRAM within the memory cell. The memory cell remains stable, and no additional masks or process steps are required. It also does not affect the complexity of the process and does not require the addition of new sites. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 It is a typical 8T2P SRAM circuit;

[0045] Figure 2 This is a typical 8T2P SRAM floor plan;

[0046] Figure 3 This is a schematic diagram of the existing process mask of 8T2P SRAM;

[0047] Figure 4 This is a typical 8T2P SRAM memory cell NMOS / PMOS source-drain current correspondence diagram;

[0048] Figure 5 1 is a schematic diagram of an embodiment of a method for manufacturing an 8T2P SRAM according to the present invention;

[0049] Figure 6 The different source-drain currents IDS correspond to the leakage currents in an embodiment of the manufacturing method of the 8T2P SRAM of the present invention. DETAILED DESCRIPTION

[0050] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without creative work are within the scope of protection of the present invention.

[0051] The terms "first", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.

[0052] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0053] Example 1

[0054] A method for manufacturing an 8-tube 2-port static random access memory (8T2P SRAM) is provided. Figure 1 As shown, the 8-transistor 2-port static random access memory (8T2P SRAM) includes a first N-transistor PD1, a second N-transistor PD2, a third N-transistor PG1, a fourth N-transistor PG2, a first P-transistor PU1, a second P-transistor PU2, a fifth N-transistor RP PG, and a sixth N-transistor RPPD;

[0055] The source terminals of the first P-transistor PU1 and the second P-transistor PU2 are connected to the operating voltage Vdd;

[0056] The gate terminal of the first P-transistor PU1, the drain terminal of the second P-transistor PU2, the gate terminal of the first N-transistor PD1, the drain terminal of the second N-transistor PD2 and the gate terminal of the fifth N-transistor RP PG are all connected to the second node n2;

[0057] The gate terminal of the second P-transistor PU2, the drain terminal of the first P-transistor PU1, the gate terminal of the second N-transistor PD2 and the drain terminal of the first N-transistor PD1 are all connected to the first node n1;

[0058] The gate terminals of the third N transistor PG1 and the fourth N transistor PG2 are connected to the A word line A-WL;

[0059] The source and drain of the third N-transistor PG1 are connected to the first node n1 and the first bit line BL1 respectively;

[0060] The source and drain of the fourth N-transistor PG2 are connected to the second node n2 and the second bit line BL2 respectively;

[0061] The fifth N-transistor RP PG has a gate terminal connected to the B word line B-WL, and a source and drain terminal connected to the drain terminal of the sixth N-transistor RP PD and the B port bit line B-BL respectively;

[0062] The source terminal of the first N-transistor PD1, the source terminal of the second N-transistor PD2 and the source terminal of the sixth N-transistor RP PD are connected to the common ground Vss;

[0063] The A-word line A-WL, the first bit line BL1, and the second bit line BL2 belong to the A port. The A port is a 6-transistor single port (6T single port) that can be written and read with a normal operating speed.

[0064] The B-word line (B-WL) and the B-port bit line belong to the B-port. The B-port is a single port capable of high-speed reading and is a read port consisting of two N-type transistors.

[0065] A first N-transistor PD1 , a second N-transistor PD2 , a third N-transistor PG1 , a fourth N-transistor PG2 , a first P-transistor PU1 , and a second P-transistor PU2 are disposed in a memory area.

[0066] Its manufacturing method is as follows Figure 5 As shown, the following steps are included:

[0067] S1. First, simultaneously perform an N-type lightly doped drain (N LDD) process on the first N transistor PD1, the second N transistor PD2, the third N transistor PG1, and the fourth N transistor PG2 in the chip memory area;

[0068] S2. Then simultaneously perform a P-type lightly doped drain (PLDD) process on the first P transistor PU1 and the second P transistor PU2 in the chip memory area;

[0069] S3. Then, while performing the lightly doped drain (LDD) process on the logic devices in the chip logic area, select an ion implantation mask for an NFET (N-type field-effect transistor) logic device, open the source and drain regions of the fifth N-transistor RP PG and the sixth N-transistor RP PD for ion implantation, and complete the N-type lightly doped drain (NLDD) process on the fifth N-transistor RP PG and the sixth N-transistor RP PD.

[0070] Preferably, in step S3, the ion implantation mask is an ion implantation mask for an HVT (high V threshold) N-type lightly doped drain (N LDD) process, an LVT (low V threshold) N-type lightly doped drain (N LDD) process, an SVT (standard V threshold) N-type lightly doped drain (N LDD) process, an UHVT (ultra high V threshold) N-type lightly doped drain (N LDD) process, or an ULVT (ultra low V threshold) N-type lightly doped drain (N LDD) process of an NFET (n-type field effect transistor) in the logic area of the chip.

[0071] Preferably, in step S3, the ion implantation mask is an ion implantation mask for an LVT (Low V threshold) N-type lightly doped drain (N LDD) process, an SVT (Standard V threshold) N-type lightly doped drain (N LDD) process, or an ULVT (Ultra Low V threshold) N-type lightly doped drain (N LDD) process for an NFET (N-type field effect transistor) within the chip's logic region. This process is suitable for 8-transistor 2-port static random access memory (8T2P SRAM) chips, which require higher speeds and can tolerate higher leakage currents.

[0072] Preferably, in step S3, the ion implantation mask is an ion implantation mask for an HVT (high V threshold) N-type lightly doped drain (N LDD) process, a UHVT (ultra high V threshold) N-type lightly doped drain (N LDD) process, or an SVT (standard V threshold) N-type lightly doped drain (N LDD) process for an NFET (N-type field effect transistor) within the chip's logic region. This process is suitable for 8-transistor 2-port static random access memory (8T2P SRAM) chips that require lower power consumption and can tolerate slower operating speeds.

[0073] Preferably, the fifth N-transistor RP PG and the sixth N-transistor RP PD are disposed in the memory area or the external logic area.

[0074] Preferably, the fifth N-transistor RP PG and the sixth N-transistor RP PD are junction field effect transistors JFETs or metal oxide semiconductor field effect transistors MOSFETs.

[0075] Preferably, the first P transistor PU1 and the second P transistor PU2 are PMOS transistors;

[0076] The first N-transistor PD1 , the second N-transistor PD2 , the third N-transistor PG1 , and the fourth N-transistor PG2 are NMOS transistors.

[0077] According to the electrical characteristics of the fifth N-transistor RP PG and the sixth N-transistor RP PD of the 8-transistor 2-port static random access memory (8T2P SRAM), the threshold voltage Vt and the source-drain conduction current Ids of the fifth N-transistor RP PG and the sixth N-transistor RP PD do not affect the read / write balance during data operations within the memory cell. Since the threshold voltage Vt and source-drain conduction current Ids of planar transistor devices can be adjusted through ion implantation, in the manufacturing method of the 8-transistor 2-port static random access memory (8T2P SRAM) of the first embodiment, the lightly doped drain (N LDD) process of the six transistors (first N transistor PD1, second N transistor PD2, third N transistor PG1, fourth N transistor PG2, first P transistor PU1, and second P transistor PU2) in the memory area of the chip uses the original memory cell N lightly doped drain mask (Cell N LDD mask) PG PD and memory cell P lightly doped drain mask (Cell P LDD mask) PU, and the fifth N transistor RP PG and the sixth N transistor RP PD of the B port (read port) are separated from the original memory cell N lightly doped drain mask (Cell N LDD mask). The original memory cell N lightly doped drain mask (Cell N LDD mask) PG PD is not used for N ion implantation, and the logic device N FET threshold voltage adjustment mask (Logic device NFET Vt is used). While performing the lightly doped drain (LDD) process for the logic devices in the logic area of the chip, one of the NRvt / NLvt / NHvt / NuHvt / NuLvt ion implantation masks is selected to open the source and drain regions of the fifth N-type transistor RPPG and the sixth N-type transistor RPPD for ion implantation, completing the N-type lightly doped drain (NLDD) process for the fifth N-type transistor RPPG and the sixth N-type transistor RPPD. This is used to adjust the threshold voltage Vt and source-drain conduction current Ids of the fifth N-type transistor RPPG and the sixth N-type transistor RPPD, thereby adjusting the read current Iread of the B port (read port) and the read speed. Figure 6This method does not affect the read / write balance of the 6T SRAM within the memory cell. The memory cell remains stable, and no additional masks or process steps are required. It also does not affect the complexity of the process and does not require the addition of new sites.

[0078] Example 2

[0079] Based on the manufacturing method of the 8-tube 2-port static random access memory (8T2P SRAM) of the embodiment 1, the chip plane layout structure of the 8-tube 2-port static random access memory (8T2P SRAM) is as follows: Figure 5 As shown:

[0080] The first P-transistor PU1 is located on the left side of the second P-transistor PU2;

[0081] The first N-transistor PD1 and the third N-transistor PG1 are located on the left side of the first P-transistor PU1, and the first P-transistor PU1 is located in front of the third N-transistor PG1;

[0082] The second N-transistor PD2 and the fourth N-transistor PG2 are located to the right of the second P-transistor PU2, and the second N-transistor PD2 is located behind the fourth N-transistor PG2;

[0083] The fifth N-transistor RP PG and the sixth N-transistor RP PD are located on the right side of the second N-transistor PD2 and the fourth N-transistor PG2 , and the sixth N-transistor RP PD is located behind the fifth N-transistor RP PG.

[0084] Preferably, the left-right center lines of the gate polysilicon of the first P-transistor PU1, the first N-transistor PD1, the fourth N-transistor PG2 and the fifth N-transistor RP PG are on the same straight line;

[0085] The left-right center lines of the gate polysilicon layers of the second P-transistor PU2 , the third N-transistor PG1 , the second N-transistor PD2 , and the sixth N-transistor RP PD are on the same straight line.

[0086] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for manufacturing an 8-tube 2-port static random access memory, characterized in that: It includes the following steps: S1. First, simultaneously perform the N LDD process of the first N transistor (PD1), the second N transistor (PD2), the third N transistor (PG1), and the fourth N transistor (PG2) in the chip memory area; S2. Then simultaneously perform the P LDD process of the first P transistor (PU1) and the second P transistor (PU2) in the chip memory area; S3. Then, when performing the LDD process for the logic devices in the chip logic area, select an ion implantation mask for an NFET logic device, open the source and drain regions of the fifth N transistor (RP PG) and the sixth N transistor (RP PD) for ion implantation, and complete the N LDD process for the fifth N transistor (RP PG) and the sixth N transistor (RP PD).

2. The method for manufacturing an 8-channel 2-port static random access memory according to claim 1, wherein: In step S3 , the ion implantation mask is an ion implantation mask for a HVT N LDD process, a LVT NLDD process, a SVT N LDD process, a UHVT N LDD process, or a ULVT N LDD process of an NFET in a logic region of the chip.

3. The method for manufacturing an 8-channel 2-port static random access memory according to claim 1, wherein: In step S3 , the ion implantation mask is an ion implantation mask for an LVT N LDD process, an SVT NLDD process, or an ULVT N LDD process of an NFET in a logic region of the chip.

4. The method for manufacturing an 8-pipe 2-port static random access memory according to claim 1, wherein: In step S3 , the ion implantation mask is an ion implantation mask for a HVT N LDD process, a UHVT NLDD process, or a SVT N LDD process of an NFET in a logic region of the chip.

5. The method for manufacturing an 8-pipe 2-port static random access memory according to claim 1, wherein: The 8-transistor 2-port static random access memory includes a first N-transistor (PD1), a second N-transistor (PD2), a third N-transistor (PG1), a fourth N-transistor (PG2), a first P-transistor (PU1), a second P-transistor (PU2), a fifth N-transistor (RPPG) and a sixth N-transistor (RPPD); The source terminals of the first P transistor (PU1) and the second P transistor (PU2) are connected to an operating voltage (Vdd); The gate terminal of the first P transistor (PU1), the drain terminal of the second P transistor (PU2), the gate terminal of the first N transistor (PD1), the drain terminal of the second N transistor (PD2) and the gate terminal of the fifth N transistor (RP PG) are connected to the second node (n2); The gate terminal of the second P transistor (PU2), the drain terminal of the first P transistor (PU1), the gate terminal of the second N transistor (PD2) and the drain terminal of the first N transistor (PD1) are all connected to the first node (n1); Gate terminals of the third N-transistor (PG1) and the fourth N-transistor (PG2) are connected to the A-word line (A-WL); The source and drain of the third N-type transistor (PG1) are respectively connected to the first node (n1) and the first bit line (BL1); The source and drain of the fourth N-type transistor (PG2) are respectively connected to the second node (n2) and the second bit line (BL2); a fifth N-transistor (RP PG), having a gate terminal connected to the B-word line (B-WL), and a source and drain terminal connected to the drain terminal of the sixth N-transistor (RP PD) and the B-port bit line (B-BL), respectively; A source terminal of the first N-transistor (PD1), a source terminal of the second N-transistor (PD2), and a source terminal of the sixth N-transistor (RP PD) are connected to a common ground (Vss); The A-word line (A-WL), the first bit line (BL1), and the second bit line (BL2) belong to the A port; The B-word line (B-WL) and the B-port bit line belong to the B-port; A first N-transistor (PD1), a second N-transistor (PD2), a third N-transistor (PG1), a fourth N-transistor (PG2), a first P-transistor (PU1) and a second P-transistor (PU2) are disposed in a memory area.

6. The method for manufacturing an 8-pipe 2-port static random access memory according to claim 5, wherein: The fifth N transistor (RP PG) and the sixth N transistor (RP PD) are disposed in the memory area or the external logic area.

7. The method for manufacturing an 8-channel 2-port static random access memory according to claim 5, wherein: The fifth N-transistor (RP PG) and the sixth N-transistor (RP PD) are JFETs or MOSFETs.

8. The method for manufacturing an 8-channel 2-port static random access memory according to claim 5, wherein: The first P transistor (PU1) and the second P transistor (PU2) are PMOS transistors; The first N-transistor (PD1), the second N-transistor (PD2), the third N-transistor (PG1) and the fourth N-transistor (PG2) are NMOS transistors.

9. The method for manufacturing an 8-pipe 2-port static random access memory according to claim 1, wherein: The chip layout structure of 8-tube 2-port static random access memory is as follows: The first P transistor (PU1) is located on the left side of the second P transistor (PU2); The first N transistor (PD1) and the third N transistor (PG1) are located on the left side of the first P transistor (PU1), and the first P transistor (PU1) is located in front of the third N transistor (PG1); The second N-transistor (PD2) and the fourth N-transistor (PG2) are located on the right side of the second P-transistor (PU2), and the second N-transistor (PD2) is located behind the fourth N-transistor (PG2); The fifth N transistor (RP PG) and the sixth N transistor (RP PD) are located on the right side of the second N transistor (PD2) and the fourth N transistor (PG2), and the sixth N transistor (RP PD) is located behind the fifth N transistor (RP PG).

10. The method for manufacturing an 8-tube 2-port static random access memory according to claim 9, wherein: The left-right center lines of the gate polysilicon of the first P transistor (PU1), the first N transistor (PD1), the fourth N transistor (PG2), and the fifth N transistor (RP PG) are on the same straight line; The left-right center lines of the gate polysilicon of the second P transistor (PU2), the third N transistor (PG1), the second N transistor (PD2) and the sixth N transistor (RP PD) are on the same straight line.

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