Semiconductor structure

Abstract

The invention provides a semiconductor structure. The semiconductor structure comprises a substrate, a first buried gate structure and a second buried gate structure, the substrate has an array region and a surrounding region. The first buried gate structure extends into the substrate along a first direction from a first surface of the substrate and is disposed in the array region. The second buried gate structure extends into the substrate along the first direction from the first surface of the substrate and is disposed in the peripheral region. A depth of the first buried gate structure is smaller than a depth of the second buried gate structure along the first direction.

Description

[0001] Cross-references

[0002] This application claims priority to U.S. patent application No. 18 / 430,890 (i.e., the priority date is "February 2, 2024"), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a semiconductor structure, and more particularly to a semiconductor structure having a plurality of relatively wide channels. Background Art

[0004] Depending on the functions and requirements of electronic components, semiconductor structures can be divided into a dense region and a sparse region. Therefore, it's not necessary to manufacture electronic components of the same size in both regions. In other words, the manufacturing processes for the dense and sparse regions don't necessarily need to be the same.

[0005] The above description of “prior art” only provides background technology, does not admit that the above description of “prior art” discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of the present disclosure. Summary of the Invention

[0006] One embodiment of the present disclosure provides a semiconductor structure comprising a substrate, a first buried gate structure, and a second buried gate structure. The substrate has an array region and a peripheral region. The first buried gate structure extends from a first surface of the substrate into the substrate along a first direction and is disposed in the array region. The second buried gate structure extends from the first surface of the substrate into the substrate along the first direction and is disposed in the peripheral region. A depth of the first buried gate structure is less than a depth of the second buried gate structure along the first direction.

[0007] Another embodiment of the present disclosure provides a method for fabricating a semiconductor structure. The method includes providing a substrate having an array region and a peripheral region; forming a first opening and a second opening in the array region and the peripheral region, respectively; forming a third opening through the second opening; and forming a first buried gate structure and a second buried gate structure. The first buried gate structure is formed in the first opening, and the second buried gate structure is formed in the second opening and the third opening.

[0008] The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those skilled in the art to which the present disclosure belongs that such equivalent constructions cannot depart from the concept and scope of the present disclosure as defined by the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] When with Figure 1 Various aspects of the present disclosure will be best understood from the following detailed description when read together. It should be understood that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0010] Figure 1 is a schematic diagram illustrating a semiconductor structure according to some embodiments of the present disclosure.

[0011] Figure 2A FIG. 4 is a schematic diagram illustrating a first buried gate structure of a semiconductor structure according to some embodiments of the present disclosure.

[0012] Figure 2B FIG. 2 is a schematic diagram illustrating a second buried gate structure of a semiconductor structure according to some embodiments of the present disclosure.

[0013] Figure 3 is a schematic diagram illustrating a semiconductor structure according to another embodiment of the present disclosure.

[0014] Figure 4 Schematic diagrams illustrating semiconductor structures according to different embodiments of the present disclosure.

[0015] Figure 5 is a schematic diagram illustrating a semiconductor structure according to an alternative embodiment of the present disclosure.

[0016] Figure 6 FIG2 is a schematic diagram illustrating a semiconductor structure according to another embodiment of the present disclosure.

[0017] Figure 7 1 is a flow chart illustrating a method for preparing a semiconductor structure according to an embodiment of the present disclosure.

[0018] Figure 8 It is a schematic diagram illustrating some embodiments of the present disclosure. Figure 1 An intermediate stage of the semiconductor structure is shown.

[0019] Figure 9 It is a schematic diagram illustrating some embodiments of the present disclosure. Figure 1An intermediate stage of the semiconductor structure is shown.

[0020] Figure 10 It is a schematic diagram illustrating some embodiments of the present disclosure. Figure 1 An intermediate stage of the semiconductor structure is shown.

[0021] Figure 11 It is a schematic diagram illustrating some embodiments of the present disclosure. Figure 1 An intermediate stage of the semiconductor structure is shown.

[0022] Figure 12 It is a schematic diagram illustrating some embodiments of the present disclosure. Figure 1 An intermediate stage of the semiconductor structure is shown.

[0023] Figure 13 It is a schematic diagram illustrating some embodiments of the present disclosure. Figure 1 An intermediate stage of the semiconductor structure is shown.

[0024] Figure 14 It is a schematic diagram illustrating some embodiments of the present disclosure. Figure 1 An intermediate stage of the semiconductor structure is shown.

[0025] Figure 15 It is a schematic diagram illustrating some embodiments of the present disclosure. Figure 1 An intermediate stage of the semiconductor structure is shown.

[0026] Figure 16 It is a schematic diagram illustrating some embodiments of the present disclosure. Figure 1 An intermediate stage of the semiconductor structure is shown.

[0027] Figure 17 It is a schematic diagram illustrating some embodiments of the present disclosure. Figure 1 An intermediate stage of the semiconductor structure is shown.

[0028] Figure 18 It is a schematic diagram illustrating some embodiments of the present disclosure. Figure 1 An intermediate stage of the semiconductor structure is shown.

[0029] Description of reference numerals:

[0030] 10: Semiconductor structure

[0031] 30: Semiconductor structure

[0032] 40: Semiconductor structure

[0033] 50: Semiconductor structure

[0034] 60: Semiconductor Structure

[0035] 70: Preparation method

[0036] 100: Base

[0037] 100B: bottom surface

[0038] 100T: upper surface

[0039] 101: Doping area

[0040] 102: Doping area

[0041] 103: Doping area

[0042] 104: Doping area

[0043] 105: Doping area

[0044] 106: Doping area

[0045] 107: Channel Area

[0046] 108: Channel Area

[0047] 120: First buried gate structure

[0048] 120D: Depth

[0049] 120P: protruding part

[0050] 120W: Width

[0051] 121: Gate dielectric layer

[0052] 122: Gate electrode

[0053] 123: Cover layer

[0054] 140: Second buried gate structure

[0055] 140D: Depth

[0056] 140P: protruding part

[0057] 140P1: lower part

[0058] 140P2: upper part

[0059] 140W: Width

[0060] 141: Gate dielectric layer

[0061] 142: Gate electrode

[0062] 143: Cover layer

[0063] 160: Isolation Structure

[0064] 160D: Depth

[0065] 180: Metal wire

[0066] 340: Second buried gate structure

[0067] 340P: Protruding part

[0068] 340P1: lower part

[0069] 340P2: Upper part

[0070] 341: Gate dielectric layer

[0071] 342: Gate electrode

[0072] 343: Cover layer

[0073] 440: Second buried gate structure

[0074] 440P: Protruding part

[0075] 440P1: lower part

[0076] 440P2: upper part

[0077] 441: Gate dielectric layer

[0078] 442: Gate electrode

[0079] 443: Cover layer

[0080] 540: Second buried gate structure

[0081] 540P: Protruding part

[0082] 540P1: lower part

[0083] 540P2: Upper part

[0084] 541: Gate dielectric layer

[0085] 542: Gate electrode

[0086] 543: Cover layer

[0087] 620: First buried gate structure

[0088] 621: Gate dielectric layer

[0089] 622: Gate electrode

[0090] 623: Cover layer

[0091] 624: Barrier Layer

[0092] 640: Second buried gate structure

[0093] 641: Gate dielectric layer

[0094] 642: Gate electrode

[0095] 643: Cover layer

[0096] 644: Barrier Layer

[0097] 701: Mask layer

[0098] 701T1: Thickness

[0099] 701T2: Thickness

[0100] 703: Dielectric layer

[0101] A: Array area

[0102] AA: Active Area

[0103] AAD: Depth

[0104] B: Surrounding area

[0105] L1: left length

[0106] L10: third bottom length

[0107] L2: right length

[0108] L3: bottom length

[0109] L4: First left length

[0110] L5: Second left length

[0111] L6: First right length

[0112] L7: Second right length

[0113] L8: first bottom length

[0114] L9: Second bottom length

[0115] O1: Opening

[0116] O2: Opening

[0117] O2B: bottom surface

[0118] O3: Opening

[0119] S72: Steps

[0120] S74: Steps

[0121] S76: Steps

[0122] S78: Steps

[0123] S80: Steps

[0124] X: Direction

[0125] Y: direction

[0126] θ1: Angle

[0127] θ2: Angle DETAILED DESCRIPTION

[0128] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, the description of a first component formed on a second component may include embodiments in which the first and second components are in direct contact, and may also include embodiments in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is for simplicity and clarity, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0129] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0130] Figure 1 FIG2 is a schematic diagram illustrating a semiconductor structure 10 according to some embodiments of the present disclosure. In some embodiments, the semiconductor structure 10 may include a memory structure, such as a dynamic random access memory (DRAM).

[0131] The semiconductor structure 10 has an array region A and a peripheral region B. In some embodiments, memory cells may be implemented in the array region A, and controller circuits may be implemented in the peripheral region B. In some embodiments, the array region A is also referred to as a dense region having a higher device density, while the peripheral region B is also referred to as a sparse region having a lower device density.

[0132] The semiconductor structure 10 includes a substrate 100 , a plurality of first buried gate structures 120 , a plurality of second buried gate structures 140 , a plurality of isolation structures 160 and a plurality of metal lines 180 .

[0133] In some embodiments, each first buried gate structure 120 is identical to each other, and each second buried gate structure 140 is identical to each other. Therefore, for the sake of brevity, the following description will only detail one of the first buried gate structures 120 and one of the second buried gate structures 140.

[0134] In some embodiments, the substrate 100 is a semiconductor wafer, such as a silicon wafer. In some embodiments, the substrate 100 may include an elemental semiconductor material, a compound semiconductor material, and / or an alloy semiconductor material. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0135] In some embodiments, substrate 100 includes an epitaxial layer. For example, substrate 100 includes an epitaxial layer covering a bulk semiconductor. In some embodiments, substrate 100 is a semiconductor-on-insulator substrate, which may include a substrate, a buried oxide layer overlying the substrate, and a semiconductor layer overlying the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate may be fabricated using separation by implantation of oxygen (SIMOX), die bonding, and / or other suitable methods.

[0136] The substrate 100 has an upper surface 100T and a lower surface 100B opposite to the upper surface 100T. The substrate 100 includes an active area AA. The active area AA is formed on the upper portion of the substrate 100, wherein the active area AA is coplanar with the upper surface 100T of the substrate 100.

[0137] A first buried gate structure 120, a second buried gate structure 140, and an isolation structure 160 are disposed in the substrate 100 and extend from the upper surface 100T along a Y-direction toward the lower surface 100B. The first buried gate structure 120 is disposed in the array region A, and the second buried gate structure 140 is disposed in the peripheral region B. The isolation structure 160 is disposed in both the array region A and the peripheral region B.

[0138] like Figure 1As shown, the first buried gate structure 120, the second buried gate structure 140, and the isolation structure 160 protrude from a lower surface of the active area AA. In other words, each of a depth 120D of the first buried gate structure 120, a depth 140D of the second buried gate structure 140, and a depth 160D of the isolation structure 160 is greater than a depth AAD of the active area AA.

[0139] The active area AA includes a doped region 101, a doped region 102, a doped region 103, a doped region 104, a doped region 105, and a doped region 106. Doped regions 101, 102, and 103 are sequentially arranged along an X-direction in the array area A, while doped regions 104, 105, and 106 are sequentially arranged along the X-direction in the peripheral area B. In some embodiments, the X-direction is perpendicular to the Y-direction. A first buried gate structure 120 intersects with the doped regions 101, 102, and 103, and a second buried gate structure 140 intersects with the doped regions 104, 105, and 106.

[0140] like Figure 1 As shown, at least two isolation structures 160 are disposed in the array region A, and at least two isolation structures 160 are disposed in the peripheral region B. The first buried gate structure 120, the doped region 101, the doped region 102, and the doped region 103 are disposed between the two isolation structures 160 in the array region A. The second buried gate structure 140, the doped region 104, the doped region 105, and the doped region 106 are disposed between the two isolation structures 160 in the peripheral region B.

[0141] In some embodiments, the isolation structure 160 is a shallow trench isolation (STI) and may include at least one of silicon nitride, silicon oxide, or silicon oxynitride.

[0142] Metal lines 180 are disposed over substrate 100 and contact doped regions 101, 102, 103, 104, 105, and 106, respectively. Metal lines 180 are electrically coupled to doped regions 101, 102, 103, 104, 105, and 106. In some embodiments, metal lines 180 include a metal, such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), alloys thereof, combinations thereof, or any metal material having an appropriate resistance value.

[0143] The first buried gate structure 120 includes a gate dielectric layer 121 and a gate electrode 122, and the second buried gate structure 140 includes a gate dielectric layer 141 and a gate electrode 142. The gate dielectric layer 121 extends along a contour of the first buried gate structure 120, and the gate electrode 122 is surrounded by the gate dielectric layer 121. The gate electrode 122 is separated and isolated from the substrate 100 by the gate dielectric layer 121. The gate dielectric layer 141 extends along a contour of the second buried gate structure 140, and the gate electrode 142 is surrounded by the gate dielectric layer 141. The gate electrode 142 is separated and isolated from the substrate 100 by the gate dielectric layer 141.

[0144] In some embodiments, the gate dielectric layer 121 and the gate dielectric layer 141 include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, a high-k dielectric material, or other suitable dielectric materials. The high-k dielectric material may include HfO2, HfErO, HfLaO, HfYO, HfGdO, HfAlO, HfZrO, HfTiO, HfTaO, ZrO2, Y2O3, La2O5, Gd2O5, TiO2, Ta2O5, SrTiO, or combinations thereof.

[0145] In some embodiments, gate electrode 122 and gate electrode 142 may include multiple layers, such as a lower electrode layer and an upper electrode layer. In such embodiments, the lower electrode layer may include a work function material, such as titanium, titanium nitride, silicon, silicon germanium, or a combination thereof; and the upper electrode layer may include polysilicon, polycrystalline germanium, polycrystalline silicon germanium, doped polysilicon, doped polycrystalline germanium, doped polysilicon germanium, or a combination thereof. In some embodiments, the upper electrode layer may be doped with a p-type dopant or an n-type dopant. It should be understood that the term "work function" refers to the overall chemical potential of a material (e.g., a metal) relative to the vacuum level.

[0146] In some embodiments, semiconductor structure 10 includes a plurality of transistors. First buried gate structure 120 and second buried gate structure 140 are configured as gates of the transistors, and doped regions 101 through 106 are configured as sources and drains of the transistors. In such embodiments, gate electrode 122 and / or gate electrode 142 are configured as a word line of a memory, and metal line 180 is configured as a bit line of the memory.

[0147] The first buried gate structure 120 further includes a capping layer 123, and the second buried gate structure 140 further includes a capping layer 143. The capping layer 123 is disposed over the gate electrode 122 and separated from the substrate 100 by the gate dielectric layer 121, and the capping layer 143 is disposed over the gate electrode 142 and separated from the substrate 100 by the gate dielectric layer 141.

[0148] like Figure 1 As shown, cap layer 123 extends over gate dielectric layer 121, and cap layer 143 extends over gate dielectric layer 141. In some embodiments, sidewalls of cap layer 123 are aligned with sidewalls of gate dielectric layer 121, and sidewalls of cap layer 143 are aligned with sidewalls of gate dielectric layer 141. Cap layer 123 and cap layer 143 are in contact with metal line 180. Metal line 180 extends over cap layer 123 and cap layer 143.

[0149] In some embodiments, the cap layer 123 and the cap layer 143 include a dielectric material. In some embodiments, the cap layer 123 and the cap layer 143 include silicon nitride, silicon oxide, or silicon oxynitride.

[0150] As described above, the density of electronic components in the array region A is greater than the density of electronic components in the peripheral region B. Therefore, the electronic components in the peripheral region B can have more space to be implemented and / or have wider spacing between each other. In this way, compared with the first buried gate structure 120, the space for implementing the second buried gate structure 140 is larger. Figure 1 As shown, a width 140W of the second buried gate structure 140 is greater than a width 120W of the first buried gate structure 120. In some embodiments, the sidewalls of the first buried gate structure 120 and the second buried gate structure 140 are not aligned with the Y direction. It should be understood that the width 120W and the width 140W are measured along the X direction at the widest portion of the first buried gate structure 120 and the widest portion of the second buried gate structure 140, respectively.

[0151] Please refer to Figure 2A and Figure 2B . Figure 2A is a schematic diagram of a first buried gate structure 120 according to some embodiments of the present disclosure. Figure 2B is a schematic diagram of a second buried gate structure 140 according to some embodiments of the present disclosure.

[0152] The first buried gate structure 120 has a protruding portion 120P protruding from the active area AA toward the lower surface 100B of the substrate 100 . The second buried gate structure 140 has a protruding portion 140P protruding from the active area AA toward the lower surface 100B of the substrate 100 .

[0153] Substrate 100 further includes a channel region 107 and a channel region 108, respectively, disposed in array region A and peripheral region B. Channel region 107 connects doped region 101 to doped region 102 along the sidewalls of protrusion 120P. Channel region 108 connects doped region 104 to doped region 105 along the sidewalls of protrusion 140P. That is, protrusion 120P is surrounded by channel region 107, and protrusion 140P is surrounded by channel region 108. For clarity, channel region 107 and channel region 108 are shown using bold double-arrow curves.

[0154] The side length of the protrusion 120P is equal to the sum of a left length L1, a right length L2, and a bottom length L3 of the protrusion 120P. Since the protrusion 120P is surrounded by the channel area 107, the side length of the protrusion 120P can be regarded as the channel length of the channel area 107.

[0155] The length of one side of the protruding portion 140P is equal to the sum of a first left length L4, a second left length L5, a first right length L6, a second right length L7, a first bottom length L8, a second bottom length L9, and a third bottom length L10 of the protruding portion 140P. Since the protruding portion 140P is surrounded by the channel region 108, the length of the side of the protruding portion 140P can be regarded as the channel length of the channel region 108.

[0156] In some embodiments, the depth 120D of the first buried gate structure 120 is less than the depth 140D of the second buried gate structure 140. Furthermore, as described above, the width 120W of the first buried gate structure 120 is less than the width 140W of the second buried gate structure 140. Therefore, the protrusion 140P has a larger dimension than the protrusion 120P, and the side length of the protrusion 140P is greater than the side length of the protrusion 120P. As a result, the channel length of the channel region 108 is longer than the channel length of the channel region 107.

[0157] Compared to the protrusion 120P, the protrusion 140P includes a lower portion 140P1 and an upper portion 140P2 located above the lower portion 140P1. The lower portion 140P1 is narrower than the upper portion 140P2 along the X direction. The lower portion 140P1 and the upper portion 140P2 form the protrusion 140P with a stepped sidewall.

[0158] The stepped sidewall includes a first left side, a first right side, a first bottom side, and a second bottom side corresponding to upper portion 140P2; and a second right side, a second left side, and a third bottom side corresponding to lower portion 140P1. The first left side has a first left length L4. The first right side has a first right length L6. The first bottom side has a first bottom length L8. The second bottom side has a second bottom length L9. The second left side has a second left length L5. The second right side has a second right length L7. The third bottom side has a third bottom length L10.

[0159] In some embodiments, the left length L1 is equal to the first left length L4, and the right length L2 is equal to the first right length L6. The bottom length L3 is less than the sum of the first bottom length L8, the second bottom length L9, and the third bottom length L10.

[0160] Because the channel length of channel region 108 is greater than that of channel region 107, channel region 108 has a lower effective resistance than channel region 107. Therefore, channel region 108 can conduct a higher current than channel region 107. Generally speaking, a higher current leads to higher performance of electronic devices. When channel region 108 conducts a higher current, electronic devices in peripheral region B can achieve higher performance.

[0161] Figure 1 、 Figure 2A and Figure 2B The semiconductor structure 10 shown is provided for illustration purposes, however, the present disclosure is not limited thereto. In various embodiments, the buried gate structure may have Figure 3 、 Figure 4 、 Figure 5 and Figure 6 Different structures shown.

[0162] Figure 3 is a schematic diagram of a semiconductor structure 30 according to other embodiments of the present disclosure. Figure 4 is a schematic diagram of a semiconductor structure 40 according to various embodiments of the present disclosure. Figure 5 is a schematic diagram of a semiconductor structure 50 according to an alternative embodiment of the present disclosure. Figure 6 is a schematic diagram of a semiconductor structure 60 according to other embodiments of the present disclosure.

[0163] Semiconductor structure 30, semiconductor structure 40, semiconductor structure 50 and semiconductor structure 60 are similar to semiconductor structure 10. Therefore, Figures 3 to 6 Like components shown are designated with the same part numbers as Figure 1 、 Figure 2A and Figure 2B The same elements shown in FIG. 1 are numbered the same as those shown in FIG. 1 , and descriptions of similar elements are omitted.

[0164] exist Figure 3 In FIG. 3 , compared with the semiconductor structure 10 , the semiconductor structure 30 has a second buried gate structure 340 that is different from the second buried gate structure 140 of the semiconductor structure 10 .

[0165] The second buried gate structure 340 includes a gate dielectric layer 341, a gate electrode 342, and a cap layer 343. The cap layer 343 is disposed above the gate electrode 342. The gate electrode 342 and the cap layer 343 are surrounded by the gate dielectric layer 341. The gate electrode 342 and the cap layer 343 are separated from the substrate 100 by the gate dielectric layer 341.

[0166] The second buried gate structure 340 has a protruding portion 340P. The protruding portion 340P includes a lower portion 340P1 and an upper portion 340P2 located above the lower portion 340P1. Figure 3 As shown, the lower portion 340P1 has a curved sidewall.

[0167] exist Figure 4 In FIG. 4 , compared with the semiconductor structure 10 , the semiconductor structure 40 has a second buried gate structure 440 that is different from the second buried gate structure 140 of the semiconductor structure 10 .

[0168] The second buried gate structure 440 includes a gate dielectric layer 441, a gate electrode 442, and a cap layer 443. The cap layer 443 is disposed above the gate electrode 442. The gate electrode 442 and the cap layer 443 are surrounded by the gate dielectric layer 441. The gate electrode 442 and the cap layer 443 are separated from the substrate 100 by the gate dielectric layer 441.

[0169] The second buried gate structure 440 has a protruding portion 440P. The protruding portion 440P includes a lower portion 440P1 and an upper portion 440P2 located above the lower portion 440P1.

[0170] like Figure 4 As shown, an angle θ1 between a sidewall of the upper portion 440P2 and a sidewall of the lower portion 440P1 is greater than 0, and the lower portion 440P1 has a bottom sidewall substantially parallel to the X direction.

[0171] exist Figure 5 In FIG. 5 , compared with the semiconductor structure 10 , the semiconductor structure 50 has a second buried gate structure 540 that is different from the second buried gate structure 140 of the semiconductor structure 10 .

[0172] The second buried gate structure 540 includes a gate dielectric layer 541, a gate electrode 542, and a cap layer 543. The cap layer 543 is disposed above the gate electrode 542. The gate electrode 542 and the cap layer 543 are surrounded by the gate dielectric layer 541. The gate electrode 542 and the cap layer 543 are separated from the substrate 100 by the gate dielectric layer 541.

[0173] The second buried gate structure 540 has a protruding portion 540P. The protruding portion 540P includes a lower portion 540P1 and an upper portion 540P2 located above the lower portion 540P1.

[0174] like Figure 5 As shown, an angle θ2 between a side wall of the upper portion 540P2 and a side wall of the lower portion 540P1 is greater than 0. In some embodiments, the angle θ2 is greater than the angle θ1, such as Figure 4 As shown. Figure 4 In contrast to the illustrated lower portion 440P1 , the lower portion 540P1 does not have a flat bottom side.

[0175] exist Figure 6 In FIG. 6 , compared with the semiconductor structure 10 , the semiconductor structure 60 has a first buried gate structure 620 and a second buried gate structure 640 that are different from the first buried gate structure 120 and the second buried gate structure 140 of the semiconductor structure 10 .

[0176] The first buried gate structure 620 includes a gate dielectric layer 621, a gate electrode 622, a cap layer 623, and a barrier layer 624. The cap layer 623 is disposed above the gate electrode 622. The gate electrode 622 and the cap layer 623 are surrounded by the gate dielectric layer 621. The gate electrode 622 and the cap layer 623 are separated from the substrate 100 by the gate dielectric layer 621. The barrier layer 624 is disposed between the gate dielectric layer 621 and the gate electrode 622 and is in contact with the cap layer 623. The gate electrode 622 is separated from the gate dielectric layer 621 by the barrier layer 624.

[0177] The second buried gate structure 640 includes a gate dielectric layer 641, a gate electrode 642, a cap layer 643, and a barrier layer 644. The cap layer 643 is disposed above the gate electrode 642. The gate electrode 642 and the cap layer 643 are surrounded by the gate dielectric layer 641. The gate electrode 642 and the cap layer 643 are separated from the substrate 100 by the gate dielectric layer 641. The barrier layer 644 is disposed between the gate dielectric layer 641 and the gate electrode 642 and is in contact with the cap layer 643. The gate electrode 642 is separated from the gate dielectric layer 641 by the barrier layer 644.

[0178] In some embodiments, barrier layers 624 and 644 are configured to prevent materials of gate electrodes 622 and 642 from diffusing into substrate 100 through gate dielectric layers 621 and 641, respectively. In some embodiments, barrier layers 624 and 644 include titanium nitride, tantalum nitride, or other suitable materials.

[0179] Please refer to Figure 7 . Figure 7 FIG1 is a flow chart of a method 70 for fabricating a semiconductor structure 10 according to some embodiments of the present disclosure. The method 70 includes steps S72, S74, S76, S78, and S80. In some embodiments, at least a portion of the method 70 may also be applied to fabricating semiconductor structures 30, 40, 50, and 60.

[0180] For ease of understanding, provide Figures 8 to 18 A schematic diagram showing an intermediate stage of forming a semiconductor structure 10, and combining Figures 8 to 18 The preparation method 70 is described.

[0181] In step S72, if Figure 8 As shown, a substrate 100 is provided. The substrate 100 has an array region A and a peripheral region B. An isolation structure 160 is provided in both the array region A and the peripheral region B of the substrate 100 .

[0182] exist Figure 9 According to some embodiments of the present disclosure, an ion implantation process is performed to form the active area AA in the substrate 100 .

[0183] In step S74, if Figure 10 As shown, a plurality of openings O1 and a plurality of openings O2 are formed in the array region A and the peripheral region B, respectively. The openings O1 are formed for the first buried gate structure 120. The openings O1 and the openings O2 pass through the active area AA toward the lower surface 100B of the substrate 100. The width of the opening O1 is equal to the width 120W of the first buried gate structure 120, and the width of the opening O2 is equal to the width 140W of the second buried gate structure 140.

[0184] In step S76, an opening O3 is formed through the openings O2, such as Figures 11 to 13 shown.

[0185] exist Figure 11, a deposition process is performed to form a mask layer 701. In some embodiments, the deposition process is an atomic layer deposition (ALD) process. The mask layer 701 is formed on the upper surface 100T of the substrate 100 and lines the openings O2. The width of the openings O2 is sufficient to form the mask layer 701 without surrounding the openings O2. However, because the width of the openings O1 is small, the mask layer 701 may surround the openings O1 due to its high aspect ratio. In some embodiments, a thickness 701T1 of the mask layer 701 above the openings O1 is greater than a thickness 701T2 of the mask layer 701 above the lower surface O2B of the openings O2.

[0186] Figure 12 In the embodiment of the present invention, an etching process is performed to remove the mask layer 701 above the lower surface O2B of the openings O2. After the etching process, the lower surface O2B is exposed. In some embodiments, the etching process is a reactive ion etching (RIE) process. Because the thickness 701T2 is less than the thickness 701T1, the openings O1 are still surrounded by the mask layer 701 when the lower surface O2B is exposed.

[0187] exist Figure 13 In the embodiment, another etching process is performed using the remaining mask layer 701 as a mask to form the openings O3. The lower surface O2B is etched toward the lower surface 100B of the substrate 100 to deepen the openings O2. The additional spaces formed by the etching process are the openings O3.

[0188] After the openings O3 are formed, the mask layer 701 is removed.

[0189] In step S78, if Figures 14 to 18 As shown, a plurality of first buried gate structures 120 and a plurality of second buried gate structures 140 are formed.

[0190] exist Figure 14 In the embodiment, a gate dielectric layer 121 is formed on the substrate 100 and lines the openings O1, and a gate dielectric layer 141 is formed on the substrate 100 and lines the openings O2 and O3. In some embodiments, the gate dielectric layer 121 and the gate dielectric layer 141 are formed simultaneously by the same process.

[0191] exist Figure 15 , a gate electrode 122 and a gate electrode 142 are formed. The gate electrode 122 partially fills the openings O1. The gate electrode 142 completely fills the openings O3 and partially fills the openings O2.

[0192] exist Figure 16In the embodiment, after the gate electrode 122 and the gate electrode 142 are formed, the gate dielectric layer 121 and the gate dielectric layer 141 above the upper surface 100T of the substrate 100 are removed.

[0193] Figure 17 In the embodiment, a dielectric layer 703 is formed over the substrate 100, the gate dielectric layer 121, the gate electrode 122, the gate dielectric layer 141, the gate electrode 142, and the isolation structure 160. The dielectric layer 703 fills the remaining spaces of the openings O1 and the openings O2 and contacts the gate electrodes 122 and 142.

[0194] exist Figure 18 In some embodiments, a photolithography process may be performed to define the cap layer 123 and the cap layer 143. Then, an etching process may be performed to remove a portion of the dielectric layer 703 based on the definition result of the photolithography process to form the cap layer 123 and the cap layer 143.

[0195] After forming the capping layer 123 and the capping layer 143 , the first buried gate structure 120 and the second buried gate structure 140 are formed.

[0196] In step S80, Figure 1 As shown, a plurality of metal lines 180 are formed over the substrate 100 , the isolation structure 160 , the cap layer 123 , and the cap layer 143 .

[0197] One embodiment of the present disclosure provides a semiconductor structure comprising a substrate, a first buried gate structure, and a second buried gate structure. The substrate has an array region and a peripheral region. The first buried gate structure extends from a first surface of the substrate into the substrate along a first direction and is disposed in the array region. The second buried gate structure extends from the first surface of the substrate into the substrate along the first direction and is disposed in the peripheral region. A depth of the first buried gate structure is less than a depth of the second buried gate structure along the first direction.

[0198] Another embodiment of the present disclosure provides a method for fabricating a semiconductor structure. The method includes providing a substrate having an array region and a peripheral region; forming a first opening and a second opening in the array region and the peripheral region, respectively; forming a third opening through the second opening; and forming a first buried gate structure and a second buried gate structure. The first buried gate structure is formed in the first opening, and the second buried gate structure is formed in the second opening and the third opening.

[0199] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the concept and scope of the present disclosure as defined in the claims. For example, many of the above processes can be implemented in different ways, and many of the above processes can be replaced by other processes or combinations thereof.

[0200] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this disclosure that existing or future developed processes, machines, manufacture, compositions of matter, means, methods, or steps that function the same as or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with this disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps are intended to be encompassed by the claims of this application.

Claims

1. A semiconductor structure comprising: A substrate having an array region and a peripheral region; a first buried gate structure extending from a first surface of the substrate into the substrate along a first direction and disposed in the array region; as well as a second buried gate structure extending from the first surface of the substrate along the first direction into the substrate and disposed in the peripheral region; A depth of the first buried gate structure is less than a depth of the second buried gate structure along the first direction.

2. The semiconductor structure of claim 1 , further comprising: A first isolation structure and a second isolation structure are disposed in the array region of the substrate; as well as a third isolation structure and a fourth isolation structure, disposed in the peripheral region of the substrate, The first buried gate structure is disposed between the first isolation structure and the second isolation structure, and the second buried gate structure is disposed between the third isolation structure and the fourth isolation structure. 3 . The semiconductor structure of claim 1 , wherein the substrate comprises an active region, wherein the active region is coplanar with the first surface of the substrate, and wherein a depth of the active region is less than a depth of the first buried gate structure.

4. The semiconductor structure of claim 3 , wherein the active region comprises: a first doping region and a second doping region, disposed in the array region; as well as a third doping region and a fourth doping region, disposed in the peripheral region; The first buried gate structure is disposed between the first doping region and the second doping region, and the second buried gate structure is disposed between the third doping region and the fourth doping region.

5. The semiconductor structure of claim 4 , wherein the first buried gate structure has a first protruding portion protruding from the active region toward a second surface of the substrate, and the second buried gate structure has a second protruding portion protruding from the active region toward the second surface of the substrate, The second surface is opposite to the first surface.

6. The semiconductor structure of claim 5, wherein the substrate further comprises a first channel region and a second channel region, wherein the first protruding portion of the first buried gate structure is surrounded by the first channel region, and the second protruding portion of the second buried gate structure is surrounded by the second channel region. The semiconductor structure as claimed in claim 5 , wherein a first side length of the first protruding portion is smaller than a second side length of the second protruding portion.

8. The semiconductor structure of claim 5, wherein the second protruding portion comprises: lower part; as well as an upper portion, located above the lower portion, The lower portion is narrower than the upper portion. 9 . The semiconductor structure as claimed in claim 8 , wherein the second protrusion has a stepped sidewall.

10. The semiconductor structure of claim 8, wherein the lower portion has a curved sidewall. The semiconductor structure according to claim 8 , wherein an angle between a sidewall of the upper portion and a sidewall of the lower portion is greater than 0. 12 . The semiconductor structure of claim 11 , wherein the lower portion has a bottom sidewall parallel to a second direction, wherein the second direction is perpendicular to the first direction.

13. The semiconductor structure of claim 4, further comprising: a first metal line disposed above the substrate and in contact with the first doped region; as well as A second metal line is disposed above the substrate and contacts the third doped region. 14 . The semiconductor structure of claim 1 , wherein a width of the first buried gate structure is smaller than a width of the second buried gate structure along a second direction perpendicular to the first direction.

15. The semiconductor structure of claim 1 , wherein the first buried gate structure comprises a first gate dielectric layer and a first gate electrode, and the second buried gate structure comprises a second gate dielectric layer and a second gate electrode, The first gate electrode is separated from the substrate by the first gate dielectric layer, and the second gate electrode is separated from the substrate by the second gate dielectric layer.

16. The semiconductor structure of claim 15, wherein the first buried gate structure further comprises a first capping layer, and the second buried gate structure further comprises a second capping layer. The first capping layer is disposed above the first gate electrode and is separated from the substrate by the first gate dielectric layer, and the second capping layer is disposed above the second gate electrode and is separated from the substrate by the second gate dielectric layer.

17. The semiconductor structure of claim 15, wherein the first buried gate structure further comprises a first barrier layer, and the second buried gate structure further comprises a second barrier layer. The first barrier layer extends between the first gate dielectric layer and the first gate electrode, and the second barrier layer extends between the second gate dielectric layer and the second gate electrode.

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