Semiconductor device including crystalline oxide semiconductor and method of manufacturing same

Abstract

The invention relates to a semiconductor device including a crystalline oxide semiconductor and a method of manufacturing the same. The semiconductor device may include: a substrate; a crystalline first oxide semiconductor pattern disposed on the substrate; a gate pattern disposed on the first oxide semiconductor pattern; and a crystallized second oxide semiconductor pattern disposed on both sides of the gate pattern on the first oxide semiconductor pattern. A method for manufacturing a semiconductor device may include: forming a crystalline first oxide semiconductor pattern on a substrate; forming a gate pattern disposed on the first oxide semiconductor pattern; forming an amorphous oxide semiconductor material on the first oxide semiconductor pattern on two sides of the gate pattern; and performing a crystallization process to convert a portion of the amorphous oxide semiconductor material in contact with the first oxide semiconductor pattern into a crystallized second oxide semiconductor pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0018665, filed on February 7, 2024, which is hereby incorporated by reference herein in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate generally to semiconductor technology, and more particularly, to semiconductor devices including oxide semiconductors and methods of manufacturing the same. Background Art

[0004] In the prior art, amorphous silicon or polycrystalline silicon is mainly used as the semiconductor layer of semiconductor devices such as transistors. Amorphous silicon has the advantage of being able to ensure uniform device characteristics through relatively inexpensive and simple processes, but has the disadvantage of low carrier mobility. Polycrystalline silicon can be obtained by crystallizing amorphous silicon and can have relatively high carrier mobility. However, when forming polycrystalline silicon, a recrystallization process may be required, and uniform device characteristics may not be ensured.

[0005] Recently, oxide semiconductors have been proposed as semiconductor materials having high carrier mobility which is an advantage of polycrystalline silicon and uniform device characteristics which are an advantage of amorphous silicon. Summary of the Invention

[0006] Various embodiments of the present disclosure are directed to providing a semiconductor device and a method of manufacturing the same, which reduces contact resistance of source / drain regions by increasing the thickness of the source / drain regions and substantially maintaining the thickness of a channel region of an oxide semiconductor layer.

[0007] A semiconductor device according to an embodiment of the present disclosure may include: a substrate; a crystallized first oxide semiconductor pattern disposed on the substrate; a gate pattern disposed on the first oxide semiconductor pattern; and a crystallized second oxide semiconductor pattern disposed on both sides of the gate pattern on the first oxide semiconductor pattern.

[0008] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include: forming a crystalline first oxide semiconductor pattern on a substrate; forming a gate pattern arranged on the first oxide semiconductor pattern; forming an amorphous oxide semiconductor material on the first oxide semiconductor pattern on both sides of the gate pattern; and performing a crystallization process to transform a portion of the amorphous oxide semiconductor material in contact with the first oxide semiconductor pattern into a crystalline second oxide semiconductor pattern.

[0009] According to an embodiment disclosed in the present invention, a crystallized second oxide semiconductor pattern is additionally grown on the crystallized first oxide semiconductor pattern of the source / drain region of the oxide semiconductor layer, so that the thickness of the source / drain region can be increased to reduce the contact resistance of the source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1 to 7 1 is a cross-sectional view for describing a semiconductor device and a method of manufacturing the same according to an embodiment of the present disclosure.

[0011] Figures 8 to 14 is a cross-sectional view for describing a semiconductor device and a method of manufacturing the same according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] Various embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0013] The drawings may not necessarily be drawn to scale, and in some embodiments, the proportions of at least some of the structures shown in the drawings may be enlarged to clearly illustrate the features of the embodiments. When a multilayer structure having two or more layers is disclosed in the drawings or detailed description, since the relative positional relationships or arrangement order of the layers shown in the drawings only reflect specific embodiments, the embodiments of the present disclosure are not limited thereto, and the relative positional relationships or arrangement order of the layers may be changed. The drawings or detailed descriptions of the multilayer structure may not reflect all the layers present in the specific multilayer structure (for example, one or more additional layers may be present between the two layers shown). For example, in the multilayer structure in the drawings or detailed description, when the first layer is located on the second layer or on the substrate, it may not only indicate that the first layer can be formed directly on the second layer or directly on the substrate, but may also indicate that one or more other layers can be present between the first layer and the second layer, or between the first layer and the substrate.

[0014] Figures 1 to 7 1 is a cross-sectional view for describing a semiconductor device and a method of manufacturing the same according to an embodiment of the present disclosure. Figure 7 The semiconductor device of this embodiment is shown, and Figures 1 to 6 Shown for manufacturing Figure 7 The intermediate process of semiconductor devices.

[0015] First, the manufacturing method will be described.

[0016] refer to Figure 1 An isolation layer 105 defining an active region may be formed within the substrate 100. The substrate 100 may include a variety of materials, such as semiconductor materials and insulating materials. For example, the substrate 100 may be a semiconductor substrate including silicon or silicon germanium. The isolation layer 105 may be formed as an oxide film using a high-density plasma (HDP) process.

[0017] In the present embodiment, the height of the top surface of the substrate 100 may be lower than the height of the top surface of the isolation layer 105. This is to provide a space in which the crystallized first oxide semiconductor pattern 110A to be described below will be formed. The isolation layer 105 may be formed by forming a hard mask pattern (not shown) exposing the isolation region on the substrate 100, forming a trench by etching the isolation region of the substrate 100 using the hard mask pattern as an etch barrier, filling the trench with an insulating material, and then removing the hard mask pattern. The top surface of the insulating material filled in the trench may be at the same height as the top surface of the hard mask pattern. Therefore, after removing the hard mask pattern, the height of the top surface of the substrate 100 may be lower than the height of the top surface of the isolation layer 105.

[0018] Subsequently, a crystallized first oxide semiconductor pattern 110A may be formed on the substrate 100. The first oxide semiconductor pattern 110A may be formed by forming an oxide semiconductor material on the substrate 100 and on the isolation layer 105 by a method such as deposition; and then removing the oxide semiconductor material to expose the top surface of the isolation layer 105. In the present embodiment, the top surface of the first oxide semiconductor pattern 110A may be substantially the same height as the top surface of the isolation layer 105. However, the embodiments of the present disclosure are not limited thereto, and in variations of the described embodiments, or in some other embodiments, the top surface of the first oxide semiconductor pattern 110A may be lower than the top surface of the isolation layer 105.

[0019] The first oxide semiconductor pattern 110A may be a crystalline metal oxide. The first oxide semiconductor pattern 110A may include at least one metal oxide selected from Group 12, Group 13, and Group 14 metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (Cd), germanium (Ge), and hafnium (Hf). For example, the first oxide semiconductor pattern 110A may include In-Sn-Ga-Zn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, etc. Since the first oxide semiconductor pattern 110A is a crystallized metal oxide, a portion of the amorphous oxide semiconductor material 140 may be transformed into a crystallized second oxide semiconductor pattern 110B during subsequent annealing of the amorphous oxide semiconductor material 140 .

[0020] Subsequently, a gate pattern 120 may be formed on the first oxide semiconductor pattern 110A. The gate pattern 120 may include a gate insulating layer 120A, a gate conductive layer 120B, and a gate hard mask layer 120C. The gate pattern 120 may be formed by sequentially depositing a gate insulating material, a gate conductive material, and a gate hard mask material on the first oxide semiconductor pattern 110A and the isolation layer 105, and then selectively etching these materials. In the cross-sectional direction, the width of the gate pattern 120 may be smaller than the width of the first oxide semiconductor pattern 110A while overlapping with the first oxide semiconductor pattern 110A. The gate insulating layer 120A may include a variety of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide, or a high dielectric material having a higher dielectric constant than silicon oxide, such as zirconium oxide, hafnium oxide, lanthanum oxide, and tantalum oxide, or titanium oxide. The gate conductive layer 120B may include any suitable conductive material, such as a metal, an alloy, or a metal compound. The gate hard mask layer 120C may include amorphous carbon, titanium nitride (TiN), tantalum (Ta), titanium (Ti), tungsten (W), silicon oxynitride (SiON), or tetraethoxysilicate (TEOS).

[0021] Subsequently, spacers 130 may be formed on both sidewalls of the gate pattern 120. For example, Figure 2 As shown, the spacer 130 may be formed to cover and contact both sidewalls of the gate pattern 120. The spacer 130 may include, for example, a nitride layer.

[0022] Reference Figure 2 , can be deposited by methods such as Figure 1 The amorphous oxide semiconductor material 140 is formed on the gate pattern 120 and the first oxide semiconductor pattern 110A. The amorphous oxide semiconductor material 140 can be conformally deposited to achieve good step coverage. Figure 1 For example, the thickness of the substantially conformal layer may vary by about 10%, 5%, 2%, 1%, or 0.5% or less.

[0023] The amorphous oxide semiconductor material 140 may include the same constituent elements as those of the first oxide semiconductor pattern 110A, or may include different constituent elements. The amorphous oxide semiconductor material 140 may include at least one metal oxide selected from Group 12, Group 13, and Group 14 metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (Cd), germanium (Ge), and hafnium (Hf). For example, the amorphous oxide semiconductor material 140 may include In-Sn-Ga-Zn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, etc.

[0024] Reference Figure 3 By performing a crystallization process, a portion of the amorphous oxide semiconductor material 140 in contact with the first oxide semiconductor pattern 110A can be transformed into a crystallized second oxide semiconductor pattern 110B. A portion of the amorphous oxide semiconductor material 140 can be transformed into the second oxide semiconductor pattern 110B on the first oxide semiconductor pattern 110A, and the remaining portion can remain unchanged. The crystallization process may include annealing, and similar to the epitaxial growth process during annealing, a portion of the amorphous oxide semiconductor material 140 can be transformed into the crystallized second oxide semiconductor pattern 110B having the same or similar crystal structure as the crystallized first oxide semiconductor pattern 110A.

[0025] The annealing process may be performed at a sufficiently high temperature to crystallize the amorphous oxide semiconductor material 140. The annealing process may be performed at a temperature of 300°C to 500°C, which is a relatively low temperature compared to other known annealing processes in semiconductor manufacturing technology. When a portion of the amorphous oxide semiconductor material 140 is crystallized, the wet etching rate may be significantly reduced due to the increase in density, so that wet etching selectivity between the amorphous oxide semiconductor material 140 and the crystallized second oxide semiconductor pattern 110B may be obtained. When the first oxide semiconductor pattern 110A and the second oxide semiconductor pattern 110B include the same material (i.e., the same constituent element), there may be no interface between the first oxide semiconductor pattern 110A and the second oxide semiconductor pattern 110B. Alternatively, the first oxide semiconductor pattern 110A and the second oxide semiconductor pattern 110B may be made of different materials having at least one different constituent element.

[0026] The crystallized oxide semiconductor layer 110, including the first oxide semiconductor pattern 110A and the second oxide semiconductor pattern 110B, can be used to provide a channel region 121 and source / drain regions 122 of the transistor. The channel region 121 is the portion overlapping the gate pattern 120, and the source / drain regions 122 serve as both sides of the channel region. The channel region 121 of the transistor may include the first oxide semiconductor pattern 110A. The source / drain regions 122 of the transistor may include a stacked structure of the first oxide semiconductor pattern 110A and the second oxide semiconductor pattern 110B. The second oxide semiconductor pattern 110B may have a top surface that is higher than the bottom surface of the gate pattern 120. Therefore, the thickness of the source / drain region 122 can be relatively increased compared to the channel region 121, resulting in a reduced contact resistance of the source / drain region 122. In addition, the second oxide semiconductor pattern 110B may be separated from the gate pattern 120 by a spacer 130.

[0027] Reference Figure 4 , the uncrystallized amorphous oxide semiconductor material 140 can be removed. The removal of the amorphous oxide semiconductor material 140 can be performed by wet etching. As described above, since the wet etching rate of the second oxide semiconductor pattern 110B is greatly reduced compared to the amorphous oxide semiconductor material 140, the amorphous oxide semiconductor material 140 can be easily and selectively removed by the wet etching process.

[0028] Reference Figure 5 , an interlayer dielectric layer 150 may be formed to cover Figure 4 The interlayer dielectric layer 150 may include any suitable insulating material, such as silicon oxide, silicon nitride, and silicon oxynitride, and may be formed to sufficiently cover the gate pattern 120 .

[0029] refer to Figure 6 , the interlayer dielectric layer 150 can be selectively etched to form two contact holes 160A, each contact hole being located on opposite sides of the gate pattern 120. The contact hole 160A can pass through the interlayer dielectric layer 150 and expose the two second oxide semiconductor patterns 110B on both sides of the gate pattern 120. Subsequently, a barrier layer 160B can be conformally formed on the bottom (or bottom surface or bottom wall) and inner sidewalls of the contact hole 160A. The barrier layer 160B can be conformally formed to cover the entire bottom wall and inner sidewall of the contact hole 160A. The barrier layer 160B may include any suitable conductive material, such as titanium nitride and tantalum nitride. In some embodiments, the barrier layer 160B may be omitted.

[0030] Subsequently, a contact plug 160C may be filled inside the contact hole 160A formed with the barrier layer 160B. The contact plug 160C may include any suitable conductive material, such as a metal, an alloy, or a metal compound. The bottom surfaces of the two contact plugs 160C may be electrically connected to the second oxide semiconductor pattern 110B by directly contacting the second oxide semiconductor pattern 110B. One of the two contact plugs 160C may serve as a source electrode, while the other may serve as a drain electrode. The area of the bottom surfaces of the two contact plugs 160C may be equal to or smaller than the area of the second oxide semiconductor pattern 110B.

[0031] Reference Figure 7 , on the interlayer dielectric layer 150 , a memory element 170 electrically connected to one of the two contact plugs 160C may be formed, and a conductive line 180 electrically connected to the other of the two contact plugs 160C may be formed.

[0032] The memory element 170 is a portion for storing data and may include, for example, a capacitor including a lower electrode 170A, an upper electrode 170C, and a dielectric 170B between the lower electrode 170A and the upper electrode 170C. However, the embodiments of the present disclosure are not limited thereto, and the memory element 170 may include a variable resistance element for storing different data by switching between different resistance states. The variable resistance element may have a single-layer structure or a multi-layer structure, including a variety of materials used in, for example, resistive RAM (RRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FRAM), etc., for example, metal oxides such as transition metal oxides and perovskite-based materials, phase change materials such as chalcogenide-based materials, ferroelectric materials, ferromagnetic materials, etc.

[0033] The conductive line 180 may include any suitable conductive material, such as metals, alloys, and metal compounds.

[0034] This embodiment describes a case where the memory element 170 and the conductive line 180 are in direct contact with the two contact plugs 160C; however, the embodiments of the present disclosure are not limited thereto. In another embodiment, another conductive pattern may be interposed between the memory element 170 and the contact plug 160C, and the memory element 170 and the contact plug 160C may be electrically connected via this conductive pattern. Alternatively, in another embodiment, another conductive pattern may be interposed between the conductive line 180 and the contact plug 160C, and the conductive line 180 and the contact plug 160 may be electrically connected via this conductive pattern. The conductive pattern may refer to a conductive pattern having various shapes, such as a through-hole.

[0035] Through the above process, it is possible to manufacture Figure 7 The semiconductor device shown.

[0036] Reference again Figure 7 According to an embodiment of the present disclosure, a semiconductor device may include a substrate 100 having an isolation layer 105 formed thereon, a crystallized first oxide semiconductor pattern 110A disposed on the substrate 100, a gate pattern 120 disposed on the first oxide semiconductor pattern 110A, spacers 130 disposed on both sidewalls of the gate pattern 120, a second oxide semiconductor pattern 110B disposed on the first oxide semiconductor pattern 110A located on both sides of the gate pattern 120, and an interlayer dielectric layer 150 covering the gate pattern 120. The semiconductor device may further include two contact plugs 160C connected to the second oxide semiconductor pattern 110B by passing through the interlayer dielectric layer 150. Each contact plug 160C may be formed inside a contact hole 160A. A barrier layer 160B may be conformally formed to cover the bottom and sidewalls of the contact hole 160A and to separate the contact plugs 160C from the interlayer dielectric layer 150 and the second oxide semiconductor pattern 110B. The semiconductor device may further include a memory element 170 and a conductive line 180 disposed on the interlayer dielectric layer 150. The memory element 170 may be connected to a first of the two contact plugs 160C, and the conductive line 180 may be connected to a second of the two contact plugs 160C.

[0037] The isolation layer 105 may be disposed on both sidewalls of the substrate 100, and the first oxide semiconductor pattern 110A may be disposed on the substrate 100. The gate pattern 120 may be disposed on the first oxide semiconductor pattern 110A, and the second oxide semiconductor pattern 110B may be disposed on both sides of the gate pattern 120. The surface height of the first oxide semiconductor pattern 110A may be the same as the top surface of the isolation layer 105.

[0038] When the first oxide semiconductor pattern 110A and the second oxide semiconductor pattern 110B include the same material (i.e., the same constituent element), no interface may exist between the first oxide semiconductor pattern 110A and the second oxide semiconductor pattern 110B. The first oxide semiconductor pattern 110A and the second oxide semiconductor pattern 110B may be made of different materials having at least one different constituent element. The first oxide semiconductor pattern 110A and the second oxide semiconductor pattern 110B may be stacked to form a crystallized oxide semiconductor layer 110.

[0039] The two second oxide semiconductor patterns 110B, the first oxide semiconductor pattern 110A, and the gate pattern 120 between the two second oxide semiconductor patterns 110 can form a transistor. The crystallized oxide semiconductor layer 110 including the first oxide semiconductor pattern 110A and the second oxide semiconductor pattern 110B can be used to provide a channel region 121 and source / drain regions 122 of the transistor, where the channel region 121 is a portion overlapping the gate pattern 120 and the source / drain regions 122 serve as both sides of the channel region 121.

[0040] According to the above-described semiconductor device and method of manufacturing the same, the following advantages can be obtained.

[0041] The thickness of the source / drain region 122 may be increased by additionally growing the crystallized second oxide semiconductor pattern 110B on the crystallized first oxide semiconductor pattern 110A of the source / drain region 122, thereby reducing the contact resistance of the source / drain region 122. As a result, the contact resistance between the source / drain electrode and the oxide semiconductor layer 110 may be reduced.

[0042] The above embodiment has described a structure in which the crystallized second oxide semiconductor pattern 110B is disposed below the contact hole 160A; however, the embodiments of the present disclosure are not limited thereto. In another embodiment, a structure in which the crystallized second oxide semiconductor pattern is disposed inside the contact hole may also be implemented. Figures 8 to 14 Describe it.

[0043] Figures 8 to 14 is a cross-sectional view for describing a semiconductor device and a method of manufacturing the same according to another embodiment of the present disclosure. Figure 14 The semiconductor device of this embodiment is shown, and Figures 8 to 13 Shown for manufacturing Figure 14 The following description focuses on the differences from the above-mentioned embodiment.

[0044] refer to Figure 8 , an isolation layer 205 defining an active region may be formed within the substrate 200 .

[0045] Subsequently, a crystallized first oxide semiconductor pattern 210A may be formed on the substrate 200. The top surface of the substrate 200 may be lower than the top surface of the isolation layer 205. The top surface of the first oxide semiconductor pattern 210A may be substantially the same as the top surface of the isolation layer 205. However, the embodiments of the present disclosure are not limited thereto, and the top surface of the first oxide semiconductor pattern 210A may be lower than the top surface of the isolation layer 205.

[0046] Subsequently, a gate pattern 220 including a gate insulating layer 220A, a gate conductive layer 220B, and a gate hard mask layer 220C may be formed on the first oxide semiconductor pattern 210A. Subsequently, spacers 230 may be formed on both sidewalls of the gate pattern 220 to cover and contact both sidewalls of the gate pattern 220.

[0047] Figure 8 The structure can be compared with the above Figure 1 That is, the substrate 200, the isolation layer 205, the first oxide semiconductor pattern 210A, the gate insulating layer 220A, the gate conductive layer 220B, the hard mask layer 220C, the gate pattern 220 and the spacer 230 may respectively correspond to the substrate 100, the isolation layer 105, the first oxide semiconductor pattern 110A, the gate insulating layer 120A, the gate conductive layer 120B, the hard mask layer 120C, the gate pattern 120 and the spacer 130 in the above embodiment. Therefore, the structure can be formed by the above-mentioned method. Figure 1 The structure is formed by basically the same process.

[0048] Reference Figure 9 , an interlayer dielectric layer 250 may be formed to cover Figure 8 The interlayer dielectric layer 250 may be formed to sufficiently cover the gate pattern 220 .

[0049] refer to Figure 10 The interlayer dielectric layer 250 may be selectively etched to form two contact holes 260A, which respectively expose the first oxide semiconductor pattern 210A on both sides of the gate pattern 220 .

[0050] Reference Figure 11 , you can Figure 10 The amorphous oxide semiconductor material 240 is deposited on the result of the process. For example, the amorphous oxide semiconductor material 240 can be deposited using physical vapor deposition (PVD). As another example, the amorphous oxide semiconductor material 240 can be deposited using atomic layer deposition (ALD). The deposition method of the amorphous oxide semiconductor material 240 may not be limited to the PVD and ALD methods, and various changes may be made. The amorphous oxide semiconductor material 240 may be conformally formed to cover the amorphous oxide semiconductor material 240 with a thin layer. Figure 10 The contact hole 260A may not be completely filled as a result of the process.

[0051] When the amorphous oxide semiconductor material 240 is deposited by a PVD method with low step coverage, the amorphous oxide semiconductor material 240 may be formed on the bottom surface of each of the two contact holes 260A. In this case, the amorphous oxide semiconductor material 240 formed on the bottom surface of the contact hole 260A may be transformed into crystals in a subsequent crystallization process, and the remaining amorphous oxide semiconductor material 240 deposited on the interlayer dielectric layer 250 is removed.

[0052] When the amorphous oxide semiconductor material 240 is deposited using an ALD method with high step coverage, the amorphous oxide semiconductor material 240 may be formed on the sidewalls and bottom surface of each of the two contact holes 260A. In this case, the amorphous oxide semiconductor material 240 formed on the bottom surface of the contact hole 260A is transformed into crystals during a subsequent crystallization process, while the amorphous oxide semiconductor material 240 deposited on the sidewalls of the contact hole 260A may remain. Even if a portion of the amorphous oxide semiconductor material 240 remains on the sidewalls of the contact hole 260A, since there is sufficient space for forming the contact plug 260C, the barrier layer 260B and the contact plug 260 may be formed in a subsequent process without removing the amorphous oxide semiconductor material 240 remaining on the sidewalls of the contact hole 260A. However, to ensure more space for forming the contact plug 260C, the amorphous oxide semiconductor material 240 remaining on the sidewalls of the contact hole 260A may be additionally removed by, for example, wet etching.

[0053] refer to Figure 12 , by performing a crystallization process, the amorphous oxide semiconductor material 240 in contact with the first oxide semiconductor pattern 210A at the bottom of the contact hole 260A can be transformed into a crystallized second oxide semiconductor pattern 210B. In this embodiment, the amorphous oxide semiconductor material 240 below the contact hole 260A can be transformed into the second oxide semiconductor pattern 210B, and its remaining portion can be retained. Therefore, the second oxide semiconductor pattern 210B can be filled in the lower portion of the contact hole 260A. When the first oxide semiconductor pattern 210A and the second oxide semiconductor pattern 210B include the same material, that is, the same constituent elements, there may be no interface between the first oxide semiconductor pattern 210A and the second oxide semiconductor pattern 210B. Alternatively, the first oxide semiconductor pattern 210A and the second oxide semiconductor pattern 210B can be made of different materials having at least one different constituent element. The top surface of the second oxide semiconductor pattern 210B can be higher than the bottom surface of the gate pattern 220.

[0054] The crystallized oxide semiconductor layer 210 including the first oxide semiconductor pattern 210A and the second oxide semiconductor pattern 210B can be used to provide a channel region 221 and a source / drain region 222 of the transistor, where the channel region 221 is a portion overlapping with the gate pattern 220, and the source / drain region 222 serves as both sides of the channel region 211. Therefore, the thickness of the source / drain region 222 can be relatively increased compared to the channel region 221, and as a result, the contact resistance of the source / drain region 222 can be reduced.

[0055] Reference Figure 13 , the amorphous oxide semiconductor material 240 that has not been crystallized but remains can be removed. For example, the amorphous oxide semiconductor material 240 can be removed using wet etching.

[0056] Subsequently, a barrier layer 260B may be conformally formed on the bottom and inner sidewalls of the contact hole 260A. A contact plug 260C may be formed inside the contact hole 260A formed with the barrier layer 260B and on the second oxide semiconductor pattern 210B to fill the remaining portion of the contact hole 260B.

[0057] Reference Figure 14 A memory element 270 electrically connected to a first contact plug of the two contact plugs 260C may be formed on the interlayer dielectric layer 250 . A conductive line 280 electrically connected to a second contact plug of the two contact plugs 260C may also be formed on the interlayer dielectric layer 250 .

[0058] Through the above process, it is possible to manufacture Figure 14 The semiconductor device shown.

[0059] Reference again Figure 14 A semiconductor device according to another embodiment of the present disclosure may include a substrate 200 having an isolation layer 205 formed thereon, a crystallized first oxide semiconductor pattern 210A disposed on the substrate 200, a gate pattern 220 disposed on the first oxide semiconductor pattern 210A, spacers 230 disposed on both sidewalls of the gate pattern 220, an interlayer dielectric layer 250 covering the gate pattern 220, a contact hole 260A penetrating through the interlayer dielectric layer 250 to expose the first oxide semiconductor pattern 210A, a second oxide semiconductor pattern 210B filling a lower portion of the contact hole 260A, and two contact plugs 260C filling a remaining portion of the contact hole 260A on the second oxide semiconductor pattern 210B. The semiconductor device may further include a memory element 270 and a conductive line 280 disposed on the interlayer dielectric layer 250 and connected to a corresponding one of the two contact plugs 260C.

[0060] According to the present embodiment, a structure in which the second oxide semiconductor pattern 210B is disposed inside the contact hole 260A can be realized. Even in the present embodiment, all the advantages described in the above embodiments can be obtained.

[0061] Although the technical concept of the present disclosure has been specifically described based on the above-mentioned embodiments, it should be noted that the above-mentioned embodiments are for description, not for limitation. In addition, it will be understood by those skilled in the art that various embodiments can be made within the scope of the technical concept of the present disclosure. In addition, these embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device comprising: a first oxide semiconductor pattern disposed on a substrate; a gate pattern disposed on the first oxide semiconductor pattern; as well as A second oxide semiconductor pattern is disposed on the first oxide semiconductor pattern at both sides of the gate pattern.

2. The semiconductor device according to claim 1, further comprising: an interlayer dielectric layer covering the gate pattern; as well as Two contact holes pass through the interlayer dielectric layer and expose the second oxide semiconductor pattern on both sides of the gate pattern.

3. The semiconductor device according to claim 2, further comprising: Two contact plugs are respectively filled in the two contact holes. The first oxide semiconductor pattern and the second oxide semiconductor pattern are crystalline.

4. The semiconductor device according to claim 3, further comprising: a storage element electrically connected to one of the two contact plugs; as well as a conductive line electrically connected to the other of the two contact plugs, The storage element and the conductive line are arranged on the interlayer dielectric layer.

5. The semiconductor device according to claim 1 , further comprising: an interlayer dielectric layer covering the gate pattern; as well as two contact holes exposing the first oxide semiconductor pattern on both sides of the gate pattern, The second oxide semiconductor pattern is formed inside a lower portion of each of the two contact holes.

6. The semiconductor device according to claim 1, further comprising: a spacer, which is disposed on both sidewalls of the gate pattern and covers both sidewalls of the gate pattern, The second oxide semiconductor pattern is separated from the gate pattern by the spacer.

7. The semiconductor device according to claim 1, wherein The first oxide semiconductor pattern and the second oxide semiconductor pattern include the same constituent elements, and no interface exists between the first oxide semiconductor pattern and the second oxide semiconductor pattern.

8. The semiconductor device according to claim 1, wherein The first oxide semiconductor pattern and the second oxide semiconductor pattern include different constituent elements.

9. The semiconductor device according to claim 1, wherein The substrate includes an isolation layer, wherein the height of the top surface of the substrate is lower than the height of the top surface of the isolation layer, and A height of a top surface of the first oxide semiconductor pattern is equal to or less than a height of a top surface of the isolation layer.

10. The semiconductor device according to claim 1, wherein A top surface of the second oxide semiconductor pattern is higher than a bottom surface of the gate pattern.

11. A method for manufacturing a semiconductor device, the method comprising: forming a crystallized first oxide semiconductor pattern on a substrate; forming a gate pattern, wherein the gate pattern is disposed on the first oxide semiconductor pattern; forming an amorphous oxide semiconductor material on the first oxide semiconductor pattern at both sides of the gate pattern; as well as A crystallization process is performed to transform a portion of the amorphous oxide semiconductor material in contact with the first oxide semiconductor pattern into a crystallized second oxide semiconductor pattern.

12. The method according to claim 11, wherein The amorphous oxide semiconductor material is formed on the gate pattern and the first oxide semiconductor pattern.

13. The method according to claim 12, further comprising: After the crystallization process: forming an interlayer dielectric layer covering the gate pattern; as well as forming a contact hole passing through the interlayer dielectric layer and exposing the second oxide semiconductor pattern; as well as A contact plug is formed to fill the contact hole.

14. The method according to claim 11, further comprising: After forming the gate pattern and before forming the amorphous oxide semiconductor material, forming an interlayer dielectric layer covering the gate pattern; as well as etching the interlayer dielectric layer to form two contact holes exposing the first oxide semiconductor pattern on both sides of the gate pattern, The amorphous oxide semiconductor material is formed on a bottom surface of each of the two contact holes.

15. The method according to claim 14, wherein The second oxide semiconductor pattern is filled in a lower portion of the contact hole.

16. The method according to claim 15, further comprising: A contact plug is formed to fill a remaining portion of the contact hole on the second oxide semiconductor pattern.

17. The method according to claim 11, wherein The first oxide semiconductor pattern and the second oxide semiconductor pattern include the same constituent elements, and no interface exists between the first oxide semiconductor pattern and the second oxide semiconductor pattern.

18. The method according to claim 11, wherein The first oxide semiconductor pattern and the second oxide semiconductor pattern include different constituent elements.

19. The method according to claim 11, wherein The crystallization process includes annealing the amorphous oxide semiconductor material at a temperature of 300° C. to 500° C.

20. The method of claim 11, further comprising: The uncrystallized amorphous oxide semiconductor material is removed.

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