Preparation method of semiconductor element

Abstract

The invention provides a preparation method of a semiconductor element. The cell contact structure includes: a bottom contact layer on a substrate and surrounded by a plurality of bit line structures and a plurality of spacer layers; a liner layer between the bottom contact layer and the substrate, between the bottom contact layer and the plurality of bit line structures, and between the bottom contact layer and the plurality of spacer layers; and a top contact layer between the bottom contact layer and the lining layer. A top surface of the bottom contact layer and a top surface of the liner layer are substantially coplanar. The liner layer includes doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. The bottom contact layer includes tungsten, titanium, or titanium nitride.

Description

[0001] This application is a divisional application of U.S. patent application No. 202410588618.8, filed May 13, 2024, and entitled “Contact structure and semiconductor element thereof.” U.S. patent application No. 202410588618.8 claims priority to and the benefit of U.S. patent application No. 18 / 433,904, filed February 6, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a unit contact structure, a semiconductor element and a method for manufacturing the same, and more particularly to a unit contact structure including a liner, a semiconductor element having the unit contact structure and a method for manufacturing the same. Background Art

[0003] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor components continue to shrink in size to meet the ever-increasing demand for computing power. However, various problems arise during the miniaturization process, and these problems are increasing. Consequently, challenges remain in improving quality, yield, performance, and reliability, while reducing complexity.

[0004] The above description of “prior art” only provides background technology, does not admit that the above description of “prior art” discloses the subject matter of the present disclosure, does not form the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of the present invention. Summary of the Invention

[0005] The present disclosure aims to provide a method for manufacturing a semiconductor device to solve at least one of the above problems.

[0006] One aspect of the present disclosure provides a cell contact structure comprising: a bottom contact layer disposed on a substrate and surrounded by a plurality of bit line structures and a plurality of spacer layers; a liner disposed between the bottom contact layer and the substrate, between the bottom contact layer and the plurality of bit line structures, and between the bottom contact layer and the plurality of spacer layers; and a top contact layer disposed between the bottom contact layer and the liner layer. A top surface of the bottom contact layer and a top surface of the liner layer are substantially coplanar. The liner layer comprises doped polysilicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. The bottom contact layer comprises tungsten, titanium, or titanium nitride.

[0007] Another aspect of the present disclosure provides a semiconductor device comprising: a substrate; two bit line structures formed on the substrate, extending along a first direction and separated from each other; two spacer layers located on the substrate, extending along a second direction perpendicular to the first direction and separated from each other along the first direction, and simultaneously contacting the two bit line structures; and a cell contact structure. The cell contact structure comprises: a bottom contact layer located on the substrate and surrounded by the two bit line structures and the two spacer layers; a liner located between the substrate and the bottom contact layer, between the two bit line structures and the bottom contact layer, and between the two spacer layers and the bottom contact layer; and a top contact layer located on the liner and the bottom contact layer. A top surface of the liner and a top surface of the bottom contact layer are substantially coplanar. The liner comprises doped polysilicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. The bottom contact layer comprises tungsten, titanium, or titanium nitride.

[0008] Another aspect of the present disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming two bit line structures on the substrate, extending along a first direction and separated from each other; forming a plurality of spacer structures on side surfaces of the two bit line structures; forming two spacer layers on the substrate, extending along a second direction perpendicular to the first direction and separated from each other, thereby creating a contact opening combined with the plurality of spacer structures; conformally forming a liner in and within the contact opening; forming a bottom contact layer on the liner and within the contact opening; and forming a top contact layer on the liner, on the bottom contact layer, and within the contact opening. The liner comprises doped polysilicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. The bottom contact layer comprises tungsten, titanium, or titanium nitride. The liner, the bottom contact layer, and the top contact layer together constitute a cell contact structure.

[0009] Due to the design of the semiconductor device disclosed herein, junction leakage of the cell contact structure can be reduced by employing a liner layer comprising doped polysilicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. Furthermore, the sheet resistance of the cell contact structure can be reduced by employing a bottom contact layer and a top contact layer comprising titanium nitride, tungsten, or titanium. Consequently, the performance of the semiconductor device can be improved.

[0010] The above has been a fairly broad overview of the technical features and advantages of the present disclosure so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that form the subject of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purposes as the present disclosure. It should also be understood by those skilled in the art to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] A more complete understanding of the present disclosure may be obtained by referring to the detailed description and claims when considered in conjunction with the accompanying drawings, in which like reference characters represent like elements throughout the drawings, and:

[0012] Figure 1 According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device is shown in the form of a flow chart.

[0013] Figure 2 A schematic top view of a middle semiconductor element is shown according to one embodiment of the present disclosure.

[0014] Figure 3 To follow Figure 2 Schematic diagram of the cross section drawn by line AA' and line BB'.

[0015] Figure 4 A schematic top view of a middle semiconductor element is shown according to one embodiment of the present disclosure.

[0016] Figure 5 To follow Figure 4 Schematic cross-sectional view drawn by line AA' and line BB'.

[0017] Figure 6 A schematic top view of a middle semiconductor element is shown according to one embodiment of the present disclosure.

[0018] Figure 7 To follow Figure 6 Schematic diagram of the cross section drawn by line AA' and line BB'.

[0019] Figure 8 A schematic top view of a middle semiconductor element is shown according to one embodiment of the present disclosure.

[0020] Figure 9 To follow Figure 8 Schematic diagram of the cross section drawn by line AA' and line BB'.

[0021] Figure 10 A schematic top view of a middle semiconductor element is shown according to one embodiment of the present disclosure.

[0022] Figure 11 To follow Figure 10 Schematic diagram of the cross section drawn by line AA' and line BB'.

[0023] Figure 12 A schematic top view of a middle semiconductor element is shown according to one embodiment of the present disclosure.

[0024] Figure 13 To follow Figure 12 Schematic diagram of the cross section drawn by line AA' and line BB'.

[0025] Figure 14 A schematic top view of a middle semiconductor element is shown according to one embodiment of the present disclosure.

[0026] Figure 15 and Figure 16 To follow Figure 14 Schematic cross-sectional view drawn along line AA′ and line BB′ in FIG. 1 , which shows a partial process of manufacturing a semiconductor device according to some embodiments.

[0027] Figure 17 A schematic top view of a middle semiconductor element is shown according to one embodiment of the present disclosure.

[0028] Figure 18 To follow Figure 17 Schematic diagram of the cross section drawn by line AA' and line BB'.

[0029] Figure 19 A schematic top view of a middle semiconductor element is shown according to one embodiment of the present disclosure.

[0030] Figures 20 to 23 To follow Figure 19 Schematic cross-sectional view drawn along line AA′ and line BB′ in FIG. 1 , which shows a partial process of manufacturing a semiconductor device according to some embodiments.

[0031] Figure 24 A schematic top view of a middle semiconductor element is shown according to one embodiment of the present disclosure.

[0032] Figure 25 and Figure 26 To follow Figure 24 Schematic cross-sectional view drawn along line AA′ and line BB′ in FIG. 1 , which shows a partial process of manufacturing a semiconductor device according to some embodiments.

[0033] Figure 27 A schematic top view of a middle semiconductor element is shown according to one embodiment of the present disclosure.

[0034] Figure 28 and Figure 29 To follow Figure 27 Schematic cross-sectional view drawn along line AA′ and line BB′ in FIG. 1 , which shows a partial process of manufacturing a semiconductor device according to some embodiments.

[0035] Figures 30 to 32 Schematic cross-sectional views of semiconductor devices are shown according to some embodiments of the present disclosure.

[0036] The reference numerals are as follows:

[0037] 1A: Semiconductor components

[0038] 1B: Semiconductor components

[0039] 1C: Semiconductor components

[0040] 1D: semiconductor components

[0041] 10: Method

[0042] 101:Substrate

[0043] 103: Isolation layer

[0044] 105: Impurity area

[0045] 105-1: Source region

[0046] 105-3: Drain region

[0047] 107: bottom dielectric layer

[0048] 109: Top insulation layer

[0049] 200: Character line structure

[0050] 201: word line dielectric layer

[0051] 203: Character line barrier layer

[0052] 205: word line conductive layer

[0053] 207: character line covering layer

[0054] 300: Bit line structure

[0055] 300S: Side

[0056] 301: Bit line top conductive layer

[0057] 303: Bit line intermediate conductive layer

[0058] 305: Bit line bottom conductive layer

[0059] 307: Bit line cover layer

[0060] 307TS: Top surface

[0061] 309: Bit line contact

[0062] 400: spacer structure

[0063] 401: Intra-bitline spacer

[0064] 401TS: Top surface

[0065] 403: Bit line spacer

[0066] 403TS: Top surface

[0067] 405: bit line spacer

[0068] 405TS: Top surface

[0069] 407: Air Gap

[0070] 500: unit contact structure

[0071] 501: Lining

[0072] 501TS: Top surface

[0073] 503: bottom contact layer

[0074] 503TS: Top surface

[0075] 505: Top contact layer

[0076] 505TS: Top surface

[0077] 601:Separation layer

[0078] 601TS: Top surface

[0079] 701: first mask layer

[0080] 801: Sacrificial layer

[0081] 803:Separator material

[0082] 805: Gasket material

[0083] 807: first conductive material

[0084] 809: second conductive material

[0085] AA: Active Area

[0086] A-A': line

[0087] B-B': line

[0088] OP1: Partition opening

[0089] OP2: contact opening

[0090] P1: Linear pattern

[0091] S11: Step

[0092] S13: Step

[0093] S15: Step

[0094] S17: Step

[0095] TR: Character line groove

[0096] W1: width

[0097] W2: width

[0098] X: direction

[0099] Y: direction

[0100] Z: direction DETAILED DESCRIPTION

[0101] The following disclosure provides many different embodiments or examples to implement different components of the embodiments of the present disclosure. The following describes specific examples of components and their arrangements to simplify the embodiments of the present disclosure. Of course, these are only examples and should not be used to limit the scope of the embodiments of the present disclosure. For example, when the description refers to a first component being formed "on" or "up" a second component, it may include an embodiment in which the first component is in direct contact with the second component, and it may also include an embodiment in which there are other components formed between the two without direct contact. In addition, the present disclosure may repeat reference symbols and / or marks in different embodiments. These repetitions are for the purpose of simplicity and clarity and are not used to define the relationship between the different embodiments and / or structures discussed.

[0102] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like are used to facilitate describing the relationship of one element or component to another element or component as depicted in the drawings. These spatially relative terms are intended to encompass different orientations of the element in use or operation other than the orientation depicted in the drawings. The element may be oriented differently (rotated 90 degrees or at other orientations), and the spatially relative adjectives used therein should be interpreted accordingly.

[0103] It will be understood that when an element or layer is referred to as being “connected” or “coupled” to another element or layer, it can be directly connected or coupled to the other element or layer or intervening elements or layers may be present.

[0104] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise specified, these terms are used only to distinguish one element from another. Thus, for example, a first element, a first component, or a first part discussed below could be referred to as a second element, a second component, or a second part without departing from the teachings of the present disclosure.

[0105] Unless the context indicates otherwise, terms like "same," "equal," "planar," or "coplanar" used herein when referring to an orientation, layout, position, shape, size, quantity, or other measurement do not necessarily mean exactly the same orientation, layout, position, shape, size, quantity, or other measurement, but are intended to encompass nearly identical orientations, layouts, positions, shapes, sizes, quantities, or other measurements within an acceptable range of variation, for example, due to manufacturing processes. The term "substantially" may be used herein to reflect this meaning. For example, items described as "substantially the same," "substantially equal," or "substantially planar" may be exactly the same, equal, or planar, or may be the same, equal, or planar within an acceptable range of variation, for example, due to manufacturing processes.

[0106] In this disclosure, a semiconductor element generally refers to an element that can function by utilizing semiconductor characteristics, and electro-optical elements, light-emitting display elements, semiconductor circuits, and electronic elements are all included in the category of semiconductor elements.

[0107] It should be noted that in the description of the present disclosure, above or up corresponds to the arrow direction of direction Z, and below or down corresponds to the arrow direction opposite to direction Z.

[0108] Figure 1 According to one embodiment of the present disclosure, a method 10 for manufacturing a semiconductor device 1A is shown in the form of a flow chart. Figure 2 A schematic top view of a middle semiconductor element is shown according to one embodiment of the present disclosure. Figure 3 To follow Figure 2 Schematic diagram of the cross section drawn by line AA' and line BB'. Figure 4 A schematic top view of a middle semiconductor element is shown according to one embodiment of the present disclosure. Figure 5 To follow Figure 4 Schematic diagram of the cross section drawn by line AA' and line BB'.

[0109] Reference Figures 1 to 5In step S11 , a substrate 101 may be provided, an isolation layer 103 may be formed in the substrate 101 to define a plurality of active areas AA, and a plurality of word line structures 200 may be formed in the substrate 101 and intersecting the plurality of active areas AA.

[0110] Reference Figure 2 and Figure 3 The substrate 101 may include a bulk semiconductor substrate. The bulk semiconductor substrate may include, for example, an elemental semiconductor such as silicon or germanium; a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V compound semiconductors or II-VI compound semiconductors; or a combination thereof.

[0111] In some embodiments, the semiconductor substrate 101 may include a semiconductor-on-insulator substrate, which includes, from bottom to top, a handle substrate, an insulating layer, and a topmost semiconductor material layer. The handle substrate and the topmost semiconductor material layer may include the same materials as the bulk semiconductor substrate described above. The insulating layer may be a crystalline or amorphous dielectric material, such as an oxide and / or a nitride. For example, the insulating layer may be a dielectric oxide, such as silicon oxide. For another example, the insulating layer may be a dielectric nitride, such as silicon nitride or boron nitride. For another example, the insulating layer may include a stack of dielectric oxides and dielectric nitrides, such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The insulating layer may have a thickness between about 10 nm and about 200 nm. The insulating layer may eliminate leakage current between adjacent components in the substrate 101 and reduce parasitic capacitance associated with the source / drain.

[0112] It should be noted that in the description of this disclosure, the word "about" used to modify the amount of an ingredient, component, or reactant used in this disclosure refers to the quantitative variation that may occur, for example, due to typical measurement and liquid handling procedures used to prepare concentrates or solutions. In addition, variations may occur due to inadvertent errors in measurement procedures, differences in the manufacture, source, or purity of ingredients used to make compositions or implement methods. In one aspect, the word "about" means within 10% of the reported value. In another aspect, the word "about" means within 5% of the reported value. In another aspect, the word "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0113] Reference Figure 2 and Figure 3, an isolation layer 103 can be formed in the substrate 101. A series of deposition processes can be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on the substrate 101. A photolithography process and a subsequent etching process, such as an anisotropic dry etching process, can be performed to form a trench that passes through the pad oxide layer, the pad nitride layer, and extends to the substrate 101. An insulating material can be deposited into the trench and a planarization process, such as chemical mechanical polishing, can be subsequently performed until the top surface of the substrate 101 is exposed to remove excess fill material, provide a substantially flat surface for subsequent processing steps, and simultaneously form the isolation layer 103. The insulating material can be, for example, silicon oxide or other applicable insulating materials. The isolation layer 103 can define a plurality of active areas AA in the substrate 101.

[0114] It should be noted that, in the description of the present disclosure, the surface of an element (or component) located at the highest vertical level along the Z axis is referred to as the top surface of the element (or component). The surface of an element (or component) located at the lowest vertical level along the Z axis is referred to as the bottom surface of the element (or component).

[0115] It should be noted that each of the plurality of active areas AA may include a portion of the substrate 101 and the space above the portion of the substrate 101. Describing an element as being disposed on the active area AA means that the element is disposed on the top surface of the portion of the substrate 101. Describing an element as being disposed in the active area AA means that the element is disposed in the portion of the substrate 101. However, the top surface of the element may be flush with the top surface of the portion of the substrate 101. Describing an element as being disposed above the active area AA means that the element is disposed above the top surface of the portion of the substrate 101.

[0116] Reference Figure 2 and Figure 3Multiple impurity regions 105 can be formed in the multiple active areas AA, respectively. In some embodiments, the fabrication technique for the multiple impurity regions 105 can include an implantation process. That is, the multiple impurity regions 105 can be transformed from a portion of the multiple active areas AA. The dopant in the implantation process can include p-type impurities (dopants) or n-type impurities (dopants). P-type dopants can be added to the intrinsic semiconductor material to create valence electron defects. In a silicon-containing substrate, examples of p-type dopants (i.e., impurities) include, but are not limited to, boron, aluminum, gallium, or indium. N-type dopants can be added to the intrinsic semiconductor material to contribute free electrons to the intrinsic semiconductor material. In a silicon-containing substrate, examples of n-type dopants (i.e., impurities) include, but are not limited to, antimony, arsenic, or phosphorus. In some embodiments, the dopant concentration of the multiple impurity regions 105 can be between approximately 1E19 atoms / cm^3 and approximately 1E21 atoms / cm^3. After the implantation process, the multiple impurity regions 105 can have an electrical type such as n-type or p-type.

[0117] Reference Figure 4 and Figure 5 , a plurality of word line trenches TR may be formed in the substrate 101 to define the positions of the plurality of word line structures 200. The fabrication technology of the plurality of word line trenches TR may include a photolithography process and a subsequent etching process. In some embodiments, in a top view perspective, the plurality of word line trenches TR may have a linear cross-sectional profile and extend along a direction X and pass through a plurality of impurity regions 105 (or intersect with a plurality of impurity regions 105). For example, each impurity region 105 may intersect with two word line trenches TR. The plurality of word line trenches TR may divide each of the plurality of impurity regions 105 into a plurality of common source regions 105-1 and a plurality of drain regions 105-3. For one impurity region 105, a common source region 105-1 may be formed between the two word line trenches TR, and two drain regions 105-3 may be formed respectively between the isolation layer 103 and the two word line trenches TR.

[0118] Reference Figure 4 and Figure 5 Multiple word line structures 200 (e.g., two word line structures 200) can be formed in multiple word line trenches TR (e.g., two word line trenches TR). For brevity, clarity, and convenience, only one word line structure 200 is described. The word line structure 200 may include a word line dielectric layer 201, a word line barrier layer 203, a word line conductive layer 205, and a word line cap layer 207.

[0119] Reference Figure 4 and Figure 5, a wordline dielectric layer 201 can be conformally formed on the inner surface of the wordline trench TR. The wordline dielectric layer 201 can have a U-shaped cross-sectional profile. In other words, the wordline dielectric layer 201 can be formed inwardly in the active area AA. In some embodiments, the wordline dielectric layer 201 can be formed by a thermal oxidation process. For example, the wordline dielectric layer 201 can be formed by oxidizing the inner surface of the wordline trench TR. In some embodiments, the wordline dielectric layer 201 can be formed by a deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The wordline dielectric layer 201 can include a high-k dielectric constant (high-k) material, an oxide, a nitride, an oxynitride, or a combination thereof. In some embodiments, after depositing a pad polysilicon layer (not shown for clarity), the wordline dielectric layer 201 can be formed by free radical oxidation of the pad polysilicon layer. In some embodiments, after forming a pad silicon nitride layer (not shown for clarity), the word line dielectric layer 201 may be formed by radically oxidizing the pad silicon nitride layer.

[0120] In some embodiments, the high-k dielectric material may include a hafnium-containing material. The hafnium-containing material may be, for example, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In some embodiments, the high-k dielectric material may be, for example, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof.

[0121] Reference Figure 4 and Figure 5 A wordline barrier layer 203 can be conformally formed on the wordline dielectric layer 201 and within the wordline trench TR. In some embodiments, the wordline barrier layer 203 can include, for example, titanium nitride, titanium, or a combination thereof. In some embodiments, the wordline barrier layer 203 can include, for example, titanium nitride. In some embodiments, the wordline barrier layer 203 can be fabricated using techniques such as atomic layer deposition, physical vapor deposition, chemical vapor deposition, or other applicable deposition processes.

[0122] Reference Figure 4 and Figure 5, a word line conductive layer 205 may be formed on the word line barrier layer 203 and within the word line trench TR. In some embodiments, to form the word line conductive layer 205, a conductive layer (not shown for clarity) may be formed to fill the word line trench TR, and a recess process may then be performed. The recess process may be performed as an etch-back process or as a planarization process and an etch-back process performed sequentially. The word line conductive layer 205 may have a recessed shape that partially fills the word line trench TR. That is, the top surface of the word line conductive layer 205 may be lower than the top surface of the substrate 101.

[0123] In some embodiments, the word line conductive layer 205 may include a metal, a metal nitride, or a combination thereof. For example, the word line conductive layer 205 may include titanium nitride, tungsten, or titanium nitride / tungsten. After conformally forming titanium nitride, the titanium nitride / tungsten may have a structure in which the word line trench TR is partially filled with tungsten. Titanium nitride or tungsten may be used alone for the word line conductive layer 205. In some embodiments, the word line conductive layer 205 may include, for example, a conductive material such as doped polysilicon, doped polycrystalline germanium, doped polycrystalline silicon germanium, or a combination thereof. In some embodiments, the word line conductive layer 205 may include, for example, tungsten, aluminum, titanium, copper, a similar material thereof, or a combination thereof.

[0124] Reference Figure 4 and Figure 5 A dielectric material (not shown) may be deposited, for example, by chemical vapor deposition to completely fill the wordline trenches TR and cover the top surface of the substrate 101. A planarization process, such as chemical mechanical polishing, may be performed to provide a substantially flat surface for subsequent processing steps and to form a wordline cap layer 207. In some embodiments, the wordline cap layer 207 may include silicon nitride or other applicable dielectric materials.

[0125] Figure 6 A schematic top view of a middle semiconductor element is shown according to one embodiment of the present disclosure. Figure 7 To follow Figure 6 Schematic diagram of the cross section drawn by line AA' and line BB'. Figure 8 A schematic top view of a middle semiconductor element is shown according to one embodiment of the present disclosure. Figure 9 To follow Figure 8 Schematic diagram of the cross section drawn by line AA' and line BB'. Figure 10 A schematic top view of a middle semiconductor element is shown according to one embodiment of the present disclosure. Figure 11 To follow Figure 10 It should be noted that some elements are omitted in the top view for the sake of clarity.

[0126] Reference Figure 1 and Figures 6 to 11 In step S13 , a plurality of bit line structures 300 may be formed on the substrate 101 , and a plurality of spacer structures 400 may be formed on the side surfaces 300S of the plurality of bit line structures.

[0127] Reference Figure 6 and Figure 7 , a bottom dielectric layer 107 may be formed on the substrate 101. In some embodiments, the bottom dielectric layer 107 may include a material having an etch selectivity to the substrate 101 and the isolation layer 103. In some embodiments, the bottom dielectric layer 107 may include, for example, silicon nitride, boron nitride, silicon boron nitride, boron phosphide, silicon carbon boron nitride, or a combination thereof. In some embodiments, the bottom dielectric layer 107 may include, for example, silicon nitride. In some embodiments, the bottom dielectric layer 107 may be fabricated using techniques such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other applicable deposition processes.

[0128] Reference Figure 6 and Figure 7 A plurality of bit line contacts 309 may be formed, each extending through the bottom dielectric layer 107 and to the plurality of common source regions 105-1. In some embodiments, the plurality of bit line contacts 309 may include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, a metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), a metal nitride (e.g., titanium nitride), a transition metal aluminide, or a combination thereof. In some embodiments, the plurality of bit line contacts 309 may have a square cross-sectional profile in a top view, but is not limited to this shape. In some embodiments, the plurality of bit line contacts 309 may have a rectangular, circular, or other applicable cross-sectional profile in a top view.

[0129] Reference Figure 8 and Figure 9 Multiple bit line structures 300 can be formed on the bottom dielectric layer 107 and electrically connected to the multiple bit line contacts 309, respectively. In a top view, the multiple bit line structures 300 can extend along direction Y and be separated from each other. In other words, in a top view, the multiple bit line structures 300 can intersect the multiple word line structures 200. For the sake of brevity, clarity, and convenience, only one bit line structure 300 is described. In some embodiments, the bit line structure 300 can include a bit line top conductive layer 301 and a bit line cap layer 307.

[0130] A bitline top conductive layer 301 may be formed on and electrically connected to the bitline contact 309. In some embodiments, the bitline top conductive layer 301 may include, for example, titanium nitride, tungsten, titanium, nickel, platinum, tantalum, cobalt, silver, copper, aluminum, other applicable conductive materials, or combinations thereof. A bitline cap layer 307 may be formed on the bitline top conductive layer 301. In some embodiments, the bitline cap layer 307 may include, for example, silicon nitride or other applicable insulating materials.

[0131] Reference Figure 10 and Figure 11 Multiple spacer structures 400 may be formed on the side surfaces 300S of the multiple bit line structures 300. In other words, in a top perspective view, the multiple spacer structures 400 may extend along direction Y. For the sake of brevity, clarity, and convenience, only one spacer structure 400 is described. In some embodiments, the spacer structure 400 may include intra-bit line spacers 401, inter-bit line spacers 403, and extra-bit line spacers 405.

[0132] The bitline spacer 401 may be formed on the side surface 300S of the bitline structure 300. In some embodiments, the bitline spacer 401 may comprise the same material as the bitline cap layer 307. In some embodiments, the bitline spacer 401 may comprise, for example, silicon nitride or other applicable insulating materials. In some embodiments, the bitline spacer 401 may be formed by conformally depositing a layer of insulating material (not shown) on the bottom dielectric layer 107 and subsequently performing an anisotropic etching process.

[0133] The bitline interspacers 403 can be conformally formed on the bitline interspacers 401. In some embodiments, the bitline interspacers 403 can include, for example, silicon oxide or other applicable insulating oxides. In some embodiments, the bitline interspacers 403 can be formed by conformally depositing a layer of insulating oxide (not shown) on the bottom dielectric layer 107 and subsequently performing an anisotropic etching process.

[0134] The bitline outer spacers 405 can be conformally formed on the bitline middle spacers 403. In some embodiments, the bitline outer spacers 405 can comprise the same material as the bitline inner spacers 401 or the bitline capping layer 307. In some embodiments, the bitline outer spacers 405 can comprise, for example, silicon nitride or other applicable insulating materials. In some embodiments, the bitline outer spacers 405 can be formed by conformally depositing a layer of insulating material (not shown) on the bottom dielectric layer 107 and subsequently performing an anisotropic etching process.

[0135] In some embodiments, the intra-bitline spacers 401 may be optional. In other words, the inter-bitline spacers 403 may be formed directly on the side surface 300S of the bitline structure 300 .

[0136] Figure 12 A schematic top view of a middle semiconductor element is shown according to one embodiment of the present disclosure. Figure 13 To follow Figure 12 Schematic diagram of the cross section drawn by line AA' and line BB'. Figure 14 A schematic top view of a middle semiconductor element is shown according to one embodiment of the present disclosure. Figure 15 and Figure 16 To follow Figure 14 Schematic cross-sectional views taken along lines AA′ and BB′ in FIG. 1 show a partial process for manufacturing a semiconductor device 1A according to some embodiments. Figure 17 A schematic top view of a middle semiconductor element is shown according to one embodiment of the present disclosure. Figure 18 To follow Figure 17 Schematic diagram of the cross section drawn by line AA' and line BB'.

[0137] Reference Figure 1 and Figures 12 to 18 In step S15, a sacrificial layer 801 may be formed to cover the plurality of bit line structures 300 and the plurality of spacer structures 400, a first mask layer 701 including a linear pattern P1 may be formed on the sacrificial layer 801 to partially expose the sacrificial layer 801, the plurality of bit line structures 300, and the plurality of spacer structures 400, the sacrificial layer 801 may be selectively removed to form a plurality of separation openings OP1, and a plurality of separation layers 601 may be formed in the plurality of separation openings OP1.

[0138] Reference Figure 12 and Figure 13 , a sacrificial layer 801 may be formed on the bottom dielectric layer 107 to cover the plurality of bit line structures 300 and the plurality of spacer structures 400. In some embodiments, the sacrificial layer 801 may include, for example, a material having an etch selectivity to the bit line outer spacers 405 or the bit line capping layer 307. In some embodiments, the sacrificial layer 801 may include, for example, silicon oxynitride, silicon nitride oxide, or other applicable materials. In some embodiments, the sacrificial layer 801 may be fabricated using, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other applicable deposition processes. In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed until the top surfaces 307TS of the plurality of bit line structures 300 are exposed to remove excess material and provide a substantially flat surface for subsequent processing steps.

[0139] It should be noted that in the description of this disclosure, silicon oxynitride refers to a substance containing silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0140] Reference Figure 12 and Figure 13 A first mask layer 701 may be formed on the sacrificial layer 801. In some embodiments, the first mask layer 701 may be a photoresist layer. In a top view, the linear pattern P1 of the first mask layer 701 may include a plurality of rectangular spaces extending along direction X and alternately arranged along direction Y. These spaces partially expose the sacrificial layer 801, the plurality of bit line structures 300, and the plurality of spacer structures 400.

[0141] Reference Figure 14 and Figure 15 , the sacrificial layer 801 exposed by the linear patterns P1 of the first mask layer 701 can be selectively removed. In some embodiments, the sacrificial layer 801 can be removed using an anisotropic etching process, such as an anisotropic dry etching process. After removing the sacrificial layer 801, a plurality of separation openings OP1 can be formed in the locations of the sacrificial layer 801 exposed by the linear patterns P1 of the first mask layer 701. After forming these separation openings OP1, the first mask layer 701 can then be removed.

[0142] Reference Figure 16 A layer of separation material 803 may be formed on the sacrificial layer 801 to completely fill the plurality of separation openings OP1. In some embodiments, the separation material 803 may be a material having an etch selectivity to the sacrificial layer 801. In some embodiments, the separation material 803 may be the same material as the bit line cap layer 307 or the bit line outer spacer 405. In some embodiments, the separation material 803 may be, for example, silicon nitride or other applicable insulating materials. In some embodiments, the separation material 803 may be fabricated using, for example, chemical vapor deposition or other applicable deposition processes.

[0143] Reference Figure 17 and Figure 18, a planarization process, such as chemical mechanical polishing, may be performed to remove excess material and provide a substantially flat surface for subsequent processing steps, and to convert the layer of spacer material 803 into a plurality of spacer layers 601. In a top view, each of the plurality of spacer layers 601 may have a linear (or rectangular) cross-sectional profile extending along direction X. The plurality of spacer layers 601 may be alternately arranged along direction X, with each corresponding bit line structure 300 located between two adjacent spacer layers 601. Along direction Y, the plurality of spacer layers 601 may be alternately arranged, with sacrificial layers 801 interposed therebetween. In a top view, the arrangement of the plurality of spacer layers 601 and the plurality of bit line structures 300 may divide the sacrificial layer 801 into a plurality of segments.

[0144] For simplicity, clarity, and convenience, only one spacer layer 601 is described. In some embodiments, after a planarization process, the intra-bitline spacers 401, the inter-bitline spacers 403, and the extra-bitline spacers 405 may be exposed. A top surface 601TS of the spacer layer 601, a top surface 401TS of the intra-bitline spacers 401, a top surface 403TS of the inter-bitline spacers 403, a top surface 405TS of the extra-bitline spacers 405, and a top surface 307TS of the bitline capping layer 307 may be substantially coplanar.

[0145] In some embodiments, after the planarization process, the bitline outer spacer 405 (not shown) may cover the bitline inner spacer 401 and the bitline middle spacer 403. In this case, the top surface 405TS of the bitline outer spacer 405 and the top surface 307TS of the bitline capping layer 307 may be substantially coplanar.

[0146] Figure 19 A schematic top view of a middle semiconductor element is shown according to one embodiment of the present disclosure. Figures 20 to 23 To follow Figure 19 Schematic cross-sectional views taken along lines AA′ and BB′ in FIG. 1 show a partial process for manufacturing a semiconductor device 1A according to some embodiments. Figure 24 A schematic top view of a middle semiconductor element is shown according to one embodiment of the present disclosure. Figure 25 and Figure 26 To follow Figure 24 Schematic cross-sectional views taken along lines AA′ and BB′ in FIG. 1 show a partial process for manufacturing a semiconductor device 1A according to some embodiments. Figure 27 A schematic top view of a middle semiconductor element is shown according to one embodiment of the present disclosure. Figure 28 and Figure 29 To follow Figure 27Schematic cross-sectional views taken along lines AA′ and BB′ in FIG. 1 show a partial process for manufacturing a semiconductor device 1A according to some embodiments.

[0147] Reference Figure 1 and Figures 19 to 29 In step S17, the sacrificial layer 801 can be selectively removed to form a plurality of contact openings OP2, a plurality of unit contact structures 500 can be formed in the plurality of contact openings OP2, and a top insulating layer 109 can be formed to cover the plurality of bit line structures 300, the plurality of spacer structures 400, and the plurality of unit contact structures 500.

[0148] Reference Figure 19 and Figure 20 , the sacrificial layer 801 can be selectively removed by an etching process. For example, the removal of the sacrificial layer 801 can be achieved by an anisotropic etching process. After removing the sacrificial layer 801, a plurality of contact openings OP2 can be formed in the positions previously occupied by the sacrificial layer 801 (in the form of multiple segments). For the sake of brevity, clarity and convenience of description, only one contact opening OP2 is described. In the cross-sectional perspective view, the contact opening OP2 can be disposed on the bottom dielectric layer 107. In the top-down perspective view, the contact opening OP2 can be surrounded by two adjacent separation layers 601 along the direction Y and can be surrounded by two adjacent bit line structures 300 (or spacer structures 400 disposed on the side surfaces 300S of two adjacent bit line structures 300) along the direction X.

[0149] Reference Figure 21 A punch-through process may be performed to remove a portion of the bottom dielectric layer 107 exposed by the plurality of contact openings OP2. In some embodiments, the punch-through process may be an anisotropic dry etching process. The punch-through process may extend the plurality of contact openings OP2 downward to the substrate 101. After the punch-through process, the plurality of drain regions 105-3 may be exposed through the plurality of contact openings OP2.

[0150] Reference Figure 22A layer of liner material 805 can be conformally formed to cover the substrate 101, the plurality of bit line structures 300, the plurality of spacer structures 400, and the plurality of separation layers 601. In some embodiments, the liner material 805 can include doped polysilicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. In some embodiments, the liner material 805 can include a p-type dopant or an n-type dopant. In some embodiments, the liner material 805 can be fabricated using techniques such as atomic layer deposition, chemical vapor deposition, or other applicable deposition processes. By using doped polysilicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium as the liner material 805 of the cell contact structure 500, junction leakage can be reduced. As a result, the performance of the semiconductor device 1A can be improved.

[0151] Reference Figure 23 A layer of first conductive material 807 may be formed on the layer of liner material 805 and completely fill the plurality of contact openings OP2. In some embodiments, the first conductive material 807 may be a material having good electrical conductivity (or a material having better electrical conductivity than doped polysilicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium). In some embodiments, the first conductive material 807 may be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, a metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), a metal nitride (e.g., titanium nitride), a transition metal aluminide, or a combination thereof. In some embodiments, the first conductive material 807 may be, for example, titanium nitride, titanium, tungsten, or a combination thereof. By using a material having good electrical conductivity, the sheet resistance of the cell contact structure 500 may be reduced. As a result, the performance of the semiconductor device 1A may be improved.

[0152] Reference Figure 24 and Figure 25 , an etch-back process may be performed to remove portions of the liner material 805 and the first conductive material 807. After the etch-back process, the remaining liner material 805 is converted into a plurality of liner layers 501 within the plurality of contact openings OP2, respectively. The remaining first conductive material 807 is converted into a plurality of bottom contact layers 503 within the plurality of contact openings OP2, respectively.

[0153] For simplicity, clarity, and convenience, only one liner 501 and one bottom contact layer 503 are described. In some embodiments, in a cross-sectional perspective, a top surface 503TS of the bottom contact layer 503 and a top surface 501TS of the liner 501 can be substantially coplanar. The top surface 503TS of the bottom contact layer 503 and the top surface 501TS of the liner 501 can be lower than the top surface 307TS of the bit line cap layer 307 (that is, the top surface of the bit line structure 300). In some embodiments, in a top-down perspective, the liner 501 can have a square-ring-shaped or rectangular-ring-shaped cross-sectional profile. The bottom contact layer 503 can have a square or rectangular cross-sectional profile.

[0154] Reference Figure 26 A layer of second conductive material 809 may be formed on the substrate 101 to completely fill the plurality of contact openings OP2 and cover the plurality of isolation layers 601, the plurality of bit line structures 300, and the plurality of spacer structures 400. In some embodiments, the second conductive material 809 may be a material having good electrical conductivity (or a material having better electrical conductivity than doped polysilicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium). In some embodiments, the second conductive material 809 may be the same material as the bottom contact layer 503. In some embodiments, the second conductive material 809 may be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, a metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), a metal nitride (e.g., titanium nitride), a transition metal aluminide, or a combination thereof. In some embodiments, the second conductive material 809 may be, for example, titanium nitride, titanium, tungsten, or a combination thereof.

[0155] Reference Figure 27 and Figure 28 , an etch-back process may be performed to remove a portion of the second conductive material 809. After the etch-back process, the remaining second conductive material 809 may be converted into a plurality of top contact layers 505 within the plurality of contact openings OP2, respectively. For the sake of brevity, clarity, and convenience of description, only one top contact layer 505 is described. In some embodiments, in a cross-sectional perspective, a top surface 505TS of the top contact layer 505 may be lower than a top surface 307TS of the bit line cap layer 307. In some embodiments, a width W1 of the top contact layer 505 may be greater than a width W2 of the bottom contact layer 503. In some embodiments, in a top-down perspective, the top contact layer 505 may have a square or rectangular cross-sectional profile. The liner 501, the bottom contact layer 503, and the top contact layer 505 together constitute a cell contact structure 500. The cell contact structure 500 may be electrically connected to the corresponding drain region 105-3.

[0156] By using the top contact layer 505 including a material having good electrical conductivity, it is possible to reduce the sheet resistance of the cell contact structure 500. As a result, the performance of the semiconductor element 1A can be further improved.

[0157] Reference Figure 29 A top insulating layer 109 may be formed on the substrate 101 to cover the plurality of separation layers 601, the plurality of cell contact structures 500, the plurality of spacer structures 400, and the plurality of bit line structures 300. In some embodiments, the top insulating layer 109 may include the same material as the bit line capping layer 307. In some embodiments, the top insulating layer 109 may include, for example, silicon nitride or other applicable insulating materials.

[0158] Using a liner 501 comprising doped polysilicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium can be used to reduce junction leakage of the cell contact structure 500. In addition, using a bottom contact layer 503 and a top contact layer 505 comprising materials such as titanium nitride, tungsten, or titanium can effectively reduce the sheet resistance of the cell contact structure 500. These enhancements can collectively improve the performance of the semiconductor device 1A.

[0159] Figures 30 to 32 Schematic cross-sectional views of semiconductor devices 1B, 1C, and 1D are shown according to some embodiments of the present disclosure.

[0160] like Figure 30 As shown, the semiconductor element 1B may have a structure similar to Figure 29 The structure shown. Figure 30 Zhongyu Figure 29 The same or similar elements are denoted by the same symbols, and repeated descriptions are omitted.

[0161] In the semiconductor device 1B, the bit line structure 300 may include a bit line bottom conductive layer 305 , a bit line middle conductive layer 303 , a bit line top conductive layer 301 , and a bit line capping layer 307 .

[0162] The bitline bottom conductive layer 305 may be disposed on the bitline contact 309. In some embodiments, the bitline bottom conductive layer 305 may include, for example, doped polysilicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium, or a combination thereof. In some embodiments, the dopant for the bitline bottom conductive layer 305 may include boron, aluminum, gallium, indium, antimony, arsenic, or phosphorus.

[0163] The bit line intermediate conductive layer 303 may be disposed on the bit line bottom conductive layer 305. In some embodiments, the bit line intermediate conductive layer 303 may include, for example, titanium silicide, nickel silicide, platinum nickel silicide, tantalum silicide, or cobalt silicide. In some embodiments, the bit line intermediate conductive layer 303 may have a thickness between approximately 2 nm and approximately 20 nm.

[0164] The bitline top conductive layer 301 may be disposed on the bitline middle conductive layer 303. In some embodiments, the bitline top conductive layer 301 may include titanium, nickel, platinum, tantalum, cobalt, silver, copper, aluminum, other applicable conductive materials, or combinations thereof.

[0165] A bit line capping layer 307 may be disposed on the bit line top conductive layer 301. In some embodiments, the bit line capping layer 307 may include, for example, silicon nitride or other applicable insulating materials.

[0166] Reference Figure 31 , the semiconductor element 1C may have a similar Figure 29 The structure shown. Figure 31 Zhongyu Figure 29 The same or similar elements are denoted by the same symbols, and repeated descriptions are omitted.

[0167] In the semiconductor device 1C, the plurality of spacer structures 400 may include a plurality of intra-bitline spacers 401, a plurality of air gaps 407, and a plurality of extra-bitline spacers 405. The plurality of intra-bitline spacers 401 may be disposed on the side surfaces 300S of the bitline structure 300, respectively. The plurality of extra-bitline spacers 405 may be disposed on the plurality of intra-bitline spacers 401, respectively. The plurality of air gaps 407 may be disposed between the plurality of intra-bitline spacers 401 and the plurality of extra-bitline spacers 405. The use of the plurality of air gaps 407 may reduce the dielectric constant of the spacer structure 400. Consequently, the parasitic capacitance between adjacent conductive components (e.g., adjacent bitline structures 300) may be reduced.

[0168] Reference Figure 32 , the semiconductor element 1D may have a similar Figure 29 The structure shown. Figure 32 Zhongyu Figure 29 The same or similar elements are denoted by the same symbols, and repeated descriptions are omitted.

[0169] One aspect of the present disclosure provides a cell contact structure comprising: a bottom contact layer disposed on a substrate and surrounded by a plurality of bit line structures and a plurality of spacer layers; a liner disposed between the bottom contact layer and the substrate, between the bottom contact layer and the plurality of bit line structures, and between the bottom contact layer and the plurality of spacer layers; and a top contact layer disposed between the bottom contact layer and the liner layer. A top surface of the bottom contact layer and a top surface of the liner layer are substantially coplanar. The liner layer comprises doped polysilicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. The bottom contact layer comprises tungsten, titanium, or titanium nitride.

[0170] Another aspect of the present disclosure provides a semiconductor device comprising: a substrate; two bit line structures formed on the substrate, extending along a first direction and separated from each other; two spacer layers located on the substrate, extending along a second direction perpendicular to the first direction and separated from each other along the first direction, and simultaneously contacting the two bit line structures; and a cell contact structure. The cell contact structure comprises: a bottom contact layer located on the substrate and surrounded by the two bit line structures and the two spacer layers; a liner located between the substrate and the bottom contact layer, between the two bit line structures and the bottom contact layer, and between the two spacer layers and the bottom contact layer; and a top contact layer located on the liner and the bottom contact layer. A top surface of the liner and a top surface of the bottom contact layer are substantially coplanar. The liner comprises doped polysilicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. The bottom contact layer comprises tungsten, titanium, or titanium nitride.

[0171] Another aspect of the present disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming two bit line structures on the substrate, extending along a first direction and separated from each other; forming a plurality of spacer structures on side surfaces of the two bit line structures; forming two spacer layers on the substrate, extending along a second direction perpendicular to the first direction and separated from each other, thereby creating a contact opening combined with the plurality of spacer structures; conformally forming a liner in and within the contact opening; forming a bottom contact layer on the liner and within the contact opening; and forming a top contact layer on the liner, on the bottom contact layer, and within the contact opening. The liner comprises doped polysilicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. The bottom contact layer comprises tungsten, titanium, or titanium nitride. The liner, the bottom contact layer, and the top contact layer together constitute a cell contact structure.

[0172] Due to the design of the semiconductor device disclosed herein, the junction leakage of the cell contact structure 500 can be reduced by using a liner layer 501 comprising doped polysilicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. Furthermore, the sheet resistance of the cell contact structure 500 can be reduced by using a bottom contact layer 503 and a top contact layer 505 comprising titanium nitride, tungsten, or titanium. Consequently, the performance of the semiconductor device 1A can be improved.

[0173] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and replacements may be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes may be implemented in different ways, and may be replaced by other processes or combinations of the above processes.

[0174] Furthermore, the scope of the present invention is not limited to the specific embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will appreciate from the disclosure herein that existing or future developed processes, machines, manufacture, compositions of matter, means, methods, or steps that function the same as or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps are intended to be encompassed by the claims of the present invention.

Claims

1. A method for preparing a semiconductor element, comprising: providing a substrate; forming two bit line structures on the substrate, extending along a first direction and separated from each other; forming a plurality of spacer structures on side surfaces of the two bit line structures; forming two separation layers on the substrate, extending along a second direction perpendicular to the first direction and separated from each other, thereby forming a contact opening combined with a plurality of the spacer structures; conformally forming a liner in and within the contact opening; forming a bottom contact layer on the liner and within the contact opening; as well as forming a top contact layer on the liner, on the bottom contact layer, and in the contact opening, wherein the liner comprises doped polysilicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium, wherein the bottom contact layer comprises tungsten, titanium, or titanium nitride, The liner, the bottom contact layer, and the top contact layer together form a unit contact structure.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein forming two separation layers comprises: forming a sacrificial layer on the substrate to cover the two bit lines and the plurality of spacer structures; performing a first planarization process until top surfaces of the two bit lines are exposed; forming a first mask layer on the sacrificial layer, wherein the first mask layer comprises a linear pattern partially exposing the sacrificial layer, the two bit line structures, and the plurality of spacer structures; selectively removing the sacrificial layer to form two separation openings; removing the first mask layer; forming a layer of separation material to completely fill the two separation openings and cover the two bit line structures and the plurality of spacer structures; A second planarization process is performed until the top surfaces of the two bit lines and the sacrificial layer are exposed, so as to convert the layer of separation material into the two separation layers. 3 . The method for fabricating a semiconductor device as claimed in claim 2 , wherein the sacrificial layer comprises silicon oxynitride or silicon nitride oxide. The method for fabricating a semiconductor device as claimed in claim 2 , wherein the layer of separation material comprises silicon nitride.

5. The method for preparing a semiconductor device according to claim 2, further comprising: The sacrificial layer is selectively removed to form the contact opening.

6. The method for fabricating a semiconductor device according to claim 5, wherein forming a plurality of the spacer structures comprises: forming a plurality of intra-bit line spacers on side surfaces of the two bit line structures; forming a plurality of bit line inter-spacers on the plurality of bit line intra-spacers; as well as A plurality of bit line outer spacers are formed on the plurality of bit line middle spacers. 7 . The method for fabricating a semiconductor device as claimed in claim 6 , wherein the plurality of intra-bit line spacers and the plurality of inter-bit line spacers comprise the same material. 8 . The method for fabricating a semiconductor device as claimed in claim 6 , wherein the top contact layer comprises tungsten, titanium, or titanium nitride. 9 . The method for fabricating a semiconductor device as claimed in claim 6 , wherein the top contact layer and the bottom contact layer comprise the same material. 10 . The method for fabricating a semiconductor device as claimed in claim 6 , wherein the liner layer comprises an n-type dopant or a p-type dopant.

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