Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the same. A semiconductor device may include: a gate structure including stacked gate lines; a first contact plug extending through the gate structure, electrically connected to a first gate line among the gate lines, and including a first portion having a tapered shape and a second portion having an inverted tapered shape; and a second contact plug extending through the gate structure, and the second contact plug is electrically connected to a second gate line among the gate lines and has a tapered shape.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to electronic devices, and more particularly, to semiconductor devices and methods of manufacturing the same. Background Art

[0002] The integration level (also known as component density or functional density) of a semiconductor device is primarily determined by the area occupied by a unit memory cell. Therefore, a higher integration level generally means more components per chip and / or higher functionality. Recently, as the integration level of semiconductor devices in which memory cells are formed as a single layer on a substrate has reached its limit, three-dimensional semiconductor devices in which memory cells are stacked on a substrate have been proposed. Furthermore, various structures and manufacturing methods are being developed to improve the operational reliability of semiconductor devices. Summary of the Invention

[0003] According to one embodiment of the present disclosure, a semiconductor device may include: a gate structure including a plurality of gate lines; a first contact plug extending through the gate structure, the first contact plug being electrically connected to a first gate line among the gate lines and including a first portion having a tapered shape and a second portion having an inverted tapered shape; and a second contact plug extending through the gate structure, being electrically connected to a second gate line among the gate lines, and having a tapered shape.

[0004] According to one embodiment of the present disclosure, a semiconductor device may include: a gate structure including stacked gate lines; a source structure disposed on the gate structure; and a first contact plug extending through the gate structure and the source structure, the first contact plug being electrically connected to a first gate line among the gate lines, and the first contact plug may include: a first portion extending through the gate structure and having a tapered shape; a second portion extending through the gate structure and having an inverted tapered shape; and a third portion extending through the source structure and having a tapered shape.

[0005] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device may include: forming a sacrificial contact structure extending from a front surface toward a rear surface of a first stack; forming a second stack on the front surface of the first stack; forming a first opening by removing the sacrificial contact structure through the rear surface of the first stack; forming a second opening in the second stack by etching the second stack through the first opening; and forming contact plugs in the first opening and the second opening.

[0006] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device may include: forming a first stack including alternately stacked first material layers and second material layers on a substrate; forming a sacrificial contact structure extending into the substrate through the first stack; forming a second stack including alternately stacked third material layers and fourth material layers on a front surface of the first stack; exposing a rear surface of the first stack by removing the substrate; forming a source structure on the rear surface of the first stack; forming an opening that extends through the source structure and exposes the sacrificial contact structure; forming a first opening by removing the sacrificial contact structure through the opening; forming a second opening by etching the second stack through the opening and the first opening; and forming contact plugs in the opening, the first opening, and the second opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1A to 1C is a simplified diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure.

[0008] Figures 2A to 2C is a simplified diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure.

[0009] Figure 3A and Figure 3B is a simplified diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure.

[0010] Figures 4A to 4E is a simplified diagram illustrating a method of manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0011] Figures 5A to 13A as well as Figures 5B to 13B is a simplified diagram illustrating a method of manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0012] Figure 14 is a structural diagram of a semiconductor device according to one embodiment of the present disclosure.

[0013] Figure 15 is a structural diagram of a semiconductor device according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] One embodiment of the present disclosure provides a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the same.

[0015] By stacking memory cells in three dimensions, the integration density of a semiconductor device can be increased. In addition, a semiconductor device having a stable structure and improved reliability can be provided.

[0016] Hereinafter, embodiments according to the technical spirit of the present disclosure will be described with reference to the accompanying drawings.

[0017] Figures 1A to 1C is a simplified diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure. Figure 1B It is along Figure 1A A cross-sectional view taken along line AA', and Figure 1C It is along Figure 1A A cross-sectional view taken along line BB'.

[0018] Reference Figures 1A to 1C The semiconductor device may include a gate structure GST and a plurality of contact plugs CT. The plurality of contact plugs CT may be spaced apart from each other at regular intervals. The semiconductor device may further include at least one of a source structure 13, a channel structure CH, a slit structure SLS, and a support member SP.

[0019] The gate structure GST may include stacked gate lines 11. In one embodiment, the gate lines 11 and the insulating layers 12 may be alternately stacked. For example, the gate lines 11 may be select lines, word lines, etc. The gate lines 11 may include a conductive material such as polysilicon or metal. The insulating layers 12 may be used to insulate the stacked gate lines 11 from each other. The insulating layers 12 may include an insulating material such as oxide or nitride and may contain voids therein.

[0020] The gate lines 11 may include a first gate line 11A, a second gate line 11B, and a third gate line 11C. The second gate line 11B may be stacked on the first gate line 11A, and the third gate line 11C may be stacked on the second gate line 11B.

[0021] The gate structure GST may include a cell region CR and a contact region CTR. The cell region CR may be a region where the memory cells are stacked. The contact region CTR may be a region where an interconnect structure is formed, through which a bias voltage for driving the stacked memory cells is transmitted. The cell region CR and the contact region CTR may be adjacent to each other in a first direction I.

[0022] The channel structure CH may extend through the cell region CR of the gate structure GST. The channel structure CH may extend into the source structure 13 through the gate structure GST. The support member SP may extend through the contact region CTR of the gate structure GST. The support member SP may have a similar structure to the channel structure CH. The slit structure SLS may pass through the source structure 13 and the cell region CR of the gate structure GST and may extend in a first direction I. The slit structure SLS may extend to the contact region CTR. The gate structure GST may be located between adjacent slit structures SLS in a second direction II.

[0023] The contact plugs CT may be arranged in the contact region CTR of the gate structure GST and may extend to various depths within the gate structure GST through the source structure 13. The contact plugs CT may include first to third contact plugs CT1, CT2, and CT3. The first contact plugs CT1 may be connected to the first gate line GL1, respectively. The second contact plugs CT2 may be connected to the second gate line GL2. The third contact plugs CT3 may be connected to the third gate line GL3. The first contact plugs CT1 may be greater than the second contact plugs CT2. The second contact plugs CT2 may be greater than the third contact plugs CT3.

[0024] According to the above structure, the contact plug CT can be extended into the gate structure GST. In addition, the contact plug CT and the gate line 11 can be connected to each other in a one-to-one correspondence. Figure 1B As shown, each contact plug may extend to a different depth inside the gate structure GST and be connected to a different one of the gate lines 11. Therefore, even if the contact region CTR is not patterned in a stepped shape, a bias voltage may be applied to each gate line 11 separately.

[0025] Figures 2A to 2C 1 is a simplified diagram illustrating a structure of a semiconductor device according to one embodiment of the present disclosure.

[0026] Reference Figure 2A The semiconductor device may include a gate structure GST, a source structure 23, a first contact plug 27A, and a first insulating spacer 28A. The gate structure GST may include gate lines 21 and insulating layers 22 stacked alternately. The source structure 23 may be located above the gate structure GST, or as shown in FIG. Figure 2A As shown, it is directly located on the gate structure GST.

[0027] The first contact plug 27A may extend through the source structure 23 and the gate structure GST and may be electrically connected to the first gate line 21A. The sidewall of the first contact plug 27A may be surrounded by a first insulating spacer 28A. The lower surface of the first contact plug 27A may be exposed by the first insulating spacer 28A and may contact the corresponding first gate line 21A.

[0028] The first contact plug 27A may have a width that varies according to the level and may be divided into a plurality of portions according to the cross-sectional shape. The first contact plug 27A may include a first portion 27A_P1 and a second portion 27A_P2 connected to the first portion 27A_P1. The upper portion of the first portion 27A_P1 and the lower portion of the second portion 27A_P2 may be connected.

[0029] The first contact plug 27A may include a first portion 27A_P1 and a first connection surface CS1 of a second portion 27A_P2. The widths of the first portion 27A_P1 and the second portion 27A_P2 may decrease as the distance from the first connection surface CS1 increases. The first portion 27A_P1 may have a tapered shape, with a lower width smaller than an upper width. The second portion 27A_P2 may have an inverted tapered shape, with an upper width smaller than a lower width. The inverted tapered shape may be repeated at least once, for example, twice, in the second portion 27A_P2. As the inverted tapered shape repeats, the first contact plug 27A may include at least one step S on its sidewalls. The second portion 27A_P2 may protrude into the source structure 23.

[0030] The first contact plug 27A may further include a third portion 27A_P3 connected to the second portion 27A_P2. The third portion 27A_P3 may extend through the source structure 23 and may have a tapered shape. The lower width of the third portion 27A_P3 may be smaller than the upper width. The third portion 27A_P3 may have a height lower than that of the source structure 23, and the second connection surface CS2 of the second portion 27A_P2 and the third portion 27A_P3 may be located in the source structure 23. The widths of the second portion 27A_P2 and the third portion 27A_P3 may increase as the distance from the second connection surface CS2 increases.

[0031] The semiconductor device may include a plurality of first contact plugs 27A. The plurality of first contact plugs 27A may be connected to a plurality of first gate lines 21A, respectively, and the first contact plugs 27A may have different heights. In one embodiment, when comparing first contact plugs 27A having different heights, the heights of the second portions 27A_P2 and third portions 27A_P3 may be the same, while the heights of the first portions 27A_P1 may be different.

[0032] Reference Figure 2B , the semiconductor device may include a gate structure GST, a source structure 23 , a second contact plug 27B, and a second insulating spacer 28B.

[0033] The second contact plug 27B may extend through the source structure 23 and the gate structure GST and may be electrically connected to the second gate line 21B. The sidewall of the second contact plug 27B may be surrounded by a second insulating spacer 28B. The lower surface of the second contact plug 27B may be exposed by the second insulating spacer 28B and may contact the corresponding second gate line 21B.

[0034] Second contact plug 27B may have a height lower than that of first contact plug 27A. Second contact plug 27B may include a first portion 27B_P1, a third portion 27B_P3, and a second portion 27B_P2 connected between first portion 27B_P1 and third portion 27B_P3. The upper portion of first portion 27B_P1 and the lower portion of second portion 27B_P2 may be connected, and the upper portion of second portion 27B_P2 and the lower portion of third portion 27B_P3 may be connected. First portion 27B_P1 and third portion 27B_P3 may have a tapered shape, and second portion 27B_P2 may have an inverted tapered shape.

[0035] The second contact plug 27B may include a first connection surface CS1 and a second connection surface CS2. The widths of the first portion 27B_P1 and the second portion 27B_P2 may decrease as the distance from the first connection surface CS1 increases, and the widths of the second portion 27B_P2 and the third portion 27B_P3 may decrease as the distance from the second connection surface CS2 increases.

[0036] The semiconductor device may include a plurality of second contact plugs 27B. The plurality of second contact plugs 27B may be connected to a plurality of second gate lines 21B, respectively, and the second contact plugs 27B may have different heights. In one embodiment, when comparing the second contact plugs 27B having different heights, the second portions 27B_P2 may have the same height, the third portions 27B_P3 may have the same height, and the first portions 27B_P1 may have different heights.

[0037] Reference Figure 2C The semiconductor device may include a gate structure GST, a source structure 23, a third contact plug 27C, and a third insulating spacer 28C. The third contact plug 27C may extend through the source structure 23 and the gate structure GST and may be electrically connected to the third gate line 21C. The third insulating spacer 28C may surround the sidewall of the third contact plug 27C.

[0038] The third contact plug 27C may have a tapered shape. The lower portion of the third contact plug 27C may have a width narrower than the width of the upper portion. In one embodiment, the third contact plug 27C may have a structure in which the tapered shape is repeated at least once. In this case, the third contact plug 27C may include at least one step S on its sidewall. The step S may be positioned to correspond to the interface between the source structure 23 and the gate structure GST.

[0039] The semiconductor device may include a plurality of third contact plugs 27C. The plurality of third contact plugs 27C may be connected to the third gate lines 21C, respectively, and the third contact plugs 27C may have different heights.

[0040] According to the above structure, the contact plugs 27A to 27C may have a structure in which a tapered shape and an inverted tapered shape are combined. The first contact plug 27A and the second contact plug 27B may have a structure in which the second portion of the inverted tapered shape is located between the first portion and the third portion of the tapered shape. The third contact plug 27C may have a structure in which the tapered shape is repeated at least once.

[0041] Figure 3A and Figure 3B 1 is a simplified diagram illustrating a structure of a semiconductor device according to one embodiment of the present disclosure.

[0042] Reference Figure 3A , the semiconductor device may include a gate structure GST, a source structure 33 and a slit structure 39. The gate structure GST may include gate lines 31 and insulating layers 32 stacked alternately. The source structure 33 may be located above the gate structure GST, or as shown in FIG. Figure 3A As shown, it is directly located on the gate structure GST.

[0043] The slit structure 39 may pass through (also referred to as extend through) the source structure 33 and the gate structure GST. The slit structure 39 may include a first portion 39_P1 extending through the gate structure GST and a second portion 39_P2 extending through the source structure 33. The upper portion of the first portion 39_P1 and the lower portion of the second portion 39_P2 may be connected. The first portion 39_P1 may have an inverted tapered shape, and the second portion 39_P2 may have a tapered shape. The inverted tapered shape may be repeated at least once (e.g., twice) in the first portion 39_P1. As the inverted tapered shape is repeated, the slit structure 39 may include at least one step S on the sidewall. The first portion 39_P1 may protrude into the source structure 33.

[0044] The slit structure 39 may include a connection surface CS of a first portion 39_P1 and a second portion 39_P2. The connection surface CS may be located in the source structure 33. The widths of the first portion 39_P1 and the second portion 39_P2 may increase as the distance from the connection surface CS increases.

[0045] The slit structure 39 may include a gap filling material or a source contact structure. For example, the gap filling material may include an insulating material (e.g., oxide or nitride) or a semiconductor material (e.g., silicon). The source contact structure may include a source contact plug electrically connected to the source structure 33 and an insulating spacer surrounding the sidewalls of the source contact plug.

[0046] Reference Figure 3B, the semiconductor device may include a gate structure GST, a source structure 33, and a channel structure CH. The channel structure CH may extend into the source structure 33 through the gate structure GST. The channel structure CH may include a channel layer 34 and may further include at least one of a memory layer 35 and an insulating core 36. The channel layer 34 may protrude into the source structure 33 and may be connected to the source structure 33. The memory layer 35 may surround the sidewalls of the channel layer 34 and may include at least one of a tunneling layer, a data storage layer, and a barrier layer. The data storage layer may include a floating gate, polysilicon, a charge trap material, a nitride, a variable resistance material, etc. The insulating core 36 may be located in the channel layer 34.

[0047] The channel structure CH may have an inverted tapered shape, and the inverted tapered shape may be repeated at least once (eg, twice). As the inverted tapered shape is repeated, the channel structure CH may include a step S on a sidewall.

[0048] According to the above structure, the slit structure 39 may have a structure in which a tapered shape and an inverted tapered shape are combined. The slit structure 39 may have a structure in which a first portion 39_P1 of a repeated inverted tapered shape and a second portion 39_P2 of a tapered shape are connected. The channel structure CH may have a structure in which an inverted tapered shape is repeated at least once.

[0049] Figures 4A to 4E is a simplified diagram illustrating a method of manufacturing a semiconductor device according to one embodiment of the present disclosure. Hereinafter, any description overlapping with the above description may be omitted.

[0050] Reference Figure 4A , a first stack ST1 including alternately stacked first material layers 41A and insulating layers 42 may be formed. The first material layer 41A may include a material having a high etching selectivity relative to the insulating layer 42. The first material layer 41A may be used to form a gate line. In one embodiment, the first material layer 41A may include a sacrificial material (e.g., nitride) or may include a conductive material (e.g., polysilicon or metal). The insulating layer 42 may be used to insulate the stacked gate lines from each other. In an embodiment, the insulating layer 42 may include an insulating material such as an oxide or a nitride and may include a void therein.

[0051] Subsequently, a sacrificial contact structure 43 may be formed in the first stack ST1. In one embodiment, a first opening OP1 may be formed in the first stack ST1, and the sacrificial contact structure 43 may be formed in the first opening OP1. The first opening OP1 may be formed by etching the first stack ST1, and according to the characteristics of the etching process, the first opening OP1 may have a tapered shape. The first opening OP1 may extend from the front surface FS1 of the first stack ST1 toward the rear surface RS1. The lower width of the first opening OP1 may be narrower than the upper width. The sacrificial contact structure 43 may include a material having a high etching selectivity with respect to the first material layer 41A and the insulating layer 42. In one embodiment, the sacrificial contact structure 43 may include carbon, tungsten, or the like.

[0052] Subsequently, a second stack ST2 can be formed on the first stack ST1. The second stack ST2 can be formed by alternately stacking a second material layer 41B and an insulating layer 42 on the front surface FS1 of the first stack ST1. The second material layer 41B may include a material having a high etch selectivity relative to the insulating layer 42. The second material layer 41B may be used to form a gate line. In one embodiment, the second material layer 41B may include a sacrificial material (e.g., a nitride) or may include a conductive material (e.g., polysilicon or metal). The insulating layer 42 may be used to insulate the stacked gate lines from each other. In one embodiment, the insulating layer 42 may include an insulating material such as an oxide or a nitride, and may contain a void therein.

[0053] Reference Figure 4B The first stack ST1 and the second stack ST2 may be inverted so that the first stack ST1 is located on the second stack ST2. Thus, the rear surface RS1 of the first stack ST1 may be the upper surface, and the front surface FS2 of the second stack ST2 may be the lower surface. The first opening OP1 has an inverted tapered shape.

[0054] Subsequently, the sacrificial contact structure 43 may be removed (eg, by selectively etching the sacrificial contact structure 43 ) through the back surface RS1 of the first stack ST1 to form a first opening OP1 (reopened). The back surface RS2 of the second stack ST2 may be exposed through the first opening OP1 .

[0055] Reference Figure 4C and Figure 4D, the second stack ST2 can be etched through the first opening OP1, and the second opening OP2 can be formed in the second stack ST2. Thus, the first opening OP1 can extend into the second stack ST2, and a contact hole CTH including the first opening OP1 in the first stack ST1 and the second opening OP2 in the second stack ST2 can be formed. The second opening OP2 can extend from the rear surface RS2 of the second stack ST2 toward the front surface FS2. The second opening OP2 can have a lower portion that is smaller than the width of the upper portion. The second opening OP2 can have a tapered shape. When a plurality of first openings OP1 are formed, a plurality of second openings OP2 can be formed by extending the first openings OP1 respectively. The second openings OP2 can extend to different depths and can expose the second material layer 41B respectively.

[0056] First, refer to Figure 4C , the second stack ST2 exposed through the first opening OP1 may be etched to form a preliminary second opening OP2A. The preliminary second opening OP2A may have substantially the same depth. Subsequently, referring to Figure 4D The preliminary second openings OP2A may extend to different depths, thereby forming second openings OP2 that expose the second material layer 41B.

[0057] Reference Figure 4E , contact plugs 45 may be formed in the first opening OP1 and the second opening OP2. After forming insulating spacers 44 on the inner walls of the first opening OP1 and the second opening OP2, contact plugs 45 may be formed. Contact plugs 45 may include a first portion 45A formed in the second opening OP2 and a second portion 45B formed in the first opening OP1. The first portion 45A may have a tapered shape, and the second portion 45B may have an inverted tapered shape.

[0058] For reference, before forming the contact plug 45, the first material layer 41A and the second material layer 41B can be replaced with a third material layer 41C. The third material layer 4C may include a conductive material. Thus, the first stack ST1 and the second stack ST2 can be replaced with a gate structure GST. A gate structure GST including the third material layer 41C and the insulating layer 42 alternately stacked can be formed. In addition, contact plugs 45 connected to the third material layers 41C can be formed.

[0059] According to the above-described manufacturing method, the first opening OP1 can be formed by etching the first stack ST1 so as to extend from the front surface FS1 toward the rear surface RS1. Furthermore, the second opening OP2 can be formed by etching the second stack ST2 so as to extend from the rear surface RS2 toward the front surface FS2. Therefore, the etching process can be performed in different directions, and the first opening OP1 and the second opening OP2 having inverted tapered shapes can be formed. Since the contact hole CTH is formed by dividing the contact hole CTH having a large aspect ratio into the first opening OP1 and the second opening OP2, the etching depth can be reduced and the process cost can be reduced.

[0060] Figures 5A to 13A and Figures 5B to 13B is a simplified diagram illustrating a method of manufacturing a semiconductor device according to one embodiment of the present disclosure. Hereinafter, any description overlapping with the above description may be omitted.

[0061] Reference Figure 5A and Figure 5B , a stack ST may be formed on a substrate 50, and a sacrificial contact structure 53 may be formed in the stack ST. In one embodiment, a first stack ST1 may be formed by alternately stacking first material layers 51A and insulating layers 52, and a first sacrificial layer 53A may be formed in the first stack ST1. Subsequently, a second stack ST2 may be formed by alternately stacking second material layers 51B and insulating layers 52, and a second sacrificial layer 53B may be formed in the second stack ST2. The second sacrificial layer 53B may be connected to some of the first sacrificial layers 53A. Subsequently, a third stack ST3 may be formed by alternately stacking third material layers 51C and insulating layers 52.

[0062] Thus, a first opening OP1 extending through the first stack ST1 and / or a first opening OP1 extending through the first stack ST1 and the second stack ST2 may be formed. Furthermore, a sacrificial contact structure 53 may be formed in the first opening OP1. The sacrificial contact structure 53 may be located in the contact region CTR. The sacrificial contact structure 53 may have a tapered shape, or may have a structure in which the tapered shape is repeated at least once.

[0063] A sacrificial slit structure 54 may be formed in the stack ST. In an embodiment, a first stack ST1 may be formed, and a first sacrificial layer 54A may be formed in the first stack ST1. Subsequently, a second stack ST2 may be formed, and a second sacrificial layer 54B connected to the first sacrificial layer 54A may be formed in the second stack ST2. Subsequently, a third stack ST3 may be formed, and a third sacrificial layer 54C connected to the second sacrificial layer 54B may be formed in the third stack ST3.

[0064] Thus, the third opening OP3 extending through the stack ST and the sacrificial slit structure 54 in the third opening OP3 may be formed. The sacrificial slit structure 54 may be formed when the sacrificial contact structure 53 is formed. The sacrificial slit structure 54 may be located in the cell region CR and the contact region CTR. The sacrificial slit structure 54 may have a structure in which a tapered shape is repeated at least once.

[0065] A sacrificial channel structure 55 may be formed in the stack ST. In an embodiment, a first stack ST1 may be formed, and a first sacrificial layer 55A may be formed in the first stack ST1. Subsequently, a second stack ST2 may be formed, and a second sacrificial layer 55B connected to the first sacrificial layer 55A may be formed in the second stack ST2. Subsequently, a third stack ST3 may be formed, and a third sacrificial layer 55C connected to the second sacrificial layer 55B may be formed in the third stack ST3.

[0066] Thus, the channel hole CHH extending through the stack ST and the sacrificial channel structure 55 in the channel hole CHH may be formed. The sacrificial channel structure 55 may be formed when the sacrificial contact structure 53 is formed. The sacrificial channel structure 55 may have a structure in which a tapered shape is repeated at least once.

[0067] A sacrificial support structure 59 may be formed in the stack ST. The sacrificial support structure 59 may have a shape similar to that of the sacrificial channel structure 55. When the sacrificial channel structure 55 is formed, the sacrificial support structure 59 may also be formed. The sacrificial support structure 59 may have a structure in which a tapered shape is repeated at least once.

[0068] Reference Figure 6A and Figure 6B , the sacrificial channel structure 55 may be replaced with a channel structure CH. A channel hole CHH may be formed (reopened) by selectively removing the sacrificial channel structure 55, and a channel structure CH may be formed in the channel hole CHH. Each channel structure CH may include a channel layer 56, a memory layer 57, and an insulating core 58.

[0069] When forming the channel structure CH, a support member SP may also be formed. The support member SP may have a structure similar to that of the channel structure CH. In an embodiment, the support member SP may include a dummy channel layer 56D, a dummy memory layer 57D, and a dummy insulating core 58D.

[0070] Subsequently, although not shown in the drawing, an interconnection structure connected to the channel structure CH, etc. may be formed. In an embodiment, a bit line connected to the channel structure CH may be formed.

[0071] Reference Figure 7A and Figure 7BThe first wafer WF1 including the stack ST and the sacrificial contact structure 53 and the second wafer WF2 including the peripheral circuit may be bonded. The first wafer WF1 and the second wafer WF2 may be electrically connected through the bonding structure BS.

[0072] Subsequently, the substrate 50 may be removed to expose the rear surface RS1 of the first stack ST1. The sacrificial contact structure 53, the sacrificial slit structure 54, and the channel structure CH may be exposed through the rear surface RS1. Subsequently, the memory layer 57 may be etched to expose the channel layer 56. Subsequently, impurities may be doped into the exposed channel layer 56.

[0073] Reference Figure 8A and Figure 8B , a source structure 61 may be formed on the rear surface RS1 of the first stack ST1. The source structure 61 may include a conductive material such as polysilicon. Subsequently, an opening OP extending through the source structure 61 may be formed. The opening OP may have a tapered shape. The opening OP may expose the sacrificial contact structure 53 or may expose the rear surface RS1 of the first stack ST1. The opening OP exposing the rear surface RS1 may have a greater depth than the opening OP exposing the sacrificial contact structure 53.

[0074] Reference Figure 9A and Figure 9B , the sacrificial contact structure 53 can be removed through the opening OP. Thus, the first opening OP1 can be formed (reopened). The reopened first opening OP1 can have an inverted tapered shape. The back surface RS2 of the second stack ST2 or the back surface RS3 of the third stack ST3 can be exposed through the first opening OP1.

[0075] Subsequently, a second opening OP2 may be formed. The second opening OP2 may have a tapered shape. In one embodiment, after forming preliminary second openings having substantially the same depth, the preliminary second openings may be extended to different depths to form second openings OP2 that expose the first to third material layers 51A to 51C, respectively.

[0076] The first stack ST1 may be etched through the opening OP to form a second opening OP2 extending into the first stack ST1. Thus, the opening OP may extend into the first stack ST1. A first contact hole CTH1 including the opening OP and the second opening OP2 and exposing the first material layer 51A may be formed. The first contact holes CTH1 may have different depths to respectively expose the first material layers 51A. The first contact holes CTH1 may have a structure in which a tapered shape is repeated at least once.

[0077] The second stack ST2 may be etched through the opening OP and the first opening OP1 to form a second opening OP2 extending into the second stack ST2. Thus, the first opening OP1 may extend into the second stack ST2. A second contact hole CTH2 may be formed that includes the opening OP, the first opening OP1, and the second opening OP2 and exposes the second material layer 51B. The second contact holes CTH2 may have different depths to expose the second material layers 51B, respectively. The second contact holes CTH2 may have a structure in which a tapered shape and an inverted tapered shape are combined.

[0078] The third stack ST3 may be etched through the opening OP and the first opening OP1 to form a second opening OP2 extending into the third stack ST3. Thus, the first opening OP1 may extend into the third stack ST3. A third contact hole CTH3 may be formed that includes the opening OP, the first opening OP1, and the second opening OP2 and exposes the third material layer 51C. The third contact holes CTH3 may have different depths to expose the third material layers 51C, respectively. The third contact holes CTH3 may have a structure in which a tapered shape and an inverted tapered shape are combined.

[0079] Reference Figure 10A and Figure 10B , an insulating liner 62 and a sacrificial layer 63 may be formed in the first to third contact holes CTH1 to CTH3. The insulating liner 62 may be formed along the inner surface of the first to third contact holes CTH1 to CTH3, and the sacrificial layer 63 may be formed to fill the first to third contact holes CTH1 to CTH3. Subsequently, the sacrificial layer 63 and the insulating liner 62 may be planarized until the source structure 61 is exposed. For example, the sacrificial layer 63 may include a material having an etching selectivity relative to the insulating liner 62. In one embodiment, the sacrificial layer 63 may include tungsten, and the insulating liner 62 may include an oxide.

[0080] Reference Figure 11A and Figure 11B , the source structure 61 may be etched to expose the sacrificial slit structure 54. Subsequently, the sacrificial slit structure 54 may be removed through the rear surface RS1 of the first stack ST1 to form (reopen) the third opening OP3. Subsequently, the third opening OP3 may be enlarged to form a slit SL. The first material layer 51A to the third material layer 51C may be etched through the third opening OP3, and the insulating layer 52 may be etched to enlarge the third opening OP3. Thus, the third openings OP3 may be connected to each other, and a slit SL having irregularities on the sidewalls may be formed.

[0081] Reference Figure 12A and Figure 12B, the first to third material layers 51A to 51C may be replaced with a fourth material layer 51D through the slit SL. In an embodiment, the first to third material layers 51A to 51C may be removed through the slit SL, and then the fourth material layer 51D may be formed. The fourth material layer 51D may form a gate line. In an embodiment, the fourth material layer 51D may include a conductive material and may include a metal such as tungsten (W) or molybdenum (Mo). Thus, a gate structure GST including the fourth material layer 51D and the insulating layer 52 alternately stacked may be formed.

[0082] Subsequently, a slit structure SLS may be formed in the slit SL. In one embodiment, the slit structure SLS may be a gap-filling layer including an insulating material, a semiconductor material, or the like.

[0083] Reference Figure 13A and Figure 13B , you can remove Figure 12A and Figure 12B The sacrificial layer 63 is shown. Thus, the insulating pad 62 ( Figure 12A and Figure 12B As shown), the first to third contact holes CTH1 to CTH3 may be reopened, and then the insulating liner 62 may be etched to form insulating spacers 62A on the inner walls of the first to third contact holes CTH1 to CTH3. Thus, the fourth material layer 51D may be exposed on the lower surfaces of the first to third contact holes CTH1 to CTH3. Figure 13A and Figure 13B As shown, contact plugs 65 may be formed in the first to third contact holes CTH1 to CTH3. The contact plugs 65 may include a conductive layer including a conductive material such as tungsten.

[0084] According to the above manufacturing method, when forming the first to third contact holes CTH1 to CTH3, a portion of each contact hole can be formed before performing the wafer bonding process, and the remaining portion of each contact hole can be formed after performing the wafer bonding process. Therefore, the process burden of forming contact holes with a large aspect ratio can be reduced. In addition, a contact plug 65 having a structure in which a tapered shape and an inverted tapered shape are combined can be formed.

[0085] The structures and manufacturing methods according to the above-described embodiments can be applied to semiconductor devices of various structures. Figure 14 and 15 A schematic configuration of a semiconductor device to which the above-described embodiments can be applied is illustrated.

[0086] Figure 14 is a structural diagram of a semiconductor device according to one embodiment of the present disclosure.

[0087] Reference Figure 14 , the semiconductor device may include a substrate SUB, a peripheral circuit PC, and a memory cell array CA. For example, the peripheral circuit PC and the memory cell array CA may be formed on the same substrate.

[0088] The substrate SUB may include a semiconductor material. In one embodiment, the semiconductor material may include at least one of a Group IV semiconductor, a Group III-V compound semiconductor, and a Group II-VI compound semiconductor. For example, a Group IV semiconductor may include single crystal silicon (Si), polycrystalline silicon, germanium (Ge), or silicon germanium (SiGe). A Group III-V compound semiconductor may include GaAs, GaN, GaP, GaAsP, GaInAsP, AlAs, AlGa, InP, InSb, or InGaAs. A Group II-VI compound semiconductor may include ZnS, ZnO, or CdS.

[0089] The substrate SUB may include a dielectric layer. The substrate SUB may be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or a glass substrate. The substrate SUB may include an organic material. In one embodiment, the substrate SUB may include graphene.

[0090] In one embodiment, the substrate SUB may be a bulk wafer. In another embodiment, the substrate SUB may include an epitaxial layer grown on, for example, a bulk wafer substrate using a selective epitaxial growth (SEG) method. For example, the substrate SUB may include an epitaxial layer of GaAs on a bulk wafer substrate of GaAs. The substrate SUB may be a layer formed using a metal induced lateral crystallization (MILC) method and may locally include metal. The substrate SUB may have a single crystal, a polycrystalline, or an amorphous state. The substrate SUB may include impurities of group II, group III, group IV, group V, or group VI. In one embodiment, the substrate SUB may include an n-well region doped with n-type impurities and / or a p-well region doped with p-type impurities.

[0091] The peripheral circuit PC may be located between the substrate SUB and the memory cell array CA. The peripheral circuit PC may include a row decoder, a column decoder, a page buffer, a logic circuit, a control circuit, a sense amplifier, an input / output circuit, etc. In one embodiment, the peripheral circuit PC may include NMOS transistors, PMOS transistors, resistors, capacitors, etc. The peripheral circuit PC may also include an interconnect structure. The interconnect structure may serve as a path for transmitting an operating voltage and may include contact plugs, wires, etc.

[0092] The memory cell array CA may include memory cells. In one embodiment, the memory cell array CA may include memory strings connected between source lines and bit lines, each memory string may include stacked memory cells. In one embodiment, the memory cell array CA may include memory cells connected between word lines and bit lines. The memory cell array CA may further include an interconnect structure.

[0093] Figure 15 is a structural diagram of a semiconductor device according to one embodiment of the present disclosure.

[0094] Reference Figure 15 The semiconductor device may include a substrate SUB, a peripheral circuit PC, a bonding structure BS, and a memory cell array CA. For example, the peripheral circuit PC and the memory cell array CA may be formed on separate substrates and then bonded together. The semiconductor device may further include a supporting base SP_B.

[0095] The substrate SUB can be used as a support member in the process of forming the peripheral circuit PC. The supporting base SP_B can be used as a support member in the process of forming the memory cell array CA. In one embodiment, after manufacturing each of a first wafer including the memory cell array CA and a second wafer including the peripheral circuit PC, the first wafer and the second wafer can be electrically connected via a bonding structure BS. After bonding, at least a portion of the supporting base SP_B of the first wafer can be removed. The supporting base SP_B can be completely removed or can be partially retained on the memory cell array CA.

[0096] The support substrate SP_B may be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or the like. The support substrate SP_B may be a bulk wafer, an epitaxial layer grown using a selective epitaxial growth (SEG) method, or a layer formed using a metal-induced lateral crystallization (MILC) method. The support substrate SP_B may be in a single crystal, polycrystalline, or amorphous state. The support substrate SP_B may include impurities of Group II, Group III, Group IV, Group V, or Group VI.

[0097] The bonding structure BS may include any suitable material and / or structure for connecting the memory cell array CA and the peripheral circuit PC. In one embodiment, the memory cell array CA and the peripheral circuit PC may be bonded using a wafer-on-wafer bonding method, a chip-on-wafer bonding method, a chip-on-chip bonding method, or the like. The bonding structure BS may include a bonding pad, a bonding layer, a bonding interface, or the like. The bonding pad may include a metal and / or alloy such as copper or aluminum. The bonding interface may include a non-metal-non-metal interface, a metal-metal interface, or the like. The memory cell array CA and the peripheral circuit PC may be electrically connected via the bonding structure BS.

[0098] For reference, the interconnect structures included in the memory cell array CA and / or the peripheral circuit PC can be directly connected without a bonding pad. In one embodiment, the bonding layer included in the memory cell array CA and the bonding layer included in the peripheral circuit PC can be bonded to form a bonding interface, and the interconnect structures included in the memory cell array CA and the interconnect structures included in the peripheral circuit PC can be directly connected. Thus, contact plugs, lines, etc. formed on different wafers can be electrically connected without separate bonding pads.

[0099] Other structures can be referred to before Figure 14 The structures described are the same or similar.

[0100] The semiconductor device may have a combination of the above reference Figure 14 and Figure 15 The structure of the embodiment described above may have a partially modified structure. Figure 14 and Figure 15 In the described embodiment, the positions of the memory cell array CA and the peripheral circuit PC may be changed. At least one memory cell array CA and / or at least one peripheral circuit PC may be additionally bonded to the reference Figure 14 In one embodiment, a portion of the peripheral circuit PC may be located in the memory cell array CA.

[0101] Although the embodiments of the technical concepts of the present disclosure have been described with reference to the accompanying drawings, this is only for describing the embodiments of the concepts of the present disclosure, and the embodiments of the present disclosure are not limited to the above-described embodiments. Within the scope of the present disclosure, those skilled in the art to which the present disclosure belongs may envision various forms of replacement, modification, change, and combination of the embodiments. In addition, these embodiments may be combined to form additional embodiments.

[0102] CROSS-REFERENCE TO RELATED APPLICATIONS

[0103] This application claims priority from Korean Patent Application No. 10-2024-0019942, filed on February 8, 2024, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor device, comprising: a gate structure comprising a plurality of gate lines; a first contact plug extending through the gate structure, the first contact plug being electrically connected to a first gate line among the gate lines and including a first portion having a tapered shape and a second portion having an inverted tapered shape; as well as A second contact plug extends through the gate structure, is electrically connected to a second gate line among the gate lines, and has a tapered shape.

2. The semiconductor device according to claim 1, wherein The first contact plug includes a connection surface where the first portion and the second portion are connected, wherein widths of the first portion and the second portion decrease as distances from the connection surface increase.

3. The semiconductor device according to claim 1, wherein The upper surface of the first portion and the lower surface of the second portion are connected.

4. The semiconductor device according to claim 1, wherein The inverted tapered shape is repeated in the second portion, and the second portion includes a step on the side wall.

5. The semiconductor device according to claim 1 , further comprising: A source structure is provided on the gate structure. The semiconductor device according to claim 5 , wherein: The first contact plug includes a third portion extending through the source structure and having a tapered shape.

7. The semiconductor device according to claim 5, wherein The second portion protrudes into the source structure.

8. The semiconductor device according to claim 5, further comprising: A channel structure extends through the gate structure into the source structure and has an inverted tapered shape.

9. The semiconductor device according to claim 5, further comprising: A slit structure includes a first portion extending through the gate structure and having an inverted tapered shape and a second portion extending through the source structure and having a tapered shape.

10. The semiconductor device according to claim 1, wherein The first contact plug has a height greater than that of the second contact plug.

11. The semiconductor device according to claim 1 , further comprising: a first insulating spacer surrounding a sidewall of the first contact plug; as well as A second insulating spacer surrounds a sidewall of the second contact plug.

12. A semiconductor device comprising: a gate structure comprising stacked gate lines; a source structure, the source structure being disposed on the gate structure; as well as a first contact plug extending through the gate structure and the source structure, the first contact plug being electrically connected to a first gate line among the gate lines; Wherein, the first contact plug comprises: a first portion extending through the gate structure and having a tapered shape; a second portion extending through the gate structure and having an inverted tapered shape; and A third portion extends through the source structure and has a tapered shape.

13. The semiconductor device according to claim 12, wherein The second portion is connected between the first portion and the third portion.

14. The semiconductor device according to claim 12, wherein The inverted tapered shape is repeated in the second portion, and the second portion includes a step on the sidewall.

15. The semiconductor device according to claim 12, further comprising: A second contact plug extends through the source structure and the gate structure, is electrically connected to a second gate line among the gate lines, and has a repeated tapered shape.

16. The semiconductor device according to claim 12, further comprising: A channel structure extends through the gate structure into the source structure and has an inverted tapered shape.

17. The semiconductor device according to claim 12, further comprising: A slit structure includes a first portion extending through the gate structure and having an inverted tapered shape and a second portion extending through the source structure and having a tapered shape.

18. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a sacrificial contact structure extending from the front surface toward the back surface of the first stack; forming a second laminate on a front surface of the first laminate; forming a first opening by removing the sacrificial contact structure through a rear surface of the first stack; forming a second opening in the second stack by etching the second stack through the first opening; as well as Contact plugs are formed in the first opening and the second opening.

19. The method according to claim 18, wherein The first opening and the second opening have tapered shapes in opposite directions.

20. The method according to claim 18, further comprising the steps of: exposing the sacrificial contact structure through the rear surface of the first stack; forming a source structure on the rear surface of the first stack; as well as An opening is formed extending through the source structure and exposing the sacrificial contact structure.

21. The method according to claim 18, further comprising the steps of: forming a sacrificial channel structure in the first stack when forming the sacrificial contact structure; and The sacrificial channel structure is replaced with a channel structure.

22. The method according to claim 18, further comprising the steps of: When forming the sacrificial contact structure, forming a sacrificial slit structure in the first stack; forming a third opening by removing the sacrificial slit structure through the rear surface of the first stack; forming a slit by enlarging the third opening; as well as The first stack and the second stack are replaced with a gate structure through the slit.

23. The method according to claim 18, further comprising the steps of: A first wafer including the first stack, the sacrificial contact structure, and the second stack is bonded to a second wafer including peripheral circuitry.

24. The method according to claim 23, wherein After bonding the first wafer and the second wafer, the sacrificial contact structure is removed.

25. The method according to claim 23, further comprising the steps of: After bonding the first wafer and the second wafer, the first stack and the second stack are replaced with a gate structure.

26. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a first stack including alternately stacked first material layers and second material layers on a substrate; forming a sacrificial contact structure extending through the first stack into the substrate; forming a second stack including alternately stacked third material layers and fourth material layers on a front surface of the first stack; exposing a rear surface of the first stack by removing the substrate; forming a source structure on the rear surface of the first stack; forming an opening through the source structure and exposing the sacrificial contact structure; forming a first opening by removing the sacrificial contact structure through the opening; forming a second opening by etching the second stack through the opening and the first opening; as well as Contact plugs are formed in the opening, the first opening, and the second opening.

27. The method according to claim 26, wherein The opening and the second opening have a tapered shape that is inversely oriented with respect to the tapered shape of the first opening.

28. The method according to claim 26, further comprising the steps of: Before removing the substrate, a first wafer including the first stack, the sacrificial contact structure, and the second stack is bonded to a second wafer including peripheral circuits.

29. The method according to claim 26, further comprising the steps of: forming a sacrificial slit structure extending into the substrate through the second stack and the first stack; forming a third opening by removing the sacrificial slit structure through the rear surface of the first stack; forming a slit by enlarging the third opening; as well as The first material layer and the third material layer are replaced with a conductive layer through the slit.

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