Storage structure and manufacturing method thereof
By setting a graphene layer and a dielectric layer on the side wall of the phase change memory, the thermal crosstalk problem of the phase change memory is solved, and the rapid conduction of heat is achieved, the misreading of the phase change memory is reduced, and the reliability of the memory is improved.
Patent Information
- Application Number
- CN202510613827.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-13
- Publication Date
- 2025-08-08
AI Technical Summary
The existing phase change memory has thermal crosstalk problems, resulting in frequent misreading.
The graphene layer and a dielectric layer are arranged on the side wall of the phase change memory cell. The graphene layer does not come into contact with the word line and the bit line. The high thermal conductivity of the graphene layer allows heat to be quickly transmitted to the word line or bit line, avoiding heat accumulation and reducing interference from the phase change memory cell to adjacent cells.
It effectively reduces misreading caused by thermal crosstalk in phase change memory, improves thermal crosstalk in word line and bit line directions, and improves memory reliability.
Smart Images
Figure CN120456562A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductors, and in particular to a storage structure and a manufacturing method thereof. Background Art
[0002] Phase-change RAM (PCRAM)'s superior properties, such as fast read and write speeds and ultra-low power consumption, make it one of the most promising and promising candidates in the field of non-volatile memory (NVM). The phase-change material in PCRAM can crystallize and amorphize based on the heat generated by an electric current, resulting in two distinct states: an amorphous (disordered) state and a crystalline (ordered) state, corresponding to two distinct resistance states. Applying a write (set) or erase (reset) pulse can cause the phase-change material to switch between the crystalline and amorphous states, enabling the storage of logical "1" and "0."
[0003] However, current phase change memories have the problem of thermal crosstalk. Summary of the Invention
[0004] In view of this, the object of the present application is to provide a storage structure and a manufacturing method thereof, so as to reduce misreading caused by thermal crosstalk in a phase change memory.
[0005] The present application provides a storage structure, including:
[0006] A word line, a phase change memory cell and a bit line are stacked, wherein the phase change memory cell comprises a phase change material layer, and the word line and the bit line extend in directions intersecting with each other;
[0007] A graphene layer and a dielectric layer located between the graphene layer and the sidewall are provided on the sidewall of the phase change memory unit, and the graphene layer is not in contact with the word line and the bit line at the same time.
[0008] Optionally, the phase change memory unit includes a first electrode layer, a phase change material layer, a second electrode layer and a gating layer stacked in sequence;
[0009] The graphene layer and the dielectric layer are at least located on side walls of a first stack including the first electrode layer, the phase-change material layer, and the second electrode layer.
[0010] Optionally, the dielectric layer includes a first dielectric layer directly covering the sidewall of the first stack, and a second dielectric layer directly covering the first dielectric layer;
[0011] The graphene layer is provided between the first dielectric layer and the second dielectric layer; or,
[0012] The graphene is disposed in the first dielectric layer or the second dielectric layer.
[0013] Optionally, the dielectric layer and the graphene layer further extend to the sidewalls of the gating layer.
[0014] Optionally, the dielectric layer includes a third dielectric layer covering sidewalls of both the first stack and the gating layer, the third dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, and the graphene layer is sandwiched between the first sub-dielectric layer and the second sub-dielectric layer.
[0015] Optionally, the first sub-dielectric layer and the second sub-dielectric layer have the same thickness.
[0016] Optionally, the graphene layer has a thickness ranging from 5 to 10 angstroms, and the first sub-dielectric layer and the second sub-dielectric layer have a thickness ranging from 10 to 15 angstroms.
[0017] Optionally, the thermal conductivity of the graphene layer is greater than 100 W / (m·K).
[0018] The present application also provides a method for manufacturing a storage structure, including:
[0019] Etching the phase change memory unit layer to form sidewalls of the phase change memory unit;
[0020] A dielectric layer and a graphene layer are sequentially formed on the sidewalls of the phase change memory unit. Optionally, the graphene layer is deposited using a methane vapor source and a molten gallium catalyst, wherein the methane content in the methane vapor source is 5% and the deposition temperature is 50-100°C.
[0021] The present application provides a storage structure and a manufacturing method thereof. The storage structure includes a stacked word line, a phase change memory cell, and a bit line. The phase change memory cell includes a phase change material layer. The extension directions of the word line and the bit line intersect. The sidewalls of the phase change memory cell have a graphene layer and a dielectric layer located between the graphene layer and the sidewall. The graphene layer does not contact the word line and the bit line at the same time, and therefore does not affect the current direction of the phase change memory cell. The graphene layer has a high thermal conductivity, so that the heat used to cause the phase change material layer to produce a phase change can be quickly conducted to the word line or bit line through the graphene layer without accumulating inside the phase change memory cell, thereby reducing the interference of the phase change memory cell on the adjacent phase change memory cell. Therefore, it can improve the thermal crosstalk in the direction of the word line and the bit line, and reduce the misreading of the phase change memory due to thermal crosstalk. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0023] Figure 1 A schematic diagram of a thermal crosstalk principle provided by an embodiment of the present application is shown;
[0024] Figure 2 A schematic diagram of a storage structure provided in an embodiment of the present application;
[0025] Figure 3 A cross-sectional view of a phase change memory cell provided in an embodiment of the present application;
[0026] Figure 4 A schematic diagram of a thermal crosstalk process provided in an embodiment of the present application;
[0027] Figure 5 A schematic structural diagram of a phase change memory unit provided in an embodiment of the present application;
[0028] Figure 6 A schematic structural diagram of another phase change memory unit provided in an embodiment of the present application;
[0029] Figure 7 、 Figure 8 and Figure 9 A schematic diagram of the structure of a phase change memory unit provided in an embodiment of the present application;
[0030] Figure 10 A schematic diagram of a heat conduction effect provided in an embodiment of the present application;
[0031] Figure 11 A flowchart of a method for manufacturing a storage structure provided in an embodiment of the present application;
[0032] Figure 12 A schematic diagram of a method for forming a third dielectric layer provided in an embodiment of the present application;
[0033] Figure 13 A schematic diagram of another method for forming a third dielectric layer provided in an embodiment of the present application. DETAILED DESCRIPTION
[0034] In order to help those skilled in the art better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.
[0035] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.
[0036] This application is described in detail with reference to schematic diagrams. When describing the embodiments of this application, for ease of explanation, cross-sectional views of device structures may be partially enlarged and not to scale. Furthermore, these schematic diagrams are merely illustrative and should not limit the scope of protection of this application. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.
[0037] As described in the background, the phase-change material in phase-change memory can crystallize and amorphize based on the heat generated by current. However, current phase-change memories suffer from misreading issues. The inventors discovered that this is because, when a selected cell is operated, the protective layer on the sidewalls of the selected cell is insufficiently able to block the heat generated by the selected cell. This continuous heat can easily affect adjacent memory cells, causing them to experience thermal crosstalk (WD) and misreading.
[0038] refer to Figure 1 As shown, a schematic diagram of the thermal crosstalk principle provided by an embodiment of the present application is provided. The storage cell includes a phase change storage material and upper and lower electrodes on both sides of the phase change storage material. Generally speaking, since amorphization requires a higher temperature and a larger current, when the reset operation is performed on the selected cell on the left, the current in the selected cell is from bottom to top, so that the phase change storage material is in an amorphous state. If the state of the adjacent storage cell is the reset state (the phase change storage material is in an amorphous state), the continuous heat (heat) of the selected cell is likely to partially crystallize the phase change storage material in the adjacent cell. This part of the material is in a crystalline state, causing it to be affected by thermal crosstalk and misread. The adjacent cell can also be called a victim cell.
[0039] Based on the above technical problems, an embodiment of the present application provides a storage structure and a manufacturing method thereof, wherein the storage structure includes a word line, a phase change memory cell and a bit line arranged in a stacked manner, the phase change memory cell includes a phase change material layer, the extension directions of the word line and the bit line intersect, the side wall of the phase change memory cell has a graphene layer and a dielectric layer located between the graphene layer and the side wall, the graphene layer does not contact the word line and the bit line at the same time, and therefore does not affect the current direction of the phase change memory cell, the thermal conductivity of the graphene layer is high, so that the heat used to cause the phase change material layer to produce a phase change can be quickly conducted to the word line or bit line through the graphene layer without accumulating inside the phase change memory cell, thereby reducing the interference of the phase change memory cell to the adjacent phase change memory cell, thereby improving the thermal crosstalk in the direction of the word line and the bit line, and reducing the misreading of the phase change memory due to thermal crosstalk.
[0040] In order to better understand the technical solutions and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
[0041] See also Figure 2 , this figure is a structural schematic diagram of a storage structure provided in an embodiment of the present application, the storage structure includes a word line (WL) 30, a phase change memory unit 20 and a bit line (BL) 10 arranged in a stacked manner.
[0042] In an embodiment of the present application, a phase change memory (PCM) cell 20 is located between a word line 30 and a bit line 10 and includes a phase change material layer 22. Phase change material layer 22 has two phases, crystalline and amorphous, corresponding to two distinct resistance states, enabling the PCM cell 20 to have two storage states. The word line 30 and the bit line 10 extend in intersecting directions, for example, perpendicularly, and are used to input control signals or read signals to the PCM cell 20.
[0043] The phase-change memory cell 20 includes a first electrode layer 21, a phase-change material layer 22, a second electrode layer 23, and a gate layer 24, which are stacked in sequence. The first electrode layer 21 can be connected to one of the word line 30 and the bit line 10, and the gate layer 24 can be connected to the other of the word line 30 and the bit line 10, so that the phase-change memory cell 20 has a stacked structure of word line 30 - first electrode layer 21 - phase-change material layer 22 - second electrode layer 23 - gate layer 24 - bit line 10, or a stacked structure of bit line 10 - first electrode layer 21 - phase-change material layer 22 - second electrode layer 23 - gate layer 24 - word line 30.
[0044] The materials of the first electrode layer 21, the second electrode layer 23, the word line 30 and the bit line 10 are conductive materials, for example, they can be at least one of tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, etc. The materials of the first electrode layer 21, the second electrode layer 23, the word line 30 and the bit line 10 can be the same or different.
[0045] The material of the phase change material layer 22 may be a chalcogenide alloy, such as GST (Ge—Sb—Te), or other phase change materials.
[0046] The gate layer 24 is used for selective conduction. For example, before the voltage on either side reaches a threshold voltage, it is in a high-resistance state, closing the circuit. When the voltage exceeds a predetermined voltage, the material enters a low-resistance state, opening the circuit. This reduces malfunctions of the phase-change memory cell. The gate layer 24 can be made of an ovonic threshold switching (OTS) material, such as ZnTe, GeTe, NbO, or SiAsTe.
[0047] The extending direction of the word line 30 is recorded as the y direction, which can also be called the WL axis (WL axis), the extending direction of the bit line 10 is recorded as the x direction, which can also be called the BL axis (BL axis), the plane formed by the x direction and the y direction is recorded as the xOy plane, and the stacking direction of the phase change memory unit is recorded as the z direction, which is perpendicular to the xOy plane.
[0048] refer to Figure 2 As shown, phase-change memory cells can be arranged in an array. The same word line 30 can be connected to multiple phase-change memory cells, and the same bit line 10 can also be connected to multiple phase-change memory cells. Taking two phase-change memory cells connected to the same word line 30 as an example, the phase-change memory cell above the word line 30 is denoted as the top cell (TC), and the phase-change memory cell below the word line 30 is denoted as the bottom cell (BC). The word line 30 then serves as both the word line of the TC and the word line of the BC. From top to bottom, the arrangement direction of the various film layers in the TC and BC is consistent, that is, both include a first electrode layer 21 - a phase-change material layer 22 - a second electrode layer 23 - a gate layer 24. In this way, current can flow from the word line 30 through the TC and BC to the BL of the TC and the BL of the BC, respectively.
[0049] refer to Figure 3 The cross-sectional view of a phase change memory cell provided in an embodiment of the present application can be obtained by a transmission electron microscope (TEM), which is equivalent to Figure 2 As shown in the top view, the phase change memory cells can be arranged in an array, and there are isolation regions 200 between the phase change memory cells 20. The isolation regions 200 can be used to set a protective layer, an isolation layer, etc.
[0050] refer to Figure 4As shown, a schematic diagram of a thermal crosstalk process provided in an embodiment of the present application is provided. The heat of the phase-change memory cell 20 located in the middle can diffuse to the adjacent phase-change memory cells along the word line extension direction and the bit line extension direction, which can easily cause thermal crosstalk in the adjacent phase-change memory cells.
[0051] refer to Figure 5 FIG. 1 is a schematic diagram of a phase change memory cell structure provided by an embodiment of the present application, which is equivalent to Figure 2 The phase change memory cell includes a first electrode layer 21 , a phase change material layer 22 , a second electrode layer 23 , and a gate layer 24 .
[0052] refer to Figure 6 FIG. 2 is a schematic diagram of the structure of another phase-change memory cell provided in an embodiment of the present application. The phase-change memory cell may further include a first electrode layer 21 facing away from the second electrode layer 23, and at least one of a first conductor layer 26, a first bonding layer 25, and a connecting layer 27 stacked in sequence, so that the first electrode layer 21 can be connected to a word line or a bit line through these film layers, wherein the first conductor layer 26 can be in contact with the first electrode layer 21. The material of the first conductor layer 26 can be carbon, the material of the first bonding layer 25 can be WSiN, and the material of the connecting layer 27 can be a conductive material, such as W.
[0053] A second conductor layer 28 may be disposed between the second electrode layer 23 and the gate layer 24. The second conductor layer 28 may be made of carbon.
[0054] At least one of a third conductor layer 29 and a second adhesive layer 2A may be disposed on a side of the gate layer 24 facing away from the second electrode layer 23, so that the gate layer 24 can be connected to a word line or a bit line through these film layers, wherein the third conductor layer 29 may be in contact with the gate layer 24. The material of the third conductor layer 29 may be carbon, and the material of the second adhesive layer 2A may be WSiN.
[0055] refer to Figure 5 、 Figure 6As shown, the sidewalls of the phase-change memory cell 20 have a protective layer 40. The protective layer 40 can be a single-layer structure or a multi-layer structure formed by stacking multiple film layers. The first electrode layer 21, the phase-change material layer 22, and the second electrode layer 23 are referred to as the first stack. For example, the protective layer 40 may include a first dielectric layer (Liner 1) 41 directly covering the reservoir sidewalls of the first stack, and a second dielectric layer (Liner 2) 42 directly covering the first dielectric layer. The material of the first dielectric layer 41 may be silicon nitride, and the material of the second dielectric layer 42 may be silicon oxide. The protective layer may also include a third dielectric layer (Liner 3) covering the sidewalls of the first stack and the gate layer. The material of the third dielectric layer may be silicon nitride. The protective layer may also include a fourth dielectric layer (Liner 4) 44 covering the third dielectric layer 43. The material of the fourth dielectric layer may be a silicon oxide layer. The protective layer extends in the z-direction, and the sidewalls of the phase-change memory cell, i.e., the third dielectric layer 43 and the fourth dielectric layer 44, may have larger dimensions in the z-direction. However, the heat insulation capability of the protective layer 40 is insufficient.
[0056] In addition, when the phase change memory unit presents a rectangular structure in the xOy plane, the first dielectric layer 41 and the second dielectric layer 42 can cover the two sidewalls of the first stack, and the third dielectric layer 43 and the fourth dielectric layer 44 can cover the four sidewalls of the first stack and the gate layer 24.
[0057] In the examples of this application, reference Figure 7 、 Figure 8 and Figure 9 FIG. 4 is a schematic diagram of the structure of a phase-change memory cell according to an embodiment of the present invention. The sidewalls of the phase-change memory cell are provided with a graphene layer 45 and a dielectric layer located between the graphene layer 45 and the sidewalls. The graphene layer 45 and the dielectric layer extend in the z-direction. The graphene layer 45 does not contact both the wordline 30 and the bitline 10 at the same time, and therefore does not affect the current flow in the phase-change memory cell. The graphene layer 45 has a high thermal conductivity, allowing the heat used to cause the phase change of the phase-change material layer 22 to be quickly transferred through the graphene layer 45 to the wordline 30 or bitline 10 without accumulating within the phase-change memory cell. This reduces interference from the phase-change memory cell to adjacent phase-change memory cells, thereby improving thermal crosstalk in the direction of the wordline 30 and bitline 10 and reducing misreading caused by thermal crosstalk in the phase-change memory. Furthermore, the addition of the graphene layer 45 to the existing protective layer effectively improves thermal crosstalk with limited cost increases.
[0058] In the embodiment of the present application, the graphene layer 45 and the dielectric layer are at least located on the sidewalls of the first stack, that is, the graphene layer 45 and the dielectric layer can be located only on the sidewalls of the first stack, or can be located on the sidewalls of the first stack and extend outward, thereby conducting heat of the phase change material layer 22 outward to varying degrees.
[0059] Specifically, when the graphene layer 45 and the dielectric layer are located on the sidewalls of the first stack, the graphene layer 45 can be inserted between the first dielectric layer 41 and the second dielectric layer 42. The dielectric layer can include the first dielectric layer 41, or the graphene layer 45 is disposed within the first dielectric layer 41 or the second dielectric layer 42, so that the dielectric layer includes a portion of the first dielectric layer 41, or the first dielectric layer 41 and a portion of the second dielectric layer 42 are stacked in sequence. The first dielectric layer 41 and the second dielectric layer 42 are only located on the sidewalls of the first stack to protect the first stack. Figure 7 As shown, the graphene layer 45 is disposed within the second dielectric layer 42, dividing the second dielectric layer 42 into a third sub-dielectric layer 421 and a fourth sub-dielectric layer 422. The dielectric layer between the graphene layer 45 and the sidewalls may include the first dielectric layer 41 and the third sub-dielectric layer 421. The graphene layer 45 may not contact the gate layer 24 to avoid short circuits.
[0060] Specifically, the graphene layer 45 may also be located on the sidewalls of the gate layer 24, for example, within the third dielectric layer 43. The third dielectric layer 43 includes a first sub-dielectric layer 431 and a second sub-dielectric layer 432. The graphene layer 45 is sandwiched between the first sub-dielectric layer 431 and the second sub-dielectric layer 432. The dielectric layer may further include a first sub-dielectric layer 431 covering the sidewalls of the gate layer 24 to protect the first stack and the gate layer 24. The first sub-dielectric layer 431 isolates the graphene layer 45 from the gate layer 24 to prevent the graphene layer 45 from connecting the gate layer 24 to unnecessary conductor layers.
[0061] In this way, the sidewalls of the phase-change memory cell further include a second sub-dielectric layer 432 and a fourth dielectric layer 44 outside the graphene layer 45. The second sub-dielectric layer 432 and the fourth dielectric layer 44 cover the sidewalls of the first stack and the sidewalls of the gate layer 24, thereby protecting the first stack and the gate layer 24. In other words, the graphene layer 45 can be inserted into the middle of the third dielectric layer 43, so that the third dielectric layer 43 is divided into a first sub-dielectric layer 431 inside the graphene layer 45 and a second sub-dielectric layer 432 outside the graphene layer 45.
[0062] When the phase change memory unit presents a rectangular structure in the xOy plane, when the graphene layer 45 only covers the side walls of the first stack, it can cover the side walls of both sides of the first stack; when the graphene layer 45 covers the side walls of the first stack and the gating layer 24, it can cover the side walls of all four sides of the first stack and the gating layer 24.
[0063] In the embodiment of the present application, the thickness of the third dielectric layer 43 is 20-30 angstroms, and the thicknesses of the first dielectric layer, the second dielectric layer, and the fourth dielectric layer are each in the range of 20-30 angstroms. The thicknesses of the first sub-dielectric layer and the second sub-dielectric layer can be the same or different, and each is in the range of 10-15 angstroms. The thickness of the graphene layer 45 is in the range of 5-10 angstroms, for example, 6 angstroms.
[0064] In the embodiment of the present application, the graphene layer 45 can have a high thermal conductivity (TC), for example, a thermal conductivity greater than 100 W / (m·K). The thermal conductivity of the silicon nitride layer is typically 0.5. When the graphene layer 45 is located between the first sub-dielectric layer and the second sub-dielectric layer, the thermal conductivity of the graphene layer 45 inside the silicon nitride is greater than 100, while the thermal conductivity of the silicon nitride is 5. This promotes heat transfer along the graphene layer 45 channel to the high thermal conductivity word lines 30 and bit lines 10, reducing heat interference with adjacent memory cells and thereby simultaneously improving thermal crosstalk between the word lines 30 and bit lines 10.
[0065] refer to Figure 10 As shown, a schematic diagram of a thermal conductivity effect provided by an embodiment of the present application is shown, wherein the horizontal axis is the size (%cln1x), the vertical axis is the temperature, the blue line is the thermal distribution curve when no graphene layer is added (No graphene) (denoted as the BASIC curve), and the red line is the thermal distribution curve when a graphene layer is added (Add graphene) (denoted as the L3 addgraphene curve). Figure 10 Figure 10A shows the heat conduction in the bit line direction (BL distribution). Figure 10 10B in the figure is the heat conduction diagram in the word line direction (WL distribution). The position with the horizontal axis of 100 is the center of the memory cell, where the temperature is the highest. After adding the graphene layer, the heat generated by the memory cell is transferred along the graphene layer to the word line or bit line. The heat transfer direction includes the word line direction and the bit line direction. Figure 10 As can be seen in Figures 10A and 10B, the red lines are more convergent, indicating that heat transfer along the bit lines and word lines is reduced, which helps to improve thermal crosstalk.
[0066] Refer to Table 1 for a comparison of the radius of the thermal simulation distribution curve. Taking 500K as an example, Figure 10 Determine the heat distribution radius in .
[0067] Table 1. Comparison of simulated thermal distribution curve radius (500K)
[0068] radius WL 500K(nm) BL 500K(nm) No graphene layer added 42.2 39.6 Adding a graphene layer 39.4 36.7
[0069] As can be seen from Table 1, after the graphene layer is added to the sidewall, the heat distribution radius in the word line and bit line direction is reduced by 3nm (about 7%), indicating that there is a certain improvement in thermal crosstalk.
[0070] The present application provides a storage structure including a stacked word line, a phase change memory cell, and a bit line. The phase change memory cell includes a phase change material layer. The word line and the bit line extend in directions that intersect. The sidewalls of the phase change memory cell are provided with a graphene layer and a dielectric layer located between the graphene layer and the sidewalls. The graphene layer does not contact the word line and the bit line at the same time, and thus does not affect the current flow of the phase change memory cell. The graphene layer has a high thermal conductivity, so that the heat used to cause the phase change material layer to undergo a phase change can be quickly conducted to the word line or the bit line through the graphene layer without accumulating within the phase change memory cell, thereby reducing interference of the phase change memory cell with adjacent phase change memory cells. Therefore, thermal crosstalk in the direction of the word line and the bit line can be improved, and misreading of the phase change memory due to thermal crosstalk can be reduced.
[0071] Based on the storage structure provided in the above embodiment, the present application also provides a method for manufacturing the storage structure, referring to Figure 11 FIG. 1 is a flow chart of a method for manufacturing a storage structure provided in an embodiment of the present application. The method may include:
[0072] S101 , etching the phase change memory cell layer to form sidewalls of the phase change memory cell.
[0073] In an embodiment of the present application, a phase change memory (PCM) cell 20 is located between a word line 30 and a bit line 10 and includes a phase change material layer 22. Phase change material layer 22 has two phases, crystalline and amorphous, corresponding to two distinct resistance states, enabling the PCM cell 20 to have two storage states. The word line 30 and the bit line 10 extend in intersecting directions, for example, perpendicularly, and are used to input control signals or read signals to the PCM cell 20.
[0074] The phase-change memory cell 20 includes a first electrode layer 21, a phase-change material layer 22, a second electrode layer 23, and a gate layer 24, which are stacked in sequence. The first electrode layer 21 can be connected to one of the word line 30 and the bit line 10, and the gate layer 24 can be connected to the other of the word line 30 and the bit line 10, so that the phase-change memory cell 20 has a stacked structure of word line 30 - first electrode layer 21 - phase-change material layer 22 - second electrode layer 23 - gate layer 24 - bit line 10, or a stacked structure of bit line 10 - first electrode layer 21 - phase-change material layer 22 - second electrode layer 23 - gate layer 24 - word line 30.
[0075] The materials of the first electrode layer 21, the second electrode layer 23, the word line 30 and the bit line 10 are conductive materials, for example, they can be at least one of tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, etc. The materials of the first electrode layer 21, the second electrode layer 23, the word line 30 and the bit line 10 can be the same or different.
[0076] The material of the phase change material layer 22 may be a chalcogenide alloy, such as GST (Ge—Sb—Te), or other phase change materials.
[0077] The gate layer 24 is used for selective conduction. For example, before the voltage on either side reaches a threshold voltage, it is in a high-resistance state, closing the circuit. When the voltage exceeds a predetermined voltage, the material enters a low-resistance state, opening the circuit. This reduces malfunctions of the phase-change memory cell. The gate layer 24 can be made of an ovonic threshold switching (OTS) material, such as ZnTe, GeTe, NbO, or SiAsTe.
[0078] The extending direction of the word line 30 is recorded as the y direction, which can also be called the WL axis (WL axis), the extending direction of the bit line 10 is recorded as the x direction, which can also be called the BL axis (BL axis), the plane formed by the x direction and the y direction is recorded as the xOy plane, and the stacking direction of the phase change memory unit is recorded as the z direction, which is perpendicular to the xOy plane.
[0079] The phase-change memory cell may further include at least one of a first conductor layer 26, a first adhesive layer 25, and a connection layer 27 stacked sequentially on a side of the first electrode layer 21 facing away from the second electrode layer 23, so that the first electrode layer 21 can be connected to a word line or a bit line through these film layers, wherein the first conductor layer 26 can be in contact with the first electrode layer 21. The material of the first conductor layer 26 can be carbon, the material of the first adhesive layer 25 can be WSiN, and the material of the connection layer 27 can be a conductive material, such as W.
[0080] A second conductor layer 28 may be disposed between the second electrode layer 23 and the gate layer 24. The second conductor layer 28 may be made of carbon.
[0081] At least one of a third conductor layer 29 and a second adhesive layer 2A may be disposed on a side of the gate layer 24 facing away from the second electrode layer 23, so that the gate layer 24 can be connected to a word line or a bit line through these film layers, wherein the third conductor layer 29 may be in contact with the gate layer 24. The material of the third conductor layer 29 may be carbon, and the material of the second adhesive layer 2A may be WSiN.
[0082] In an embodiment of the present application, a phase-change memory cell layer can be obtained by sequentially stacking film layers corresponding to word lines, bit lines, and phase-change memory cells. The phase-change memory cell layer is then subjected to a first etching (cell etch) in a first direction and a second etching (cell etch) in a second direction to obtain independent phase-change memory cells. The phase-change memory cells have sidewalls. The first direction can be consistent with the extension direction of one of the word lines and the bit lines, and the second direction can be consistent with the extension direction of the other of the word lines and the bit lines.
[0083] S102 , forming a dielectric layer and a graphene layer in sequence on the sidewalls of the phase change memory unit.
[0084] The sidewalls of the phase-change memory cell 20 have a protective layer 40. This protective layer 40 can be a single-layer structure or a multi-layer structure composed of multiple stacked layers. The first electrode layer 21, phase-change material layer 22, and second electrode layer 23 are referred to as the first stack. For example, the protective layer 40 may include a first dielectric layer (Liner 1) 41 directly covering the reservoir sidewalls of the first stack, and a second dielectric layer (Liner 2) 42 directly covering the first dielectric layer. The first dielectric layer 41 may be made of silicon nitride, and the second dielectric layer 42 may be made of silicon oxide. The protective layer may also include a third dielectric layer (Liner 3) covering the sidewalls of the first stack and the gate layer. The third dielectric layer may be made of silicon nitride. The protective layer may also include a fourth dielectric layer (Liner 4) 44 covering the third dielectric layer 43. The fourth dielectric layer may be made of silicon oxide. The protective layer extends in the z-direction, and the third and fourth dielectric layers 43 and 44 may have larger dimensions in the z-direction, circumferentially around the sidewalls of the phase-change memory cell. However, this protective layer 40 does not provide sufficient heat isolation.
[0085] In addition, when the phase change memory unit presents a rectangular structure in the xOy plane, the first dielectric layer 41 and the second dielectric layer 42 can cover both sidewalls of the first stack, and the third dielectric layer and the fourth dielectric layer can cover the four sidewalls of the first stack and the gate layer 24.
[0086] In an embodiment of the present application, the sidewalls of the phase-change memory cell are provided with a graphene layer 45 and a dielectric layer located between the graphene layer 45 and the sidewalls. The graphene layer 45 and the dielectric layer extend in the z-direction. The graphene layer 45 does not contact both the word line 30 and the bit line 10 at the same time, and therefore does not affect the current flow in the phase-change memory cell. The graphene layer 45 has a high thermal conductivity, allowing the heat used to cause the phase change of the phase-change material layer 22 to be quickly transferred through the graphene layer 45 to the word line 30 or the bit line 10 without accumulating within the phase-change memory cell, thereby reducing interference from the phase-change memory cell to adjacent phase-change memory cells. This improves thermal crosstalk in the direction of the word line 30 and the bit line 10, and reduces misreading of the phase-change memory due to thermal crosstalk. Furthermore, the addition of the graphene layer 45 to the existing protective layer effectively improves thermal crosstalk with limited cost increases.
[0087] In the embodiment of the present application, the graphene layer 45 and the dielectric layer are at least located on the sidewalls of the first stack, that is, the graphene layer 45 and the dielectric layer can be located only on the sidewalls of the first stack, or can be located on the sidewalls of the first stack and extend outward, thereby conducting heat of the phase change material layer 22 outward to varying degrees.
[0088] Specifically, when the graphene layer 45 and the dielectric layer are located on the sidewalls of the first stack, the graphene layer 45 can be inserted between the first dielectric layer 41 and the second dielectric layer 42. The dielectric layer can include the first dielectric layer 41, or the graphene layer 45 is disposed within the first dielectric layer 41 or the second dielectric layer 42, so that the dielectric layer includes a portion of the first dielectric layer 41, or the first dielectric layer 41 and a portion of the second dielectric layer 42 are stacked in sequence. The first dielectric layer 41 and the second dielectric layer 42 are only located on the sidewalls of the first stack to protect the first stack. Figure 7 As shown, the graphene layer 45 is disposed within the second dielectric layer 42, dividing the second dielectric layer 42 into a third sub-dielectric layer 421 and a fourth sub-dielectric layer 422. The dielectric layer between the graphene layer 45 and the sidewalls may include the first dielectric layer 41 and the third sub-dielectric layer 421. The graphene layer 45 may not contact the gate layer 24 to avoid short circuits.
[0089] Specifically, the graphene layer 45 may also be located on the sidewalls of the gate layer 24, for example, within the third dielectric layer 43. The third dielectric layer 43 includes a first sub-dielectric layer 431 and a second sub-dielectric layer 432. The graphene layer 45 is sandwiched between the first sub-dielectric layer 431 and the second sub-dielectric layer 432. The dielectric layer may further include a first sub-dielectric layer 431 covering the sidewalls of the gate layer 24 to protect the first stack and the gate layer 24. The first sub-dielectric layer 431 isolates the graphene layer 45 from the gate layer 24 to prevent the graphene layer 45 from connecting the gate layer 24 to unnecessary conductor layers.
[0090] In this way, the sidewalls of the phase-change memory cell further include a second sub-dielectric layer 432 and a fourth dielectric layer 44 outside the graphene layer 45. The second sub-dielectric layer 432 and the fourth dielectric layer 44 cover the sidewalls of the first stack and the sidewalls of the gate layer 24, thereby protecting the first stack and the gate layer 24. In other words, the graphene layer 45 can be inserted into the middle of the third dielectric layer 43, so that the third dielectric layer 43 is divided into a first sub-dielectric layer 431 inside the graphene layer 45 and a second sub-dielectric layer 432 outside the graphene layer 45.
[0091] When the phase change memory unit presents a rectangular structure in the xOy plane, when the graphene layer 45 only covers the side walls of the first stack, it can cover the side walls of both sides of the first stack; when the graphene layer 45 covers the side walls of the first stack and the gating layer 24, it can cover the side walls of all four sides of the first stack and the gating layer 24.
[0092] In the embodiment of the present application, the first dielectric layer 41 and the second dielectric layer 42 can be formed after the first etching in the first direction, and they extend along the first direction; the third dielectric layer (Liner3) 43 and the fourth dielectric layer (Liner4) 44 can be formed after the second etching in the second direction, and their extension direction is the z direction and the circumference of the side wall of the phase change memory unit.
[0093] refer to Figure 12 As shown, it is a schematic diagram of a method for forming a third dielectric layer provided in an embodiment of the present application. On the side wall of the storage cell (Cell), the third dielectric layer can be formed by multiple deposition (Dep) cycles, for example, 12 deposition cycles (Dep 12cycle), and the deposition temperature can be, for example, 250°C.
[0094] refer to Figure 13 As shown, it is a schematic diagram of another method for forming a third dielectric layer provided in an embodiment of the present application. In the case where a graphene layer is provided in the third dielectric layer, on the sidewall of the storage unit (Cell), the portion of the third dielectric layer inside the graphene layer (i.e., the first sub-dielectric layer) can be obtained by multiple deposition cycles, for example, the first sub-dielectric layer is obtained by 6 deposition cycles (Dep 6cycle), and the deposition temperature can be, for example, 250°C; then, a graphene layer is formed by a deposition (Dep) process, and the thickness of the graphene layer is, for example, 6A; and then, the portion of the third dielectric layer outside the graphene layer (i.e., the second sub-dielectric layer) is obtained by multiple deposition cycles, for example, the second sub-dielectric layer is obtained by 6 deposition cycles (Dep 6cycle), and the deposition temperature can be, for example, 250°C.
[0095] The graphene layer can be deposited by a methane vapor source and a molten gallium catalyst, wherein the methane content in the methane vapor source is about 5%, and the deposition temperature can be 50-100°C.
[0096] In the embodiment of the present application, the combined thickness of the first and second sub-dielectric layers (i.e., the thickness of the third dielectric layer 43) is 20-30 angstroms, and the thicknesses of the first, second, and fourth dielectric layers are each 20-30 angstroms. The thicknesses of the first and second sub-dielectric layers can be the same or different, and each is 10-15 angstroms. The thickness of the graphene layer 45 is 5-10 angstroms, for example, 6 angstroms.
[0097] In the embodiment of the present application, the graphene layer 45 can have a high thermal conductivity (TC), for example, a thermal conductivity greater than 100 W / (m·K). The thermal conductivity of the silicon nitride layer is typically 0.5. When the graphene layer 45 is located between the first sub-dielectric layer and the second sub-dielectric layer, the thermal conductivity of the graphene layer 45 inside the silicon nitride is greater than 100, while the thermal conductivity of the silicon nitride is 5. This promotes heat transfer along the graphene layer 45 channel to the high thermal conductivity word lines 30 and bit lines 10, reducing heat interference with adjacent memory cells and thereby simultaneously improving thermal crosstalk between the word lines 30 and bit lines 10.
[0098] The present application provides a method for manufacturing a storage structure, comprising etching a phase-change memory cell layer to form sidewalls of the phase-change memory cell, and sequentially forming a dielectric layer and a graphene layer on the sidewalls of the phase-change memory cell. The graphene layer does not contact the word line and the bit line at the same time, and thus does not affect the current flow of the phase-change memory cell. The graphene layer has a high thermal conductivity, so that the heat used to cause the phase-change material layer to undergo a phase change can be quickly conducted to the word line or the bit line through the graphene layer without accumulating within the phase-change memory cell, thereby reducing interference of the phase-change memory cell with adjacent phase-change memory cells. Therefore, thermal crosstalk in the word line and bit line directions can be improved, and misreading of the phase-change memory due to thermal crosstalk can be reduced.
[0099] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between the various embodiments can be referred to in conjunction with each other. Regarding the methods disclosed in the embodiments, since they correspond to the structures disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the structural description.
[0100] The above is only a preferred embodiment of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above-disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of protection of the technical solution of the present application.
Claims
1. A storage structure, characterized in that: include: A word line, a phase change memory cell and a bit line are stacked, wherein the phase change memory cell comprises a phase change material layer, and the word line and the bit line extend in directions intersecting with each other; A graphene layer and a dielectric layer located between the graphene layer and the sidewall are provided on the sidewall of the phase change memory unit, and the graphene layer is not in contact with the word line and the bit line at the same time.
2. The storage structure according to claim 1, characterized in that: The phase-change memory cell comprises a first electrode layer, a phase-change material layer, a second electrode layer and a gating layer stacked in sequence; The graphene layer and the dielectric layer are at least located on side walls of a first stack including the first electrode layer, the phase-change material layer, and the second electrode layer.
3. The storage structure according to claim 2, characterized in that: The sidewalls of the phase change memory unit include a first dielectric layer directly covering the sidewalls of the first stack, and a second dielectric layer directly covering the first dielectric layer; The graphene layer is provided between the first dielectric layer and the second dielectric layer; or, The graphene layer is disposed in the first dielectric layer or in the second dielectric layer.
4. The storage structure according to claim 2 or 3, characterized in that: The dielectric layer and the graphene layer further extend to the sidewall of the gating layer.
5. The storage structure according to claim 4, characterized in that: The dielectric layer includes a third dielectric layer covering sidewalls of the first stack and the gating layer. The third dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer. The graphene layer is sandwiched between the first sub-dielectric layer and the second sub-dielectric layer.
6. The storage structure according to claim 5, characterized in that: The first sub-dielectric layer and the second sub-dielectric layer have the same thickness.
7. The storage structure according to claim 6, characterized in that: The thickness of the graphene layer is in the range of 5-10 angstroms, and the thickness of the first sub-dielectric layer and the second sub-dielectric layer is in the range of 10-15 angstroms.
8. The storage structure according to claim 1, characterized in that: The thermal conductivity of the graphene layer is greater than 100 W / (m·K).
9. A method for manufacturing a storage structure, characterized in that: The method comprises: Etching the phase change memory unit layer to form sidewalls of the phase change memory unit; A dielectric layer and a graphene layer are sequentially formed on the sidewalls of the phase-change memory unit.
10. The storage structure according to claim 9, characterized in that: The graphene layer is deposited by a methane vapor source and a molten gallium catalyst, the methane content in the methane vapor source is 5%, and the deposition temperature is 50-100°C.