Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, the semiconductor structure comprises a semiconductor substrate, a plurality of fin parts are formed on the surface of the semiconductor substrate, each fin part comprises a plurality of stacked channel layers, and starting layers and stopping layers of the fin parts are channel layers; the in-fin groove is positioned in the fin part and extends into the starting layer; the in-fin channel layer is located at the bottom and the side wall of the in-fin groove; and the metal gates are located between the adjacent channel layers and the in-fin grooves are filled with the in-fin grooves. According to the semiconductor structure and the forming method thereof, the structure of a vertical nanosheet field effect transistor can be further improved, the channel width is increased, the device performance is improved, the process is easy to implement, and the semiconductor structure and the forming method thereof are completely compatible with a conventional vertical nanosheet field effect transistor process.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Due to better electrostatic gate controllability, gate-all-around field-effect transistors (GAAFETs) are promising candidate devices to replace FinFETs in CMOS technology. In order to improve the drive current of GAAFETs, vertically stacked nanosheets (NSFETs) are considered to be the preferred channel structure, which maximizes the effective channel width at the same footprint. Vertical nanosheet field-effect transistors (NSFETs) have wider channels than traditional FinFETs, providing excellent performance and drive current. Different ranges of different nanosheet (NS) widths can provide additional benefits in terms of design flexibility. For large-scale production, not only performance improvements but also the ease of process conversion from the previous process node must be considered.

[0003] Therefore, how to further improve the structure of vertical nanosheet field-effect transistors and increase the channel width under the condition that the process can be easily implemented and compatible is an issue that needs to be considered. Summary of the Invention

[0004] The present application provides a semiconductor structure and a method for forming the same, which can further improve the structure of a vertical nanosheet field-effect transistor, increase the channel width, and thus improve device performance. The process is easy to implement and is fully compatible with conventional vertical nanosheet field-effect transistor processes.

[0005] One aspect of the present application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein a plurality of fins are formed on the surface of the semiconductor substrate, the fins comprising a plurality of channel layers and sacrificial layers stacked in sequence, wherein the starting layer and the ending layer of the fins are both channel layers; etching the fins to form an intra-fin groove extending into the starting layer; forming an intra-fin channel layer at the bottom and sidewalls of the intra-fin groove and an intra-fin sacrificial layer filling the intra-fin groove; removing the sacrificial layer and the intra-fin sacrificial layer and forming a metal gate at the positions of the sacrificial layer and the intra-fin sacrificial layer.

[0006] In some embodiments of the present application, the method for forming the semiconductor structure also includes: before etching the fin to form an intra-fin groove extending into the starting layer, forming a covering layer covering the semiconductor substrate on the semiconductor substrate, the top surface of the covering layer being flush with the top surface of the fin; after forming an intra-fin channel layer at the bottom and sidewalls of the intra-fin groove and an intra-fin sacrificial layer filling the intra-fin groove, removing the covering layer.

[0007] In some embodiments of the present application, the thickness of the channel layer in the fin is not less than the thickness of the channel layer.

[0008] In some embodiments of the present application, the thickness of the sacrificial layer in the fin is not less than the thickness of the sacrificial layer.

[0009] In some embodiments of the present application, an isolation structure is further formed in the semiconductor substrate between adjacent fins.

[0010] In some embodiments of the present application, the thickness of the starting layer in the fin is greater than the thickness of other channel layers and the sacrificial layer.

[0011] In some embodiments of the present application, the method of forming the intra-fin channel layer at the bottom and sidewall of the intra-fin trench and the intra-fin sacrificial layer filling the intra-fin trench includes an epitaxial growth process.

[0012] Another aspect of the present application also provides a semiconductor structure, including: a semiconductor substrate, a plurality of fins formed on the surface of the semiconductor substrate, the fins including a plurality of stacked channel layers, wherein the starting layer and the ending layer of the fins are both channel layers; an intra-fin trench, located in the fin and extending into the starting layer; an intra-fin channel layer, located at the bottom and sidewalls of the intra-fin trench; and a metal gate, located between adjacent channel layers and in the intra-fin trench to fill the intra-fin trench.

[0013] In some embodiments of the present application, the thickness of the channel layer in the fin is not less than the thickness of the channel layer.

[0014] In some embodiments of the present application, the thickness of the metal gate located in the trench in the fin is not less than the thickness of the metal gate located between adjacent channel layers.

[0015] In some embodiments of the present application, an isolation structure is further formed in the semiconductor substrate between adjacent fins.

[0016] In some embodiments of the present application, the thickness of the starting layer in the fin is greater than the thickness of other channel layers.

[0017] The present application provides a semiconductor structure and a method for forming the same, which can further improve the structure of a vertical nanosheet field-effect transistor, increase the channel width, and thus improve device performance. The process is easy to implement and is fully compatible with conventional vertical nanosheet field-effect transistor processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The following figures describe in detail exemplary embodiments disclosed in this application. Like reference numerals denote similar structures throughout the several views of the drawings. Those skilled in the art will appreciate that these embodiments are non-limiting, exemplary embodiments, and that the drawings are provided for illustration and description purposes only and are not intended to limit the scope of this application. Other embodiments may also achieve the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0019] in:

[0020] Figures 1 to 8 Schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application. DETAILED DESCRIPTION

[0021] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content of this application. Various local modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but is intended to be of the widest scope consistent with the claims.

[0022] The technical solution of the present invention is described in detail below with reference to the embodiments and drawings.

[0023] Figures 1 to 8 The following is a structural diagram of each step in the method for forming a semiconductor structure according to an embodiment of the present application. The method for forming a semiconductor structure according to an embodiment of the present application is described in detail with reference to the accompanying drawings.

[0024] refer to Figure 1 and Figure 2 As shown, Figure 1 For top view, Figure 2 For the Figure 1 A semiconductor substrate 100 is provided, on which a plurality of fins 110 are formed. The fins 110 include a plurality of channel layers 111 and sacrificial layers 112 stacked in sequence. The starting layer and the ending layer of the fins 110 are both channel layers 111 .

[0025] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.

[0026] In some embodiments of the present application, a plurality of fins 110 may be formed on the semiconductor substrate 100. In this embodiment, for the purpose of simplicity and to facilitate showing more details of the fin 110, only one fin is used as an example.

[0027] refer to Figure 1 As shown, in some embodiments of the present application, the semiconductor substrate 100 includes an x-direction and a y-direction that are perpendicular to each other, wherein the plurality of fins 110 extend along the x-direction and are arranged along the y-direction.

[0028] Continue to refer Figure 1 and Figure 2 As shown, in some embodiments of the present application, an isolation structure 101 is further formed in the semiconductor substrate 100 between adjacent fins 110. The isolation structure 101 is used to isolate adjacent fins 110. The isolation structure 101 is made of an insulating material such as silicon oxide.

[0029] In some embodiments of the present application, the material of the sacrificial layer 112 is silicon germanium, and the material of the channel layer 111 is silicon.

[0030] In some embodiments of the present application, the number of the sacrificial layer 112 and the channel layer 111 is multiple layers. In this embodiment, only three layers of sacrificial layers 112 and four layers of channel layers 111 are used as an example.

[0031] refer to Figure 2 As shown, in some embodiments of the present application, the thickness of the starting layer (i.e., the bottommost channel layer 111) in the fin 110 is greater than the thickness of the other channel layers 111 and the sacrificial layer 112. Since the subsequent etching to form the trench in the fin needs to stop in the starting layer, the thickness of the starting layer needs to be slightly thicker to avoid process errors or precision problems that cause the trench in the fin to penetrate the starting layer or fail to reach the starting layer.

[0032] refer to Figure 3 As shown, a capping layer 120 is formed on the semiconductor substrate 100 to cover the semiconductor substrate 100. The top surface of the capping layer 120 is flush with the top surface of the fin 110. The capping layer 120 is used to protect the surface of the semiconductor substrate 100 (e.g., the isolation structure 101) from damage or contamination during the subsequent etching of the fin 110 and filling of the trench in the fin.

[0033] In some embodiments of the present application, the material of the cover layer 120 is SOC (spin on carbon).

[0034] refer to Figure 4As shown, the fin 110 is etched to form an intra-fin trench 130 extending into the starting layer. The key point in the etching process is to stop the etching in the starting layer and not to penetrate the starting layer or stop above the starting layer.

[0035] refer to Figure 5 As shown, an intra-fin channel layer 140 and an intra-fin sacrificial layer 150 filling the intra-fin trench 130 are formed at the bottom and sidewall of the intra-fin trench 130 .

[0036] In some embodiments of the present application, the method of forming the intra-fin channel layer 140 at the bottom and sidewall of the intra-fin trench 130 and the intra-fin sacrificial layer 150 filling the intra-fin trench 130 includes an epitaxial growth process.

[0037] In some embodiments of the present application, the material of the channel layer 140 in the fin is silicon, and the material of the sacrificial layer 150 in the fin is silicon germanium.

[0038] In some embodiments of the present application, the thickness of the intra-fin channel layer 140 is not less than the thickness of the channel layer 111 .

[0039] In some embodiments of the present application, the thickness of the in-fin sacrificial layer 150 is not less than the thickness of the sacrificial layer 112 .

[0040] refer to Figure 6 As shown, the cover layer 120 is removed.

[0041] In a conventional GAAFET, the fin 110 is as shown in FIG. Figure 2 The sacrificial layer 112 in the fin 110 is subsequently replaced by a gate layer, and the gate layer is Figure 2 The channel layer 111 is surrounded by the upper and lower sides and the left and right sides to realize the gate full surrounding structure. Figure 6 As shown, in the technical solution of the present application, the fin 110 in the conventional process is improved, and the channel layer 111 and the channel layer 140 in the fin form a sawtooth structure. After the sacrificial layer 112 and the sacrificial layer 150 in the fin are subsequently replaced with the gate layer, the contact area between the gate layer and the channel layer 111 (which serves as the channel) and the channel layer 140 in the fin is increased. In other words, the technical solution of the present application improves the fin structure of the GAAFET and increases the channel width, thereby improving device performance.

[0042] In the technical solution of the present application, the processing improvement is mainly carried out on the fin 110, and it only involves the etching of the groove in the fin and the growth of the channel layer and the sacrificial layer in the fin. The process is simple and easy to implement, and there are not many changes to the existing GAAFET process. It is fully compatible with the conventional GAAFET process.

[0043] The technical solution of this application mainly improves the processing of the fin 110 and changes the structure of the fin 110, but the fin 110 as a whole is still a rectangular parallelepiped, which has no impact on the subsequent process. In other words, the subsequent process is still compatible with the conventional process and is basically the same, without any impact.

[0044] Specifically, for example, after removing the cover layer 120, a dummy gate structure covering the surface of the fin 110 is formed as in the conventional process; Figure 1 The two ends of the fin 110 are etched in the x-direction to form source and drain trenches that expose the semiconductor substrate 100; then the sacrificial layer is etched in the x-direction and the inner spacer is formed; the source and drain layers are grown using the semiconductor substrate at the bottom of the source and drain trenches as the matrix; an interlayer dielectric layer is formed to cover the source and drain layers and the semiconductor substrate, etc. Since these steps are basically the same as the corresponding steps of conventional GAAFET, they will not be described in detail here. However, those skilled in the art should be able to fully understand the corresponding steps of this application in combination with the corresponding processes of conventional GAAFET.

[0045] refer to Figure 7 As shown, the sacrificial layer 112 and the sacrificial layer 150 in the fin (including the dummy gate structure not shown) are removed. Figure 8 As shown, a metal gate 160 is formed at the positions of the sacrificial layer 112 and the sacrificial layer 150 in the fin (including a dummy gate structure not shown).

[0046] In some embodiments of the present application, the metal gate 160 is made of copper, tungsten, aluminum, or the like.

[0047] In the technical solution of the present application, the fin 110 is improved to form a channel structure with a serrated structure (including a channel layer 111 and an intra-fin channel layer 140), which increases the channel width, increases the device driving current, increases the effective physical area of the device, and thus improves the device performance.

[0048] The present application provides a method for forming a semiconductor structure, which can further improve the structure of a vertical nanosheet field-effect transistor, increase the channel width, and thus improve device performance. The process is easy to implement and is fully compatible with conventional vertical nanosheet field-effect transistor processes.

[0049] The embodiment of the present application further provides a semiconductor structure, referring to Figure 8As shown, it includes: a semiconductor substrate 100, a plurality of fins 110 are formed on the surface of the semiconductor substrate 100, and the fins 110 include a plurality of stacked channel layers 111, wherein the starting layer and the ending layer of the fins 110 are both channel layers; an intra-fin groove, located in the fin 110 and extending into the starting layer; an intra-fin channel layer 140, located at the bottom and sidewall of the intra-fin groove; a metal gate 160, located between adjacent channel layers 111 and in the intra-fin groove to fill the intra-fin groove.

[0050] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.

[0051] In some embodiments of the present application, a plurality of fins 110 may be formed on the semiconductor substrate 100. In this embodiment, for the purpose of simplicity and to facilitate showing more details of the fin 110, only one fin is used as an example.

[0052] refer to Figure 1 As shown, in some embodiments of the present application, the semiconductor substrate 100 includes an x-direction and a y-direction that are perpendicular to each other, wherein the plurality of fins 110 extend along the x-direction and are arranged along the y-direction.

[0053] Continue to refer Figure 8 As shown, in some embodiments of the present application, an isolation structure 101 is further formed in the semiconductor substrate 100 between adjacent fins 110. The isolation structure 101 is used to isolate adjacent fins 110. The isolation structure 101 is made of an insulating material such as silicon oxide.

[0054] In some embodiments of the present application, the material of the channel layer 111 is silicon.

[0055] In some embodiments of the present application, the number of the channel layers 111 is multiple layers. In this embodiment, only four channel layers 111 are used as an example.

[0056] refer to Figure 8 As shown, in some embodiments of the present application, the thickness of the starting layer (ie, the bottommost channel layer 111 ) in the fin 110 is greater than the thickness of other channel layers 111 .

[0057] In some embodiments of the present application, the thickness of the intra-fin channel layer 130 is not less than the thickness of the channel layer 111 .

[0058] In some embodiments of the present application, the material of the intra-fin channel layer 140 is silicon.

[0059] In some embodiments of the present application, the thickness of the metal gate located in the trench in the fin is not less than the thickness of the metal gate located between adjacent channel layers.

[0060] The technical solution of this application mainly improves and processes the fin 110, changing the structure of the fin 110, but the fin 110 as a whole is still a rectangular parallelepiped, and has no significant impact on other structures. In other words, other structures remain basically the same as the conventional structure and have no impact.

[0061] Specifically, for example, Figure 1 The metal gate sidewall in the x direction is formed with an inner spacer; Figure 1 The fin sidewalls in the x-direction are formed with source and drain layers; an interlayer dielectric layer is formed to cover the source and drain layers and the semiconductor substrate. Since these structures are essentially the same as those of conventional GAAFETs, they will not be described in detail in this application. However, those skilled in the art should be able to fully understand the corresponding structures of this application in conjunction with the corresponding structures of conventional GAAFETs.

[0062] In some embodiments of the present application, the metal gate 160 is made of copper, tungsten, aluminum, or the like.

[0063] In the technical solution of the present application, the fin 110 is improved to form a channel structure with a serrated structure (including a channel layer 111 and an intra-fin channel layer 140), which increases the channel width, increases the device driving current, increases the effective physical area of the device, and thus improves the device performance.

[0064] In a conventional GAAFET, the fin 110 is as shown in FIG. Figure 2 The sacrificial layer 112 in the fin 110 is subsequently replaced by a gate layer, and the gate layer is Figure 2 The channel layer 111 is surrounded by the upper and lower sides and the left and right sides to realize the gate full surrounding structure. Figure 8 As shown, in the technical solution of the present application, the fin 110 in the conventional process is improved, and the channel layer 111 and the intra-fin channel layer 140 form a sawtooth structure, which increases the contact area between the metal gate 160 and the channel layer 111 (which serves as the channel) and the intra-fin channel layer 140. In other words, the technical solution of the present application improves the fin structure of the GAAFET and increases the channel width, thereby improving device performance.

[0065] The present application provides a semiconductor structure and a method for forming the same, which can further improve the structure of a vertical nanosheet field-effect transistor, increase the channel width, and thus improve device performance. The process is easy to implement and is fully compatible with conventional vertical nanosheet field-effect transistor processes.

[0066] In summary, after reading the contents of this application, those skilled in the art will understand that the foregoing contents are presented by way of example only and are not intended to be limiting. Although not expressly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0067] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may also be present.

[0068] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In contrast, the term "directly" indicates that there are no intervening elements. It should also be understood that the terms "comprising," "including," "include," or "comprising," when used in this specification, indicate the presence of recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0069] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present application, the first element in some embodiments may be referred to as the second element in other embodiments. The same reference numerals or the same reference designators represent the same elements throughout the specification.

[0070] In addition, this specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: A semiconductor substrate is provided, wherein a plurality of fins are formed on a surface of the semiconductor substrate, wherein the fins include a plurality of channel layers and sacrificial layers stacked in sequence, wherein both the starting layer and the ending layer of the fins are channel layers; etching the fin to form an intra-fin trench extending into the starting layer; forming an intra-fin channel layer and an intra-fin sacrificial layer filling the intra-fin trench at the bottom and sidewall of the intra-fin trench; The sacrificial layer and the sacrificial layer in the fin are removed and a metal gate is formed at the positions of the sacrificial layer and the sacrificial layer in the fin.

2. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: Before etching the fin to form an intra-fin trench extending into the starting layer, forming a cover layer covering the semiconductor substrate on the semiconductor substrate, wherein a top surface of the cover layer is flush with a top surface of the fin; After forming an intra-fin channel layer at the bottom and sidewall of the intra-fin trench and an intra-fin sacrificial layer filling the intra-fin trench, the covering layer is removed.

3. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the channel layer in the fin is not less than the thickness of the channel layer.

4. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the sacrificial layer in the fin is not less than the thickness of the sacrificial layer.

5. The method for forming a semiconductor structure according to claim 1, wherein: An isolation structure is also formed in the semiconductor substrate between adjacent fins.

6. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the starting layer in the fin is greater than the thickness of other channel layers and the sacrificial layer.

7. The method for forming a semiconductor structure according to claim 1, wherein: The method of forming an intra-fin channel layer on the bottom and sidewall of the intra-fin trench and an intra-fin sacrificial layer filling the intra-fin trench includes an epitaxial growth process.

8. A semiconductor structure, characterized in that include: A semiconductor substrate having a plurality of fins formed on a surface thereof, wherein the fins include a plurality of stacked channel layers, wherein both the starting layer and the ending layer of the fins are channel layers; an intra-fin trench located in the fin portion and extending into the initiation layer; an intra-fin channel layer, located at the bottom and sidewalls of the intra-fin trench; The metal gate is located between adjacent channel layers and in the inner trench of the fin to fill the inner trench of the fin.

9. The semiconductor structure according to claim 8, wherein: The thickness of the channel layer in the fin is not less than the thickness of the channel layer.

10. The semiconductor structure according to claim 8, wherein The thickness of the metal gate located in the trench in the fin is not less than the thickness of the metal gate located between adjacent channel layers.

11. The semiconductor structure according to claim 8, wherein An isolation structure is also formed in the semiconductor substrate between adjacent fins.

12. The semiconductor structure according to claim 8, wherein The thickness of the starting layer in the fin is greater than the thickness of other channel layers.

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