Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which is internally provided with a drift region, and the doping type of the drift region is different from that of the substrate; forming a dielectric layer, wherein the dielectric layer covers a part of the drift region and a part of the substrate adjacent to the part of the drift region; a body region is formed in the substrate exposed out of one side of the dielectric layer, the body region is adjacent to the drift region, and the doping types of the body region and the drift region are different; forming a source region in the body region, wherein the doping type of the source region is different from that of the substrate; forming a drain region in the drift region exposed on the other side of the dielectric layer, wherein the doping type of the drain region is consistent with that of the drift region; a field plate is formed on the dielectric layer, the field plate is of a multi-stage step structure with the top face height gradually reduced in the first direction, the first direction is parallel to the surface of the drift region, and the first direction points to the source region from the drain region. By adopting the technical scheme, the breakdown voltage of the semiconductor structure can be improved, and the electrical performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] A voltage-controlled power device is an electronic device that achieves power control by controlling voltage. It is commonly used in AC / DC (Alternating Current / Direct Current) conversion, DC / DC (Direct Current / Direct Current) conversion, and voltage regulation in power supplies.

[0003] However, existing voltage-controlled power devices have poor electrical performance.

[0004] Therefore, how to provide a technical solution to improve the electrical performance of voltage-controlled power devices has become a technical problem that needs to be solved urgently. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, which can improve the electrical performance of the semiconductor structure.

[0006] To solve the above technical problems, the present disclosure provides a method for forming a semiconductor structure, the method comprising:

[0007] Providing a substrate, wherein the substrate has a drift region therein, wherein the doping type of the drift region is different from the doping type of the substrate;

[0008] forming a dielectric layer, wherein the dielectric layer covers a portion of the drift region and a portion of the substrate adjacent to the portion of the drift region;

[0009] forming a body region in the substrate exposed on one side of the dielectric layer, wherein the body region is adjacent to the drift region, and a doping type of the body region is different from a doping type of the drift region;

[0010] forming a source region in the body region, wherein the doping type of the source region is different from the doping type of the substrate;

[0011] forming a drain region in the drift region exposed on the other side of the dielectric layer, wherein the doping type of the drain region is consistent with the doping type of the drift region;

[0012] A field plate is formed on the dielectric layer. The field plate is a multi-step structure with a top surface height gradually decreasing along a first direction. The first direction is parallel to the surface of the drift region and points from the drain region to the source region.

[0013] Optionally, the dielectric layer is a multi-step structure with a top surface height gradually decreasing along the first direction, wherein the number of steps in the dielectric layer is greater than or equal to three.

[0014] Optionally, the dielectric layer includes a first dielectric layer and a second dielectric layer, and the step of forming the dielectric layer includes:

[0015] forming a first dielectric material layer and a second dielectric material layer on the substrate, wherein the second dielectric material layer covers the first dielectric material layer;

[0016] removing a portion of the first dielectric material layer and a portion of the second dielectric material layer to obtain the first dielectric layer and an initial second dielectric layer, wherein the first dielectric layer covers a portion of the drift region and a portion of the substrate adjacent to the portion of the drift region along a first direction, and the initial second dielectric layer covers the first dielectric layer;

[0017] A portion of the initial second dielectric layer is removed to obtain a second dielectric layer, wherein the second dielectric layer covers a portion of the drift region and exposes the first dielectric layer located above the drift region and an adjacent area of the substrate, and the top surface height of the multi-level stepped structure formed by the second dielectric layer and the first dielectric layer gradually decreases along the first direction.

[0018] Optionally, the second dielectric layer is a multi-step structure with a top surface height gradually decreasing along the first direction.

[0019] Optionally, a projection position of a corner position on the top surface of the field plate on the surface of the drift region does not overlap with a projection position of a corner position on the top surface of the dielectric layer on the surface of the drift region.

[0020] Optionally, there are multiple second dielectric layers, and the second dielectric layers are spaced apart along a second direction, wherein the second direction is parallel to the surface of the drift region and perpendicular to the first direction.

[0021] Optionally, before forming the field plate, the method further comprises the following steps:

[0022] forming a gate body on the first dielectric layer exposed by the second dielectric layer, wherein the gate body is located above a portion of the drift region and a portion of the substrate adjacent to the portion of the drift region;

[0023] forming a gate spacer on a sidewall of the gate body;

[0024] The first dielectric layer covered by the gate body is used as a gate dielectric layer, and the remaining first dielectric layer and the second dielectric layer except the gate dielectric layer are used as field dielectric layers.

[0025] Optionally, the steps of each second dielectric layer are consistent, and at least one of the distances between steps of the same step number in each second dielectric layer and the gate body is different in size from the other distances.

[0026] Optionally, there are multiple field plates, each field plate is distributed at intervals along the second direction, and one field plate corresponds to one second dielectric layer.

[0027] Optionally, the steps of the field plates are consistent, and at least one of the corresponding spacings between steps of the same step in each field plate and the gate body is different in size from the other spacings.

[0028] The present disclosure also provides a semiconductor structure, comprising:

[0029] a substrate having a drift region therein, wherein the drift region has a doping type different from that of the substrate;

[0030] a dielectric layer covering a portion of the drift region and a portion of the substrate adjacent to the portion of the drift region;

[0031] a body region, located on one side of the dielectric layer and adjacent to the drift region, wherein a doping type of the body region is different from a doping type of the drift region;

[0032] a source region located in the body region, wherein a doping type of the source region is different from a doping type of the substrate;

[0033] a drain region, located in the drift region exposed on the other side of the dielectric layer, wherein the doping type of the drain region is consistent with the doping type of the drift region;

[0034] A field plate covers the dielectric layer and is a multi-step structure with a top surface height gradually decreasing along a first direction, wherein the first direction is parallel to the surface of the drift region and points from the drain region to the source region.

[0035] Optionally, the dielectric layer is a multi-step structure with a top surface height gradually decreasing along the first direction, wherein the number of steps in the dielectric layer is greater than or equal to three.

[0036] Optionally, the dielectric layer includes:

[0037] a first dielectric layer covering a portion of the drift region and a portion of the substrate adjacent to the portion of the drift region along a first direction;

[0038] The second dielectric layer covers a portion of the drift region and exposes the first dielectric layer above the drift region and the adjacent region of the substrate. The top surface height of the multi-level stepped structure formed by the second dielectric layer and the first dielectric layer gradually decreases along the first direction.

[0039] Optionally, the second dielectric layer is a multi-step structure that gradually decreases along the first direction.

[0040] Optionally, a projection position of a corner position on the top surface of the field plate on the surface of the drift region does not overlap with a projection position of a corner position on the top surface of the dielectric layer on the surface of the drift region.

[0041] Optionally, there are multiple second dielectric layers, and the second dielectric layers are spaced apart along a second direction, wherein the second direction is parallel to the surface of the drift region and perpendicular to the first direction.

[0042] Optionally, the semiconductor structure further includes:

[0043] a gate body, located on the first dielectric layer exposed by the second dielectric layer, and located above a portion of the drift region and a portion of the substrate adjacent to the portion of the drift region;

[0044] A gate sidewall, located on a sidewall of the gate body;

[0045] The first dielectric layer covered by the gate body is used as a gate dielectric layer, and the remaining first dielectric layer and the second dielectric layer except the gate dielectric layer are used as field dielectric layers.

[0046] Optionally, the steps of each second dielectric layer are consistent, and at least one of the distances between steps of the same step number in each second dielectric layer and the gate body is different in size from the other distances.

[0047] Optionally, there are multiple field plates, each field plate is distributed at intervals along the second direction, and one field plate corresponds to one second dielectric layer.

[0048] Optionally, the steps of the field plates are consistent, and at least one of the distances between steps of the same step in each field plate and the gate body is different in size from the other distances.

[0049] Compared with the prior art, the technical solution of the embodiment of the present disclosure has the following advantages:

[0050] In an embodiment of the present disclosure, a dielectric layer is formed on a substrate, the dielectric layer covering a portion of a drift region within the substrate and a portion of the substrate adjacent to the drift region; a body region is formed within the substrate exposed on one side of the dielectric layer, the body region being adjacent to the drift region and having different doping types from the drift region; a source region is formed within the body region, the doping type of the source region being different from the doping type of the substrate; a drain region is formed within the drift region exposed on the other side of the dielectric layer, the doping type of the drain region being consistent with the doping type of the drift region; and a field plate is formed on the dielectric layer, the field plate being a multi-step structure with a top surface height gradually decreasing along a first direction, wherein the first direction is parallel to the surface of the drift region and points from the drain region to the source region. Using the above solution, the field plate is a multi-step structure with a top surface height gradually decreasing along the first direction, and the corner positions on the top surface of the field plate can introduce multiple electric field peaks distributed along the first direction on the substrate surface, thereby optimizing the electric field distribution along the first direction on the substrate surface, improving the breakdown voltage of the semiconductor structure, and thereby improving the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions of the embodiments of this specification, the following briefly introduces the drawings required for use in the embodiments of this specification or the description of the prior art. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0052] Figure 1 is a flow chart of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0053] Figures 2 to 5 is a schematic cross-sectional structural diagram corresponding to each step in a method for forming a semiconductor structure in an embodiment of the present disclosure;

[0054] Figure 6 is a schematic top view of a semiconductor structure according to an embodiment of the present disclosure;

[0055] Figure 7 It is a schematic top view of a semiconductor structure in an embodiment of the present disclosure.

[0056] Description of reference numerals:

[0057] Substrate 100, drift region 110, body region 120, source region 130, drain region 140, extraction region 150;

[0058] Dielectric layer 200 , first dielectric material layer 210 , first dielectric layer 211 , second dielectric material layer 220 , initial second dielectric layer 221 , second dielectric layer 222 .

[0059] Gate body 310, gate sidewall 320;

[0060] Field plate 400, bottom field plate unit 410, middle field plate unit 420, top field plate unit 430;

[0061] First direction F1, second direction F2. DETAILED DESCRIPTION

[0062] As described in the background art, the performance of existing voltage-controlled power devices is poor.

[0063] Taking a MOS diffused-double lateral, LDMOS device as an example, if the peak electric field in the LDMOS device exceeds the critical electric field, the device breaks down. The voltage at this time is called the breakdown voltage of the LDMOS device.

[0064] The breakdown voltage of existing LDMOS devices is low.

[0065] In order to solve the above technical problems, in an embodiment of the present disclosure, a dielectric layer is formed on the substrate, which covers a portion of the drift region in the substrate and a portion of the substrate adjacent to the portion of the drift region; a body region is formed in the substrate exposed on one side of the dielectric layer, the body region is adjacent to the drift region, and the body region and the drift region have different doping types; a source region is formed in the body region, and the doping type of the source region is different from the doping type of the substrate; a drain region is formed in the drift region exposed on the other side of the dielectric layer, and the doping type of the drain region is consistent with the doping type of the drift region; a field plate is formed on the dielectric layer, and the field plate is a multi-step structure with a top surface height gradually decreasing along a first direction, wherein the first direction is parallel to the surface of the drift region and points from the drain region to the source region.

[0066] By adopting the above scheme, the field plate has a multi-step structure with a top surface height gradually decreasing along the first direction. The corner position on the top surface of the field plate can introduce multiple electric field peaks distributed along the first direction on the substrate surface, thereby optimizing the electric field distribution on the substrate surface along the first direction, improving the breakdown voltage of the semiconductor structure, and thus improving the electrical performance of the semiconductor structure.

[0067] In order to make the above-mentioned objectives, features and beneficial effects of the present disclosure more obvious and easy to understand, the specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0068] Reference Figure 1 , Figure 1 A flow chart of a method for forming a semiconductor structure in an embodiment of the present disclosure is shown. The method for forming a semiconductor device may include steps S11 to S16:

[0069] Step S11: providing a substrate, wherein the substrate has a drift region, and the doping type of the drift region is different from the doping type of the substrate;

[0070] Step S12: forming a dielectric layer, where the dielectric layer covers a portion of the drift region and a portion of the substrate adjacent to the portion of the drift region;

[0071] Step S13: forming a body region in the substrate exposed on one side of the dielectric layer, wherein the body region is adjacent to the drift region, and the doping type of the body region is different from the doping type of the drift region;

[0072] Step S14: forming a source region in the body region, where the doping type of the source region is different from the doping type of the substrate;

[0073] Step S15: forming a drain region in the drift region exposed on the other side of the dielectric layer, wherein the doping type of the drain region is consistent with the doping type of the drift region;

[0074] Step S16: forming a field plate on the dielectric layer, wherein the field plate is a multi-step structure with a top surface height gradually decreasing along a first direction, wherein the first direction is parallel to the surface of the drift region and points from the drain region to the source region.

[0075] The following combination Figures 2 to 7 The above-mentioned formation method will be explained.

[0076] Figures 2 to 5 It is a schematic diagram of the cross-sectional structure corresponding to each step in a method for forming a semiconductor structure in an embodiment of the present disclosure.

[0077] Reference Figure 2 , providing a substrate 100.

[0078] The substrate 100 is used to provide a process platform for the subsequent formation of semiconductor structures.

[0079] The substrate 100 may be a silicon substrate, or the material of the substrate 100 may also include germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The substrate 100 may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or a substrate with an epitaxial layer (Epi layer) grown thereon.

[0080] The doping type of the substrate 100 may be P-type doping or N-type doping.

[0081] A drift region 110 is formed in the substrate 100 .

[0082] The doping type of the drift region 110 may be N-type doping or P-type doping.

[0083] The doping type of the substrate 100 is different from the doping type of the drift region 110 .

[0084] It should be noted that, in the following description, N-type doping may be used as an example for illustration, but this does not constitute a limitation on the specific doping type used in the drift region 110 .

[0085] Continue to refer to Figure 2 , a first dielectric material layer 210 is formed on the substrate 100 .

[0086] Specifically, the first dielectric material layer 210 covers the drift region 110 and the substrate 100 adjacent to the drift region 110 along a first direction F1 , wherein the first direction F1 is parallel to the top surface of the drift region 110 .

[0087] In some embodiments, the first dielectric material layer 210 is formed by a thermal oxidation process.

[0088] Compared with the low-temperature deposition process, the interface state between the first dielectric material layer 210 and the substrate 100 formed on the substrate 100 by the thermal oxidation process is lower, the interface defect density is smaller, and the interface quality is higher.

[0089] In some embodiments, the first dielectric material layer 210 may be a silicon dioxide layer.

[0090] In some embodiments, the thickness of the first dielectric material layer 210 may be between 100 angstroms and 300 angstroms. For example, the thickness of the first dielectric material layer 210 may be 120 angstroms.

[0091] It should be noted that the thickness referred to herein refers to the dimension along a direction perpendicular to the top surface of the substrate 100 .

[0092] Continue to refer to Figure 2 , a second dielectric material layer 220 is formed on the first dielectric material layer 210 .

[0093] Specifically, the second dielectric material layer 220 covers the drift region 110 .

[0094] In some embodiments, the second dielectric material layer 220 is formed using a low-temperature deposition process, such as plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD).

[0095] The process temperature of the thermal oxidation process is generally higher than 800 degrees Celsius, and the process temperature of the low-temperature deposition process is generally lower than 300 degrees Celsius. Compared with the degree of redistribution of the doping concentrations in the various doping regions in the substrate 100 caused by the thermal oxidation process to form the second dielectric material layer 220, the degree of redistribution of the doping concentrations in the various doping regions in the substrate 100 caused by the low-temperature deposition process to form the second dielectric material layer 220 is negligible.

[0096] It should be noted that both the first dielectric material layer 210 and the second dielectric material layer 220 are used to form the final dielectric layer 200. Compared to directly forming the final dielectric layer 200 through a thermal oxidation process or a low-temperature deposition process, in the embodiment of the present disclosure, the first dielectric material layer 210 is first formed through a thermal oxidation process, and then the second dielectric material layer 220 is formed through a low-temperature deposition process to form the final dielectric layer 200. This can achieve a balance between reducing the "interface defect density between the field dielectric layer 200 and the drift region 110" and reducing the "redistribution of the doping concentration in each doped region within the substrate 100 during the formation of the field dielectric layer 200."

[0097] In some embodiments, the thickness of the second dielectric material layer 220 is greater than that of the first dielectric material layer 210 . The thickness of the second dielectric material layer 220 may be between 100 nanometers and 300 nanometers. For example, the thickness of the second dielectric material layer 220 may be 200 nanometers.

[0098] In some embodiments, the second dielectric material layer 220 may be a silicon dioxide layer.

[0099] Combined with reference Figure 2 and Figure 3 , partially removing the first dielectric material layer 210 and the second dielectric material layer 220 to obtain a first dielectric layer 211 and an initial second dielectric layer 221 .

[0100] The first dielectric layer 211 covers a portion of the drift region 110 and a portion of the substrate 100 adjacent to the portion of the drift region 110 along the first direction F1 , and the initial second dielectric layer 221 covers the first dielectric layer 211 .

[0101] Specifically, forming the first dielectric layer 211 and the initial second dielectric layer 221 may include the following steps: forming a patterned mask layer (not shown in the figure), the mask layer covering the area on the second dielectric material layer 220 corresponding to the initial second dielectric layer 221; using the mask layer as a mask, removing the remaining second dielectric material layers 220 outside the area covered by the mask layer and the remaining first dielectric material layers 210 outside the area covered by the initial second dielectric layer 221, so as to obtain the initial second dielectric layer 221 and the first dielectric layer 211.

[0102] Combined with reference Figure 3 and Figure 4 , a portion of the initial second dielectric layer 221 is removed to obtain a second dielectric layer 222 .

[0103] Among them, the second dielectric layer 222 covers a portion of the drift region 110 and exposes the first dielectric layer 211 located above the area adjacent to the drift region 110 and the substrate 100. The dielectric layer 200 composed of the second dielectric layer 222 and the first dielectric layer 211 is a multi-step structure with a top surface height gradually decreasing along the first direction F1. The number of steps in the dielectric layer 200 is greater than or equal to three.

[0104] The dielectric layer 200 has a multi-step structure with a top surface height gradually decreasing along the first direction F1. The corner positions on the top surface of the dielectric layer 200 can introduce multiple electric field peaks distributed along the first direction F1 into the drift region 110, thereby optimizing the lateral electric field distribution in the drift region 110 along the first direction F1 and improving the electrical performance of the semiconductor structure.

[0105] It should be noted that in the embodiment of the present disclosure, the first direction F1 is a direction parallel to the surface of the drift region 110 and pointing from the drain region 140 to the source region 130 .

[0106] Specifically, the initial second dielectric layer 221 has a first end and a second end, wherein the first end of the initial second dielectric layer 221 points to the second end thereof along the first direction F1. Forming the second dielectric layer 222 may include:

[0107] Step S21: forming a patterned mask layer (not shown in the figure), the mask layer exposing the initial second dielectric layer 221 located above the region adjacent to the drift region 110 and the substrate 100. Using the mask layer as a mask, the remaining portion of the initial second dielectric layer 221 outside the region covered by the mask layer is removed to expose the first dielectric layer 211 located above the region adjacent to the drift region 110 and the substrate 100.

[0108] In step S22, the previous mask layer is removed to form a new patterned mask layer (not shown in the figure). The mask layer exposes the area of the initial second dielectric layer 221 near its second end. Using the mask layer as a mask, a portion of the thickness of the initial second dielectric layer 221 outside the area covered by the mask layer is removed to obtain the second dielectric layer 222.

[0109] It should be noted that different steps in the process of forming the second dielectric layer 222 use different patterns of the mask layer.

[0110] In some embodiments, reference Figure 4 Step S22 is only performed once, and the second dielectric layer 222 thus obtained has a two-stage stepped structure with two inflection points on its top surface. Correspondingly, the dielectric layer 200 composed of the second dielectric layer 222 and the first dielectric layer 211 has a three-stage stepped structure with three inflection points on its top surface.

[0111] In other embodiments, step S22 may be performed multiple times, for example, three times, so that the second dielectric layer 222 obtained has a four-step structure with four inflection points on its top surface. Correspondingly, the dielectric layer 200 composed of the second dielectric layer 222 and the first dielectric layer 211 has a five-step structure with five inflection points on its top surface.

[0112] It should be noted that when step S22 is performed multiple times, the area near the second end of the initial second dielectric layer 221 exposed by the mask layer each time is larger than the area near the second end of the initial second dielectric layer 221 exposed by the mask layer in the previous time, so that the second dielectric layer 222 finally formed has a multi-step structure with a top surface height gradually decreasing along the first direction F1.

[0113] Continue to refer to Figure 4 , forming a gate body 310.

[0114] The gate body 310 is located on the first dielectric layer 211 exposed by the second dielectric layer 222 , and is located above a portion of the drift region 110 and a portion of the substrate 100 adjacent to the portion of the drift region 110 .

[0115] Continue to refer to Figure 4 , forming a gate spacer 320.

[0116] The gate spacers 320 are located on both sides of the gate body 310 , and the gate spacers 320 located close to the second dielectric layer 222 cover the top surface of the first dielectric layer 211 , while the gate spacers 320 located away from the second dielectric layer 222 cover the top surface of the substrate 100 .

[0117] In the embodiment of the present disclosure, the first dielectric layer 211 covered by the gate body 310 and the gate spacer 320 is used as the gate dielectric layer 200 , and the remaining first dielectric layer 211 and the second dielectric layer 222 other than the gate dielectric layer 200 are used as the field dielectric layer 200 .

[0118] It can be understood that the remaining first dielectric layer 211 outside the gate dielectric layer 200 and the gate dielectric layer 200 both belong to the first dielectric layer 211 and are adjacent layer structures formed in the same process. The electrical characteristics on both sides of the interface between the two are continuously distributed, and the interface between the two will not cause electric field spikes at the corresponding position of the substrate 100.

[0119] It should be noted that the first dielectric layer 211 can reduce the intensity of the electric field spike caused by the edge position of the gate body 310 at the corresponding position of the substrate 100 by separating the gate body 310 and the substrate 100, thereby optimizing the lateral electric field distribution within the substrate 100, where the lateral direction refers to the direction parallel to the top surface of the substrate 100.

[0120] Continue to refer to Figure 4 , forming the body region 120.

[0121] The doping type of the body region 120 is different from the doping type of the drift region 110.

[0122] Specifically, the step of forming the body region 120 may include: forming a patterned mask layer (not shown in the figure), the mask layer exposing the substrate 100 on the side close to the first dielectric layer 211; using the mask layer as a mask, doping the portion of the substrate 100 exposed by the mask layer to obtain the body region 120.

[0123] In some embodiments, after the body region 120 is formed, the semiconductor structure is annealed.

[0124] The annealing process can cause the body region 120 and the drift region 110 to diffuse relative to each other until they are adjacent to each other, and the interface between the two is located below the gate body 310 .

[0125] It should be noted that the first dielectric layer 211 and the second dielectric layer 222 are formed successively using different processes, and due to the difference in process temperature, a large number of defects exist at the interface between the first dielectric layer 211 and the second dielectric layer 222. These defects will capture and accumulate carriers, causing the threshold voltage to drift.

[0126] Annealing the semiconductor structure after forming the first dielectric layer 211 and the second dielectric layer 222 can promote atomic diffusion at the interface between the first dielectric layer 211 and the second dielectric layer 222, thereby reducing the amount of defects at the interface. This can reduce the amount of carriers captured and accumulated at the interface between the first field dielectric layer 200 and the second field dielectric layer 200, thereby reducing the shift in threshold voltage.

[0127] Continue to refer to Figure 4 A source region 130 is formed in the body region 120 exposed by the first dielectric layer 211 , and a drain region 140 is formed in the drift region 110 exposed by the first dielectric layer 211 .

[0128] The source region 130 and the body region 120 have different doping types, the drain region 140 has the same doping type as the source region 130 and the drift region 110 , and the doping concentration of the drain region 140 is higher than that of the drift region 110 .

[0129] In some embodiments, the source region 130 and the drain region 140 can be formed in various orders. For example, the drain region 140 can be formed during the formation of the source region 130. For example, the source region 130 can be formed after the drain region 140. For example, the source region 130 can be formed before the drain region 140.

[0130] Continue to refer to Figure 4 , an extraction region 150 is formed in the source region 130 .

[0131] Among them, the bottom surface of the extraction region 150 is adjacent to the body region 120, and the extraction region 150 has the same doping type as the body region 120, and the doping concentration is higher than that of the body region 120. In this way, the extraction region 150 can extract the charges accumulated in the body region 120, thereby reducing the potential fluctuation of the body region 120.

[0132] In some embodiments, the number of the second dielectric layer 222 may be one or more.

[0133] Figure 6 A schematic top view of a semiconductor structure in an embodiment of the present disclosure is shown.

[0134] As a specific example, refer to Figure 4 and Figure 6 There are multiple second dielectric layers 222 , and the second dielectric layers 222 are spaced apart along the second direction F2 , wherein the second direction F2 is parallel to the surface of the drift region 110 and perpendicular to the first direction F1 .

[0135] Compared to an integrated second dielectric layer 222, by providing a plurality of second dielectric layers 222 spaced apart along the second direction F2, adjacent edges of each second dielectric layer 222 in the second direction F2 can introduce a plurality of new electric field peaks distributed along the second direction F2 in the drift region 110, thereby optimizing the distribution of the lateral electric field in the drift region 110 in the second direction F2, thereby improving the breakdown voltage of the semiconductor structure and thereby improving the electrical performance of the semiconductor structure.

[0136] Continue to refer to Figure 6 The steps of each second dielectric layer 222 are consistent, and at least one of the distances between the steps of the same step number in each second dielectric layer 222 and the gate body 310 is different in size from the other distances.

[0137] This can increase the spacing between the locations of the electric field peaks introduced by adjacent second dielectric layers 222 and reduce the superposition strength between the corresponding adjacent electric field peaks, thereby simultaneously optimizing the distribution of the lateral electric field in the drift region 110 in the first direction F1 and the second direction F2, thereby improving the breakdown voltage of the semiconductor structure and thus improving the electrical performance of the semiconductor structure.

[0138] Combined with reference Figure 4 and Figure 5 , a field plate 400 is formed on the dielectric layer 200 .

[0139] In actual use, the field plate 400 is used to connect to an external electrode (not shown in the figure). By connecting to the external electrode, the field plate 400 can form an electric field perpendicular to the top surface of the substrate 100. This electric field can disperse the carriers captured and accumulated at the interface between the first dielectric layer 211 and the second dielectric layer 222, thereby reducing the drift of the threshold voltage.

[0140] In addition, the field plate 400 can also introduce a fixed potential by connecting to an external electrode, thereby preventing the first field dielectric layer 200 and the second dielectric layer 222 from introducing a random potential due to a floating effect, ensuring that the first dielectric layer 211 and the second dielectric layer 222 are at a fixed potential, thereby stabilizing the lateral electric field in the substrate 100.

[0141] In some embodiments, the field plate 400 is a multi-step structure with a top surface height gradually decreasing along the first direction F1 .

[0142] In this way, the corner position on the top surface of the field plate 400 can introduce multiple electric field peaks distributed along the first direction F1 in the drift region 110, thereby optimizing the distribution of the lateral electric field in the drift region 110 in the first direction F1, improving the breakdown voltage of the semiconductor structure, and thus improving the electrical performance of the semiconductor structure.

[0143] In some embodiments, the projection position of the corner position on the top surface of the field plate 400 on the surface of the drift region 110 does not overlap with the projection position of the corner position on the top surface of the dielectric layer 200 on the surface of the drift region 110 .

[0144] In this way, the positions of the multiple electric field peaks distributed along the first direction F1 introduced into the drift region 110 by the corners on the top surface of the field plate 400 do not overlap with the positions of the multiple electric field peaks distributed along the first direction F1 introduced into the drift region 110 by the corners on the top surface of the dielectric layer 200. Therefore, more electric field peaks distributed along the first direction F1 can be introduced into the drift region 110, thereby further optimizing the distribution of the lateral electric field in the drift region 110 in the first direction F1.

[0145] It should be noted that the aforementioned non-overlapping projection positions may include complete non-overlapping and partial non-overlapping.

[0146] In some examples, the projection position of the corner position on the top surface of the field plate 400 on the surface of the drift region 110 does not overlap at all with the projection position of the corner position on the top surface of the dielectric layer 200 on the surface of the drift region 110 .

[0147] This can avoid superposition of the electric field spike introduced in the drift region 110 by the corner position on the top surface of the field plate 400 and the electric field spike introduced in the drift region 110 by the corner position on the top surface of the dielectric layer 200, thereby avoiding premature breakdown of the semiconductor structure at the superposition position.

[0148] In other examples, the projection position of the corner position on the top surface of the field plate 400 on the surface of the drift region 110 may partially overlap or partially not overlap with the projection position of the corner position on the top surface of the dielectric layer 200 on the surface of the drift region 110 .

[0149] In some embodiments, the field plate 400 may be made of polysilicon.

[0150] Continue to refer to Figure 5 The second dielectric layer 222 in the dielectric layer 200 of the three-step structure is a two-stage stepped structure. As a specific example, forming the field plate 400 on the dielectric layer 200 of the three-step structure may include the following steps:

[0151] In step S31, a field plate material layer (not shown in the figure) is deposited on the dielectric layer 200; a patterned mask layer (not shown in the figure) is formed, where the mask layer covers the field plate material layer above the first dielectric layer 211 between the gate sidewall 320 and the second dielectric layer 222; and the mask layer is used as a mask to remove the remaining field plate material layer outside the mask layer-covered area to form a bottom field plate unit 410, wherein the top surface of the bottom field plate unit 410 is flush with the top surface of the lowest step on the top surface of the second dielectric layer 222.

[0152] The bottom field plate unit 410 has a first end and a second end, wherein the first end of the bottom field plate unit 410 points to the second end thereof along the first direction F1. In some embodiments, the second end of the bottom field plate unit 410 is spaced apart from the gate spacer 320 along the first direction F1.

[0153] In this way, the position of the electric field peak introduced by the second end of the bottom field plate unit 410 in the drift region 110 will not overlap with the position of the electric field peak introduced by the gate sidewall 320 in the drift region 110, so that more electric field peaks distributed along the first direction F1 can be introduced in the drift region 110, thereby further optimizing the electric field distribution in the drift region 110 along the first direction F1, improving the breakdown voltage of the semiconductor structure, and thus improving the electrical performance of the semiconductor structure.

[0154] Step S32: remove the previous mask layer; deposit a new field plate material layer (not shown) on the second dielectric layer 222 and the bottom field plate unit 410; form a new patterned mask layer (not shown) that covers the field plate material layer above the step with the lowest top surface height of the second dielectric layer 222 and the field plate material layer above a portion of the bottom field plate unit 410 near the step; use the mask layer as a mask to remove the remaining field plate material layer outside the mask layer-covered area to form a middle field plate unit 420, wherein the top surface of the middle field plate unit 420 is flush with the top surface of the step with the highest top surface height of the second dielectric layer 222.

[0155] The middle field plate unit 420 has a first end and a second end, wherein the first end of the middle field plate unit 420 points to its second end along the first direction F1. In some embodiments, the projection position of the second end of the middle field plate unit 420 on the surface of the drift region 110 and the projection positions of the first end and the second end of the bottom field plate unit 410 on the surface of the drift region 110 have a spacing along the first direction F1, and are located between the projection positions of the first end and the second end of the bottom field plate unit 410 on the surface of the drift region 110 along the first direction F1.

[0156] In this way, the position of the electric field peak introduced by the second end of the middle field plate unit 420 in the drift region 110 will not overlap with the position of the electric field peak introduced by the first end and the second end of the bottom field plate unit 410 in the drift region 110. Therefore, more electric field peaks distributed along the first direction F1 can be introduced in the drift region 110, thereby further optimizing the electric field distribution in the drift region 110 along the first direction F1, improving the breakdown voltage of the semiconductor structure, and thus improving the electrical performance of the semiconductor structure.

[0157] Step S33: remove the previous mask layer; deposit a new field plate material layer (not shown in the figure) on the second dielectric layer 222 and the middle field plate unit 420; form a new patterned mask layer (not shown in the figure), which covers the field plate material layer above the highest step on the top surface of the second dielectric layer 222 and the field plate material layer above the portion of the middle field plate unit 420 near the step; use the mask layer as a mask to remove the other field plate material layers outside the mask layer coverage area to form a top field plate unit 430, wherein the bottom field plate unit 410, the middle field plate unit 420, and the top field plate unit 430 together constitute the field plate 400.

[0158] The top field plate unit 430 has a first end and a second end, wherein the first end of the top field plate unit 430 points to its second end along the first direction F1. In some embodiments, the projection position of the second end of the top field plate unit 430 on the surface of the drift region 110 has a spacing along the first direction F1 from the projection position of the first end of the bottom field plate unit 410 on the surface of the drift region 110 and the projection position of the middle field plate unit 420 on the surface of the drift region 110, and is located between the projection position of the first end of the bottom field plate unit 410 on the surface of the drift region 110 and the projection position of the middle field plate unit 420 on the surface of the drift region 110 along the first direction F1.

[0159] In this way, the position of the electric field peak introduced by the second end of the top field plate unit 430 in the drift region 110 will not overlap with the position of the electric field peak introduced by the first end and the second end of the bottom field plate unit 410 in the drift region 110. Therefore, more electric field peaks distributed along the first direction F1 can be introduced in the drift region 110, thereby further optimizing the electric field distribution in the drift region 110 along the first direction F1, improving the breakdown voltage of the semiconductor structure, and thus improving the electrical performance of the semiconductor structure.

[0160] It should be noted that for a dielectric layer 200 having a step number greater than three, the corresponding second dielectric layer 222 has a step number greater than two. Accordingly, during the process of forming the field plate 400, step S32 is performed multiple times to form multiple middle field plate units 420 until the top surface of the last formed middle field plate unit 420 is flush with the top surface of the highest step of the second dielectric layer 222.

[0161] In some embodiments, the number of the field plates 400 may be one or more.

[0162] Figure 7 A schematic top view of a semiconductor structure in an embodiment of the present disclosure is shown.

[0163] As a specific example, refer to Figure 5 and Figure 7 There are multiple field plates 400 , and the field plates 400 are spaced apart along the second direction F2 . One field plate 400 corresponds to one second dielectric layer 222 .

[0164] Compared with an integrated field plate 400, by providing a plurality of field plates 400 spaced apart along the second direction F2, the adjacent edges of each field plate 400 in the second direction F2 can introduce a plurality of new electric field peaks distributed along the second direction F2 in the drift region 110, thereby optimizing the distribution of the lateral electric field in the drift region 110 in the second direction F2.

[0165] In some embodiments, the steps of the field plates 400 are consistent, and at least one of the distances between the steps of the same step in the field plates 400 and the gate body 310 is different in size from the other distances.

[0166] This can increase the spacing between the locations of the electric field peaks introduced by adjacent field plates 400 and reduce the superposition strength between the corresponding adjacent electric field peaks, thereby simultaneously optimizing the distribution of the lateral electric field in the drift region 110 in the first direction F1 and the second direction F2, further improving the breakdown voltage of the semiconductor structure, and thus improving the electrical performance of the semiconductor structure.

[0167] In some embodiments, along the second direction F2 , a projection position of each field plate 400 on the surface of the drift region 110 is spaced from a projection position of the corresponding second dielectric layer 222 on the surface of the drift region 110 .

[0168] In this way, the positions of the electric field peaks introduced by each field plate 400 in the drift region 110 will not overlap with the positions of the electric field peaks introduced by the corresponding second dielectric layer 222 in the drift region 110. Therefore, more electric field peaks distributed along the second direction F2 can be introduced in the drift region 110, thereby further optimizing the electric field distribution in the drift region 110 along the second direction F2, improving the breakdown voltage of the semiconductor structure, and thus improving the electrical performance of the semiconductor structure.

[0169] In some embodiments, the semiconductor structure may be a symmetrical LDMOS device. The symmetrical LDMOS device includes two symmetrical semiconductor units. The body region 120 belongs to the semiconductor unit, and the two semiconductor units share the same body region 120 .

[0170] In some embodiments, the semiconductor structure may be an LDMOS device, which includes a semiconductor unit, wherein the semiconductor unit may include a drift region 110 , a body region 120 , a source region 130 , a drain region 140 , an extraction region 150 , a gate body 310 , a gate spacer 320 , a dielectric layer 200 , and a field plate 400 .

[0171] Furthermore, the semiconductor structure may be a symmetrical LDMOS device, which includes two symmetrical semiconductor units. The two symmetrical semiconductor units share the same body region 120 , source region 130 , and extraction region 150 .

[0172] Specifically, sharing the same body region 120 , source region 130 , and extraction region 150 can improve the current driving capability of the LDMOS device, while also simplifying the layout and improving the integration of the device.

[0173] It should be noted that, in addition to the shared body region 120, source region 130, and extraction region 150, each semiconductor unit in the symmetric LDMOS device may have its own drift region 110, drain region 140, gate body 310, gate spacer 320, dielectric layer 200, and field plate 400, and the aforementioned parts may or may not be completely consistent.

[0174] It should be noted that each semiconductor unit has its own first direction F1. The first direction F1 of each semiconductor unit refers to the direction from the source region 130 to the drain region 140 in the semiconductor unit. The first directions F1 of different semiconductor units may be different, for example Figures 4 to 7The first directions F1 of two semiconductor units in the same semiconductor structure may be opposite to each other.

[0175] In the embodiment of the present disclosure, a semiconductor structure can also be provided, combined with reference to Figures 2 to 7 The semiconductor structure may include: a substrate 100 , a dielectric layer 200 , a body region 120 , a source region 130 , a drain region 140 and a field plate 400 .

[0176] The substrate 100 includes a drift region 110, and the doping type of the drift region 110 is different from the doping type of the substrate 100; the dielectric layer 200 covers a portion of the drift region 110 and a portion of the substrate 100 adjacent to the portion of the drift region 110; the body region 120 is located on one side of the dielectric layer 200 and is adjacent to the drift region 110, and the doping type of the body region 120 is different from the doping type of the drift region 110; the source region 130 is located in the body region 120, and the doping type of the source region 130 is different from the doping type of the substrate 100; the drain region 140 is located in the drift region 110 exposed on the other side of the dielectric layer 200, and the doping type of the drain region 140 is consistent with the doping type of the drift region 110; the field plate 400 covers the dielectric layer 200, and the field plate 400 is a multi-step structure with a top surface height gradually decreasing along a first direction F1, wherein the first direction F1 is parallel to the surface of the drift region 110 and points from the drain region 140 to the source region 130.

[0177] In some embodiments, the dielectric layer 200 has a multi-step structure with a top surface height gradually decreasing along the first direction F1 , wherein the number of steps in the dielectric layer 200 is greater than or equal to three.

[0178] In some embodiments, the dielectric layer 200 includes a first dielectric layer 211 and a second dielectric layer 222 .

[0179] Among them, the first dielectric layer 211 covers a portion of the drift region 110 and a portion of the substrate 100 adjacent to the portion of the drift region 110 along the first direction F1; the second dielectric layer 222 covers a portion of the drift region 110 and exposes the first dielectric layer 211 located above the area adjacent to the drift region 110 and the substrate 100. The top surface height of the multi-level stepped structure formed by the second dielectric layer 222 and the first dielectric layer 211 gradually decreases along the first direction F1.

[0180] In some embodiments, the second dielectric layer 222 has a multi-step structure that gradually decreases along the first direction F1 .

[0181] In some embodiments, the projection position of the corner position of the top surface of the field plate 400 on the surface of the drift region 110 does not overlap with the projection position of the corner position of the top surface of the dielectric layer 200 on the surface of the drift region 110 .

[0182] In some embodiments, there are multiple second dielectric layers 222 , and the second dielectric layers 222 are spaced apart along the second direction F2 , wherein the second direction F2 is parallel to the surface of the drift region 110 and perpendicular to the first direction F1 .

[0183] In some embodiments, the semiconductor structure further includes a gate body 310 and a gate spacer 320 .

[0184] In which, the gate body 310 is located on the first dielectric layer 211 exposed by the second dielectric layer 222, and is located above a portion of the drift region 110 and a portion of the substrate 100 adjacent to the portion of the drift region 110; the gate sidewall 320 is located on the sidewall of the gate body 310; it should be noted that the first dielectric layer 211 covered by the gate body 310 is used as the gate dielectric layer 200, and the remaining first dielectric layer 211 and the second dielectric layer 222 except for the gate dielectric layer 200 are used as the field dielectric layer 200.

[0185] In some embodiments, the steps of each second dielectric layer 222 are consistent, and at least one of the distances between steps of the same step number in each second dielectric layer 222 and the gate body 310 is different in size from the other distances.

[0186] In some embodiments, there are multiple field plates 400 , and the field plates 400 are spaced apart along the second direction F2 . One field plate 400 corresponds to one second dielectric layer 222 .

[0187] In some embodiments, the steps of the field plates 400 are consistent, and at least one of the distances between the steps of the same step in each field plate 400 and the gate body 310 is different in size from the other distances.

[0188] It should be noted that for the principle, specific implementation and beneficial effects of the semiconductor structure, please refer to the previous article and Figures 2 to 7 The description of the method for forming the semiconductor structure is not repeated here.

[0189] It should be understood that the term "and / or" in this document simply describes an association relationship between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. Furthermore, the character " / " in this document indicates that the related objects are in an "or" relationship.

[0190] It is understood that the term "multiple" as used herein refers to two or more. The terms "first," "second," and "third" in the embodiments of this application are for illustrative purposes only and are intended to distinguish the objects being described. They are not in any particular order and do not represent a specific limit on the number of devices in the embodiments of this application. They do not constitute any limitation on the embodiments of this application.

[0191] It is understandable that multiple embodiment schemes are described herein, and the various optional methods introduced in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment schemes, which can all be considered as embodiment schemes disclosed and disclosed in this disclosure.

[0192] Although the embodiments of the present disclosure are disclosed above, the present disclosure is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has a drift region therein, wherein the doping type of the drift region is different from the doping type of the substrate; forming a dielectric layer, wherein the dielectric layer covers a portion of the drift region and a portion of the substrate adjacent to the portion of the drift region; forming a body region in the substrate exposed on one side of the dielectric layer, wherein the body region is adjacent to the drift region, and a doping type of the body region is different from a doping type of the drift region; forming a source region in the body region, wherein the doping type of the source region is different from the doping type of the substrate; forming a drain region in the drift region exposed on the other side of the dielectric layer, wherein the doping type of the drain region is consistent with the doping type of the drift region; A field plate is formed on the dielectric layer. The field plate is a multi-step structure with a top surface height gradually decreasing along a first direction. The first direction is parallel to the surface of the drift region and points from the drain region to the source region.

2. The forming method according to claim 1, wherein: The dielectric layer is a multi-step structure with a top surface height gradually decreasing along the first direction, wherein the number of steps in the dielectric layer is greater than or equal to three.

3. The forming method according to claim 2, wherein: The dielectric layer includes a first dielectric layer and a second dielectric layer, and the steps of forming the dielectric layer include: forming a first dielectric material layer and a second dielectric material layer on the substrate, wherein the second dielectric material layer covers the first dielectric material layer; removing a portion of the first dielectric material layer and a portion of the second dielectric material layer to obtain the first dielectric layer and an initial second dielectric layer, wherein the first dielectric layer covers a portion of the drift region and a portion of the substrate adjacent to the portion of the drift region along a first direction, and the initial second dielectric layer covers the first dielectric layer; A portion of the initial second dielectric layer is removed to obtain a second dielectric layer, wherein the second dielectric layer covers a portion of the drift region and exposes the first dielectric layer located above the drift region and an adjacent area of the substrate, and the top surface height of the multi-level stepped structure formed by the second dielectric layer and the first dielectric layer gradually decreases along the first direction.

4. The forming method according to claim 3, wherein: The second dielectric layer is a multi-step structure with a top surface height gradually decreasing along the first direction.

5. The forming method according to claim 4, wherein: A projection position of a corner position of the top surface of the field plate on the surface of the drift region does not overlap with a projection position of a corner position of the top surface of the dielectric layer on the surface of the drift region.

6. The forming method according to claim 5, wherein: There are multiple second dielectric layers, and the second dielectric layers are spaced apart along a second direction, wherein the second direction is parallel to the surface of the drift region and perpendicular to the first direction.

7. The forming method according to claim 6, wherein: Before forming the field plate, the method further includes the following steps: forming a gate body on the first dielectric layer exposed by the second dielectric layer, wherein the gate body is located above a portion of the drift region and a portion of the substrate adjacent to the portion of the drift region; forming a gate spacer on a sidewall of the gate body; The first dielectric layer covered by the gate body is used as a gate dielectric layer, and the remaining first dielectric layer and the second dielectric layer except the gate dielectric layer are used as field dielectric layers.

8. The forming method according to claim 7, wherein: The second dielectric layers have the same number of steps, and at least one of the distances between the steps of the same number in the second dielectric layers and the gate body is different in size from the other distances.

9. The forming method according to claim 7, wherein: There are multiple field plates, each of which is spaced apart and distributed along the second direction, and one field plate corresponds to one second dielectric layer.

10. The forming method according to claim 9, wherein: The order of each field plate is consistent, and among the corresponding spacings between steps of the same order in each field plate and the gate body, at least one spacing has a size different from the other spacings.

11. A semiconductor structure, characterized in that include: a substrate having a drift region therein, wherein the drift region has a doping type different from that of the substrate; a dielectric layer covering a portion of the drift region and a portion of the substrate adjacent to the portion of the drift region; a body region, located on one side of the dielectric layer and adjacent to the drift region, wherein a doping type of the body region is different from a doping type of the drift region; a source region located in the body region, wherein a doping type of the source region is different from a doping type of the substrate; a drain region, located in the drift region exposed on the other side of the dielectric layer, wherein the doping type of the drain region is consistent with the doping type of the drift region; A field plate covers the dielectric layer and is a multi-step structure with a top surface height gradually decreasing along a first direction, wherein the first direction is parallel to the surface of the drift region and points from the drain region to the source region.

12. The semiconductor structure according to claim 11, wherein: The dielectric layer is a multi-step structure with a top surface height gradually decreasing along the first direction, wherein the number of steps in the dielectric layer is greater than or equal to three.

13. The semiconductor structure according to claim 12, wherein: The dielectric layer includes: a first dielectric layer covering a portion of the drift region and a portion of the substrate adjacent to the portion of the drift region along a first direction; The second dielectric layer covers a portion of the drift region and exposes the first dielectric layer above the drift region and the adjacent region of the substrate. The top surface height of the multi-level stepped structure formed by the second dielectric layer and the first dielectric layer gradually decreases along the first direction.

14. The semiconductor structure according to claim 13, wherein: The second dielectric layer is a multi-step structure that gradually decreases along the first direction.

15. The semiconductor structure according to claim 14, wherein: A projection position of a corner position of the top surface of the field plate on the surface of the drift region does not overlap with a projection position of a corner position of the top surface of the dielectric layer on the surface of the drift region.

16. The semiconductor structure according to claim 15, wherein: There are multiple second dielectric layers, and the second dielectric layers are spaced apart along a second direction, wherein the second direction is parallel to the surface of the drift region and perpendicular to the first direction.

17. The semiconductor structure according to claim 16, wherein: The semiconductor structure further comprises: a gate body, located on the first dielectric layer exposed by the second dielectric layer, and located above a portion of the drift region and a portion of the substrate adjacent to the portion of the drift region; A gate sidewall, located on a sidewall of the gate body; The first dielectric layer covered by the gate body is used as a gate dielectric layer, and the remaining first dielectric layer and the second dielectric layer except the gate dielectric layer are used as field dielectric layers.

18. The semiconductor structure according to claim 17, wherein: The second dielectric layers have the same number of steps, and at least one of the distances between the steps of the same number in the second dielectric layers and the gate body is different in size from the other distances.

19. The semiconductor structure according to claim 18, wherein: There are multiple field plates, each of which is spaced apart and distributed along the second direction, and one field plate corresponds to one second dielectric layer.

20. The semiconductor structure according to claim 19, wherein: The number of steps of the field plates is consistent, and at least one of the distances between the steps of the same number in each field plate and the gate body is different in size from the other distances.

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