Semiconductor device

Abstract

A semiconductor substrate of a semiconductor device includes a first conductivity type upper region, a second conductivity type electric field relaxation region, a super junction region, and a plurality of first conductivity type connection regions. When the semiconductor substrate is viewed from above, the second conductivity-type column regions and the first conductivity-type column regions of the super junction region extend linearly along the first direction and are arranged alternately along the second direction. A plurality of opening portions provided in the electric field relaxation region are arranged so as to be scattered. Each of the first conductivity-type connection regions is disposed in the corresponding opening, and connects the first conductivity-type upper region and the corresponding first conductivity-type column region. The second conductivity type impurity concentration of each second conductivity type column region is lower than the second conductivity type impurity concentration of the electric field relaxation region. When the semiconductor substrate is viewed from above, each of the second conductivity-type column regions does not overlap each of the openings.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a semiconductor device. Background Art

[0002] Patent Document 1 discloses a MOSFET (metal-oxide-semiconductor field-effect transistor) comprising a semiconductor substrate, a source electrode, and a drain electrode. In this MOSFET, the semiconductor substrate has an upper parallel pn structure and a lower parallel pn structure. The upper parallel pn structure comprises an upper p-type column region and an upper n-type column region. The upper p-type column region and the upper n-type column region extend linearly along a first direction when the semiconductor substrate is viewed from above and are alternately arranged along a second direction orthogonal to the first direction. The lower parallel pn structure is arranged below the upper parallel pn structure and comprises a lower p-type column region and a lower n-type column region. The lower p-type column region and the lower n-type column region extend linearly along a second direction when the semiconductor substrate is viewed from above and are alternately arranged along the first direction.

[0003] When this MOSFET is off, the electric field applied to the gate oxide film is mitigated by the depletion layer extending from the upper p-type column region to the upper n-type column region. Furthermore, when this MOSFET is off, the depletion layer rapidly expands laterally from the pn junction at the interface between the upper p-type column region and the upper n-type column region, and from the pn junction at the interface between the lower p-type column region and the lower n-type column region. Consequently, this MOSFET can maintain a high withstand voltage.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2020-150182 Summary of the Invention

[0007] In Patent Document 1, the upper p-type column region and the upper n-type column region both extend in a straight line and are arranged alternately. This structure limits the miniaturization of the spacing between the upper and lower parallel pn structures. Consequently, when the n-type impurity concentration in each n-type column region is increased to reduce on-resistance, the n-type column regions are less likely to be depleted when the MOSFET is turned off, reducing the breakdown voltage of the MOSFET. Thus, the MOSFET of Patent Document 1 struggles to achieve both high breakdown voltage and reduced on-resistance. This specification proposes a technique for ensuring high breakdown voltage while reducing on-resistance.

[0008] The semiconductor device disclosed in this specification comprises: a semiconductor substrate; an upper electrode disposed on the upper surface of the semiconductor substrate; and a lower electrode disposed on the lower surface of the semiconductor substrate. The semiconductor device is configured so that current flows between the upper electrode and the lower electrode. The semiconductor substrate comprises: a first conductivity type upper region; a second conductivity type electric field relaxation region disposed below the first conductivity type upper region and connected to the upper electrode; a super junction region disposed below the electric field relaxation region; and a plurality of first conductivity type connection regions. The super junction region comprises a plurality of second conductivity type column regions and a plurality of first conductivity type column regions. When the semiconductor substrate is viewed from above, the second conductivity type column regions and the first conductivity type column regions extend linearly along a first direction and are alternately arranged along a second direction orthogonal to the first direction. The electric field relaxation region comprises a plurality of openings extending from the upper end to the lower end of the electric field relaxation region. The plurality of openings are dispersed within a plane parallel to the upper surface of the semiconductor substrate. Each of the first-conductivity-type connection regions is disposed within a corresponding opening, connecting the first-conductivity-type upper region to the corresponding first-conductivity-type column region. The second-conductivity-type impurity concentration of each of the second-conductivity-type column regions is lower than the second-conductivity-type impurity concentration of the electric field relaxation region. When the semiconductor substrate is viewed from above, each of the second-conductivity-type column regions does not overlap with a respective opening.

[0009] In this specification, the first conductivity type is either n-type or p-type, and the second conductivity type is the other of n-type and p-type. If the first conductivity type is n-type, the second conductivity type is p-type, and if the first conductivity type is p-type, the second conductivity type is n-type.

[0010] In the above-described semiconductor device, an opening is provided in the second-conductivity-type electric field relaxation region, and a first-conductivity-type connection region is provided within the opening. Because the electric field relaxation region is connected to the upper electrode, when the semiconductor device is turned off, a reverse voltage is applied to the pn junction at the interface between the electric field relaxation region and the first-conductivity-type semiconductor region (the first-conductivity-type upper region, the first-conductivity-type connection region, and the first-conductivity-type column region). As a result, a depletion layer extends from the electric field relaxation region into the first-conductivity-type semiconductor region, relaxing the electric field applied within the semiconductor region. Furthermore, because the openings in the electric field relaxation region are dispersed within a plane parallel to the upper surface of the semiconductor substrate, the first-conductivity-type connection region can be more finely divided within the plane compared to conventional structures in which the second-conductivity-type and first-conductivity-type regions are alternately arranged in strips. Therefore, even if the first-conductivity-type impurity concentration in the first-conductivity-type connection region is increased, when the semiconductor device is turned off, the depletion layer extends from the electric field relaxation region to substantially the entire area within the first-conductivity-type connection region. As described above, in this semiconductor device, the first conductivity type impurity concentration in the first conductivity type connection region can be made sufficiently high, and thus the on-resistance can be reduced.

[0011] Furthermore, in this semiconductor device, a superjunction region is disposed below the electric field relaxation region. The second conductivity type column regions and the first conductivity type column regions of the superjunction region extend linearly along the first direction and are alternately arranged along the second direction. When the semiconductor device is turned off, a depletion layer extends from the pn junction at the interface between the second conductivity type column regions and the first conductivity type column regions into both the second conductivity type column regions and the first conductivity type column regions. Because the second conductivity type column regions and the first conductivity type column regions are arranged in a stripe pattern, when the semiconductor device is turned off, both the second conductivity type column regions and the first conductivity type column regions (i.e., the superjunction regions) are easily and uniformly depleted. This ensures a high withstand voltage in this semiconductor device. Furthermore, in this semiconductor device, since each second conductivity type column region is positioned so as not to overlap with the opening, the current path is not restricted by the second conductivity type column regions. Consequently, current flows appropriately from the lower electrode to the upper electrode via the first conductivity type column regions, the first conductivity type connection region, and the first conductivity type upper region, thereby suppressing degradation of on-resistance. As described above, in this semiconductor device, it is possible to ensure a high breakdown voltage and reduce on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a perspective cross-sectional view of the semiconductor device of Example 1.

[0013] Figure 2 yes Figure 1 Cross-sectional view at plane II.

[0014] Figure 3 yes Figure 1Cross-sectional view at plane III.

[0015] Figure 4 These are diagrams for explaining the manufacturing process of the semiconductor device of Example 1.

[0016] Figure 5 These are diagrams for explaining the manufacturing process of the semiconductor device of Example 1.

[0017] Figure 6 These are diagrams for explaining the manufacturing process of the semiconductor device of Example 1.

[0018] Figure 7 These are diagrams for explaining the manufacturing process of the semiconductor device of Example 1.

[0019] Figure 8 This is a perspective cross-sectional view of the semiconductor device of Example 2.

[0020] Figure 9 This is a cross-sectional view of the semiconductor device of Example 3.

[0021] Figure 10 This is a plan view of the semiconductor device of Example 3.

[0022] Figure 11 yes Figure 9 Cross-sectional view at plane XI.

[0023] Figure 12 yes Figure 9 Cross-sectional view at plane XII.

[0024] Figure 13 This is a cross-sectional view of the semiconductor device of Example 4.

[0025] Figure 14 This is a plan view of the semiconductor device of Example 4.

[0026] Figure 15 yes Figure 13 Cross-sectional view at plane XV of .

[0027] Figure 16 yes Figure 13 Cross-sectional view at plane XVI of . DETAILED DESCRIPTION

[0028] In one example of a semiconductor device disclosed in this specification, when the semiconductor substrate is viewed from above, the semiconductor device may be configured to include a plurality of rows of the openings spaced apart along the first direction. The rows may be spaced apart in the second direction. Adjacent openings may be spaced equally apart in the first direction. Adjacent rows may be spaced equally apart in the second direction.

[0029] In such a structure, the first conductivity type connection regions in each opening are regularly arranged in a plane, thereby making it possible to make the on-resistance uniform across the entire semiconductor device.

[0030] In the semiconductor device of an example disclosed in this specification, the super junction region may be the first super junction region, the second conductive type column region may be the first second conductive type column region, and the first conductive type column region may be the first first conductive type column region. There may also be a second super junction region arranged at the lower part of the first super junction region. The second super junction region may have a plurality of second second conductive type column regions and a plurality of second first conductive type column regions. When the semiconductor substrate is observed from above, each of the second second conductive type column regions and each of the second first conductive type column regions extend in a straight line along a third direction intersecting the first direction, and are alternately arranged along a fourth direction orthogonal to the third direction. The second conductive type impurity concentration of each of the second second conductive type column regions may be lower than the second conductive type impurity concentration of the electric field relaxation region.

[0031] In this structure, the inclusion of a second superjunction region increases the overall length of the superjunction region in the thickness direction of the semiconductor substrate, thereby ensuring a higher breakdown voltage. Furthermore, the first second conductivity type column region and the first first conductivity type column region are arranged in a staggered pattern, as are the second second conductivity type column region and the second first conductivity type column region. Therefore, even if misalignment occurs between the first and second superjunction regions, variations in the current path area can be minimized.

[0032] The semiconductor device of one example disclosed in this specification may further include a second conductivity type connection region extending upward from the upper surface of the electric field relaxation region and connecting the electric field relaxation region and the upper electrode.

[0033] In such a structure, the potential of the electric field relaxation region can be easily fixed to the potential of the upper electrode, and the function of the electric field relaxation region can be exerted.

[0034] In one example of a semiconductor device disclosed in this specification, the device may further include: a trench provided on the upper surface of the semiconductor substrate; a gate insulating film covering the inner surface of the trench; and a gate electrode provided inside the trench and insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate may further include: a first conductivity type source region exposed on the upper surface of the semiconductor substrate and in contact with the gate insulating film; and a second conductivity type body region in contact with the gate insulating film below the source region, separating the first conductivity type upper region from the source region. The first conductivity type upper region may be in contact with the gate insulating film below the body region. Furthermore, when the semiconductor substrate is viewed from above, each of the openings may not overlap with the trench.

[0035] In this structure, when the semiconductor substrate is viewed from above, each opening is positioned so as not to overlap with the trench (i.e., the electric field relaxation region overlaps the trench). Therefore, when the semiconductor device is turned off, the electric field applied to the lower end of the trench can be appropriately relaxed by the electric field relaxation region.

[0036] In one example of the semiconductor device disclosed in this specification, a gate electrode may be further provided on the upper surface of the semiconductor substrate via a gate insulating film. Alternatively, the semiconductor substrate may further include: a source region of the first conductivity type, exposed on the upper surface of the semiconductor substrate; and a body region of the second conductivity type, provided adjacent to the source region and exposed on the upper surface of the semiconductor substrate. Alternatively, the first conductivity type upper region may be provided adjacent to the body region, separated from the source region by the body region, and exposed on the upper surface of the semiconductor substrate. Alternatively, the gate electrode may be provided opposite to the first conductivity type upper region via the gate insulating film, and opposite to the body region located between the source region and the first conductivity type upper region. Furthermore, when the semiconductor substrate is viewed from above, each of the openings may overlap with the gate electrode.

[0037] In this structure, when the semiconductor device is turned on, a channel is formed in the body region in the area opposite the gate electrode, and electrons flow from the source region through the channel to the first-conductivity-type upper region. In this structure, when the semiconductor substrate is viewed from above, each opening is located at a position overlapping the gate electrode. In other words, each opening is located at a position overlapping the first-conductivity-type upper region facing the gate electrode. Therefore, the current path from the first-conductivity-type connection region within each opening, through the first-conductivity-type upper region, the channel, and the source region is short, reducing the on-resistance.

[0038] In one example of the semiconductor device disclosed in this specification, the first conductivity type upper region may be exposed on the upper surface of the semiconductor substrate. The upper electrode may form a Schottky junction with the upper surface of the semiconductor substrate. Furthermore, each opening may overlap with a Schottky junction surface when the semiconductor substrate is viewed from above.

[0039] In this structure, each opening is positioned so as to overlap the Schottky junction when the semiconductor substrate is viewed from above. Therefore, the current path from the Schottky junction through the first conductivity type upper region, the first conductivity type connection region within the opening, and the first conductivity type column region is shortened, thereby reducing on-resistance.

[0040] (Example 1)

[0041] Hereinafter, a semiconductor device 10 according to the first embodiment will be described with reference to the drawings. Figure 1 The semiconductor device 10 shown is a vertical MOSFET (metal-oxide-semiconductor field-effect transistor) having a semiconductor substrate 12, electrodes, an insulating film, and the like. The semiconductor substrate 12 is made of SiC. However, the material constituting the semiconductor substrate 12 is not particularly limited; for example, other semiconductor materials such as Si and GaN may also be used. Hereinafter, a direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x-direction, a direction parallel to the upper surface 12a of the semiconductor substrate 12 and perpendicular to the x-direction is referred to as the y-direction, and the thickness direction of the semiconductor substrate 12 is referred to as the z-direction.

[0042] A plurality of trenches 22 are formed on the upper surface 12a of the semiconductor substrate 12. Figure 1 As shown, the trenches 22 are arranged at intervals in the x-direction. Each trench 22 extends long in the y-direction. A gate insulating film 24 and a gate electrode 26 are arranged in each trench 22. The gate insulating film 24 covers the inner surface of each trench 22. The gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24. The upper surface of the gate electrode 26 is covered by an interlayer insulating film 28. A source electrode 70 is arranged on the upper surface 12a of the semiconductor substrate 12. The source electrode 70 is in contact with the upper surface 12a of the semiconductor substrate 12 in a portion where the interlayer insulating film 28 is not provided. The source electrode 70 is insulated from the gate electrode 26 by the interlayer insulating film 28. A drain electrode 72 is arranged on the lower surface 12b of the semiconductor substrate 12. The drain electrode 72 is in contact with substantially the entire area of the lower surface 12b of the semiconductor substrate 12.

[0043] Inside the semiconductor substrate 12, there are provided a plurality of source regions 30, a body region 32, an n-type upper region 34, an electric field relaxation region 36, a super junction (hereinafter referred to as "SJ") region 38, a plurality of n-type connection regions 40, a plurality of p-type connection regions 42, a drift region 44 and a drain region 46.

[0044] Each source region 30 is of n-type and is exposed on the upper surface 12a of the semiconductor substrate 12. Each source region 30 is in ohmic contact with the source electrode 70. Each source region 30 is in contact with the gate insulating film 24 at the upper end of the trench 22.

[0045] The body region 32 is p-type. It includes a contact region 32a and a main region 32b. The contact region 32a is exposed on the upper surface 12a of the semiconductor substrate 12 and is in ohmic contact with the source electrode 70. The contact region 32a is positioned within the region sandwiched between the two source regions 30. The contact region 32a extends elongated along the y-direction. The main region 32b is positioned below the source region 30 and the contact region 32a. The main region 32b is in contact with the gate insulating film 24 below the source region 30. The p-type impurity concentration in the main region 32b is lower than that in the contact region 32a.

[0046] The n-type upper region 34 is arranged below the body region 32. The n-type upper region 34 is separated from each source region 30 by the body region 32. The n-type upper region 34 is in contact with the gate insulating film below the body region 32 in a range where a p-type connection region 42 described later is not present.

[0047] The electric field relaxation region 36 is of p-type. The electric field relaxation region 36 is arranged on the lower side of the n-type upper region 34. Figure 2 As shown in FIG. 1 , when observing the semiconductor substrate 12 from above, the electric field relaxation region 36 is composed of a plurality of portions 36a extending in the x-direction and a plurality of portions 36b extending in the y-direction. Each portion 36b is arranged in a range exposed at the bottom surface of the corresponding trench 22. Each portion 36b is in contact with the gate insulating film 24 at the bottom surface of the trench 22. The electric field relaxation region 36 is arranged in a grid pattern by the plurality of portions 36a and the plurality of portions 36b. A plurality of openings 37 are provided in the electric field relaxation region 36. Each opening 37 is located at Figure 2 The openings 37 are dispersed and arranged in the plane shown. Specifically, each opening 37 is formed by two portions 36b adjacent in the x-direction and two portions 36a adjacent in the y-direction. Therefore, when the semiconductor substrate 12 is viewed from above, each opening 37 does not overlap with the trench 22. The intervals d1 between adjacent openings 37 in the x-direction are equal. In addition, the intervals d2 between adjacent openings 37 in the y-direction are equal. Each opening 37 extends from the upper end to the lower end of the electric field relaxation region 36. An n-type connection region 40 is arranged within each opening 37.

[0048] The SJ region 38 is arranged below the electric field relaxation region 36. The SJ region 38 includes a plurality of p-type column regions 38a and a plurality of n-type column regions 38b.

[0049] like Figure 3 As shown, when viewing the semiconductor substrate 12 from above, the p-type column regions 38a and the n-type column regions 38b extend linearly along the x-direction and are alternately arranged along the y-direction. The p-type impurity concentration in each p-type column region 38a is lower than the p-type impurity concentration in the electric field relaxation region 36. Each p-type column region 38a is arranged directly below and connected to a portion 36a of the electric field relaxation region 36. That is, when viewing the semiconductor substrate 12 from above, the p-type column regions 38a do not overlap with the openings 37.

[0050] like Figure 1 As shown, each n-type connection region 40 is arranged in the corresponding opening 37 as described above. Each n-type connection region 40 connects the n-type upper region 34 and the corresponding n-type column region 38b.

[0051] When viewing the semiconductor substrate 12 from above, each p-type connection region 42 extends linearly in the x-direction. Each p-type connection region 42 is positioned directly above the portion 36a of the electric field relaxation region 36. That is, when viewing the semiconductor substrate 12 from above, each p-type connection region 42 does not overlap with the openings 37. Each p-type connection region 42 extends upward from the upper surface of the electric field relaxation region 36. Each p-type connection region 42 connects the electric field relaxation region 36 to the body region 32. In other words, the electric field relaxation region 36 and the p-type column region 38a are connected to the source electrode 70 via each p-type connection region 42 and the body region 32.

[0052] The drift region 44 is n-type and contacts the SJ region 38 from below. The n-type impurity concentration of the drift region 44 is lower than that of the n-type upper region 34, the n-type connection region 40, and the n-type column region 38b.

[0053] The drain region 46 contacts the drift region 44 from below. The drain region 46 is exposed at the lower surface 12 b of the semiconductor substrate 12 . The drain region 46 makes ohmic contact with the drain electrode 72 . The n-type impurity concentration in the drain region 46 is higher than that in the drift region 44 .

[0054] Next, the operation of the semiconductor device 10 will be described. When the semiconductor device 10 is in use, a higher voltage is applied to the drain electrode 72 than to the source electrode 70. When a voltage equal to or higher than the gate threshold is applied to the gate electrode 26, a channel is formed in the body region 32 in contact with the gate insulating film 24, turning on the semiconductor device 10. When the voltage applied to the gate electrode 26 is reduced to below the gate threshold, the channel disappears, turning off the semiconductor device 10.

[0055] When semiconductor device 10 is in the off state, the potential of drain electrode 72 is much higher than that of source electrode 70. In this state, n-type upper region 34 and n-type connection region 40 have a potential close to that of drain electrode 72. Furthermore, as described above, electric field relaxation region 36 has a potential substantially equal to that of source electrode 70. Therefore, a depletion layer extends from electric field relaxation region 36 into n-type upper region 34 and n-type connection region 40. In particular, since electric field relaxation region 36 is positioned directly below trench 22, the depletion layer extending from electric field relaxation region 36 into n-type upper region 34 effectively suppresses electric field concentration near the lower end of trench 22.

[0056] Furthermore, in this embodiment, the openings 37 provided in the electric field relaxation region 36 are dispersed within a plane (xy plane) parallel to the upper surface 12a of the semiconductor substrate 12. This allows the n-type connection region 40 to be more finely divided within this plane compared to conventional structures in which p-type and n-type regions are alternately arranged in stripes. Therefore, even if the n-type impurity concentration in the n-type connection region 40 is increased, when the semiconductor device 10 is turned off, the depletion layer extends from the electric field relaxation region 36 to substantially the entire area within the n-type connection region 40. Thus, according to this semiconductor device 10, the n-type impurity concentration in the n-type connection region 40 can be sufficiently increased, thereby reducing the resistance of the n-type connection region 40, i.e., the on-resistance. In particular, in this embodiment, the intervals d1 and d2 between the openings 37 are equal. Thus, since the openings 37 are regularly arranged within this plane, the on-resistance can be made uniform across the entire area of the semiconductor device 10.

[0057] Furthermore, when semiconductor device 10 is in the off state, n-type column region 38b of SJ region 38 has a potential close to that of drain electrode 72, while p-type column region 38a has a potential approximately equal to that of source electrode 70. Consequently, a high reverse voltage is applied to the pn junction at the interface between p-type column region 38a and n-type column region 38b. Consequently, a depletion layer expands laterally (in the xy plane) from p-type column region 38a into n-type column region 38b. Furthermore, the depletion layer also expands laterally from n-type column region 38b into p-type column region 38a. This depletion layer maintains the voltage applied between drain electrode 72 and source electrode 70.

[0058] The p-type column regions 38a and n-type column regions 38b of the SJ region 38 extend linearly along the x-direction and are alternately arranged along the y-direction. Since the p-type column regions 38a and n-type column regions 38b are arranged in a stripe pattern, when the semiconductor device 10 is turned off, the p-type column regions 38a and n-type column regions 38b (i.e., the SJ region 38) are easily and evenly depleted. Consequently, this semiconductor device 10 can ensure a high withstand voltage. Furthermore, in this semiconductor device 10, since each p-type column region 38a is positioned so as not to overlap with the opening 37, the current path is not restricted by the p-type column regions 38a when the semiconductor device 10 is turned on. Consequently, current flows appropriately from the drain electrode 72 to the source electrode 70 via the n-type column regions 38b, the n-type connection region 40, and the n-type upper region 34, suppressing degradation in on-resistance. As described above, the semiconductor device 10 of this embodiment can ensure a high withstand voltage while reducing on-resistance.

[0059] Next, refer to Figures 4 to 7 The manufacturing method of the semiconductor device 10 is described. Figure 4 As shown, a semiconductor substrate 12x is prepared in which an n-type drift region 44 and an n-type semiconductor layer 50 having a higher n-type impurity concentration than the drift region 44 are sequentially formed on the upper surface of an n-type drain region 46. The semiconductor substrate 12x can be manufactured, for example, by sequentially growing the drift region 44 and the semiconductor layer 50 on the upper surface of the drain region 46 by epitaxial growth.

[0060] Then, if Figure 5 As shown, p-type impurities (such as aluminum, etc.) are selectively ion-implanted from the upper surface of the semiconductor layer 50. Thus, a plurality of p-type column regions 38a and Figure 2The multiple portions 36a in the electric field relaxation region 36 are shown. Here, by adjusting the p-type impurity implantation energy, p-type column regions 38a and portions 36a are formed so that p-type column regions 38a are located below corresponding portions 36a. Furthermore, by adjusting the p-type impurity dosage, p-type column regions 38a and portions 36a are formed so that the p-type impurity concentration in p-type column regions 38a is lower than that in portions 36a. Within the depth range where p-type column regions 38a are formed, the n-type semiconductor region adjacent to p-type column regions 38a becomes n-type column regions 38b.

[0061] Then, if Figure 6 As shown, p-type connection regions 42 are formed directly above portions 36a by ion implanting p-type impurities from the upper surface of semiconductor layer 50. Next, body regions 32 and source regions 30 are formed by selectively implanting p-type and n-type impurities.

[0062] Then, if Figure 7 As shown, a trench 22 is formed on the upper surface of the semiconductor layer 50, and a p-type impurity is ion-implanted into the bottom of the trench 22 to form a Figure 2 Here, the depth of the trench 22 and the energy of the p-type impurity injection are adjusted so that the portion 36b is formed in the same depth range as the portion 36a. Thus, when the semiconductor layer 50 is viewed from above, the electric field relaxation region 36 having a plurality of openings 37 is formed. In addition, within the depth range in which the electric field relaxation region 36 is formed, the n-type semiconductor region surrounded by the electric field relaxation region 36 becomes the n-type connection region 40. Then, the gate insulating film 24, the gate electrode 26, the interlayer insulating film 28, the source electrode 70, and the drain electrode 72 are formed by a conventionally known method, thereby Figure 1 The semiconductor device 10 shown is completed.

[0063] (Example 2)

[0064] The semiconductor device 100 of the second embodiment further includes an SJ region 138 compared to the first embodiment. Hereinafter, for the convenience of description, the SJ region 38 is referred to as the first SJ region 38, and the SJ region 138 is referred to as the second SJ region 138. In the second embodiment, Figure 8 As shown, the second SJ region 138 is in contact with the first SJ region 38 from the bottom side.

[0065] The second SJ region 138 includes a plurality of p-type column regions 138a and a plurality of n-type column regions 138b. Figure 8As shown, when viewing the semiconductor substrate 112 from above, the p-type column regions 138a and n-type column regions 138b extend linearly along the y-direction and are alternately arranged along the x-direction. Specifically, the p-type column regions 138a and n-type column regions 138b extend linearly in a direction perpendicular to the p-type column regions 38a and n-type column regions 38b of the first SJ region 38. Each p-type column region 138a is located below the corresponding trench 22. Each p-type column region 138a is spaced apart from the portion 36b of the electric field relaxation region 36. The p-type impurity concentration of each p-type column region 138a is lower than that of the electric field relaxation region 36. Each p-type column region 138a is connected to each other. In other words, the potential of each p-type column region 138a is approximately equal to the potential of the source electrode 70.

[0066] In the semiconductor device 100 of the second embodiment, the provision of the second SJ region 138 increases the overall length of the SJ region in the thickness direction (z-direction) of the semiconductor substrate 112, thereby ensuring a higher breakdown voltage. Furthermore, the p-type column region 38a and the n-type column region 38b are arranged orthogonally to the p-type column region 138a and the n-type column region 138b in the xy plane. Therefore, even if misalignment occurs between the first SJ region 38 and the second SJ region 138, variations in the current path area can be suppressed.

[0067] (Example 3)

[0068] The semiconductor devices 10 and 100 of Examples 1 and 2 are vertical MOSFETs with a trench gate structure, but the semiconductor device 200 of Example 3 is a vertical MOSFET with a planar gate structure. The semiconductor device 200 includes a semiconductor substrate 212, electrodes, an insulating film, and the like.

[0069] like Figure 9 As shown, a source electrode 270 and a gate electrode 226 are arranged on the upper surface 212a of the semiconductor substrate 212. The gate electrode 226 is arranged on the upper surface 212a of the semiconductor substrate 212 via a gate insulating film 224. The source electrode 270 is in contact with the upper surface 212a of the semiconductor substrate 212 in a portion where the gate insulating film 224 is not provided. The gate electrode 226 is insulated from the source electrode 270 by the gate insulating film 224. Figure 10 As shown in FIG. 2 , when the semiconductor substrate 212 is viewed from above, the gate electrode 226 extends in a lattice shape along the x-direction and the y-direction. Figure 10 In the figure, the source electrode 270 is omitted.

[0070] Inside the semiconductor substrate 212 , multiple source regions 230 , multiple body regions 232 , an n-type upper region 234 , an electric field relaxation region 236 , an SJ region 238 , multiple n-type connection regions 240 , multiple p-type connection regions 242 , a drift region 244 , and a drain region 246 are provided.

[0071] Each source region 230 is exposed on the upper surface 212 a of the semiconductor substrate 212 . Each source region 230 makes ohmic contact with the source electrode 270 .

[0072] Each body region 232 is exposed on the upper surface 212a of the semiconductor substrate 212. Each body region 232 extends from a position adjacent to a side surface of the source region 230 to the lower side of the source region 230. The body region 232 is in ohmic contact with the source electrode 270.

[0073] The n-type upper region 234 is exposed on the upper surface 212a of the semiconductor substrate 212. The n-type upper region 234 is provided adjacent to the side surface of the body region 232. The n-type upper region 234 is separated from the corresponding source region 230 by each body region 232.

[0074] The gate electrode 226 faces the n-type upper region 234 via the gate insulating film 224 . The gate electrode 226 faces the body region 232 located between the source region 230 and the n-type upper region 234 .

[0075] The electric field relaxation region 236 is arranged on the lower side of the n-type upper region 234. Figure 11 As shown, a plurality of openings 237 are provided in the electric field relaxation region 236. When the semiconductor substrate 212 is viewed from above, each opening 237 has a substantially circular shape. Figure 11 The openings 237 are dispersed within the plane shown. When the semiconductor substrate 212 is viewed from above, each opening 237 is located at a position overlapping the gate electrode 226 (i.e., directly below the gate electrode 226). Each opening 237 extends from the upper end to the lower end of the electric field relaxation region 236. An n-type connection region 240 is disposed within each opening 237.

[0076] The SJ region 238 is arranged below the electric field relaxation region 236. The SJ region 238 includes a plurality of p-type column regions 238a and a plurality of n-type column regions 238b.

[0077] like Figure 12As shown, when viewing the semiconductor substrate 212 from above, the p-type column regions 238a and the n-type column regions 238b extend linearly along a direction intersecting both the x-axis and the y-axis (hereinafter referred to as the s-direction) and are alternately arranged along a direction perpendicular to the s-direction (hereinafter referred to as the t-direction). The p-type impurity concentration of each p-type column region 238a is lower than the p-type impurity concentration of the electric field relaxation region 236. Each p-type column region 238a is connected to the electric field relaxation region 236 directly below the electric field relaxation region 236. In other words, when viewing the semiconductor substrate 212 from above, the p-type column regions 238a do not overlap with the openings 237. Furthermore, as in Example 1, the spacing between adjacent openings 237 in the s-direction is equal, and the spacing between adjacent openings 237 in the t-direction is equal.

[0078] As described above, each n-type connection region 240 is disposed within the corresponding opening 237. The n-type impurity concentration of each n-type connection region 240 is higher than the n-type impurity concentration of the n-type upper region 234. However, the n-type impurity concentration of each n-type connection region 240 may be substantially equal to the n-type impurity concentration of the n-type upper region 234. Each n-type connection region 240 connects the n-type upper region 234 to the corresponding n-type column region 238b.

[0079] Each p-type connection region 242 extends from a position exposed on the upper surface 212a of the semiconductor substrate 212 through the source region 230 and the body region 232 to the upper surface of the electric field relaxation region 236. Each p-type connection region 242 connects the source electrode 270 to the electric field relaxation region 236.

[0080] The structures of the drift region 244 and the drain region 246 are the same as those in the first embodiment.

[0081] In the semiconductor device 200 of Example 3, as in Example 1, the electric field relaxation region 236 and the SJ region 238 achieve both high breakdown voltage and reduced on-resistance. Furthermore, in this embodiment, each opening 237 is positioned to overlap the gate electrode 226 when the semiconductor substrate 212 is viewed from above. Specifically, each opening 237 is positioned to overlap the n-type upper region 234 facing the gate electrode 226. Consequently, in this semiconductor device 200, the current path from the drain electrode 272 through the drain region 246, the drift region 244, the n-type column region 238b, the n-type connection region 240, and the n-type upper region 234 is shortened, further reducing on-resistance.

[0082] (Example 4)

[0083] The semiconductor device 300 of the fourth embodiment is a Schottky barrier diode and includes a semiconductor substrate 312 , electrodes, and the like.

[0084] like Figure 13 As shown, an upper electrode 370 is provided on the upper surface 312 a of the semiconductor substrate 312 . The upper electrode 370 covers substantially the entire area of the upper surface 312 a of the semiconductor substrate 312 .

[0085] An n-type upper region 334 , an electric field relaxation region 336 , an SJ region 338 , multiple n-type connection regions 340 , multiple p-type connection regions 342 , a drift region 344 , and an n-type region 346 are provided within the semiconductor substrate 312 .

[0086] The n-type upper region 334 is exposed at the upper surface 312a of the semiconductor substrate 312. Figure 14 As shown in FIG. 3 , when the semiconductor substrate 312 is viewed from above, the n-type upper region 334 extends in a lattice shape along the x-direction and the y-direction. The n-type upper region 334 forms a Schottky junction with the upper electrode 370. Figure 14 The upper electrode 370 is omitted in the figure.

[0087] The electric field relaxation region 336 is arranged on the lower side of the n-type upper region 334. Figure 15 As shown, a plurality of openings 337 are provided in the electric field relaxation region 336. When the semiconductor substrate 312 is viewed from above, each opening 337 has a substantially circular shape. Figure 15 The openings 337 are dispersed within the plane shown. When viewing the semiconductor substrate 312 from above, each opening 337 is located at a position overlapping the upper electrode 370 and the Schottky junction 350 of the n-type upper region 334 (i.e., directly below the n-type upper region 334). Each opening 337 extends from the upper end to the lower end of the electric field relaxation region 336. An n-type connection region 340 is disposed within each opening 337.

[0088] The SJ region 338 is arranged below the electric field relaxation region 336. The SJ region 338 includes a plurality of p-type column regions 338a and a plurality of n-type column regions 338b.

[0089] like Figure 16As shown, when viewing the semiconductor substrate 312 from above, the p-type column regions 338a and the n-type column regions 338b extend linearly along a direction intersecting both the x-axis and the y-axis (hereinafter referred to as the u-direction) and are alternately arranged along a direction perpendicular to the u-direction (hereinafter referred to as the v-direction). The p-type impurity concentration of each p-type column region 338a is lower than the p-type impurity concentration of the electric field relaxation region 336. Each p-type column region 338a is connected to the electric field relaxation region 336 directly below the electric field relaxation region 336. That is, when viewing the semiconductor substrate 312 from above, the p-type column regions 338a do not overlap with the openings 337. Furthermore, as in Example 1, the spacing between adjacent openings 337 in the u-direction is equal, and the spacing between adjacent openings 337 in the v-direction is equal.

[0090] As described above, each n-type connection region 340 is disposed within the corresponding opening 337. The n-type impurity concentration of each n-type connection region 340 is higher than the n-type impurity concentration of the n-type upper region 334. However, the n-type impurity concentration of each n-type connection region 340 may be substantially equal to the n-type impurity concentration of the n-type upper region 334. Each n-type connection region 340 connects the n-type upper region 334 to the corresponding n-type column region 338b.

[0091] Each p-type connection region 342 extends from a position exposed on the upper surface 312a of the semiconductor substrate 312 to the upper surface of the electric field relaxation region 336. Each p-type connection region 342 is provided adjacent to a side surface of the n-type upper region 334. Each p-type connection region 342 connects the upper electrode 370 to the electric field relaxation region 336.

[0092] The structures of the drift region 344 and the n-type region 346 are the same as those of the drift region 44 and the drain region 46 in the first embodiment, respectively.

[0093] Next, the operation of semiconductor device 300 will be described. During operation of semiconductor device 300, a higher voltage is applied to upper electrode 370 than to lower electrode 372. This lowers the Schottky barrier between upper electrode 370 and n-type upper region 334. Consequently, electrons injected from lower electrode 372 into n-type upper region 334 via n-type region 346, drift region 344, n-type column region 338b, and n-type connection region 340 bypass the lowered Schottky barrier and flow toward upper electrode 370, turning semiconductor device 300 on.

[0094] In the semiconductor device 300 of Example 4, as in Example 1, the electric field relaxation region 336 and the SJ region 338 achieve both high breakdown voltage and reduced on-resistance. Furthermore, in this embodiment, each opening 337 is positioned to overlap with the Schottky junction 350 when the semiconductor substrate 312 is viewed from above. Consequently, in this semiconductor device 300, the current path from the Schottky junction 350 through the n-type upper region 334, the n-type connection region 340 within the opening 337, the n-type column region 338b, the drift region 344, and the n-type region 346 is shortened, further reducing on-resistance.

[0095] While the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and alterations of the specific examples described above.

[0096] In the first embodiment described above, the openings 37 are regularly arranged along the x-direction and the y-direction. However, when the semiconductor substrate 12 is viewed from above, the openings 37 may be arranged in the x-direction and the y-direction as long as they do not overlap with the p-type column region 38a. Figure 2 The shapes of the openings 37 and the like are not particularly limited. They may be rectangular or circular as in the above-mentioned embodiments, or they may be other shapes.

[0097] The second SJ region 138 described in the second embodiment can also be applied to the third and fourth embodiments.

[0098] In Example 2, the p-type column region 138a and the n-type column region 138b of the second SJ region 138 do not need to be perpendicular to the p-type column region 38a and the n-type column region 38b of the first SJ region 38. The p-type column region 138a and the n-type column region 138b may extend across the p-type column region 38a and the n-type column region 38b.

[0099] In the first embodiment described above, the p-type column region 38a of the SJ region 38 may not be in contact with the electric field relaxation region 36. This is also true in other embodiments. In the second embodiment, the second SJ region 138 may not be in contact with the first SJ region 38.

[0100] In the first embodiment, the p-type contact region 42 may not be provided. Instead, the electric field relaxation region 36 may be connected to the source electrode 70 at a position not shown. The same applies to the other embodiments.

[0101] While the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technologies described in the claims include various variations and modifications of the specific examples exemplified above. The technical elements described in this specification or the drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies exemplified in this specification or the drawings achieve multiple objectives simultaneously, and achieving just one of these objectives alone is technically useful.

Claims

1. A semiconductor device, characterized in that: have: semiconductor substrates; an upper electrode provided on the upper surface of the semiconductor substrate; and A lower electrode is provided on the lower surface of the semiconductor substrate; The semiconductor device is configured such that a current flows between the upper electrode and the lower electrode; The semiconductor substrate has: a first conductivity type upper region; a second conductivity type electric field relaxation region disposed below the first conductivity type upper region and connected to the upper electrode; a super junction region disposed below the electric field relaxation region; as well as a plurality of first conductive type connection regions; The super junction region comprises a plurality of second conductivity type column regions and a plurality of first conductivity type column regions; When the semiconductor substrate is viewed from above, the second conductivity type column regions and the first conductivity type column regions extend linearly along a first direction and are alternately arranged along a second direction orthogonal to the first direction. The electric field relaxation region is provided with a plurality of openings extending from the upper end to the lower end of the electric field relaxation region; The plurality of openings are dispersedly arranged in a plane parallel to the upper surface of the semiconductor substrate; Each of the first conductive type connection regions is disposed in the corresponding opening portion, connecting the first conductive type upper region to the corresponding first conductive type column region; The second conductivity type impurity concentration of each of the second conductivity type column regions is lower than the second conductivity type impurity concentration of the electric field relaxation region; When the semiconductor substrate is viewed from above, each of the second conductivity type column regions does not overlap with each of the openings.

2. The semiconductor device according to claim 1, wherein When the semiconductor substrate is viewed from above, the semiconductor device is arranged to form a plurality of rows in which the openings are arranged at intervals along the first direction; The columns are spaced apart in the second direction. In the first direction, the intervals between adjacent openings are equal; In the second direction, the intervals between adjacent columns are equal.

3. The semiconductor device according to claim 1, wherein The super junction region is a first super junction region; The second conductivity type column region is the first second conductivity type column region; The first conductivity type column region is a first first conductivity type column region; further comprising a second super junction region disposed below the first super junction region; The second super junction region comprises a plurality of second second conductivity type column regions and a plurality of second first conductivity type column regions; When the semiconductor substrate is viewed from above, the second second-conductivity-type column regions and the second first-conductivity-type column regions extend linearly along a third direction intersecting the first direction, and are alternately arranged along a fourth direction orthogonal to the third direction. The second conductivity type impurity concentration of each of the second second conductivity type column regions is lower than the second conductivity type impurity concentration of the electric field relaxation region.

4. The semiconductor device according to claim 1, wherein A second conductive type connection region is provided, which extends upward from the upper surface of the electric field relaxation region and connects the electric field relaxation region and the upper electrode.

5. The semiconductor device according to any one of claims 1 to 4, wherein Also features: A groove is provided on the upper surface of the semiconductor substrate; a gate insulating film covering the inner surface of the trench; and a gate electrode provided in the trench and insulated from the semiconductor substrate by the gate insulating film; The semiconductor substrate further comprises: a first conductivity type source region exposed on the upper surface of the semiconductor substrate and in contact with the gate insulating film; and a second conductive type body region in contact with the gate insulating film below the source region and separating the first conductive type upper region from the source region; The first conductivity type upper region is in contact with the gate insulating film on the lower side of the body region.

6. The semiconductor device according to claim 5, wherein When the semiconductor substrate is viewed from above, each of the openings does not overlap with the trench.

7. The semiconductor device according to any one of claims 1 to 4, wherein further comprising a gate electrode provided on the upper surface of the semiconductor substrate via a gate insulating film; The semiconductor substrate further comprises: a first conductivity type source region exposed on the upper surface of the semiconductor substrate; and a second conductivity type body region, provided adjacent to the source region and exposed on the upper surface of the semiconductor substrate; The first conductivity type upper region is provided adjacent to the body region, separated from the source region by the body region, and exposed on the upper surface of the semiconductor substrate; The gate electrode faces the first conductivity type upper region via the gate insulating film, and faces the body region located between the source region and the first conductivity type upper region.

8. The semiconductor device according to claim 7, wherein When the semiconductor substrate is viewed from above, each of the openings overlaps with the gate electrode.

9. The semiconductor device according to any one of claims 1 to 4, wherein The first conductivity type upper region is exposed on the upper surface of the semiconductor substrate; The upper electrode and the upper surface of the semiconductor substrate form a Schottky junction.

10. The semiconductor device according to claim 9, wherein When the semiconductor substrate is viewed from above, each of the openings overlaps with a Schottky junction surface.

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