Semiconductor device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor chips, in particular to a semiconductor device and a preparation method thereof. The semiconductor device comprises a first region and a second region located around the first region, the semiconductor device comprises a substrate, a functional layer and a drift layer, the functional layer is arranged on the substrate, and the drift layer is arranged on the side, away from the substrate, of the functional layer. The doping type of the drift layer is the same as that of the functional layer, the functional layer comprises a first sub-functional layer and a second sub-functional layer, the first sub-functional layer is arranged in the second region, the second sub-functional layer is arranged in the first region, and the first sub-functional layer is arranged in the second region. And the doping concentration of the second sub-functional layer is greater than that of the first sub-functional layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] As one of the core components of modern power electronics systems, power semiconductor devices undertake key functions such as the conversion, control and management of electric energy. They are widely used in new energy vehicles and rail transit electric drives, power systems, infrastructure power supply for communications and data centers, consumer electronics and general power supplies, special equipment and other fields.

[0003] Power semiconductor devices can be categorized as lateral or vertical based on the primary direction of current flow within the device. Vertical power semiconductor devices offer numerous advantages, including high blocking voltage, low conduction losses, and enhanced heat dissipation, and have been widely adopted and developed in medium- and high-power applications.

[0004] However, in actual device design and manufacturing, its withstand voltage performance is often limited by many factors. Therefore, an improved semiconductor device is expected to solve the above problems. Summary of the Invention

[0005] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, aiming to solve the voltage resistance problem of the semiconductor device.

[0006] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions: In one aspect, a semiconductor device is provided, comprising a first region and a second region surrounding the first region. The semiconductor device comprises a substrate, a functional layer, and a drift layer. The functional layer is disposed on the substrate. The drift layer is disposed on a side of the functional layer away from the substrate, and the drift layer has the same doping type as the functional layer. The functional layer comprises a first sub-functional layer and a second sub-functional layer, the first sub-functional layer being disposed in the second region, and the second sub-functional layer being disposed in the first region. The doping concentration of the second sub-functional layer is greater than the doping concentration of the first sub-functional layer.

[0007] The semiconductor device includes a first region and a second region located around the first region. A functional layer is provided in the semiconductor device, and the functional layer includes a second sub-functional layer located in the first region and a first sub-functional layer located in the second region. The first sub-functional layer can affect the size of the depletion region of the second region in a third direction. The doping concentration of the first sub-functional layer is lower than the doping concentration of the second sub-functional layer, so as to increase the thickness of the effective drift region of the second region, thereby increasing the size of the depletion region of the second region in the third direction. This can effectively reduce the surface electric field of the second region and improve the voltage resistance of the second region of the semiconductor device.

[0008] The thickness and / or doping concentration of the second subfunctional layer can affect the size of the depletion region in the first region in the third direction. The presence of the second subfunctional layer increases the sum of the sizes of the second subfunctional layer and the drift layer in the third direction, which also increases the size of the depletion region in the first region in the third direction. In this case, by increasing the doping concentration of the second subfunctional layer so that the doping concentration of the second subfunctional layer is greater than that of the first subfunctional layer, the size of the depletion region in the first region in the third direction can be effectively reduced. Furthermore, the doping concentration of the second subfunctional layer being greater than that of the drift layer can further reduce the thickness of the effective drift region in the first region, thereby reducing the size of the depletion region in the first region in the third direction, thereby effectively improving the conductive performance of the first region.

[0009] In a feasible embodiment, the functional layer also includes: at least one third sub-functional layer, arranged in the first region, the doping concentration of the third sub-functional layer is less than the doping concentration of the second sub-functional layer; the functional layer includes a plurality of the second sub-functional layers, and the third sub-functional layer is arranged between at least two adjacent second sub-functional layers.

[0010] During the formation of the second sub-functional layer, processes such as ion implantation can be used, which can cause lattice damage in the second sub-functional layer, thereby affecting the epitaxial growth quality of the drift layer. By reducing the area of the second sub-functional layer, the lattice damage to the functional layer can be effectively reduced, the growth quality of the drift layer can be improved, and thus the electrical performance of the semiconductor device can be improved.

[0011] In a feasible embodiment, the second sub-functional layer and the third sub-functional layer both extend along the first direction, and the second sub-functional layer and the third sub-functional layer are alternately arranged along the second direction; the first direction and the second direction are both perpendicular to the thickness direction of the substrate, and the first direction and the second direction are perpendicular to each other.

[0012] In a feasible embodiment, among the multiple second sub-functional layers, a portion of the second sub-functional layers extends along the first direction, and another portion of the second sub-functional layers extends along the second direction, and the portion of the second sub-functional layers and the another portion of the second sub-functional layers intersect with each other to form a network structure; the third sub-functional layer is located in the opening of the network structure.

[0013] In a feasible embodiment, the second sub-functional layer is an annular structure, and a plurality of the second sub-functional layers are sequentially nested and spaced apart; the third sub-functional layer is located between two radially adjacent second sub-functional layers of the second sub-functional layer.

[0014] In a feasible embodiment, the first sub-functional layer is also disposed in the first region, and the first sub-functional layer is located around the second sub-functional layer.

[0015] In a feasible embodiment, the first sub-functional layer may also be located in the first region, that is, the area of the first sub-functional layer is larger than that of the second region. In this case, part of the first sub-functional layer may extend to the first region.

[0016] In a feasible embodiment, the doping concentration of the second sub-functional layer is greater than or equal to the doping concentration of the drift layer.

[0017] In a feasible embodiment, the method further includes: a buffer layer, wherein the buffer layer is located between the substrate and the functional layer, the doping type of the buffer layer is the same as the doping type of the functional layer, and the buffer layer is in contact with the functional layer.

[0018] The buffer layer can prevent the depletion layer of the semiconductor device from extending toward the substrate in the reverse blocking state, thereby preventing substrate defects from affecting the long-term reliability of the semiconductor device.

[0019] In one feasible embodiment, the device further includes at least one junction termination structure and a passivation layer. The junction termination structure is disposed on a side of the drift layer away from the substrate; the junction termination structure is disposed in the second region and surrounds the first region. The passivation layer is disposed on a side of the drift layer away from the substrate and is located in the second region; the passivation layer covers the at least one junction termination structure.

[0020] The junction termination structure can reduce the surface electric field of the second region of the semiconductor device, alleviate the electric field concentration phenomenon in the second region, thereby reducing the breakdown risk of the second region, and thus improving the voltage resistance of the semiconductor device.

[0021] The passivation layer can electrically isolate the junction terminal structure and the second metal layer to prevent short circuit damage to the semiconductor device. In addition, the passivation layer can regulate the electric field, improve the electric field concentration phenomenon to a certain extent, and improve the voltage resistance of the second region of the semiconductor device.

[0022] In a feasible embodiment, it also includes: a first doped region, which is arranged on a side of the drift layer away from the substrate and is located in the first area; the doping type of the first doped region is different from the doping type of the drift layer; a first metal layer, which is arranged on a side of the substrate away from the drift layer; and a second metal layer, which is arranged on a side of the first doped layer away from the substrate and is in contact with the first doped region.

[0023] As a possible implementation manner, the semiconductor power device may be a diode.

[0024] In a feasible embodiment, it also includes: a source region, which is arranged on a side of the drift layer away from the substrate and is located in the first area; the doping type of at least part of the source region is different from the doping type of the drift layer; a gate, which is arranged in the first area, is located on a side of the drift layer away from the substrate and is connected to a part of the source region; and a drain, which is arranged on a side of the substrate away from the drift layer.

[0025] As a possible implementation, the semiconductor power device may be a field effect transistor.

[0026] On the other hand, a method for preparing a semiconductor device is provided, the method comprising: forming an initial functional layer on one side of a substrate; performing ion implantation on a target area of the initial functional layer to form a second sub-functional layer, and forming a first sub-functional layer in an area of the initial functional layer other than the target area; the first sub-functional layer surrounds the second sub-functional layer, and the first sub-functional layer and the second sub-functional layer constitute a functional layer; and forming a drift layer on a side of the functional layer away from the substrate.

[0027] It can be understood that the beneficial effects achieved by the method for preparing the semiconductor device provided by the above embodiment of the present disclosure can be referred to the beneficial effects of the semiconductor device described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0029] Figure 1 A structural diagram of an electronic device provided according to some embodiments; Figure 2 A structural diagram of a chip provided according to some embodiments; Figure 3 A structural diagram of a semiconductor device provided according to some embodiments; Figure 4 is a structural diagram of another semiconductor device provided according to some embodiments; Figure 5 for Figure 4 AA direction view of the middle functional layer; Figure 6 for Figure 3The local doping concentration distribution diagram of the semiconductor device B region shown; Figure 7 for Figure 4 The local doping concentration distribution diagram of the semiconductor device B region shown; Figure 8 is a cathode voltage-cathode current curve of a semiconductor device; Figure 9 for Figure 3 The electric field distribution diagram of the semiconductor device B region shown; Figure 10 for Figure 4 The electric field distribution diagram of the semiconductor device B region shown; Figure 11 is a lateral electric field distribution curve of a semiconductor device; Figure 12 It is the longitudinal electric field distribution curve of the semiconductor device; Figure 13 for Figure 3 The distribution diagram of avalanche breakdown impact ionization rate of semiconductor devices shown; Figure 14 for Figure 4 The distribution diagram of avalanche breakdown impact ionization rate of semiconductor devices shown; Figure 15 is a structural diagram of another semiconductor device provided according to some embodiments; Figure 16 for Figure 15 An AA-directional view of the middle functional layer; Figure 17 for Figure 15 Another AA-direction view of the middle functional layer; Figure 18 for Figure 15 Another AA-direction view of the middle functional layer; Figure 19 for Figure 15 Another AA-direction view of the middle functional layer; Figure 20 A structural diagram of a semiconductor device provided according to some embodiments; Figure 21 A flow chart of a method for manufacturing a semiconductor device according to some embodiments; Figure 22 A flow chart of another method for manufacturing a semiconductor device according to some embodiments; Figures 23 to 27 for Figure 22 Structural diagram of the semiconductor structure corresponding to different steps in the preparation method shown. DETAILED DESCRIPTION

[0030] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0031] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0032] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0033] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0034] When describing some embodiments, the term "connected" and its derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0035] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0036] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0037] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values may, in practice, be based on additional conditions or values beyond those stated.

[0038] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0039] In the context of this disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers, and “over” or “over” means not only “over” or “above” something, but also includes “over” or “above” something with no intervening features or layers (i.e., directly on something).

[0040] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0041] As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0042] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0043] Figure 1 FIG. 1 is a structural diagram of an electronic device provided according to some embodiments. Figure 1 As shown, an embodiment of the present disclosure provides an electronic device 1000. The electronic device 1000 can be a product or component with a power conversion function, such as a power conversion system for an electric vehicle, a charging device for a mobile phone, or a power adapter for a laptop computer. The electronic device 1000 can also be different types of user equipment or terminal devices, such as a laptop computer, a tablet computer, a mobile phone, a wearable device, and an in-vehicle device. It can also be a power amplification device used in the above electronic devices. It should be understood that the electronic device 1000 can also be a device or component with a signal receiving / transmitting function in a device such as an amplifier, a modulator, a base station, or a radar. The embodiments of the present application do not place any special restrictions on the specific form of the above electronic device 1000.

[0044] The following uses the electronic device 1000 as an example of an electronic device having a power conversion function to schematically illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure is not limited to this, and any other display device can also be considered as long as the same technical concept is applied.

[0045] exist Figure 1 In the embodiment, the electronic device 1000 includes a chip 1001 and a circuit board 1002, wherein the chip 1001 is coupled to the circuit board 1002, and the circuit board 1002 is configured to supply power to the chip 1001 and transmit signals. Figure 2 , Figure 2 FIG1 is a structural diagram of a chip according to some embodiments. The chip 1001 includes a semiconductor device 100 and a package substrate 200 , and the semiconductor device 100 is coupled to the package substrate 200 .

[0046] Figure 3 FIG1 is a structural diagram of a semiconductor device according to some embodiments. The semiconductor device 100 may be a diode and includes a substrate 101 , a buffer layer 102 , a drift layer 104 , and a first doped layer 105 .

[0047] The buffer layer 102 is disposed on one side of the substrate 101 , the drift layer 104 is disposed on a side of the buffer layer 102 away from the substrate 101 , and the first doped layer 105 is disposed on a side of the drift layer 104 away from the drift layer 104 .

[0048] In some feasible embodiments, the semiconductor device 100 further includes a first doped layer 105, a first metal layer 201, and a second metal layer 202. The first doped layer 105 is disposed on a side of the drift layer 104 away from the substrate 101 and is located in the first region Q1. The doping type of the first doped layer 105 is different from that of the drift layer 104. The first metal layer 201 is disposed on a side of the substrate 101 away from the drift layer 104 and is in contact with the substrate 101. The second metal layer 202 is disposed on a side of the first doped layer 105 away from the substrate 101 and is in contact with the first doped layer 105.

[0049] In some feasible embodiments, the semiconductor device 100 further includes a passivation layer 203 . The passivation layer 203 is disposed on a side of the drift layer 104 away from the substrate 101 and located in the second region Q2 . The passivation layer 203 contacts the second metal layer 202 .

[0050] The first region Q1 may be an active region of a power device, and the second region Q2 may be a terminal region of the power device. The first region Q1 mainly functions to conduct current and withstand voltage to achieve the electrical function of the semiconductor device 100 .

[0051] In some feasible embodiments, a transition region is further included between the first region Q1 and the second region Q2 , and the transition region serves to connect the terminal region and the active region, so that the first region Q1 can be smoothly connected to the second region Q2 .

[0052] The voltage resistance of the semiconductor device 100 is limited by many factors. The applicant has discovered that the longitudinal voltage resistance characteristics of the first region Q1 and the second region Q2 are essentially the same. However, because the second region Q2 is located at the edge of the chip, it is affected by the lateral voltage. Under the combined effects of the longitudinal and lateral voltages, the second region Q2 experiences a greater electric field, making it more susceptible to breakdown and other problems. In light of this, the present disclosure proposes an improved semiconductor device 100 to enhance the voltage resistance of the semiconductor device 100.

[0053] Figure 4 FIG1 is a structural diagram of another semiconductor device according to some embodiments, wherein the semiconductor device 100 includes a substrate 101, a functional layer 103, and a drift layer 104. The semiconductor device 100 may include a first region Q1 and a second region Q2 located around the first region Q1.

[0054] The material of the substrate 101 includes any one of silicon (Si), silicon carbide (SiC) or gallium nitride (GaN). Exemplarily, the doping type of the substrate 101 is N-type.

[0055] The functional layer 103 is disposed on one side of the substrate 101. The functional layer 103 includes a first sub-functional layer 103a and a second sub-functional layer 103b. The first sub-functional layer 103a is disposed in the first region Q1, and the second sub-functional layer 103b is disposed in the second region Q2. The second sub-functional layer 103b has a higher doping concentration than the first sub-functional layer 103a. Exemplarily, the functional layer 103 is doped with an N-type.

[0056] See also Figure 5 , Figure 5 for Figure 4 The area of the second sub-functional layer 103b may be smaller than or equal to the area of the first region Q1. When the area of the second sub-functional layer 103b is smaller than the area of the first region Q1, part of the first sub-functional layer 103a may extend to the first region Q1.

[0057] The drift layer 104 is disposed on a side of the functional layer 103 away from the substrate 101, and the doping type of the drift layer 104 is the same as the doping type of the functional layer 103. Exemplarily, the doping type of the drift layer 104 is N-type.

[0058] See also Figure 6 and Figure 7 , Figure 6 for Figure 3 The local doping concentration distribution diagram of the semiconductor device B region is shown. Figure 7 for Figure 4 The local doping concentration distribution diagram of the semiconductor device B area is shown. Figure 6 and Figure 7 In FIG, the vertical axis is the size of the semiconductor device 100 in the third direction z, in micrometers, with the surface of the drift layer 104 away from the substrate 101 as the zero point. Figure 3 and Figure 6 It can be seen that the size of the drift layer 104 in the first region Q1 along the third direction z is about 4.7 nanometers, and the size of the drift layer 104 in the second region Q2 along the third direction z is about 4.7 nanometers. Figure 4 and Figure 7 It can be seen that the size of the drift layer 104 in the first region Q1 in the third direction z is approximately 4.7 nanometers, and the sum of the sizes of the drift layer 104 in the second region Q2 and the first sub-functional layer 103a in the third direction z is approximately 6 nanometers. Therefore, the existence of the first sub-functional layer 103a can increase the effective drift region thickness of the semiconductor device 100 in the second region Q2, so that the size of the depletion region of the second region Q2 in the third direction z is larger than the size of the depletion region of the first region Q1 in the third direction z.

[0059] For example, see Figure 8 , Figure 8is the cathode voltage-cathode current curve of the semiconductor device, Figure 9 In the figure, the horizontal axis is the cathode voltage in volts (V), the vertical axis is the cathode current in amperes (A), and the solid line is Figure 3 The voltage-current curve of the semiconductor device 100 is shown in FIG. Figure 4 The voltage-current curve of the semiconductor device 100 is shown in FIG. 1 , where the exemplary first metal layer 201 is a cathode. It can be seen that when the cathode current is greater than 10-23 amperes, Figure 4 The cathode voltage of the semiconductor device 100 is shown to be greater than Figure 3 The cathode voltage of the semiconductor device 100 is shown, and thus Figure 4 The semiconductor device 100 shown has better voltage resistance.

[0060] See also Figure 9 and Figure 10 , Figure 9 for Figure 3 The electric field distribution diagram of the semiconductor device B area is shown. Figure 10 for Figure 4 The electric field distribution diagram of the semiconductor device B area is shown. Figure 9 and Figure 10 The electric field distribution diagram of the semiconductor device 100 when the anode voltage is 900 volts is shown in FIG. Figure 3 and Figure 9 As you can see, Figure 3 The electric field of the semiconductor device 100 shown is mainly distributed in the drift layer 104. Figure 4 and Figure 10 As you can see, Figure 4 The semiconductor device 100 shown is not only distributed in the drift layer 104, but also in the first sub-functional layer 103a. Figure 9 , Figure 10 The orange and yellow areas used to represent high voltage are smaller, indicating that Figure 4 The semiconductor device 100 shown can improve the electric field concentration phenomenon in the second region Q2 , making the electric field distribution in the second region Q2 more uniform, thereby improving the withstand voltage of the second region Q2 of the semiconductor device 100 .

[0061] See also Figure 11 and Figure 12 , Figure 11 is the lateral electric field distribution curve of the semiconductor device, Figure 12 This is a graph showing the longitudinal electric field distribution of a semiconductor device. Figure 11 , the horizontal axis is the size of the semiconductor device 100 in the second direction x, in micrometers (µm), and the vertical axis is the electric field of the semiconductor device 100 at a depth of 0.5 micrometers in the first direction y, in volts per centimeter (V / cm). Figure 12 In the figure, the horizontal axis is the size of the semiconductor device 100 in the first direction y, in micrometers (µm), and the vertical axis is the electric field of the semiconductor device 100 at a depth of 0.5 micrometers in the second direction x, in volts per centimeter (V / cm). Figure 3 The electric field distribution curve of the semiconductor device 100 is shown in FIG. Figure 4 The electric field distribution curve of the semiconductor device 100 is shown in FIG. Combine Figure 3 、 Figure 4 as well as Figure 11 It can be seen that at about 26 microns on the horizontal axis, Figure 4 The peak electric field of the semiconductor device 100 is about 1.8×10 6 V / cm. Figure 3 The peak electric field of the semiconductor device 100 is about 2.3×10 6 V / cm. Figure 4 The semiconductor device 100 shown has a lower lateral peak electric field, which is beneficial to improving the voltage resistance of the semiconductor device 100 .

[0062] Combine Figure 3 、 Figure 4 as well as Figure 12 It can be seen that when the horizontal axis is greater than or equal to 3 microns, Figure 4 The electric field of the semiconductor device 100 shown is equal to Figure 3 The semiconductor device 100 shown, Figure 4 The electric field of the semiconductor device 100 shown is improved, and the overall electric field distribution is more uniform, which is beneficial to reducing the electric field concentration phenomenon of the semiconductor device 100 and improving the voltage resistance of the semiconductor device 100.

[0063] See also Figure 13 and Figure 14 , Figure 13 for Figure 3 The distribution diagram of avalanche breakdown collision ionization rate of semiconductor devices shown in the figure is as follows: Figure 14 for Figure 4 The distribution diagram of the avalanche breakdown collision ionization rate of the semiconductor device shown. For example, the avalanche breakdown is when the cathode current is equal to 10-19 amperes. Figure 3 and Figure 13 , you can see, Figure 3 The highest point of the impact ionization rate of the semiconductor device 100 is located at the edge of the second region Q2. Figure 4 and Figure 14 As you can see, Figure 4 The highest point of the impact ionization rate of the semiconductor device 100 is located on a side of the first doping layer 105 in the first region Q1 close to the substrate 101 . Figure 4The breakdown point of the semiconductor device 100 shown is located inside the semiconductor device 100 , which is beneficial to protecting the surface structure of the semiconductor device 100 and improving the reliability of the semiconductor device 100 .

[0064] To summarize, the semiconductor device 100 includes a first region Q1 and a second region Q2 located around the first region Q1. A functional layer 103 is provided in the semiconductor device 100. The functional layer 103 includes a second sub-functional layer 103b located in the first region Q1 and a first sub-functional layer 103a located in the second region Q2. The first sub-functional layer 103a can affect the size of the depletion region of the second region Q2 in the third direction z. The doping concentration of the first sub-functional layer 103a is lower than the doping concentration of the second sub-functional layer 103b, so as to increase the thickness of the effective drift region of the second region Q2, thereby increasing the size of the depletion region of the second region Q2 in the third direction z. This can effectively reduce the surface electric field of the second region Q2 and improve the voltage resistance of the second region Q2 of the semiconductor device 100.

[0065] The thickness and / or doping concentration of the second subfunctional layer 103b can affect the size of the depletion region of the first region Q1 in the third direction z. The presence of the second subfunctional layer 103b increases the sum of the sizes of the second subfunctional layer 103b and the drift layer 104 in the third direction z, which also increases the size of the depletion region of the first region Q1 in the third direction z. In this case, by increasing the doping concentration of the second subfunctional layer 103b so that the doping concentration of the second subfunctional layer 103b is greater than that of the first subfunctional layer 103a, the size of the depletion region of the first region Q1 in the third direction z can be effectively reduced. Furthermore, the doping concentration of the second subfunctional layer 103b being greater than that of the drift layer 104 can further reduce the thickness of the effective drift region of the first region Q1, thereby reducing the size of the depletion region of the first region Q1 in the third direction z, thereby effectively improving the conduction performance of the first region Q1.

[0066] Continue to see Figure 4 In some feasible embodiments, the semiconductor device 100 further includes a buffer layer 102, which is located between the substrate 101 and the functional layer 103. The buffer layer 102 has the same doping type as the functional layer 103, and the buffer layer 102 is in contact with the functional layer 103. The buffer layer 102 has the same doping type as the drift layer 104. Exemplarily, the buffer layer 102 has an N-type doping type.

[0067] The buffer layer 102 can block the depletion layer of the semiconductor device 100 from extending toward the substrate 101 in the reverse blocking state, thereby preventing defects in the substrate 101 from affecting the long-term reliability of the semiconductor device 100 .

[0068] In some feasible embodiments, the semiconductor device 100 further includes at least one junction termination structure 106, which is disposed on a side of the drift layer 104 away from the substrate 101. The junction termination structure 106 is disposed in the second region Q2 and surrounds the first region Q1. Exemplarily, the junction termination structure 106 can be any one of a field limiting ring, a field plate, or a junction termination extension.

[0069] The junction termination structure 106 can reduce the surface electric field of the second region Q2 of the semiconductor device 100 and alleviate the surface electric field concentration phenomenon of the second region Q2 to reduce the breakdown risk of the second region Q2, thereby improving the voltage resistance of the semiconductor device 100.

[0070] In some feasible embodiments, the semiconductor device 100 further includes a passivation layer 203. The passivation layer 203 is disposed on a side of the drift layer 104 away from the substrate 101 and located in the second region Q2. The passivation layer 203 covers the at least one junction termination structure 106. Exemplarily, the material of the passivation layer 203 includes silicon oxide (SiO2).

[0071] The passivation layer 203 can electrically isolate the junction terminal structure 106 and the second metal layer 202 to prevent the semiconductor device 100 from being damaged by a short circuit. In addition, the passivation layer 203 can regulate the electric field, improve the electric field concentration phenomenon to a certain extent, and improve the voltage resistance of the second region Q2 of the semiconductor device 100.

[0072] In some feasible embodiments, the semiconductor device 100 further includes a first doped layer 105, a first metal layer 201, and a second metal layer 202. The first doped layer 105 is disposed on a side of the drift layer 104 away from the substrate 101 and is located in the first region Q1. The doping type of the first doped layer 105 is different from that of the drift layer 104. The first metal layer 201 is disposed on a side of the substrate 101 away from the drift layer 104 and is in contact with the substrate 101. The second metal layer 202 is disposed on a side of the first doped layer 105 away from the substrate 101 and is in contact with the first doped layer 105. As a possible implementation, the semiconductor device 100 may be a diode.

[0073] In some possible embodiments, see Figure 15 and Figure 16 , Figure 15 is a structural diagram of another semiconductor device provided according to some embodiments, Figure 16 for Figure 15 An AA-directional view of the middle functional layer.

[0074] The semiconductor device 100 includes a substrate 101, a functional layer 103, and a drift layer 104. The semiconductor device 100 may include a first region Q1 and a second region Q2 located around the first region Q1.

[0075] The functional layer 103 is disposed on one side of the substrate 101. The functional layer 103 includes a first sub-functional layer 103a, a second sub-functional layer 103b, and a third sub-functional layer 103c. The first sub-functional layer 103a is disposed in the first region Q1, and the second sub-functional layer 103b is disposed in the second region Q2. The doping concentration of the second sub-functional layer 103b is greater than that of the first sub-functional layer 103a. The third sub-functional layer 103c is disposed in the first region Q1, and the doping concentration of the third sub-functional layer 103c is less than that of the second sub-functional layer 103b. For example, the functional layer 103 includes multiple second sub-functional layers 103b, with the third sub-functional layer 103c disposed between at least two adjacent second sub-functional layers 103b. For example, the second sub-functional layers 103b may be rectangular.

[0076] The second subfunctional layer 103b and the third subfunctional layer 103c both extend along a first direction y, and the second subfunctional layers 103b and the third subfunctional layers 103c are alternately arranged along a second direction x. The first direction y and the second direction x are both perpendicular to the thickness direction z of the substrate 101, and the first direction y and the second direction x are perpendicular to each other. For example, the doping concentration of the first subfunctional layer 103a can be the same as the doping concentration of the third subfunctional layer 103c.

[0077] Figure 15 The rest of the structure of the semiconductor device 100 is similar to Figure 4 The semiconductor devices 100 shown are basically the same, so they are not described in detail again.

[0078] In the process of forming the second sub-functional layer 103b, processes such as ion implantation can be used, which will cause lattice damage to the functional layer 103. By reducing the area of the second sub-functional layer 103b, the lattice damage to the functional layer 103 can be effectively reduced, and the growth quality of the drift layer 104 can be improved, thereby improving the electrical performance of the semiconductor device 100.

[0079] In some possible embodiments, see Figure 15 and Figure 17 , Figure 15 is a structural diagram of another semiconductor device provided according to some embodiments, Figure 17 for Figure 15 Another AA view of the middle functional layer.

[0080] The semiconductor device 100 includes a substrate 101, a functional layer 103, and a drift layer 104. The semiconductor device 100 may include a first region Q1 and a second region Q2 located around the first region Q1.

[0081] The functional layer 103 is disposed on one side of the substrate 101. The functional layer 103 includes a first sub-functional layer 103a, a second sub-functional layer 103b, and a third sub-functional layer 103c. The first sub-functional layer 103a is disposed in the first region Q1, and the second sub-functional layer 103b is disposed in the second region Q2. The doping concentration of the second sub-functional layer 103b is higher than that of the first sub-functional layer 103a. The third sub-functional layer 103c is disposed in the first region Q1, and the doping concentration of the third sub-functional layer 103c is lower than that of the second sub-functional layer 103b. For example, the functional layer 103 includes multiple second sub-functional layers 103b. Among the multiple second sub-functional layers 103b, some extend along the first direction y, while others extend along the second direction x. The second sub-functional layers 103b extending along the first direction y intersect with the other second sub-functional layers 103b extending along the second direction x, forming a network structure. The third sub-functional layer 103c is located in the opening of the mesh structure. For example, the third sub-functional layer 103c may be in a rectangular, circular or other shape.

[0082] Figure 15 The rest of the structure of the semiconductor device 100 is similar to Figure 4 The semiconductor devices 100 shown are basically the same, so they are not described in detail again.

[0083] In some possible embodiments, see Figure 15 and Figure 18 , Figure 15 is a structural diagram of another semiconductor device provided according to some embodiments, Figure 18 for Figure 15 Another AA view of the middle functional layer.

[0084] The semiconductor device 100 includes a substrate 101, a functional layer 103, and a drift layer 104. The semiconductor device 100 may include a first region Q1 and a second region Q2 located around the first region Q1.

[0085] The functional layer 103 is disposed on one side of the substrate 101. The functional layer 103 includes a first sub-functional layer 103a, a second sub-functional layer 103b, and a third sub-functional layer 103c. The first sub-functional layer 103a is disposed in the first region Q1, and the second sub-functional layer 103b is disposed in the second region Q2. The doping concentration of the second sub-functional layer 103b is greater than that of the first sub-functional layer 103a. The third sub-functional layer 103c is disposed in the first region Q1, and the doping concentration of the third sub-functional layer 103c is less than that of the second sub-functional layer 103b. For example, the functional layer 103 includes multiple second sub-functional layers 103b. Each second sub-functional layer 103b has an annular structure. The multiple second sub-functional layers 103b are nested and spaced apart. The third sub-functional layer 103c is located between two radially adjacent second sub-functional layers 103b.

[0086] In some feasible embodiments, the first sub-functional layer 103a, the second sub-functional layer 103b and the third sub-functional layer 103c may also be as follows: Figure 19 The circular ring shown, Figure 19 for Figure 15 Another AA view of the middle functional layer.

[0087] In some feasible embodiments, the semiconductor device 100 may also be a semiconductor device such as a field effect transistor, such as Figure 20 As shown, Figure 20 A structural diagram of a semiconductor device provided according to some embodiments.

[0088] The semiconductor device 100 includes a substrate 101, a functional layer 103, and a drift layer 104. The semiconductor device 100 may include a first region Q1 and a second region Q2 located around the first region Q1.

[0089] The functional layer 103 is disposed on one side of the substrate 101. The functional layer 103 includes a first sub-functional layer 103a and a second sub-functional layer 103b. The first sub-functional layer 103a is disposed in the first region Q1, and the second sub-functional layer 103b is disposed in the second region Q2. The doping concentration of the second sub-functional layer 103b is greater than that of the first sub-functional layer 103a.

[0090] The semiconductor device 100 further includes a source region 302, a gate 303, and a drain. The source region 302 is located on the side of the drift layer 104 away from the substrate 101 and is located in a first region Q1. At least a portion of the source region 302 has a different doping type than the drift layer 104. The gate 303 is located in the first region Q1. The gate 303 is located on the side of the drift layer 104 away from the substrate 101 and is connected to a portion of the source region 302. The semiconductor device 100 further includes a gate dielectric layer 304, which is at least disposed between the drift layer 104 and the gate 303. The drain can be located on the side of the substrate 101 away from the drift layer 104, or it can be part of the substrate 101 and located on the side away from the drift layer 104.

[0091] In some feasible embodiments, the source region 302 includes a first sub-source region 302a and a second sub-source region 302b. The first sub-source region 302a and the second sub-source region 302b are arranged along the second direction x, and the second sub-source region 302b is closer to the gate 303 than the first sub-source region 302a. Exemplarily, the doping type of the first sub-source region 302a is different from the doping type of the drift layer 104, and the doping type of the second sub-source region 302b is the same as the doping type of the first sub-source region 302a.

[0092] In some feasible embodiments, the semiconductor device 100 further includes a first doped layer 105 , which is disposed between the source region 302 and the drift layer 104 . A portion of the first doped layer 105 extends toward the gate 303 and contacts the gate dielectric layer 304 .

[0093] In some feasible embodiments, the semiconductor device 100 further includes a buffer layer 102 , which is located between the substrate 101 and the functional layer 103 . The buffer layer 102 has the same doping type as the functional layer 103 , and the buffer layer 102 is in contact with the functional layer 103 .

[0094] In some feasible embodiments, the semiconductor device 100 further includes at least one junction termination structure 106, which is disposed on a side of the drift layer 104 away from the substrate 101. The junction termination structure 106 is disposed in the second region Q2 and surrounds the first region Q1.

[0095] In some feasible embodiments, the semiconductor device 100 further includes a passivation layer 203 , which is disposed on a side of the drift layer 104 away from the substrate 101 and located in the second region Q2 . The passivation layer 203 covers the at least one junction termination structure 106 .

[0096] In some feasible embodiments, the semiconductor device 100 further includes a first metal layer 201 and a second metal layer 202. The first metal layer 201 is disposed on a side of the substrate 101 away from the drift layer 104 and in contact with the drain. The second metal layer 202 is disposed on a side of the drift layer 104 away from the substrate 101 and in contact with the first doped layer 105. A gate dielectric layer 304 is further disposed between the gate 303 and the second metal layer 202.

[0097] It should be noted that when the semiconductor device 100 is a field effect transistor, the structure of the functional layer 103 can also be as follows: Figure 15 as well as Figure 16-Figure 18 The functional layer structure shown.

[0098] Based on the above embodiments, the present disclosure also provides a method for preparing a semiconductor device, see Figure 21 , Figure 21 1 is a flow chart of a method for manufacturing a semiconductor device according to some embodiments. The method for manufacturing a semiconductor device 100 includes steps S10 to S30.

[0099] In step S10 , an initial functional layer 1031 is formed on one side of the substrate 101 .

[0100] In step S20, ion implantation is performed on the target region of the initial functional layer 1031 to form the second sub-functional layer 103b. The region other than the target region of the initial functional layer 1031 forms the first sub-functional layer 103a. Exemplarily, the first sub-functional layer 103a surrounds the second sub-functional layer 103b, and the first sub-functional layer 103a and the second sub-functional layer 103b constitute the functional layer 103.

[0101] In step S30 , a drift layer 104 is formed on a side of the functional layer 103 away from the substrate 101 .

[0102] The present disclosure also provides a method for preparing a semiconductor device, such as Figures 22 to 27 As shown, Figure 22 is a flow chart of another method for manufacturing a semiconductor device according to some embodiments. Figures 23 to 27 for Figure 22 Structural diagram of the semiconductor structure corresponding to different steps in the preparation method shown.

[0103] The method for manufacturing the semiconductor device 100 includes steps S40 to S70 .

[0104] In step S40, a buffer layer 102 is formed on one side of the substrate 101 to obtain Figure 23 A semiconductor structure 500 is shown.

[0105] In step S50, an initial functional layer 1031 is formed on the side of the buffer layer 102 away from the substrate 101, and the following is obtained: Figure 24 A semiconductor structure 500 is shown.

[0106] In step S60, ion implantation is performed on the target region of the initial functional layer 1031 to form the second sub-functional layer 103b, and the region other than the target region of the initial functional layer 1031 forms the first sub-functional layer 103a, so as to obtain the following: Figure 26 The semiconductor structure 500 is shown. Exemplarily, the first sub-functional layer 103 a surrounds the second sub-functional layer 103 b , and the first sub-functional layer 103 a and the second sub-functional layer 103 b constitute the functional layer 103 .

[0107] In step S70, a drift layer 104 is formed on the side of the functional layer 103 away from the substrate 101, and the following is obtained: Figure 27 A semiconductor structure 500 is shown.

[0108] After step S70, other processes are used to form the semiconductor structure 500 as follows: Figure 4 、 Figure 15 or Figure 20 The semiconductor device 100 is shown in FIG.

[0109] In some feasible embodiments, step S60 includes step S61 and step S62.

[0110] In step S61 , the second sub-functional layer 103 b is formed in the target region of the initial functional layer 1031 by using the mask layer 401 and the ion implantation process, and the first sub-functional layer 103 a is formed in the region other than the target region of the initial functional layer 1031 .

[0111] For example, a mask layer 401 is formed on a side away from the substrate 101, and the mask layer 401 is patterned so that the mask layer 401 exposes a target area of the initial functional layer 1031 and covers the remaining area except the target area, so as to obtain the following: Figure 25 The semiconductor structure 500 shown is formed by ion implantation in a target region of the initial functional layer 1031 to form a second sub-functional layer 103b. The initial functional layer 1031 is covered with a mask layer 401 in regions other than the target region to form a first sub-functional layer 103a.

[0112] By forming different patterns of the mask layer 401, the following can be obtained: Figure 5 、 Figure 16 、 Figure 17 、 Figure 18 or Figure 19 The functional layer 103 has a structure similar to that of FIG.

[0113] In step S62, the mask layer 401 is removed to obtain Figure 26 A semiconductor structure 500 is shown.

[0114] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises a first region and a second region located around the first region, and includes: substrate; a functional layer, disposed on the substrate; a drift layer, disposed on a side of the functional layer away from the substrate, wherein the drift layer has the same doping type as the functional layer; The functional layer includes a first sub-functional layer and a second sub-functional layer, the first sub-functional layer is arranged in the second area, and the second sub-functional layer is arranged in the first area; The doping concentration of the second sub-functional layer is greater than the doping concentration of the first sub-functional layer.

2. The semiconductor device according to claim 1, wherein The functional layer further comprises: at least one third sub-functional layer, disposed in the first region, wherein the doping concentration of the third sub-functional layer is lower than the doping concentration of the second sub-functional layer; The functional layer includes a plurality of the second sub-functional layers, and the third sub-functional layer is at least provided between two adjacent second sub-functional layers.

3. The semiconductor device according to claim 2, wherein: The second sub-functional layer and the third sub-functional layer both extend along the first direction, and the second sub-functional layer and the third sub-functional layer are alternately arranged along the second direction; The first direction and the second direction are both perpendicular to the thickness direction of the substrate, and the first direction and the second direction are perpendicular to each other.

4. The semiconductor device according to claim 2, wherein Among the plurality of second sub-functional layers, a portion of the second sub-functional layers extends along the first direction, another portion of the second sub-functional layers extends along the second direction, and the portion of the second sub-functional layers and the another portion of the second sub-functional layers intersect with each other to form a network structure; The third sub-functional layer is located in the openings of the network structure.

5. The semiconductor device according to claim 2, wherein The second sub-functional layer is an annular structure, and a plurality of the second sub-functional layers are sequentially nested and spaced apart; The third sub-functional layer is located between two second sub-functional layers adjacent to each other in the radial direction of the second sub-functional layer.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that The first sub-functional layer is also disposed in the first region, and the first sub-functional layer is located around the second sub-functional layer.

7. The semiconductor device according to any one of claims 1 to 5, characterized in that The doping concentration of the second sub-functional layer is greater than or equal to the doping concentration of the drift layer.

8. The semiconductor device according to any one of claims 1 to 5, wherein: Also includes: A buffer layer is located between the substrate and the functional layer. The doping type of the buffer layer is the same as that of the functional layer, and the buffer layer is in contact with the functional layer.

9. The semiconductor device according to any one of claims 1 to 5, wherein: Also includes: at least one junction termination structure, the junction termination structure being disposed on a side of the drift layer away from the substrate; the junction termination structure being disposed in the second region and surrounding the first region; a passivation layer, the passivation layer being disposed on a side of the drift layer away from the substrate and located in the second region; The passivation layer covers the at least one junction termination structure.

10. The semiconductor device according to any one of claims 1 to 5, characterized in that Also includes: a first doped region, disposed on a side of the drift layer away from the substrate and located in the first region; The doping type of the first doping region is different from the doping type of the drift layer; a first metal layer, disposed on a side of the substrate away from the drift layer; The second metal layer is disposed on a side of the first doping region away from the substrate and in contact with the first doping region.

11. The semiconductor device according to any one of claims 1 to 5, wherein: Also includes: a source region, disposed on a side of the drift layer away from the substrate and located in the first area; The doping type of at least a portion of the source region is different from the doping type of the drift layer; a gate, disposed in the first region, the gate being located on a side of the drift layer away from the substrate and connected to a portion of the source region; The drain is arranged on a side of the substrate away from the drift layer.

12. A method for preparing a semiconductor device, characterized in that: The preparation method comprises: forming an initial functional layer on one side of the substrate; Ion implantation is performed on a target area of the initial functional layer to form a second sub-functional layer, and an area of the initial functional layer other than the target area forms a first sub-functional layer; the first sub-functional layer surrounds the second sub-functional layer, and the first sub-functional layer and the second sub-functional layer constitute a functional layer; A drift layer is formed on a side of the functional layer away from the substrate.

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