Semiconductor device and manufacturing method thereof
By using a second metal element with a low formation enthalpy to form a diffusion barrier layer in semiconductor devices, the problem of impurity atoms hindering nucleation when metal and silicon are in contact, and the contact resistivity and the improvement of conductivity are achieved.
Patent Information
- Application Number
- CN202510535153.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-25
- Publication Date
- 2025-08-08
AI Technical Summary
In the prior art, when metal and silicon are in direct contact, impurity atoms remaining on the interface hinder the nucleation of metal silicides, resulting in an increase in contact resistivity, making it difficult to effectively improve the conductivity of semiconductor devices.
A second metal element with a thickness of no more than 1 nm is used, and its formation enthalpy is less than the formation enthalpy of the metal material with the first metal element, forming a diffusion barrier layer to combine interface impurity atoms, promote full contact and diffusion between metal and silicon atoms, form high-quality metal silicides, and reduce contact resistivity.
By suppressing impurity atoms occupying the interfacial gap position, the nucleation rate of metal silicides is improved, the contact resistivity is reduced, the conductivity of semiconductor devices is improved, and the process steps are simplified.
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Figure CN120456599A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor device capable of reducing contact resistivity and a manufacturing method thereof. Background Art
[0002] The improvement of semiconductor device performance depends on the reduction of contact resistivity. As semiconductor technology enters the submicron and below development nodes, the continuous reduction of device size puts higher requirements on the metal-semiconductor contact resistivity. Summary of the Invention
[0003] In view of this, the present disclosure provides a semiconductor device capable of reducing contact resistivity and a method for manufacturing the same.
[0004] One aspect of the present disclosure provides a semiconductor device, comprising: a substrate; a gate on the substrate; source / drain regions, respectively located on opposite sides of the gate; and source / drain contacts on the source / drain regions, comprising a first layer on the source / drain regions, a metal layer on the first layer, and a diffusion barrier layer on the metal layer, wherein the first layer comprises a silicide of a first metal element, the metal layer comprises a second metal element, and the formation enthalpy of the metal material of the second metal element is less than the formation enthalpy of the metal material of the first metal element.
[0005] According to an embodiment of the present disclosure, the thickness of the metal layer does not exceed 1 nm, preferably 0.5 nm to 1 nm.
[0006] According to an embodiment of the present disclosure, the first metal element includes at least one of Ti, Co, and Ni, and the second metal element includes at least one of Y, Sc, and Hf.
[0007] According to an embodiment of the present disclosure, the diffusion barrier layer includes a conductive metal nitride, such as TiN.
[0008] Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising: forming a gate and source / drain regions on a substrate, wherein the source / drain regions are respectively located on opposite sides of the gate; depositing a dielectric layer on the substrate; etching source / drain contact holes in the dielectric layer, wherein the source / drain contact holes at least partially expose the source / drain regions; forming a first layer, a metal layer, and a diffusion barrier layer in the source / drain contact holes in sequence, wherein the first layer includes a first metal element, the metal layer includes a second metal element, and the formation enthalpy of the metal material of the second metal element is less than the formation enthalpy of the metal material of the first metal element; and performing an annealing treatment to cause the first layer to react with the source / drain regions to generate a silicide including the first metal element.
[0009] According to an embodiment of the present disclosure, the first metal element includes at least one of Ti, Co, and Ni, and the second metal element includes at least one of Y, Sc, and Hf.
[0010] According to an embodiment of the present disclosure, the diffusion barrier layer includes a conductive metal nitride, such as TiN.
[0011] According to an embodiment of the present disclosure, the method further includes: forming source / drain electrodes on the diffusion barrier layer.
[0012] According to an embodiment of the present disclosure, a first layer, a metal layer, and a diffusion barrier layer are sequentially formed in the source / drain contact holes by physical vapor deposition (PVD).
[0013] According to an embodiment of the present disclosure, the thickness of the metal layer does not exceed 1 nm, preferably 0.5 nm to 1 nm.
[0014] According to an embodiment of the present disclosure, the source / drain contact portion includes a first layer, a metal layer, and a barrier diffusion layer. Because the formation enthalpy of the metal material of the second metal element in the metal layer is lower than the formation enthalpy of the metal material of the first metal element in the first layer, the metal layer can preferentially combine with impurity atoms (especially oxygen atoms) remaining at the interface between the first layer and the source / drain region, inhibiting the impurity atoms from occupying the interstitial positions of the silicide of the first metal element at the interface, thereby promoting sufficient contact and diffusion between the atoms of the first metal element and the silicon atoms in the source / drain region, thereby increasing the nucleation rate of the silicide of the first metal element, reducing the contact resistivity, and improving the conductive performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:
[0016] Figure 1 A cross-sectional view of a semiconductor device according to an embodiment of the present disclosure is schematically shown.
[0017] Figure 2 The flowchart schematically shows a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.
[0018] Figures 3 to 8 Schematically shows Figure 2 A cross-sectional view of the structure obtained after executing part of the process in the method shown. DETAILED DESCRIPTION
[0019] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.
[0020] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.
[0021] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.
[0022] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and for the purpose of clarity, certain details are magnified and certain details may be omitted. The shapes of the various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element.
[0023] Metal silicides such as titanium silicide (TiSi x ) In current semiconductor devices such as 3D FinFET (FinField-Effect Transistor, fin field effect transistor) devices, not only can + -Si (i.e. n-type doped silicon) and p + -SiGe (i.e. p-type doped silicon germanium) achieves relatively excellent ohmic contact characteristics, which is conducive to the smooth flow of current. At the same time, due to its silicon-dominated diffusion method, it effectively avoids a series of problems that may be caused by lateral diffusion of metals, and is therefore used as the first choice for source / drain contact materials to improve the conductivity of the device by reducing the contact resistivity.
[0024] However, the inventors discovered that when a metal such as titanium (Ti) is in direct contact with silicon (Si), impurity atoms such as oxygen and carbon that may remain on the interface will occupy the interstitial positions of the silicide of the first metal element formed, hindering the diffusion and contact of metal atoms and Si atoms, thereby delaying the nucleation of the metal silicide, thereby increasing the resistivity of the final metal silicide and making it difficult to effectively improve the conductive performance of the device.
[0025] In view of this, an embodiment of the present disclosure provides a semiconductor device, comprising: a substrate; a gate on the substrate; source / drain regions, respectively located on opposite sides of the gate; and source / drain contacts on the source / drain regions, comprising a first layer on the source / drain regions, a metal layer on the first layer, and a diffusion barrier layer on the metal layer, the first layer comprising a silicide of a first metal element, the metal layer comprising a second metal element, and the formation enthalpy of the metal material of the second metal element being less than the formation enthalpy of the metal material of the first metal element.
[0026] Figure 1 A cross-sectional view of a semiconductor device according to an embodiment of the present disclosure is schematically shown.
[0027] like Figure 1 As shown, the semiconductor device 100 according to this embodiment includes a substrate 110, a gate 120 on the substrate 110, and source / drain regions 130 located on opposite sides of the gate 120. The source / drain contact 140 on the source / drain region 130 includes a first layer 141 on the source / drain region 130, a metal layer 142 on the first layer 141, and a diffusion barrier layer 143 on the metal layer 142. The first layer 141 includes a silicide 141' of a first metal element, and the metal layer 142 includes a second metal element, wherein the formation enthalpy of the metal material of the second metal element is lower than the formation enthalpy of the metal material of the first metal element.
[0028] According to an embodiment of the present disclosure, the substrate 110 may be a silicon substrate, or an SOI substrate (Silicon-On-Insulator), etc., which is not limited herein.
[0029] According to an embodiment of the present disclosure, a dielectric layer 150 is further provided on the substrate 110. The dielectric layer 150 may include a bottom oxide, a middle nitride, and a top oxide stacked in sequence. Other types of dielectric materials may also be used depending on the environment and actual needs, and are not limited here.
[0030] According to an embodiment of the present disclosure, the substrate 110 may further include a device isolation layer 160 for achieving electrical isolation between different devices, with shallow trench isolation (STI) being used as an example. In addition, other methods may be used, which are not limited here.
[0031] According to an embodiment of the present disclosure, the barrier diffusion layer 143 further includes a source / drain electrode 170. The source / drain electrode 170 may be made of a conductive metal such as aluminum (Al), which is not limited here.
[0032] According to an embodiment of the present disclosure, the thickness of the metal layer 142 does not exceed 1 nm, preferably 0.5 nm to 1 nm.
[0033] According to an embodiment of the present disclosure, the first metal element may include at least one of titanium (Ti), cobalt (Co), and nickel (Ni), and the second metal element may include at least one of yttrium (Y), scandium (Sc), and hafnium (Hf).
[0034] For example, when the first metal element is Ti, the first layer includes titanium-based silicide (TiSi x ), at this time, the selection of the second metal element must satisfy the formation enthalpy of the metal material is less than the formation enthalpy of Ti.
[0035] According to an embodiment of the present disclosure, the diffusion barrier layer includes a conductive metal nitride, such as TiN.
[0036] Since the metal material with lower formation enthalpy can preferentially combine with the impurity atoms in the interface between the first layer and the source / drain region, the impurity atoms are inhibited from occupying the interstitial positions of the interface, and the influence of impurities on the mutual contact and diffusion of the atoms of the first metal element and silicon atoms is eliminated.
[0037] According to an embodiment of the present disclosure, the source / drain contact portion includes a first layer, a metal layer, and a barrier diffusion layer. Because the formation enthalpy of the metal material of the second metal element in the metal layer is lower than the formation enthalpy of the metal material of the first metal element in the first layer, the metal layer can preferentially combine with impurity atoms (especially oxygen atoms) remaining at the interface between the first layer and the source / drain region, inhibiting the impurity atoms from occupying the interstitial positions of the silicide of the first metal element at the interface, thereby promoting sufficient contact and diffusion between the atoms of the first metal element and the silicon atoms in the source / drain region, thereby increasing the nucleation rate of the silicide of the first metal element, reducing the contact resistivity, and improving the conductive performance of the device.
[0038] Furthermore, the metal transition layer formed by the metal layer and the impurity elements not only does not require additional wet process removal, but also has almost no negative impact on the contact resistivity. Therefore, the process steps can be simplified and the overall performance can be improved.
[0039] Figure 2 The flowchart schematically shows a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.
[0040] Figures 3 to 8 Schematically shows Figure 2 A cross-sectional view of the structure obtained after executing part of the process in the method shown.
[0041] like Figure 2 As shown, the method 200 according to this embodiment may include operations S210 to S250.
[0042] In operation S210 , a gate and source / drain regions are formed on a substrate.
[0043] like Figure 3 As shown, a substrate 110 can be provided. Trenches can be formed by etching the substrate, and the trenches are filled with a dielectric material, such as silicon oxide, and planarized to form a device isolation layer 160, thereby defining an active region on the substrate 110. Methods other than shallow trench isolation (STI) can also be used, which are not limited here. A gate 120 is formed on the surface of the substrate 110. For example, the gate 120 can include a high-K / metal gate. Source / drain regions 130 are formed on opposite sides of the gate 120. The source / drain regions 130 can include doped regions in the substrate 110 or semiconductor layers grown separately on the substrate 110. The source / drain regions 130 can include various suitable semiconductor materials, such as Si for n-type FETs and SiGe for p-type FETs. The source / drain regions 130 can be doped to the desired conductivity type (n-type for n-type semiconductor devices and p-type for p-type semiconductor devices) by, for example, in-situ doping or ion implantation. A gate spacer may be formed on the sidewall of the gate 120 and may be located between the gate 120 and the source / drain region 130. For convenience, the specific structures of the gate spacer, gate dielectric layer, gate conductive layer, etc. are not shown in the figure.
[0044] In operation S220 , a dielectric layer is deposited on the substrate.
[0045] like Figure 4 As shown, a dielectric layer 150 is deposited on a substrate 110. For example, a bottom oxide layer, a middle nitride layer, and a top oxide layer can be sequentially formed by deposition processes such as chemical vapor deposition (CVD). A planarization process such as chemical mechanical polishing (CMP) can be performed to provide a substantially flat top surface for the dielectric layer 150.
[0046] In operation S230 , source / drain contact holes are etched in the dielectric layer, the source / drain contact holes at least partially exposing the source / drain regions.
[0047] like Figure 5As shown, a mask pattern is first formed on the surface of dielectric layer 150, for example, by photolithography, to define the locations of source / drain contact holes 120'. For convenience, a hard mask structure that may be used in the patterning process is not shown. Dielectric layer 150 is then dry-etched, for example, using reactive ion etching (RIE). To prevent damage to source / drain regions 130 during the etching process, at least a portion of dielectric layer 150, such as a certain thickness of an underlying oxide layer, is retained on source / drain regions 130.
[0048] like Figure 6 As shown, an etching solution such as HF may be used to remove at least a portion of the dielectric layer 150 remaining on the source / drain region 130 to at least partially expose the source / drain region 130 , thereby forming a source / drain contact hole 120 ′.
[0049] In operation S240 , a first layer, a metal layer, and a diffusion barrier layer are sequentially formed in the source / drain contact holes.
[0050] like Figure 7 As shown, a first layer 141, a metal layer 142, and a diffusion barrier layer 143 can be sequentially formed in the source / drain contact hole 120' by, for example, physical vapor deposition (PVD). The first layer 141, the metal layer 142, and the diffusion barrier layer 143 cover the bottom and sidewalls of the source / drain contact hole 120' and the surface of the dielectric layer 150. The first layer 141 includes a first metal element, and the metal layer 142 includes a second metal element, where the formation enthalpy of the metal material of the second metal element is lower than the formation enthalpy of the metal material of the first metal element. The diffusion barrier layer includes a conductive metal nitride, such as TiN. The first metal element includes at least one of Ti, Co, and Ni, and the second metal element includes at least one of Y, Sc, and Hf. The thickness of the metal layer 142 can be no more than 1 nm, preferably 0.5 nm to 1 nm.
[0051] In operation S250 , an annealing process is performed to react the first layer with the source / drain regions to generate silicide including the first metal element.
[0052] like Figure 7 As shown, the source / drain regions 130 can be treated using rapid annealing or laser annealing to allow silicon atoms in the source / drain regions 130 to diffuse and react with atoms of the first metal element, such as Ti atoms, in the first layer 141 to form a silicide 141' of the first metal element. Annealing process parameters, such as temperature and duration, can be adaptively set based on the material and are not limited here.
[0053] like Figure 8As shown, a conductive metal film can be deposited on the surface of the diffusion barrier layer 143 by, for example, a sputtering process, and then the metal film in the non-electrode area can be removed by photolithography and etching to form the source / drain electrodes 170. In addition, the portion of the contact portion 140 outside the contact hole can also be removed by etching.
[0054] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.
[0055] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.
Claims
1. A semiconductor device comprising: substrate; a gate on the substrate; source / drain regions, respectively located on opposite sides of the gate; as well as The source / drain contact portion on the source / drain region includes a first layer on the source / drain region, a metal layer on the first layer and a diffusion barrier layer on the metal layer, the first layer includes a silicide of a first metal element, the metal layer includes a second metal element, and the formation enthalpy of the metal material of the second metal element is less than the formation enthalpy of the metal material of the first metal element.
2. The semiconductor device according to claim 1, wherein The thickness of the metal layer does not exceed 1 nm, preferably 0.5 nm to 1 nm.
3. The semiconductor device according to claim 1, wherein The first metal element includes at least one of Ti, Co, and Ni, and the second metal element includes at least one of Y, Sc, and Hf.
4. The semiconductor device according to claim 1, wherein The diffusion barrier layer includes a conductive metal nitride, such as TiN.
5. A method for manufacturing a semiconductor device, comprising: forming a gate and source / drain regions on a substrate, wherein the source / drain regions are respectively located on opposite sides of the gate; depositing a dielectric layer on the substrate; Etching a source / drain contact hole in the dielectric layer, wherein the source / drain contact hole at least partially exposes the source / drain region; forming a first layer, a metal layer, and a diffusion barrier layer in the source / drain contact hole in sequence, wherein the first layer includes a first metal element, the metal layer includes a second metal element, and the formation enthalpy of the metal material of the second metal element is smaller than the formation enthalpy of the metal material of the first metal element; and An annealing process is performed to allow the first layer to react with the source / drain region to generate a silicide including a first metal element.
6. The method according to claim 5, wherein: The first metal element includes at least one of Ti, Co, and Ni, and the second metal element includes at least one of Y, Sc, and Hf.
7. The method according to claim 5, wherein: The diffusion barrier layer includes a conductive metal nitride, such as TiN.
8. The method according to claim 5, further comprising: Source / drain electrodes are formed on the diffusion barrier layer.
9. The method according to claim 8, wherein The first layer, the metal layer and the diffusion barrier layer are sequentially formed in the source / drain contact hole by physical vapor deposition (PVD).
10. The method according to claim 5, wherein The thickness of the metal layer does not exceed 1 nm, preferably 0.5 nm to 1 nm.