Semiconductor device and method of producing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of producing the same. A semiconductor device includes transistor cells formed in a semiconductor substrate and electrically coupled in parallel to form power transistors. The transistor cell includes a trench extending into the semiconductor substrate from a first major surface of the semiconductor substrate in a vertical direction. The trench includes: a gate electrode; a field electrode under the gate electrode; and at least one dielectric material separating the gate electrode and the field electrode from each other and separating the gate electrode and the field electrode from the semiconductor substrate. The at least one dielectric material is thicker between the field electrode and the bottom of the trench than between the field electrode and each sidewall of the trench. Each trench has a tapered width that decreases in the vertical direction over the depth of the trench. A method of producing a semiconductor device is also described.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to semiconductor devices and methods of producing semiconductor devices. Background Art

[0002] DC-DC power conversion for servers, high-performance computing (HPC) and artificial intelligence (AI) requires higher efficiency and higher density. As the frequency increases, the quality factor FOMoss = Rdson * Qoss becomes the main power loss mechanism, where Rdson is the on-resistance and Qoss is the output charge. Some traditional power semiconductor devices used in DC-DC power conversion systems utilize a double polysilicon field plate design, in which the field plate is used to fully compensate the drift region. For these devices, FOMoss is reduced by reducing Rdson. After several generations of geometry reduction, these devices have been optimized for low Rdson, making further reduction of FOMoss difficult. Single polysilicon trench devices with trench bottom oxide have a R*AA (on-resistance multiplied by active area) quality factor that is too high for modern space-constrained high-performance applications. Monolithic devices for high-frequency DCDC power conversion cannot achieve vertical power flow like vertical trench MOSFETs (metal oxide semiconductor field effect transistors).

[0003] Therefore, there is a need for an improved semiconductor device design optimized for DC-DC power conversion systems. Summary of the Invention

[0004] According to an embodiment of a semiconductor device, the semiconductor device includes: a semiconductor substrate; and a plurality of transistor cells formed in the semiconductor substrate and electrically coupled in parallel to form a power transistor, wherein the plurality of transistor cells include a plurality of trenches extending from a first main surface of the semiconductor substrate into the semiconductor substrate in a vertical direction, wherein each of the plurality of trenches includes: a gate electrode; a field electrode located below the gate electrode; and at least one dielectric material separating the gate electrode and the field electrode from each other and from the semiconductor substrate, wherein the at least one dielectric material is thicker between the field electrode and a bottom of the trench than between the field electrode and each sidewall of the trench, wherein each trench has a tapered width that decreases over a depth of the trench in the vertical direction.

[0005] According to an embodiment of a method for producing a semiconductor device, the method includes: forming a plurality of transistor cells in a semiconductor substrate; and electrically coupling the plurality of transistor cells in parallel to form a power transistor, wherein forming the plurality of transistor cells includes: etching a plurality of trenches into a first main surface of the semiconductor substrate, and the plurality of trenches extending into the semiconductor substrate in a vertical direction; and in each trench, forming a gate electrode, a field electrode located below the gate electrode, and at least one dielectric material, the at least one dielectric material separating the gate electrode and the field electrode from each other and from the semiconductor substrate, wherein the at least one dielectric material is thicker between the field electrode and a bottom of the trench than between the field electrode and each sidewall of the trench, wherein each trench has a tapered width that decreases over a depth of the trench in the vertical direction.

[0006] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The elements of the drawings are not necessarily drawn to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. The embodiments are depicted in the drawings and are detailed in the following description.

[0008] Figure 1A A partial top plan view of a semiconductor device formed in a region of several adjacent transistor cells in a semiconductor substrate is shown.

[0009] Figure 1B The diagram follows Figure 1A A cross-sectional view of the semiconductor device taken along line AA' in FIG.

[0010] Figure 2 FIG. 1 shows a diagram according to another embodiment of the present invention. Figure 1A A cross-sectional view of the semiconductor device taken along line AA' in FIG.

[0011] Figures 3A to 3F A partial cross-sectional view between two (2) adjacent trenches of a semiconductor device during different production stages in accordance with an embodiment is illustrated. DETAILED DESCRIPTION

[0012] The embodiments described herein provide a semiconductor device optimized for a DC-DC power conversion system and a method for producing the same. A thick dielectric region is provided below the field electrode (plate) of a power transistor cell to significantly reduce FOMoss. The thick dielectric region is thicker than the field oxide surrounding the field electrode in the lateral direction, for example, 1.5 to 10 times thicker. Compared to conventional devices without thick dielectric regions, the field electrode can extend to a shallower depth in the semiconductor substrate.

[0013] The field oxide surrounding the field electrode can be thinner or thicker than in conventional devices to optimize the Rdson-Qoss tradeoff. Epitaxial doping can be reduced compared to conventional devices to reduce Qoss. Thick dielectric regions, trench depth, and field electrode depth can be optimized.

[0014] The new design can be based on a striped double-polysilicon structure, where the field electrode is located below the gate electrode in the same trench and a thick dielectric region is located below the field electrode. However, the new design can also be applied to needle-trenches or striped device designs that use gate trenches separate from the field electrode trenches. In this case, the gate trench can contain a thick dielectric region below the gate electrode, or it can be free of a thick dielectric region below the gate electrode.

[0015] Thick dielectric regions provide several benefits in power MOSFET devices. First, the thick dielectric region partially shields the field electrode from the drain potential, resulting in smaller changes in the local field electrode voltage when the drain voltage is switched. Second, the thick dielectric region provides a certain dielectric resurf (reduced surface field) to enable higher epitaxial doping and lower Rdson compared to simple trench devices. Third, the thick dielectric region introduces beneficial crystal stress into the drift region, increasing carrier (e.g., electron) mobility and reducing Rdson. Fourth, because the source-drain capacitance of the field electrode is reduced, the output capacitance is reduced.

[0016] Next, embodiments of a semiconductor device and a method of producing the same will be described with reference to the drawings.

[0017] Figure 1A A partial top plan view of a semiconductor device formed in a region of several adjacent transistor cells 100 in a semiconductor substrate 102 is shown. Figure 1B The diagram follows Figure 1A A cross-sectional view of the semiconductor device taken along line AA' in FIG.

[0018] The transistor cells 100 are electrically coupled in parallel to form a power transistor, such as a vertical power MOSFET (metal oxide semiconductor field effect transistor), wherein the transistor cells 100 have the same or similar construction. Typically, a semiconductor device may have tens, hundreds, thousands, or even more transistor cells 100.

[0019] The semiconductor substrate 102 in which the transistor cell 100 is formed includes one or more semiconductor materials used to form a power semiconductor device, such as, for example, a Si or SiC power MOSFET. For example, the semiconductor substrate 102 may include Si, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), etc. The semiconductor body 100 may include one or more epitaxial layers.

[0020] The transistor cell 100 formed in the semiconductor substrate 102 includes a trench 104 extending in a vertical direction ( Figure 1A and 1B In the z-direction (in the ? direction) from the first major surface 106 of the semiconductor substrate 102 into the semiconductor substrate 102. Figure 1A In the embodiment, the trench 104 is a stripe-shaped trench. As used herein, the term 'stripe-shaped' means a trench having a stripe shape generally aligned with the depth direction ( Figure 1A and 1B The direction perpendicular to the z direction in the Figure 1A and 1B The structure with the longest linear dimension in the y direction (in the y direction).

[0021] Each trench 104 includes: a gate electrode 108; a field electrode 110 located below the gate electrode 108; and at least one dielectric material (such as a single dielectric material or a material stack) 112, which separates the gate electrode 108 and the field electrode 110 from each other and from the semiconductor substrate 102. Each transistor cell 100 also includes a source region 114 of a first conductivity type and a body region 116 of a second conductivity type opposite to the first conductivity type. The source region 114 of each transistor cell 100 is separated from a (common) drift region 118 of the first conductivity type by a corresponding body region 116. In the case of a vertical power transistor, a drain region 120 is disposed on the back side of the semiconductor substrate 102.

[0022] For an n-channel device formed from transistor cell 100, the first conductivity type is n-type and the second conductivity type is p-type, while for a p-channel device formed from transistor cell 100, the first conductivity type is p-type and the second conductivity type is n-type. For either the n-channel or p-channel device, source region 114 and body region 116 form part of transistor cell 100, and transistor cell 100 is electrically connected in parallel between source (S) and drain (D) terminals of a semiconductor device to form a power transistor.

[0023] The body region 116 of the transistor cell 100 may include a body contact region 122 of the second conductivity type. The body contact region 122 has a higher doping concentration than the body region 116 to provide an ohmic connection to a source / emitter metallization 124 through a contact structure 126 (e.g., a conductive via), which extends through an interlayer dielectric 128 that separates the source metallization 124 from the semiconductor substrate 102. The source region 114 of the transistor cell 100 is also electrically connected to the source metallization 124 through the contact structure 126. The source metallization 124, the contact structure 126, and the interlayer dielectric 128 are electrically connected to each other. Figure 1A 1 is not shown to provide an unobstructed view of the semiconductor substrate 102 .

[0024] The gate electrode 108 is electrically connected to the gate terminal (G) by, for example, gate metallization (not shown in the drawings). The gate metallization may be part of a structured power metallization that also includes a source metallization 124. Such structured power metallization may include: a thick power metal layer comprising Cu, Al, AlCu, AlSiCu, etc.; a diffusion barrier layer and / or an adhesion promoter such as Ti and / or TiN and / or W, located between the thick power metal layer and the interlayer dielectric 128. On the side of the semiconductor substrate 102 opposite the source metallization 128, a drain metallization 130 may be provided.

[0025] Figure 1A The adjacent (neighboring) trenches 104 shown in FIG are 'active' trenches because the semiconductor mesas 111 defined by the active trenches 104 facilitate the primary current flow of the semiconductor device. For these adjacent / adjacent active trenches 104, the trenches 104 may have the same dimensions (e.g., depth, width, length) throughout the active area of the device where the primary current flow occurs, the active area being the portion of the semiconductor substrate 102 that includes the source region 114. The gate electrode 108 may have the same dimensions (e.g., depth, width, length) throughout the active area of the device. The field electrode 110 may have the same dimensions (e.g., depth, width, length) throughout the active area of the device. The thickness T_b_ox of the at least one dielectric material 112 between the field electrode 110 and the bottom 132 of the trench 104 may be uniform throughout the active area of the device. The trench width (and therefore, the width of the gate electrode 108) may vary along the length of the trench 104 ( Figure 1A and 1B The y-direction in the active trench 104 may vary at some location, for example to accommodate a gate contact outside the active area. Figure 1A and 1BA region in the y-direction (in the y direction) without the gate electrode 108 is defined, and in which the field electrode 110 is contacted outside the active region. For example, the field electrode 110 can extend to the first major surface 106 at this location.

[0026] The at least one dielectric material (e.g., a single dielectric material or a stack of materials) 112 disposed in the trench 104 and separating the gate electrode 108 and the field electrode 110 from each other and from the semiconductor substrate 102 may be formed using the same material throughout, such as a thermal oxide and / or a deposited oxide. In one embodiment, between the gate electrode 108 and the body region 116, the at least one dielectric material 112 includes any combination of thermal SiO2 and / or deposited SiO2. Between the field electrode 110 and the drift region 118, the at least one dielectric material 112 may include any combination of thermal SiO2 and / or deposited SiO2, and an oxynitride or nitride may be included (e.g., included in a stack). In other embodiments, the at least one dielectric material 112 may include a stack of thermal oxide, HDP (high-density plasma) oxide, and deposited oxide from a field oxidation process between the field electrode 110 and the drift region 118, and an oxynitride or nitride may be included (e.g., included in a stack). In some embodiments, the at least one dielectric material 112 may include a stack of thermal oxide and HDP oxide between the gate electrode 108 and the field electrode 110. Still other insulating material combinations are contemplated for the at least one dielectric material 112.

[0027] The at least one dielectric material 112 is thicker between the field electrode 110 and the bottom 132 of the trench 104 than between the field electrode 110 and each sidewall 134 of the trench 104 (T_b_ox>W_f_ox). Figure 1A and 1B The trench 104 may have a uniform width (CD1=CD2) over the depth 'D_t' of the trench 104 in the z-direction (in the z-direction), or may have a tapered width (CD1>CD2) that decreases along the depth D_t of the trench 104.

[0028] In one embodiment, the thickness of the at least one dielectric material (e.g., a single dielectric material or a material stack) 112 is 1.5 to 10 times, for example, 4 to 10 times, for example, 2 to 6 times, greater between the field electrode 110 and the bottom 132 of the trench 104 than between the field electrode 110 and each sidewall 134 of the trench 104. For example, the thickness T_b_ox of the at least one dielectric material 112 between the field electrode 110 and the bottom 132 of the trench 104 may be approximately 200 nm, and the thickness W_f_ox of the at least one dielectric material 112 between the field electrode 110 and each sidewall 134 of the trench 104 may be approximately 70 nm. Additional benefits may be obtained by further increasing T_b_ox to 300 nm, 400 nm, or greater. For T_b_ox between 200 nm and 400 nm, FOMoss (i.e., Rdson*Qoss) is further reduced by approximately 10%.

[0029] Between the field electrode 110 and the bottom 132 of the trench 104, the at least one dielectric material 112 may extend from 10% to 67% of the overall trench depth 'D_t'. For example, the trench depth D_t may be approximately 870 nm, and the thickness T_b_ox of the at least one dielectric material 112 between the field electrode 110 and the bottom 132 of the trench 104 may be approximately 200 nm. For a D_t of 1000 nm and a T_b_ox of 150 nm, the at least one dielectric material 112 extends from 15% of D_t between the field electrode 110 and the bottom 132 of the trench 104. The overall trench depth D_t may be proportional to the nominal (breakdown) voltage rating of the device, and a higher % thickness of the at least one dielectric material 112 between the field electrode 110 and the bottom 132 of the trench 104 relative to D_t results in a greater Qoss reduction. For the minimum case, D_t may be 1000 nm, T_b_ox may be 100 nm, and the at least one dielectric material stack 112 may pass through 10% of D_t between the field electrode 110 and the bottom 132 of the trench 104. For the maximum case, D_t may be 900 nm, T_b_ox may be 600 nm, and the at least one dielectric material 112 may pass through 67% of D_t between the field electrode 110 and the bottom 132 of the trench 104.

[0030] The field electrode 110 may be arranged in a vertical direction ( Figure 1A and 1BThe at least one dielectric material 112 may have a thickness 'T_f' in the z-direction (in the z-direction) in the range of 100 nm to 1200 nm, and between the field electrode 110 and the bottom 132 of the trench 104, the at least one dielectric material 112 may have a thickness T_b_ox in the vertical direction in the range of 100 nm to 600 nm. For a nominal (breakdown) voltage rating of 25 V, T_f may be in the range of 150 nm to 400 nm. For higher voltage devices, the T_f value may be increased, and for lower voltage devices, the T_f value may be decreased. The field plate thickness T_f is a variable that allows adjustment of the Rdson-breakdown-Qoss tradeoff (for the same breakdown voltage, no field electrode produces the highest Rdson but the lowest Qoss, while the highest field electrode produces the lowest Rdson but the highest Qoss).

[0031] For nominal rated voltages up to 40V, T_f may be in the range of 100nm to 1200nm, T_b_ox may be in the range of 100nm to 600nm, and the ratio of T_f / T_b_ox may be in the range of a minimum of 0.17 (100nm / 600nm) to a maximum of 6 (600nm / 100nm). For example, for a nominal rated voltage of 25V, T_f may be in the range of 100nm to 600nm, and for a nominal rated voltage of 40V, T_f may be in the range of 100nm to 1200nm. For nominal rated voltages up to 40V, in the vertical direction ( Figure 1A and 1B The thickness 'T_g' of the gate electrode 108 in the z-direction (in the z-direction) may be in the range of 100 nm to 500 nm, and the thickness 'T_f_ox' of the at least one dielectric material 112 between the gate electrode 108 and the field electrode 110 may be in the range of 50 nm to 300 nm. The thickness T_f_ox of the at least one dielectric material 112 between the gate electrode 108 and the field electrode 110 may be greater or less than the thickness T_b_ox of the at least one dielectric material 112 between the field electrode 110 and the bottom 132 of the trench 104.

[0032] According to the process for forming the at least one dielectric material 112 described in more detail later herein, each sidewall 134 of the trench 104 may have a step profile 136 near the bottom 138 of the field electrode 110. The step profile 136 may occur if a thermal oxide liner is used to achieve good oxide interface quality with a small number of interface states. The step profile 136 may be avoided by using a SiN liner that remains in the trench 104. In another embodiment, the trench 104 has a uniform width over the trench depth D_t (i.e., no step profile 136).

[0033] The field electrode 110 may terminate at a depth of 33% to 90% of the trench depth D_t, where this depth is measured from the first major surface 106 of the semiconductor substrate 102 and is given by D_t minus T_b_ox. For example, the field electrode 110 may terminate at a depth of approximately 620 nm, while the trench 104 terminates at a depth of approximately 870 nm. The depth of the field electrode 110 helps determine the rated breakdown voltage of the device and also influences the R*AA-Qoss tradeoff. For a nominal rated voltage of 25 V, the depth of the field electrode 110 may be in the range of 620 nm + / - 150 nm. The trench depth beyond the field electrode termination point is then equal to the thickness T_b_ox of the at least one dielectric material 112 between the field electrode 110 and the bottom 132 of the trench 104. More generally, the field electrode 110 may terminate at a depth in the range of 300 nm to 900 nm, and the trench 104 may terminate at a depth of 350 nm to 2600 nm.

[0034] exist Figure 1B In the embodiment, the trench 104 vertically terminates in the drift region 118 of the semiconductor device. In one embodiment, the drift region 118 has a 2e16 cm -3 to 2e17 cm -3 The doping concentration of the drift region 118 is in the range of . The doping concentration of the drift region 118 depends on the voltage level of the device. Even in the case of a certain increase in the on-resistance (Rdson), the reduction in Qoss is sufficient to compensate for this increase. For example, Rdson may be 10 to 30% higher, but Qoss may be 50 to 60% lower. At a switching frequency of 1.5 to 2 MHz, for example, higher efficiency can be achieved across the load range.

[0035] A transition region 140 having a higher average doping concentration than the drift region 118 may be inserted between the drift region 118 and the drain region 120 in a vertical direction. The drain region 120 has a higher average doping concentration than the transition region 140. The drift region 118, the transition region 140, and the drain region 120 have the same conductivity type (e.g., n-type for an n-channel device and p-type for a p-channel device).

[0036] Figure 2 FIG. 1 shows a diagram according to another embodiment of the present invention. Figure 1A A cross-sectional view of the semiconductor device taken along the line marked AA' in FIG. Figure 2 In FIG. 1 , the trench 104 extends vertically through the drift region 118 and into the more highly doped transition region 140. Figure 2The trench 104 ends before the drain region 120 in the trench 104. A more highly doped transition region 140 results in lower hot carrier injection during avalanche, but increases Qoss. For some devices, a lower doped transition region 140 may be beneficial. Figure 2 If the Qoss is extended into the transition region 140 as shown in FIG. 1 , the Qoss will not increase as much.

[0037] Figures 3A to 3F A partial cross-sectional view between two (2) adjacent trenches 104 of a semiconductor device during different production stages in accordance with an embodiment is shown.

[0038] Figure 3A The semiconductor substrate 102 is shown after the trench 104 is etched to a depth D_t in the first major surface 106 of the semiconductor substrate 102 and a liner 200 is formed on each sidewall 134 and the bottom 132 of the trench 104. The liner 200 can be a single layer (e.g., thermal oxide or SiN) or a stack of layers (e.g., thermal oxide and SiN).

[0039] Figure 3B Semiconductor substrate 102 is shown after trench 104 is at least partially filled with high density plasma chemical vapor deposition (HDP-CVD) oxide 202. HDP-CVD is a form of plasma enhanced chemical vapor deposition (PECVD) that uses an inductively coupled plasma source that provides a high plasma density.

[0040] Because of the sputtering component, the HDP-CVD oxide 202 grows thick on the planar surfaces and the trench bottom 132, but grows thin on the sidewalls 134. To avoid the formation of gaps in the HDP-CVD oxide 202, an iterative process may be employed, such as Figure 3B and 3C As shown in , and according to an iterative process, the trench 104 is at least partially filled with the HDP-CVD oxide 202 in two or more iterations of the HDP-CVD process followed by a wet etching process before the next iteration.

[0041] exist Figure 3B In the embodiment of the present invention, the sidewall HDP-CVD oxide is removed by a wet etching process. If the liner 200 includes only a single layer of thermal oxide or an outer layer of thermal oxide, the thermal oxide is also removed by a wet etching process, such as Figure 3B If the liner 200 comprises only a single layer of SiN or an outer layer of SiN with an inner layer of thermal oxide, the liner 200 will not be affected by the wet etch.

[0042] exist Figure 3CIn the embodiment, the HDP-CVD process and the wet etching process are repeated at least once to completely fill the trench 104 with the HDP-CVD oxide 202. In some embodiments, the HDP-CVD oxide 202 can alternatively be formed using a single HDP-CVD / etching step, but the HDP-CVD process may be limited by the trench aspect ratio.

[0043] Figure 3D The semiconductor substrate 102 is shown after the HDP-CVD oxide 202 and the liner 200 are removed from the first major surface 106 of the semiconductor substrate 102 by a planarization process. For example, the HDP-CVD oxide 202 and the liner 200 may be removed from the first major surface 106 of the semiconductor substrate 102 by CMP (chemical mechanical polishing).

[0044] Figure 3E The semiconductor substrate 102 is shown after the HDP-CVD oxide 202 is removed from the upper portion of the trench 104. In one embodiment, the HDP-CVD oxide 202 is removed from the upper portion of the trench 104 by a wet etching process to avoid rounding of the corners of the trench 104. If the liner 200 includes only a single layer of thermal oxide or a thermal oxide outer layer, the HDP-CVD oxide 202 is removed from the upper portion of the trench 104 by a wet etching process to avoid rounding of the corners of the trench 104. Figure 1A The depicted sidewall step profile 136 may be present. By making the thermal oxide layer thinner, the step profile 136 can be minimized, which improves field electrode shielding.

[0045] The liner 200 can alternatively comprise only a single layer of SiN or an outer layer of SiN with an inner layer of thermal oxide. Such a liner composition will avoid step profiles 136 along the trench sidewalls 134. In addition, since the wet etching process will not attack the SiN, the liner 200 can remain in the upper and lower portions of the trench 104. The SiN liner can be removed using a separate SiN liner removal process prior to forming the field plate / gate electrode stack. The SiN liner can alternatively remain permanently on each sidewall 134 in the upper portion of the trench 104 and form part of the at least one dielectric material 112. A liner (thermal) oxide can be formed below the nitride to form a liner stack structure.

[0046] In each case, Figure 3EThe recessed etching of the HDP-CVD oxide 202 from the upper portion of the trench 104 defines a thickness T_b_ox of the at least one dielectric material 112 between the field electrode 110 and the bottom 132 of the trench 104. T_b_ox may be in the range of 100 nm to 600 nm. Removal of the HDP-CVD oxide 202 from the upper portion of the trench 104 may involve a bulk etch followed by a controlled wet etch to produce a well-controlled trench bottom oxide height or thickness T_b_ox.

[0047] Figure 3F The semiconductor substrate 102 is shown after lining each exposed trench sidewall 134 with an electrically insulating material 204 in the upper portion of the trench 104. For example, the electrically insulating material 204 may include a thinner thermal oxide (e.g., ~5 nm) 206, which is capped by a thicker oxide (e.g., 30 nm) 208 formed by ALD (atomic layer deposition) and / or TEOS (tetraethoxysilane). For example, the electrically insulating material 204 may include approximately 30 nm of thermal oxide and approximately 50 nm of deposited oxide (e.g., TEOS). For better control, the electrically insulating material 204 may alternatively be formed using only ALD.

[0048] The method continues with standard trench processing to form a gate electrode 108 and a field electrode 110 in the trench 104. This may include polysilicon deposition followed by polysilicon recessing to define the field electrode 110. The oxide component of the at least one dielectric material 112 is then deposited on the field electrode 110, and the gate electrode 108 is formed on the field oxide.

[0049] Although the present disclosure is not limited in this regard, the following numbered examples demonstrate one or more aspects of the present disclosure.

[0050] Example 1. A semiconductor device comprising: a semiconductor substrate; and a plurality of transistor cells formed in the semiconductor substrate and electrically coupled in parallel to form a power transistor, wherein each trench of the plurality of transistor cells comprises a plurality of trenches extending from a first major surface of the semiconductor substrate into the semiconductor substrate in a vertical direction, wherein the plurality of trenches comprise: a gate electrode; a field electrode located below the gate electrode; and at least one dielectric material separating the gate electrode and the field electrode from each other and from the semiconductor substrate, wherein the at least one dielectric material is thicker between the field electrode and a bottom of the trench than between the field electrode and each sidewall of the trench, wherein each trench has a tapered width that decreases across a depth of the trench in the vertical direction.

[0051] Example 2. The semiconductor device of Example 1, wherein the at least one dielectric material is 1.5 to 10 times thicker between the field electrode and the bottom of the trench than between the field electrode and each sidewall of the trench.

[0052] Example 3. The semiconductor device of Example 1 or 2, wherein between the field electrode and the bottom of the trench, the at least one dielectric material traverses 10% to 67% of the depth of the trench.

[0053] Example 4. The semiconductor device of any of Examples 1 to 3, wherein the field electrode has a thickness in the vertical direction that is in a range from 100 nm to 600 nm, and wherein between the field electrode and the bottom of the trench, the at least one dielectric material has a thickness in the vertical direction that is in a range from 100 nm to 600 nm.

[0054] Example 5. The semiconductor device of any of Examples 1 to 4, wherein each sidewall of the trench has a step profile near a bottom of the field electrode.

[0055] Example 6. The semiconductor device of any of Examples 1 to 4, wherein the trench has a uniform width across the trench depth.

[0056] Example 7. The semiconductor device of any of Examples 1 to 6, wherein in the vertical direction, the trench terminates in a drift region of the semiconductor device, and wherein the drift region has a 2e16 cm -3 to 2e17 cm -3 The doping concentration is in the range of .

[0057] Example 8. The semiconductor device of any one of Examples 1 to 7, wherein in the vertical direction, the trench extends through a drift region of the semiconductor device and into a transition region, the transition region having a higher average doping concentration than the drift region, wherein the transition region is interposed between the drift region and a substrate region in the vertical direction, the substrate region having a higher average doping concentration than the transition region, and wherein the drift region, the transition region, and the substrate region have the same conductivity type.

[0058] Example 9. The semiconductor device of any of Examples 1 to 8, wherein the field electrode terminates at a depth of 33% to 90% of the trench depth.

[0059] Example 10. The semiconductor device of any of Examples 1 to 9, wherein the power transistor has a nominal rated voltage of 40 V or less.

[0060] Example 11. The semiconductor device of any of Examples 1 to 10, wherein the field electrode has a thickness in the vertical direction that is in a range from 100 nm to 1200 nm, and wherein the gate electrode has a thickness in the vertical direction that is in a range from 100 nm to 500 nm.

[0061] Example 12. The semiconductor device of any of Examples 1 to 11, wherein between the field electrode and the bottom of the trench, the at least one dielectric material has a thickness in the vertical direction that is in a range from 100 nm to 600 nm, and wherein between the gate electrode and the field electrode, the at least one dielectric material has a thickness in the vertical direction that is in a range from 50 nm to 300 nm.

[0062] Example 13. The semiconductor device of any of Examples 1 to 12, wherein the at least one dielectric material is 4 to 10 times thicker between the field electrode and the bottom of the trench than between the field electrode and each sidewall of the trench.

[0063] Example 14. The semiconductor device of any of Examples 1 to 13, wherein the semiconductor device has a nominal voltage rating of 25 V or less, wherein the field electrode has a thickness in the vertical direction that is in a range from 100 nm to 600 nm, and wherein between the field electrode and the bottom of the trench, the at least one dielectric material has a thickness in the vertical direction that is in a range from 100 nm to 600 nm.

[0064] Example 15. The semiconductor device of any of Examples 1 to 13, wherein the semiconductor device has a nominal rated voltage of 40 V or less, wherein the field electrode has a thickness in the vertical direction that is in a range from 100 nm to 1200 nm, and wherein between the field electrode and the bottom of the trench, the at least one dielectric material has a thickness in the vertical direction that is in a range from 100 nm to 600 nm.

[0065] Example 16. A method of producing a semiconductor device, the method comprising: forming a plurality of transistor cells in a semiconductor substrate; and electrically coupling the plurality of transistor cells in parallel to form a power transistor, wherein forming the plurality of transistor cells comprises: etching a plurality of trenches into a first major surface of the semiconductor substrate, the plurality of trenches extending in a vertical direction into the semiconductor substrate; and forming, in each trench, a gate electrode, a field electrode below the gate electrode, and at least one dielectric material separating the gate electrode and the field electrode from each other and from the semiconductor substrate, wherein the at least one dielectric material is thicker between the field electrode and a bottom of the trench than between the field electrode and each sidewall of the trench, wherein each trench has a tapered width that decreases across a depth of the trench in the vertical direction.

[0066] Example 17. The method of Example 16, wherein forming the at least one dielectric material comprises: forming a liner on each sidewall and the bottom of the trench; after forming the liner, at least partially filling the trench with a high-density plasma chemical vapor deposition (HDP-CVD) oxide; and removing the HDP-CVD oxide from an upper portion of the trench.

[0067] Example 18. The method of claim 16, wherein forming the dielectric material or material stack comprises: forming a liner on each sidewall and the bottom of the trench; after forming the liner, completely filling the trench with a high-density plasma chemical vapor deposition (HDP-CVD) oxide; and removing the HDP-CVD oxide from an upper portion of the trench.

[0068] Example 19. The method of Example 18, wherein the liner is a thermal oxide, and wherein the thermal oxide and the HDP-CVD oxide are removed from the upper portion of the trench by a wet etching process.

[0069] Example 20. The method of Example 19, further comprising lining each sidewall with an electrically insulating material in the upper portion of the trench after removing the thermal oxide and the HDP-CVD oxide from the upper portion of the trench.

[0070] Example 21. The method of Example 18, wherein the liner is silicon nitride.

[0071] Example 22. The method of Example 21, further comprising: after removing the HDP-CVD oxide from the upper portion of the trench, removing the silicon nitride from the upper portion of the trench.

[0072] Example 23. The method of Example 21, wherein the silicon nitride liner permanently remains on each sidewall in the upper portion of the trench.

[0073] Example 24. The method of Example 18, wherein the liner comprises a thermal oxide capped by silicon nitride.

[0074] Example 25. The method of Example 18, wherein completely filling the trench with the HDP-CVD oxide comprises two or more iterations of an HDP-CVD process followed by a wet etch process before the next iteration.

[0075] Terms such as "first," "second," and the like are used to describe various elements, regions, sections, and the like, and are also not intended to be limiting. Similar terms refer to similar elements throughout the description.

[0076] As used herein, the terms "having," "containing," "including," "comprising," and the like are open-ended terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0077] The expression "and / or" should be interpreted as covering all possible conjunction and disjunctive combinations, unless expressly indicated otherwise. For example, the expression "A and / or B" should be interpreted as meaning only A, only B, or both A and B. The expression "at least one of" should be interpreted in the same manner as "and / or," unless expressly indicated otherwise. For example, the expression "at least one of A and B" should be interpreted as meaning only A, only B, or both A and B.

[0078] It is to be understood that the features of the various embodiments described herein may be combined with each other unless specifically noted otherwise.

[0079] Although specific embodiments have been illustrated and described herein, it will be understood by those skilled in the art that various alternatives and / or equivalent implementations may replace the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. It is therefore intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A semiconductor device comprising: semiconductor substrates; and a plurality of transistor cells formed in the semiconductor substrate and electrically coupled in parallel to form a power transistor; wherein the plurality of transistor cells include a plurality of trenches extending in a vertical direction from a first main surface of the semiconductor substrate into the semiconductor substrate, wherein each transistor of the plurality of trenches comprises: gate electrode; a field electrode located below the gate electrode; and at least one dielectric material separating the gate electrode and the field electrode from each other and from the semiconductor substrate, wherein the at least one dielectric material is thicker between the field electrode and the bottom of the trench than between the field electrode and each sidewall of the trench, Each of the grooves has a tapered width that decreases with depth of the groove in the vertical direction. 2 . The semiconductor device of claim 1 , wherein the at least one dielectric material is 1.5 to 10 times thicker between the field electrode and the bottom of the trench than between the field electrode and each sidewall of the trench. 3 . The semiconductor device of claim 2 , wherein the at least one dielectric material is 4 to 10 times thicker between the field electrode and the bottom of the trench than between the field electrode and each sidewall of the trench. 4 . The semiconductor device of claim 1 , wherein between the field electrode and the bottom of the trench, the at least one dielectric material penetrates 10% to 67% of the depth of the trench.

5. The semiconductor device of claim 1 , wherein the field electrode has a thickness in the vertical direction that is in the range from 100 nm to 600 nm, and wherein between the field electrode and the bottom of the trench, the at least one dielectric material has a thickness in the vertical direction that is in the range from 100 nm to 600 nm. 6 . The semiconductor device according to claim 1 , wherein each sidewall of the trench has a step profile near a bottom of the field electrode.

7. The semiconductor device of claim 1 , wherein in the vertical direction, the trench terminates in a drift region of the semiconductor device, and wherein the drift region has a -3 to 2e17 cm -3 The doping concentration is in the range of .

8. A semiconductor device as described in claim 1, wherein in the vertical direction, the trench extends through the drift region of the semiconductor device and extends into the transition region, the transition region has an average doping concentration higher than that of the drift region, wherein the transition region is inserted between the drift region and the substrate region in the vertical direction, the substrate region has an average doping concentration higher than that of the transition region, and wherein the drift region, the transition region and the substrate region have the same conductivity type. 9 . The semiconductor device of claim 1 , wherein the field electrode terminates at a depth of 33% to 90% of the trench depth.

10. The semiconductor device according to claim 1, wherein the power transistor has a nominal rated voltage of 40 V or less.

11. The semiconductor device according to claim 1, wherein the field electrode has a thickness in the vertical direction, which is in a range from 100 nm to 1200 nm, and wherein the gate electrode has a thickness in the vertical direction, which is in a range from 100 nm to 500 nm.

12. The semiconductor device of claim 1 , wherein between the field electrode and the bottom of the trench, the at least one dielectric material has a thickness in the vertical direction that is in a range from 100 nm to 600 nm, and wherein between the gate electrode and the field electrode, the at least one dielectric material has a thickness in the vertical direction that is in a range from 50 nm to 300 nm.

13. The semiconductor device of claim 1 , wherein the semiconductor device has a nominal rated voltage of 25 V or less, wherein the field electrode has a thickness in the vertical direction that is in a range from 100 nm to 600 nm, and wherein between the field electrode and the bottom of the trench, the at least one dielectric material has a thickness in the vertical direction that is in a range from 100 nm to 600 nm.

14. The semiconductor device of claim 1 , wherein the semiconductor device has a nominal rated voltage of 40 V or less, wherein the field electrode has a thickness in the vertical direction that is in a range from 100 nm to 1200 nm, and wherein between the field electrode and the bottom of the trench, the at least one dielectric material has a thickness in the vertical direction that is in a range from 100 nm to 600 nm.

15. A method for producing a semiconductor device, the method comprising: forming a plurality of transistor cells in a semiconductor substrate; and electrically coupling the plurality of transistor cells in parallel to form a power transistor, Wherein forming the plurality of transistor primitives comprises: etching a plurality of trenches into the first major surface of the semiconductor substrate, wherein the plurality of trenches extend into the semiconductor substrate in a vertical direction; and In each trench, a gate electrode, a field electrode located below the gate electrode, and at least one dielectric material are formed, the at least one dielectric material separating the gate electrode and the field electrode from each other and from the semiconductor substrate, wherein the at least one dielectric material is thicker between the field electrode and the bottom of the trench than between the field electrode and each sidewall of the trench, Each of the grooves has a tapered width that decreases with depth of the groove in the vertical direction.

16. The method of claim 15, wherein forming the at least one dielectric material comprises: forming a liner on each sidewall and the bottom of the trench; After forming the liner, at least partially filling the trench with a high density plasma chemical vapor deposition (HDP-CVD) oxide; and The HDP-CVD oxide is removed from an upper portion of the trench.

17. The method of claim 15, wherein forming the at least one dielectric material comprises: forming a liner on each sidewall and the bottom of the trench; After forming the liner, completely filling the trench with a high density plasma chemical vapor deposition (HDP-CVD) oxide; and The HDP-CVD oxide is removed from an upper portion of the trench.

18. The method of claim 17, wherein the liner is a thermal oxide, and wherein the thermal oxide and the HDP-CVD oxide are removed from the upper portion of the trench by a wet etching process.

19. The method of claim 18, further comprising: After removing the thermal oxide and the HDP-CVD oxide from the upper portion of the trench, each sidewall is lined with an electrically insulating material in the upper portion of the trench.

20. The method of claim 17, wherein the liner is silicon nitride.

21. The method of claim 20, further comprising: After removing the HDP-CVD oxide from the upper portion of the trench, the silicon nitride is removed from the upper portion of the trench.

22. The method of claim 20, wherein the silicon nitride liner permanently remains on each sidewall in the upper portion of the trench.

23. The method of claim 17, wherein the liner comprises a thermal oxide covered by silicon nitride.

24. The method of claim 17, wherein completely filling the trench with the HDP-CVD oxide comprises two or more iterations of a HDP-CVD process followed by a wet etch process before the next iteration.

Images