Semiconductor device and method of manufacturing the same

Abstract

The invention provides a semiconductor device and a method for manufacturing the same, which can prevent the impurity concentration of an n-type well region directly below a wiring from decreasing and can prevent the generation of a leakage path. A method of manufacturing a semiconductor device includes: forming a second conductivity type well region on an upper surface side of a first conductivity type semiconductor substrate; forming a plurality of channel formation regions of the first conductivity type on the upper surface side of the well region; a plurality of drift regions of the second conductivity type are formed on the upper surface side of the well region so as to be alternately formed with the plurality of channel formation regions; forming a plurality of gate electrodes on the upper surface side of the channel formation region via a gate insulating film; and forming a wiring above the well region, in which the step of forming the well region includes: forming a plurality of slit-shaped first ion implantation regions having different widths, and forming a second ion implantation region at a position overlapping the wiring on the end side of the first ion implantation region having a relatively narrow width; and forming a well region by heat treatment.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Patent Document 1 discloses a lateral MOSFET in which a plurality of source regions and a plurality of drain regions are alternately arranged along a short-side direction (gate length direction) perpendicular to the long-side direction of a gate electrode.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2015-233056 Summary of the Invention

[0006] Problems to be solved by the invention

[0007] In semiconductor devices such as lateral MOSFETs, an n-type well region, forming a voltage-resistant structure, is provided on the top surface of a p-type semiconductor substrate. To adjust the impurity concentration in the n-type well region, n-type impurity ions are implanted into multiple slits. Heat treatment is then performed to activate the implanted n-type impurities, forming a single n-type well region.

[0008] However, if there are narrow sections within the slit-shaped ion implantation region, the implanted n-type impurities may not diffuse sufficiently in the lateral direction, resulting in a locally low impurity concentration region in the n-type well region. When wiring overlaps this low impurity concentration region, a channel forms on the surface of the low impurity concentration region, becoming a leakage path.

[0009] In view of the above problems, an object of the present disclosure is to provide a semiconductor device and a method for manufacturing the same that can prevent a decrease in the impurity concentration of an n-type well region directly below a wiring and prevent the generation of a leakage path.

[0010] Solutions for solving problems

[0011] According to one embodiment of the present disclosure, a semiconductor device comprises: a semiconductor substrate of a first conductivity type; a well region of a second conductivity type, which is arranged on the upper surface side of the semiconductor substrate; a plurality of channel formation regions of the first conductivity type, which are arranged on the upper surface side of the well region and extend parallel to each other in one direction when viewed from above; a plurality of drift regions of the second conductivity type, which are alternately arranged on the upper surface side of the well region with the plurality of channel formation regions and extend parallel to each other in one direction; a carrier supply region of the second conductivity type, which is arranged on the upper surface side of each of the plurality of channel formation regions; and a carrier receiving region of the second conductivity type. , which are arranged on the upper surface side of each of the multiple drift regions; multiple gate electrodes, which are arranged on the upper surface side of the channel formation region sandwiched by the carrier supply region and the well region through a gate insulating film, and extend parallel to each other in one direction; and wiring, which is arranged above the well region, and the end sides of the multiple channel formation regions in one direction and the end sides of the multiple drift regions extend in a direction orthogonal to the one direction, wherein the impurity concentration of the well region at the end side of the channel formation region sandwiched by adjacent drift regions and overlapping with the wiring is higher than the impurity concentration of the well region at the end side of the multiple drift regions and overlapping with the wiring.

[0012] In addition, the main purpose is a method for manufacturing a semiconductor device, which is the method for manufacturing the above-mentioned semiconductor device, in which the process of forming a well region includes: forming a plurality of first ion implantation regions in the shape of slits extending parallel to each other in one direction and having different widths by ion implanting impurities of a second conductive type, and forming a second ion implantation region extending in a direction orthogonal to the one direction at a position overlapping with the wiring and on the end side of the first ion implantation region having a relatively narrow width among the plurality of first ion implantation regions; and forming the well region by causing the impurities implanted into the first ion implantation region and the second ion implantation region to diffuse in the lateral direction through heat treatment.

[0013] Effects of the Invention

[0014] According to the present disclosure, it is possible to provide a semiconductor device and a method for manufacturing the semiconductor device that can prevent a decrease in the impurity concentration of an n-type well region immediately below a wiring and prevent the generation of a leakage path. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a cross-sectional view of the semiconductor device according to the first embodiment.

[0016] Figure 2 It is a top view of the semiconductor device according to the first embodiment.

[0017] Figure 3 It is a top view of the semiconductor device according to the first embodiment.

[0018] Figure 4 It is along Figure 2 and Figure 3 This is a cross-sectional view taken along line AA′.

[0019] Figure 5 It is along Figure 2 and Figure 3 The cross-sectional view is taken along line BB′.

[0020] Figure 6 It is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment.

[0021] Figure 7 It is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment.

[0022] Figure 8A It is a plan view for explaining the method for manufacturing the semiconductor device according to the first embodiment.

[0023] Figure 8B It is a plan view for explaining the method for manufacturing the semiconductor device according to the first embodiment.

[0024] Figure 9 It is along Figure 8A and Figure 8B This is a cross-sectional view taken along line AA′.

[0025] Figure 10 It is along Figure 8A and Figure 8B The cross-sectional view is taken along line BB′.

[0026] Figure 11 This is a continuation of the description of the method for manufacturing a semiconductor device according to the first embodiment. Figure 6 Later cross-section.

[0027] Figure 12 yes Figure 11 Along the stage Figure 8A and Figure 8B This is a cross-sectional view taken along line AA′.

[0028] Figure 13 yes Figure 11 Along the stage Figure 8A and Figure 8B The cross-sectional view is taken along line BB′.

[0029] Figure 14 This is a continuation of the description of the method for manufacturing a semiconductor device according to the first embodiment. Figure 11 Later cross-section.

[0030] Figure 15This is a continuation of the description of the method for manufacturing a semiconductor device according to the first embodiment. Figure 14 Later cross-section.

[0031] Figure 16 This is a continuation of the description of the method for manufacturing a semiconductor device according to the first embodiment. Figure 15 Later cross-section.

[0032] Figure 17 is a cross-sectional view of a semiconductor device according to a first comparative example.

[0033] Figure 18 It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to the first comparative example.

[0034] Figure 19 It is a plan view for explaining a method for manufacturing a semiconductor device according to a second comparative example.

[0035] Figure 20 It is a plan view for explaining the method for manufacturing the semiconductor device according to the second embodiment.

[0036] Figure 21 It is a plan view for explaining a method for manufacturing a semiconductor device according to the third embodiment. DETAILED DESCRIPTION

[0037] Below, the first to third embodiments of the present disclosure are described with reference to the accompanying drawings. In the description of the drawings, the same or similar parts are marked with the same or similar figure marks, and repeated descriptions are omitted. However, the drawings are schematic, and the relationship between thickness and plane size, the ratio of the thickness of each layer, etc. are sometimes different from the actual situation. In addition, the drawings also include parts with different dimensional relationships and ratios. In addition, the first to third embodiments shown below are used to illustrate the devices and methods for concretizing the technical ideas of the present disclosure. The technical ideas of the present disclosure do not specify the material, shape, structure, configuration, etc. of the structural components to the following materials, shapes, structures, configurations, etc.

[0038] In this specification, the term "carrier supply region" refers to a semiconductor region that supplies the majority carriers that constitute the main current, such as the source region of a field-effect transistor (FET) or static induction transistor (SIT), or the emitter region of an insulated-gate bipolar transistor (IGBT). Furthermore, in diodes, static induction (SI) thyristors, or gate-turn-off (GTO) thyristors, the anode region serves as the carrier supply region. Furthermore, the term "carrier receiving region" refers to a semiconductor region that receives the majority carriers that constitute the main current, such as the drain region of a FET or SIT, or the collector region of an IGBT. In diodes, SI thyristors, or GTO thyristors, the cathode region functions as the carrier receiving region.

[0039] In addition, the definitions of directions such as up and down in this specification are for ease of explanation only and are not intended to limit the technical concepts of this disclosure. For example, if an object is rotated 90°, up and down will be read as left and right, while if it is rotated 180°, up and down will be read in reverse. This is self-evident.

[0040] In addition, in this specification, the case where the first conductivity type is p-type and the second conductivity type is n-type is described as an example. However, the conductivity types can also be selected to be in the opposite relationship, with the first conductivity type being n-type and the second conductivity type being p-type. In addition, the “+” and “-” marked for “n” and “p” refer to semiconductor regions with a relatively high or relatively low impurity concentration compared to semiconductor regions not marked with “+” and “-”. However, even if the semiconductor regions are marked with the same “n” and “n”, it does not mean that the impurity concentrations of the semiconductor regions are strictly the same. Moreover, in the following description, even if there is no special explicit limitation, the components and regions to which the “first conductivity type” and “second conductivity type” are limited refer to components and regions composed of semiconductor materials.

[0041] (First embodiment)

[0042] <Structure of Semiconductor Device>

[0043] As the semiconductor device according to the first embodiment, a lateral n-channel metal oxide semiconductor field effect transistor (MOSFET) is exemplified. Figure 1 As shown in FIG, a plurality of transistor units T1 to T6 are arranged in an array. Figure 1 In the embodiment, the arrangement of six transistor cells T1 to T6 is illustrated, but the number of transistor cells arranged is not particularly limited. The withstand voltage of the semiconductor device according to the first embodiment is, for example, approximately 60 V or higher.

[0044] The semiconductor device according to the first embodiment includes a semiconductor substrate 1 of a first conductivity type (p-type). The semiconductor substrate 1 is composed of, for example, a semiconductor substrate such as a silicon (Si) substrate. Alternatively, the semiconductor substrate 1 may be composed of a semiconductor substrate such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), gallium arsenide (GaAs), or diamond. The semiconductor substrate 1 may also be a p-type semiconductor region (semiconductor layer) formed on the upper surface of a p-type or n-type semiconductor substrate.

[0045] On the upper surface side (upper part) of the semiconductor substrate 1, a second conductivity type (n -A p-type well region (Deep NWell; DNW) 2 is formed. Multiple p-type channel formation regions (well regions) 3a to 3d are provided separately from one another on the upper surface (upper portion) of well region 2. Multiple n-type drift regions 4a to 4c, having an impurity concentration higher than that of well region 2, are provided separately from one another on the upper surface (upper portion) of well region 2. The multiple drift regions 4a to 4c are provided alternately with the multiple channel formation regions 3a to 3d.

[0046] On the upper surface side (upper portion) of the channel formation region 3a, a p + Type contact areas 7a and n + The semiconductor substrate 1 includes a carrier supply region (source region) 8a. The contact region 7a and the source region 8a are in contact with each other. The impurity concentration of the contact region 7a is higher than that of the channel formation region 3a. The contact region 7a is connected to the source electrode 22 provided on the upper surface side of the interlayer insulating film 32 via a through hole 22a that penetrates the interlayer insulating film 32 provided on the upper surface side of the semiconductor substrate 1. The source region 8a is connected to the source electrode 22 via a through hole 22b that penetrates the interlayer insulating film 32. The source electrode 22 is covered by a protective insulating film 33 provided on the upper surface side of the interlayer insulating film 32.

[0047] As the interlayer insulating film 32, for example, an undoped silicon oxide film (SiO2 film) that does not contain phosphorus (P) or boron (B), known as "NSG," can be used. Alternatively, the interlayer insulating film 32 may be a phosphorus-doped silicon oxide film (PSG film), a boron-doped silicon oxide film (BSG film), a boron- and phosphorus-doped silicon oxide film (BPSG film), a silicon nitride film (Si3N4 film), or a stacked film thereof. For example, a resin such as polyimide can be used as the protective insulating film 33.

[0048] An n-type impurity layer having an impurity concentration higher than that of the drift region 4a is provided on the upper surface side (upper portion) of the drift region 4a. + The drain region 9a is connected to the drain electrode 23 provided on the upper surface of the interlayer insulating film 32 via a through-hole 23a that penetrates the interlayer insulating film 32. An insulating film (element isolation insulating film) 31 is provided on the side surfaces of both sides of the drift region 4a and the drain region 9a.

[0049] The element isolation insulating film 31 is composed of an oxide film such as a local insulating film (LOCOS film) selectively (locally) formed by a local oxidation of silicon (LOCOS) method, for example.

[0050] A gate electrode 11a is provided on the upper surface of the channel formation region 3a and the well region 2 sandwiched between the source region 8a and the drain region 9a via a gate insulating film 10a. Sidewall insulating films 12a are provided on both sides of the gate electrode 11a.

[0051] The gate insulating film 10a may be made of, for example, a silicon oxide film (SiO2 film), a silicon oxynitride film (SiON film), a strontium oxide film (SrO film), a silicon nitride film (Si3N4 film), an aluminum oxide film (Al2O3 film), a magnesium oxide film (MgO film), a yttrium oxide film (Y2O3 film), a hafnium oxide film (HfO2 film), a zirconium oxide film (ZrO2 film), a tantalum oxide film (Ta2O5 film), or a bismuth oxide film (Bi2O3 film), or a composite film formed by stacking multiple layers thereof. The gate electrode 11a may be made of, for example, a polysilicon layer (doped polysilicon layer) to which p-type impurities such as boron (B) or n-type impurities such as phosphorus (P) are added at a high concentration, or a high-melting-point metal.

[0052] On the upper surface side (upper portion) of the channel formation region 3b, an n + Type carrier supply region (source region) 8b, p + Type contact area 7b and n + The channel formation region 3b has a carrier supply region (source region) 8c. The source region 8b is in contact with the contact region 7b. The contact region 7b is in contact with the source region 8c. The source region 8b is connected to the source electrode 24 provided on the upper surface side of the interlayer insulating film 32 via a through hole 24a penetrating the interlayer insulating film 32. The impurity concentration of the contact region 7b is higher than the impurity concentration of the channel formation region 3b. The contact region 7b is connected to the source electrode 24 via a through hole 24b penetrating the interlayer insulating film 32. The source region 8c is connected to the source electrode 24 via a through hole 24c penetrating the interlayer insulating film 32. The source electrode 24 is covered by a protective insulating film 33.

[0053] A gate electrode 11b is provided on the upper surface of the channel formation region 3b and the well region 2 sandwiched between the drain region 9a and the source region 8b via a gate insulating film 10b. Sidewall insulating films 12b are provided on both sides of the gate electrode 11b.

[0054] An n-type impurity layer having an impurity concentration higher than that of the drift region 4b is provided on the upper surface side (upper portion) of the drift region 4b. + The drain region 9b is connected to the drain electrode 25 provided on the upper surface of the interlayer insulating film 32 via a through-hole 25a that penetrates the interlayer insulating film 32. An element isolation insulating film 31 is provided on the side surfaces of both sides of the drift region 4b and the drain region 9b.

[0055] A gate electrode 11c is provided on the upper surface of the channel formation region 3b and the well region 2 sandwiched between the source region 8c and the drain region 9b via a gate insulating film 10c. Sidewall insulating films 12c are provided on both sides of the gate electrode 11c.

[0056] On the upper surface side (upper portion) of the channel formation region 3c, an n + Type carrier supply region (source region) 8d, p + Type contact area 7c and n + The channel formation region 3c has a carrier supply region (source region) 8e. The source region 8d is in contact with the contact region 7c. The contact region 7c is in contact with the source region 8e. The source region 8d is connected to the source electrode 26 provided on the upper surface side of the interlayer insulating film 32 via a through-hole 26a penetrating the interlayer insulating film 32. The impurity concentration of the contact region 7c is higher than the impurity concentration of the channel formation region 3c. The contact region 7c is connected to the source electrode 26 via a through-hole 26b penetrating the interlayer insulating film 32. The source region 8e is connected to the source electrode 26 via a through-hole 26c penetrating the interlayer insulating film 32. The source electrode 26 is covered by a protective insulating film 33.

[0057] A gate electrode 11d is provided on the upper surface of the channel formation region 3c and the well region 2 sandwiched between the drain region 9b and the source region 8d via a gate insulating film 10d. Sidewall insulating films 12d are provided on both sides of the gate electrode 11d.

[0058] An n-type impurity layer having an impurity concentration higher than that of the drift region 4c is provided on the upper surface side (upper portion) of the drift region 4c. + The drain region 9c is connected to the drain electrode 27 provided on the upper surface of the interlayer insulating film 32 via a through hole 27a that penetrates the interlayer insulating film 32. An element isolation insulating film 31 is provided on the side surfaces of both sides of the drift region 4c and the drain region 9c.

[0059] A gate electrode 11e is provided on the upper surface of the channel formation region 3c and the well region 2 sandwiched between the source region 8e and the drain region 9c via a gate insulating film 10e. Sidewall insulating films 12e are provided on both sides of the gate electrode 11e.

[0060] On the upper surface side (upper portion) of the channel formation region 3d, an n + Type carrier supply region (source region) 8f and p + The channel formation region 3d has a contact region 7d. The source region 8f is in contact with the contact region 7d. The source region 8f is connected to the source electrode 28 provided on the upper surface of the interlayer insulating film 32 via a through-hole 28a that penetrates the interlayer insulating film 32. The impurity concentration in the contact region 7d is higher than that in the channel formation region 3d. The contact region 7d is connected to the source electrode 28 via a through-hole 28b that penetrates the interlayer insulating film 32. The source electrode 28 is covered by a protective insulating film 33.

[0061] A gate electrode 11f is provided on the upper surface of the channel formation region 3d and the well region 2 sandwiched between the drain region 9c and the source region 8f via a gate insulating film 10f. Sidewall insulating films 12f are provided on both sides of the gate electrode 11f.

[0062] Transistor cell T1 includes a contact region 7a, a source region 8a, a drain region 9a, and a gate electrode 11a. Transistor cell T2 has a structure that is line-symmetrical with transistor cell T1, with drain region 9a as the center. Transistor cell T2 includes a contact region 7b, a source region 8b, a drain region 9a, and a gate electrode 11b. Drain region 9a is shared by transistor cells T1 and T2.

[0063] Transistor cell T3 has a line-symmetric structure with transistor cell T2 with contact region 7b as the center. Transistor cell T3 includes contact region 7b, source region 8c, drain region 9b, and gate electrode 11c. Contact region 7b is shared by transistor cells T2 and T3.

[0064] Transistor cell T4 has a line-symmetric structure with transistor cell T3 with drain region 9b as the center. Transistor cell T4 includes contact region 7c, source region 8d, drain region 9b, and gate electrode 11d. Drain region 9b is shared by transistor cells T3 and T4.

[0065] Transistor cell T5 has a line-symmetric structure with transistor cell T4 with contact region 7c as the center. Transistor cell T5 includes contact region 7c, source region 8e, drain region 9c, and gate electrode 11d. Contact region 7c is shared by transistor cells T4 and T5.

[0066] Transistor cell T6 has a line-symmetric structure with transistor cell T5 with drain region 9c as the center. Transistor cell T6 includes contact region 7d, source region 8f, drain region 9c, and gate electrode 11f. Drain region 9c is shared by transistor cells T5 and T6.

[0067] On the upper surface side (upper portion) of the semiconductor substrate 1, a p-type well region 5 having an impurity concentration higher than that of the semiconductor substrate 1 is provided outside the well region 2. + The contact region 6 is connected to the substrate contact electrodes 21 and 29 provided on the upper surface side of the interlayer insulating film 32 via the through holes 21a and 29a penetrating the interlayer insulating film 32. The substrate contact electrodes 21 and 29 can be Figure 1 The front side and the back side of the substrate are connected to each other. The substrate contact electrodes 21 and 29 are covered with a protective insulating film 33. An element isolation insulating film 31 is provided on the side surfaces of both sides of the well region 5 and the contact region 6.

[0068] Figure 2 yes Figure 1 FIG. 1 is a top view of a portion of a semiconductor device according to the first embodiment. Figure 2 The cross section cut along the CC′ line corresponds to Figure 1 The left side of the cross section includes the transistor units T1 to T4. Figure 2 In, omitted Figure 1 The diagram shows the interlayer insulating film 32 , the protective insulating film 33 , the through holes 21 a , 22 a , 22 b , 23 a , 24 a to 24 c , and 25 a , the substrate contact electrode 21 , the source electrodes 22 , 24 , and the drain electrodes 23 , 25 .

[0069] like Figure 2 As shown, the gate electrodes 11a to 11d have a Figure 2 The gate wiring 42 has a stripe-shaped planar pattern extending parallel to each other in the vertical direction (the vertical direction). The gate wiring 42 is provided above the end of the gate electrodes 11a to 11d. The gate wiring 42 has a direction perpendicular to the extending direction of the gate electrodes 11a to 11d ( Figure 2 The gate wiring 42 is electrically connected to the gate electrodes 11a to 11d. Figure 1 The gate electrodes 11e and 11f shown in the figure also have a direction ( Figure 2 A strip-shaped planar pattern extending parallel to each other in the up and down directions) and electrically connected to the gate wiring 42.

[0070] The wiring 41 is provided in a manner separated from the gate wiring 42. The wiring 41 has an extending direction ( Figure 2 The wiring 41 may be a strip-shaped planar pattern extending parallel to the left and right directions of the wiring 41. Figure 1 The source wiring 41 may be connected to the source electrodes 22, 24, 26, and 28 shown in FIG. Figure 1 The drain wiring 41 is connected to the drain electrodes 23, 25, and 27. The wiring 41 may be a wiring to which a potential is applied other than the source wiring or the drain wiring.

[0071] The element isolation insulating film 31 is provided with openings 31a to 31e. Figure 2In the figure, the portions of the openings 31a and 31c of the element isolation insulating film 31 that are hidden directly below the gate electrodes 11a to 11c are schematically shown by dotted lines. The contact region 7a and the source region 8a are exposed in the opening 31a of the element isolation insulating film 31. The drain region 9a is exposed in the opening 31b of the element isolation insulating film 31. The contact region 7b and the source regions 8a and 8c are exposed in the opening 31c of the element isolation insulating film 31. The drain region 9b is exposed in the opening 31d of the element isolation insulating film 31. The contact region 6 is exposed in the opening 31e of the element isolation insulating film 31.

[0072] Figure 3 is shown with Figure 2 FIG. 1 is a top view of the semiconductor device according to the first embodiment at the same position in the plane shown in FIG. Figure 3 In the figure, the solid line schematically shows the n-type semiconductor substrate 1 provided in the p-type semiconductor substrate 1. - type well region 2, p-type channel formation regions 3a, 3b, p-type connection region 3e and p-type well region 5.

[0073] like Figure 3 As shown in FIG. 1 , the well region 2 has a substantially rectangular planar pattern. The channel forming regions 3a and 3b are provided inside the well region 2. The channel forming regions 3a and 3b have a substantially rectangular planar pattern. Figure 3 The connection region 3e is connected to the ends of the channel formation regions 3a and 3b in the extending direction. The connection region 3e has a stripe-shaped planar pattern extending in the direction perpendicular to the extending direction of the gate electrodes 11a to 11d ( Figure 3 In addition, Figure 1 The channel formation regions 3c and 3d shown in the figure also have the same structure as the channel formation regions 3a and 3b in the extending direction of the gate electrodes 11a to 11d ( Figure 3 The well region 5 has a stripe-shaped planar pattern extending in the vertical direction (in the vertical direction) and is connected to the connection region 3e. The well region 5 has a ring-shaped planar pattern surrounding the well region 2.

[0074] Although Figure 3 The illustration is omitted, but Figure 1 The drift regions 4a-4c shown also have an extension direction of the gate electrodes 11a-11d ( Figure 3 The ends of the drift regions 4a to 4c are located inside the well region 2.

[0075] exist Figure 3In the figure, a dotted-line region A1 shows the position of the end of the well region 2, which is located on the end side in the extending direction of the gate electrode 11a and the channel formation region 3a and overlaps with the wiring 41. In addition, a dotted-line region A2 shows the position of the end of the well region 2, which is located on the end side in the extending direction of the gate electrode 11b and the channel formation region 3b and overlaps with the wiring 41. In addition, a dotted-line region A3 shows the position of the end of the well region 2, which is located on the end side in the extending direction of the gate electrode 11c and the channel formation region 3b and overlaps with the wiring 41.

[0076] In the semiconductor device according to the first embodiment, the impurity concentration of the well region 2 at the locations indicated by the dashed lines, regions A2 and A3, is greater than the impurity concentration of the well region 2 at locations overlapping with the wiring 41, excluding the locations indicated by the dashed lines. For example, the impurity concentration of the well region 2 at the locations indicated by the dashed lines, regions A2 and A3, is greater than the impurity concentration of the well region 2 at the locations indicated by the dashed lines, region A1. Furthermore, the impurity concentration of the well region 2 at the locations indicated by the dashed lines, regions A2 and A3, is greater than the impurity concentration of the well region 2 at the locations on the end sides of the drift regions 4a to 4c in the extending direction and overlapping with the wiring 41.

[0077] Figure 4 Shown along Figure 2 and Figure 3 The cross section is cut along the line AA′ passing through the gate electrode 11a. Figure 3 and Figure 4 As shown, the end of the channel formation region 3a is positioned outside the end of the gate electrode 11a in the extending direction of the gate electrode 11a. The end of the well region 2 is positioned outside the end of the channel formation region 3a and overlaps with the wiring 41. An element isolation insulating film 31 is provided on the upper surface side of the end of the channel formation region 3a and the end of the well region 2. The dotted area A1 surrounds the surface of the end of the well region 2.

[0078] Figure 5 Shown along Figure 2 and Figure 3 The cross section is cut along the line BB′ passing through the gate electrode 11b. Figure 3 and Figure 5 As shown, the end of the channel formation region 3b is positioned outside the end of the gate electrode 11b in the extending direction of the gate electrode 11b. The end of the well region 2 is positioned outside the end of the channel formation region 3b and overlaps with the wiring 41. An element isolation insulating film 31 is provided on the upper surface side of the end of the channel formation region 3b and the end of the well region 2. The dotted area A2 surrounds the surface of the end of the well region 2.

[0079] According to the semiconductor device according to the first embodiment, Figures 3 to 5The impurity concentration of the well region 2 at the positions indicated by the dotted lines in the regions A2 and A3 is adjusted to be greater than the impurity concentration of the well region 2 at positions other than the positions indicated by the dotted lines in the regions A2 and A3 that overlap with the wiring 41. Therefore, even if a potential is applied to the wiring 41, it is possible to prevent a channel from being formed on the surface of the well region 2 at the positions indicated by the dotted lines in the regions A2 and A3, thereby preventing the generation of a leakage path.

[0080] <Method for Manufacturing Semiconductor Device>

[0081] Next, an example of a method for manufacturing a semiconductor device according to the first embodiment will be described. Figure 1 The semiconductor device manufacturing method described below is an example, and it is obvious that the semiconductor device can be realized by various other manufacturing methods including the modified examples as long as it is within the scope of the gist described in the claims.

[0082] First, prepare a p-type semiconductor substrate 1 (see Figure 6 ). A photoresist film is applied to the upper surface of the semiconductor substrate 1, and a pattern is formed on the photoresist film using a photolithography technique. The patterned photoresist film is used as a mask for ion implantation, and the ions used to form the n - The n-type impurity ions such as phosphorus (P) in the n-type well region 2 are removed. Then, the photoresist film is removed.

[0083] Next, a photoresist film is applied to the upper surface of the semiconductor substrate 1 and patterned using photolithography. The patterned photoresist film is used as an ion implantation mask to implant p-type impurity ions such as boron (B) to form the p-type channel formation regions 3a to 3d and the p-type well region 5. The photoresist film is then removed.

[0084] Next, a photoresist film is applied to the upper surface of the semiconductor substrate 1 and a pattern is formed in the photoresist film using photolithography. The patterned photoresist film is used as an ion implantation mask to implant n-type impurity ions such as phosphorus (P) to form the n-type drift regions 4a to 4c. The photoresist film is then removed. The order of the ion implantation for forming the well region 2, the ion implantation for forming the p-type channel formation regions 3a to 3d and the p-type well region 5, and the ion implantation for forming the n-type drift regions 4a to 4c is not limited.

[0085] Figure 6 The dashed lines schematically illustrate the - Regions (ion implantation regions) 2a to 2g of the n-type well region 2 into which n-type impurity ions are implanted. Figure 7 The following situation is schematically shown: Figure 1The semiconductor device according to the first embodiment shown in FIG. Figure 6 The ion implantation areas 2a to 2g shown in FIG. - For example, before the breakdown voltage reaches approximately 50 V, a single ion implantation region is formed to form the well region 2. On the other hand, when the breakdown voltage reaches approximately 60 V or higher, the impurity concentration of the well region 2 needs to be lowered. Therefore, multiple slit-shaped ion implantation regions are formed to implant n-type impurities for forming the well region 2. Then, a heat treatment is performed to diffuse the implanted n-type impurities in the lateral direction, forming a single well region 2.

[0086] like Figure 6 and Figure 7 As shown, the ion implantation region 2a is formed to have a width w11 at a position overlapping with the channel formation region 3a. The ion implantation region 2b is formed to have a width w21 wider than the width w11 at a position overlapping with the drift region 4a. The ion implantation region 2c is formed to have a width w31 narrower than the widths w11 and w21 at a position overlapping with the channel formation region 3b. The ion implantation region 2d is formed to have a width w22 of the same degree as the width w21 at a position overlapping with the drift region 4b. The ion implantation region 2e is formed to have a width w32 of the same degree as the width w31 at a position overlapping with the channel formation region 3c. The ion implantation region 2f is formed to have a width w23 of the same degree as the widths w21 and w22 at a position overlapping with the drift region 4c. The ion implantation region 2g is formed to have a width w12 of the same degree as the width w11 at a position overlapping with the channel formation region 3d.

[0087] Figure 8A yes Figure 6 The top view of the stage is schematically shown, with the ion implantation areas 2a to 2d and 2x surrounded by dotted lines and marked with downward diagonal hatching. Figure 8A In FIG, ion implantation regions 3x to 3z for forming p-type channel formation regions 3a, 3b and p-type connection region 3e, and ion implantation region 5x for forming p-type well region 5 are schematically shown by dotted lines. Figure 8A In FIG. 1 , gate electrodes 11 a to 11 d , a wiring 41 , and a gate wiring 42 to be formed in a subsequent step are schematically shown by dotted lines.

[0088] The ion implantation regions 2a to 2d have an extension direction ( Figure 8A The ends of the ion implantation regions 2a to 2d in the extending direction overlap with the wiring 41.

[0089] The ion implantation region 2x is formed so as to overlap with the wiring 41 at the end side of the ion implantation region 2c having a relatively narrow width w31 among the ion implantation regions 2a to 2d. The ion implantation region 2x has a direction perpendicular to the extending direction of the ion implantation region 2c ( Figure 8A The ion implantation region 2x is connected to the end of the ion implantation region 2c. The ion implantation region 2x and the ion implantation region 2c form a T-shaped planar pattern. The ion implantation region 2x is separated from the ion implantation regions 2b and 2d.

[0090] The length L1 of the ion implantation region 2x in the extension direction can be appropriately adjusted within the range of separation from the ion implantation regions 2b and 2d. The width w2 of the ion implantation region 2x in the direction perpendicular to the extension direction can be appropriately adjusted. Figure 8A In the example, the width w2 of the ion implantation region 2x is narrower than the width w1 of the wiring 41. However, the width w2 of the ion implantation region 2x may be the same as the width w1 of the wiring 41 or may be wider than the width w1 of the wiring 41. Figure 8A In the example, the entire ion implantation region 2x overlaps with the wiring 41 , but only a portion of the ion implantation region 2x may overlap with the wiring 41 and the other portion of the ion implantation region 2x may be located outside the wiring 41 .

[0091] also, Figure 6 The ion implantation regions 2e to 2g shown in the figure also have the same shape as the ion implantation regions 2a to 2d, in the extending direction of the gate electrodes 11a to 11d ( Figure 8A The planar pattern is a stripe extending in the vertical direction (in the vertical direction). Furthermore, an ion implantation region similar to the ion implantation region 2x is connected to the end of the relatively narrow ion implantation region 2e having a width w32. Furthermore, the ion implantation region 5x for forming the p-type well region 5, which is not hatched downward and obliquely to the right, has a ring-shaped planar pattern.

[0092] exist Figure 8A In FIG, the ion implantation regions 2a to 2d and 2x are marked with oblique shadows tilted downward to the right. In contrast, Figure 8B In FIG. 1 , ion implantation regions 3x to 3z for forming p-type channel formation regions 3a and 3b and a p-type connection region 3e are schematically shown by being hatched with downward diagonal lines.

[0093] The ion implantation regions 3x and 3y have an extension direction ( Figure 8B The ion implantation region 3z has a stripe-shaped planar pattern extending in the vertical direction of the ion implantation regions 3x and 3y. Figure 8B The strip-shaped portion extending in the vertical direction) and the strip-shaped portion extending in the direction perpendicular to the extending direction of the ion implantation regions 3x and 3y ( Figure 8B A planar pattern of a strip-shaped portion extending in the left and right directions).

[0094] Figure 9 Shown along Figure 8A and Figure 8B The cross section is cut along the AA′ line. Figure 9 As shown, ion implantation regions 3x and 3z for forming a p-type channel formation region 3a and a p-type connection region 3e, and an ion implantation region 5x for forming a p-type well region 5 are formed on the upper portion of the semiconductor substrate 1.

[0095] Figure 10 Shown along Figure 8A and Figure 8B The cross section is cut along the BB′ line. Figure 10 As shown, ion implantation regions 3y and 3z for forming a p-type channel formation region 3b and a p-type connection region 3e, and an ion implantation region 5x for forming a p-type well region 5 are formed on the upper portion of the semiconductor substrate 1. Furthermore, an ion implantation region 5x for forming an n-type well region 5 is formed between the ion implantation regions 3y and 5x on the upper portion of the semiconductor substrate 1. - The ion implantation region 2x of the well region 2 is of the type.

[0096] After the ion implantation for forming the well region 2, the ion implantation for forming the p-type channel formation regions 3a to 3d and the p-type well region 5, and the ion implantation for forming the n-type drift regions 4a to 4c, the p-type impurities and n-type impurities implanted into the semiconductor substrate 1 are activated by heat treatment. As a result, the n-type impurities in the ion implantation regions 2a to 2g diffuse in the lateral direction, as shown in FIG. Figure 11 As shown, an n - A p-type well region 2 is formed. Furthermore, p-type channel formation regions 3a to 3d and n-type drift regions 4a to 4c are formed on the upper surface side of the well region 2. Furthermore, a p-type well region 5 is formed on the upper surface side of the semiconductor substrate 1, outside the well region 2. Figure 11 Along the stage Figure 8A and Figure 8B The cross section cut along the AA′ line corresponds to Figure 12 .in addition, Figure 11 Along the stage Figure 8A and Figure 8B The cross section of the BB′ line corresponds to Figure 13 .

[0097] Furthermore, the heat treatment for forming the well region 2, the heat treatment for forming the channel formation regions 3a to 3d and the well region 5, and the heat treatment for forming the drift regions 4a to 4c may not be performed together but may be performed separately for each ion implantation.

[0098] Then, if Figure 14 As shown, an element isolation insulating film 31 is formed on the upper surface side of the semiconductor substrate 1 by a LOCOS method or the like. Next, a gate insulating film is formed on the upper surface side of the semiconductor substrate 1 by a thermal oxidation method or a chemical vapor deposition (CVD) method or the like. Furthermore, a polysilicon layer (doped polysilicon layer) to which n-type impurities or p-type impurities are added at a high concentration is deposited by a CVD method or the like using a doping gas. Thereafter, a portion of the doped polysilicon layer and the gate insulating film is selectively removed by photolithography and dry etching to form gate insulating films 10a to 10f and gate electrodes 11a to 11f (see Figure 15 ). Then, sidewall insulating films 12a to 12f are formed on the sides of the gate electrodes 11a to 11f by CVD method and dry etching. As a result, Figure 15 As shown, gate electrodes 11a to 11f are formed on the upper surface of the semiconductor substrate 1 via gate insulating films 10a to 10f, and sidewall insulating films 12a to 12f are formed on both sides of the gate electrodes 11a to 11f.

[0099] Then, through photolithography, ion implantation and heat treatment, such as Figure 16 As shown, n is formed on the upper surface side of the channel formation regions 3a to 3d. + Type source regions 8a to 8d and p + In addition, n type contact regions 7a to 7d are formed on the upper surface side of the drift regions 4a to 4c. + In addition, p-type drain regions 9a to 9c are formed on the upper surface side of the well region 5. + Type contact area 6.

[0100] Next, an interlayer insulating film 32 is deposited by CVD or the like to cover the gate electrodes 11a to 11f. Then, a portion of the interlayer insulating film 32 is selectively removed by photolithography and dry etching, thereby forming contact holes that expose the upper surfaces of the source regions 8a to 8d, drain regions 9a to 9c, contact regions 7a to 7d, and contact region 6. Furthermore, the contact holes are filled with a metal film by sputtering, photolithography, and dry etching, thereby forming through-holes 21a, 22a, 22b, 23a, 24a to 24c, 25a, 26a to 26c, 27a, 28a, 28b, and 29a, substrate contact electrodes 21 and 29, source electrodes 22, 24, 26, and 28, and drain electrodes 23, 25, and 27. Then, a protective insulating film 33 is formed to cover the substrate contact electrodes 21, 29, the source electrodes 22, 24, 26, 28, and the drain electrodes 23, 25, 27. Figure 1 The semiconductor device according to the first embodiment shown is completed.

[0101] Here, a semiconductor device according to a first comparative example will be described. Figure 17 is a cross-sectional view of a semiconductor device according to the first comparative example. Figure 17 As shown, the semiconductor device according to the first comparative example is Figure 1 The difference between the semiconductor device according to the first embodiment shown is that the semiconductor device according to the first comparative example is a lateral MOSFET that is not in an array. The semiconductor device according to the first comparative example includes a p-type semiconductor substrate 101 and an n-type semiconductor substrate 101 provided on the upper surface side. - A p-type well region 102 is formed. On the upper surface side of the well region 102, p-type channel formation regions 103a and 103b are provided so as to be separated from each other.

[0102] On the upper surface side of the channel formation region 103a, a p + Type contact areas 107a and n + The contact region 107a is connected to the source electrode 122 via a through hole 122a penetrating the interlayer insulating film 132. The source region 108a is connected to the source electrode 122 via a through hole 122b penetrating the interlayer insulating film 132. The source electrode 122 is covered by a protective insulating film 133.

[0103] An n-type drift region 104 is provided in the center of the upper surface of the well region 102. + The drain region 109 is connected to the drain electrode 123 via a through hole 123a that penetrates the interlayer insulating film 132. An element isolation insulating film 131 is provided on the side surfaces of both sides of the drift region 104 and the drain region 109.

[0104] A gate electrode 111a is provided via a gate insulating film 110a on the upper surfaces of the channel formation region 103a and the well region 102 sandwiched between the source region 108a and the drain region 109. Sidewall insulating films 112a are provided on both sides of the gate electrode 111a.

[0105] On the upper surface side of the channel formation region 103b, an n + Type source region 108b and p + The source region 108b is connected to the source electrode 124 via a through hole 124a penetrating the interlayer insulating film 132. The contact region 107b is connected to the source electrode 124 via a through hole 124b penetrating the interlayer insulating film 132.

[0106] A gate electrode 111b is provided on the upper surface of the channel formation region 103b and the well region 102 sandwiched between the drain region 109 and the source region 108b via a gate insulating film 110b. Sidewall insulating films 112b are provided on both sides of the gate electrode 111b.

[0107] Transistor cell T11 includes a contact region 107a, a source region 108a, a drain region 109, and a gate electrode 111a. Transistor cell T12 has a line-symmetric structure with transistor cell T11, centered around drain region 109. Transistor cell T12 includes a contact region 107b, a source region 108b, a drain region 109, and a gate electrode 111b. Drain region 109 is shared by transistor cells T11 and T12.

[0108] A p-type well region 105 is provided on the upper surface side of the semiconductor substrate 101 at a position outside the well region 102. + The contact region 106 is connected to the substrate contact electrode 121 via a through hole 121a penetrating the interlayer insulating film 132. An element isolation insulating film 131 is provided on the side surfaces of both sides of the well region 105 and the contact region 106.

[0109] Relative to Figure 17 The semiconductor device according to the first comparative example shown, Figure 18 is instead of n - A cross-sectional view schematically illustrates ion implantation regions 102a to 102c used to form the well region 102 during fabrication of the semiconductor device according to the first comparative example, using a well region 102 of the same type as the well region 102. The ion implantation region 102a is formed to have a width w41 so as to overlap with the channel formation region 103a. The ion implantation region 102b is formed to have a width w42 wider than the width w41 so as to overlap with the drift region 104. The ion implantation region 102c is formed to have a width w43 equal to the width w41 so as to overlap with the channel formation region 103b.

[0110] On the other hand, in the semiconductor device according to the first embodiment, Figure 6 and Figure 7 As shown, the widths w31 and w32 of the ion implantation regions 2c and 2e at the locations overlapping the channel formation regions 3b and 3c among the ion implantation regions 2a to 2f are narrower than the widths w41 to w43 of the ion implantation regions 102a to 102c of the semiconductor device according to the first comparative example. Therefore, in the semiconductor device according to the first embodiment, the n-type impurities contained in the ion implantation regions 2c and 2e are not sufficiently diffused in the lateral direction by the heat treatment, and a region with a low impurity concentration is locally formed in the well region 2.

[0111] Next, a semiconductor device according to a second comparative example will be described. The semiconductor device according to the second comparative example is similar to the semiconductor device according to the first embodiment in that both are lateral MOSFETs in an array form. Figure 19 is a plan view for explaining a method for manufacturing a semiconductor device according to a second comparative example. Figure 19 Corresponding to the description Figure 8A A plan view showing a method for manufacturing a semiconductor device according to the first embodiment is shown.

[0112] like Figure 19 As shown, the manufacturing method of the semiconductor device according to the second comparative example is Figure 8A The method for manufacturing a semiconductor device according to the first embodiment shown in the figure is different in that, in the method for manufacturing a semiconductor device according to the second comparative example, in the step for forming n - In the ion implantation step of the well region 2 of the φ-type, ion implantation regions 2a to 2d are formed, but the ion implantation region 2x connected to the ion implantation region 2c is not formed.

[0113] exist Figure 19 In the figure, a dotted area A1 shows the position of the end of the well region 2 at the end of the gate electrode 11a and directly below the wiring 41. In addition, a dotted area A2 shows the position of the end of the well region 2 at the end of the gate electrode 11b and directly below the wiring 41. In addition, a dotted area A3 shows the position of the end of the well region 2 at the end of the gate electrode 11c and directly below the wiring 41.

[0114] In the semiconductor device according to the second comparative example, ion-implanted regions 2a, 2b, and 2d are thicker than ion-implanted region 2c. Therefore, the n-type impurities diffuse sufficiently laterally during the heat treatment. Consequently, the impurity concentration at the end of well region 2, corresponding to the position between ion-implanted regions 2a and 2b, indicated by the dashed line region A1, does not decrease. Consequently, even directly below wiring 41, no channel forms on the surface of the end of well region 2.

[0115] On the other hand, ion-implanted region 2c is thinner than ion-implanted regions 2a, 2b, and 2d, so the n-type impurities do not diffuse sufficiently laterally due to the heat treatment. Consequently, the impurity concentration at the end of well region 2, corresponding to the area between ion-implanted regions 2b and 2c, as indicated by the dashed line A2, becomes lower than the impurity concentration of well region 2 at the location indicated by the dashed line A1. Furthermore, the impurity concentration at the end of well region 2, corresponding to the area between ion-implanted regions 2c and 2d, as indicated by the dashed line A3, becomes lower than the impurity concentration of well region 2 at the location indicated by the dashed line A1. Therefore, when a potential is applied to wiring 41, a channel forms on the surface of the region of well region 2, indicated by the dashed lines A2 and A3, where the impurity concentration is relatively low, and becomes a leakage path.

[0116] In contrast, according to the semiconductor device according to the first embodiment, Figure 8A As shown, in the ion implantation process for forming the well region 2, the ion implantation region 2x is formed on the end side of the ion implantation region 2c that is thinner than the ion implantation regions 2a, 2b, and 2d. As a result, the impurity concentration at the end of the well region 2 corresponding to the position between the ion implantation regions 2b and 2c, as shown by the dotted line region A2, becomes greater than the impurity concentration of the well region 2 at the position shown by the dotted line region A1. In addition, the impurity concentration at the end of the well region 2 corresponding to the position between the ion implantation regions 2c and 2d, as shown by the dotted line region A3, becomes greater than the impurity concentration of the well region 2 at the position shown by the dotted line region A1. Therefore, even if a potential is applied to the wiring 41, it is possible to prevent a channel from being formed on the surface of the well region 2 at the positions shown by the dotted line regions A2 and A3, thereby preventing the generation of a leakage path.

[0117] (Second embodiment)

[0118] Figure 20 is a plan view for explaining a method for manufacturing a semiconductor device according to a second embodiment. Figure 20 Corresponding to the description Figure 8A FIG. 1 is a top view of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. Figure 20 As shown, the manufacturing method of the semiconductor device according to the second embodiment is Figure 8A The difference of the method for manufacturing a semiconductor device according to the first embodiment shown is that the method for forming n - In the ion implantation step of the well region 2, the ion implantation region 2x is formed separately from the ion implantation region 2c. The other steps of the method for manufacturing a semiconductor device according to the second embodiment are substantially the same as those of the method for manufacturing a semiconductor device according to the first embodiment, and therefore, repeated descriptions are omitted.

[0119] According to the method for manufacturing a semiconductor device according to the second embodiment, similarly to the method for manufacturing a semiconductor device according to the first embodiment, the ion implantation region 2x can be formed to prevent the semiconductor device from being implanted. Figures 3 to 5 The impurity concentration of the well region 2 at the positions indicated by the dotted lines A2 and A3 is reduced. Therefore, even if a potential is applied to the wiring 41, it is possible to prevent a channel from forming on the surface of the well region 2 at the positions indicated by the dotted lines A2 and A3, thereby preventing the generation of a leakage path.

[0120] (Third embodiment)

[0121] Figure 21 is a plan view for explaining a method for manufacturing a semiconductor device according to a third embodiment. Figure 21 Corresponding to the description Figure 8AFIG. 1 is a top view of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. Figure 21 As shown in FIG. 8 , the method for manufacturing a semiconductor device according to the third embodiment differs from the method for manufacturing a semiconductor device according to the first embodiment in that the method for forming n - During the ion implantation step of the well region 2, ion implantation regions 2y and 2z are formed separately from ion implantation region 2c. Ion implantation regions 2y and 2z are formed separately from each other. The remaining steps of the method for manufacturing a semiconductor device according to the third embodiment are substantially the same as those of the method for manufacturing a semiconductor device according to the first embodiment, and therefore, repeated descriptions are omitted.

[0122] According to the method for manufacturing a semiconductor device according to the third embodiment, similarly to the method for manufacturing a semiconductor device according to the first embodiment, the ion implantation regions 2y and 2z can be formed to prevent the semiconductor device from being damaged. Figures 3 to 5 The impurity concentration of the well region 2 at the positions indicated by the dotted lines A2 and A3 is reduced. Therefore, even if a potential is applied to the wiring 41, it is possible to prevent a channel from forming on the surface of the well region 2 at the positions indicated by the dotted lines A2 and A3, thereby preventing the generation of a leakage path.

[0123] (Other embodiments)

[0124] As described above, the present disclosure is described through the first to third embodiments, but the description and drawings constituting part of the present disclosure should not be construed as limiting the present disclosure. Based on the present disclosure, various alternative embodiments, examples, and application techniques will become apparent to those skilled in the art.

[0125] For example, in the method for manufacturing the semiconductor device according to the first to third embodiments, Figure 7 As shown in the figure, the ion implantation regions 2c and 2e in the ion implantation regions 2a to 2g that overlap with the channel formation regions 3b and 3c are relatively thin, but the present invention is not limited to this. For example, the ion implantation regions 2b, 2d, and 2f that overlap with the drift regions 4a to 4c may also be relatively thin. In this case, the ends of the relatively thin ion implantation regions 2b, 2d, and 2f are formed to overlap with the channel formation regions 3b and 3c. Figure 8A The ion implantation region 2x shown may be the same ion implantation region.

[0126] Furthermore, although lateral MOSFETs are exemplified as the semiconductor devices according to the first to third embodiments, the semiconductor devices can also be applied to lateral IGBTs.

[0127] Furthermore, the structures disclosed in the first to third embodiments can be appropriately combined within the scope of non-inconsistency. As such, it goes without saying that the present disclosure includes various embodiments not described herein. Therefore, the scope of protection of the present disclosure is determined solely by the invention-specific matters covered by the claims, which are appropriately derived from the above description.

[0128] Description of Reference Numerals

[0129] 1. 101: semiconductor substrate; 2. 102: well region; 2a-2d, 2x-2z, 102a-102c: ion implantation region; 3a-3d, 103a, 103b: channel formation region (well region); 3e: connection region; 3x-3z: ion implantation region; 4a-4c, 104: drift region; 5. 105: well region; 5x: ion implantation region; 6. 7a-7d, 106, 107a, 107b: contact region; 8a-8f, 108a, 108b: carrier supply region (source region); 9a-9c, 109: carrier receiving region (drain region); 10a-10f, 110a, 110b: gate insulating film; 11a-11f, 111a, 111b: gate electrode; 12a-12f, 112a, 112b: sidewall insulating film; 21, 29, 121: substrate contact electrode; 21a, 22a, 22b, 23a, 24a~24c, 25a, 26a~26c, 27a, 28a, 28b, 29a, 121a, 122a, 122b, 123a, 124a, 124b: through hole; 22, 24, 26, 28, 122, 124: source electrode; 23, 25, 27, 123: drain electrode; 31, 131: element isolation insulating film; 31a~31e: opening; 32, 132: interlayer insulating film; 33, 133: protective insulating film; 41: wiring; 42: gate wiring; A1~A3: region; T1~T6, T11, T12: transistor unit.

Claims

1. A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a well region of a second conductivity type, which is provided on the upper surface side of the semiconductor substrate; a plurality of channel formation regions of a first conductivity type, the plurality of channel formation regions being provided on an upper surface side of the well region and extending parallel to one another in one direction when viewed from above; a plurality of drift regions of the second conductivity type, the plurality of drift regions and the plurality of channel formation regions being alternately provided on the upper surface side of the well region and extending parallel to each other along the one direction; a second conductive type carrier supply region provided on the upper surface side of each of the plurality of channel formation regions; a carrier receiving region of the second conductivity type, disposed on the upper surface side of each of the plurality of drift regions; a plurality of gate electrodes provided on an upper surface side of the channel formation region sandwiched between the carrier supply region and the well region via a gate insulating film, and extending parallel to each other in the one direction; as well as a wiring provided above the well region and extending in a direction perpendicular to the one direction at end sides of the plurality of channel formation regions and end sides of the plurality of drift regions in the one direction; The impurity concentration of the well region located on the end side of the channel formation region sandwiched between the adjacent drift regions and overlapping with the wiring is higher than the impurity concentration of the well region located on the end side of the plurality of drift regions and overlapping with the wiring.

2. The semiconductor device according to claim 1, wherein Two transistor cells each including one of the adjacent gate electrodes share the carrier supply region and are arranged line-symmetrically with the carrier supply region as the center.

3. The semiconductor device according to claim 1, wherein Two transistor units, each including one of the adjacent gate electrodes, share the carrier receiving region and are arranged in line symmetry with the carrier receiving region as the center.

4. A method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device according to claim 1, wherein: The process of forming the well region includes: A plurality of first ion implantation regions extending parallel to each other in the one direction and having different widths are formed by ion implantation of second conductivity type impurities, and a second ion implantation region extending in a direction orthogonal to the one direction is formed at an end side of a first ion implantation region having a relatively narrow width among the plurality of first ion implantation regions and overlapping with the wiring; as well as The impurities implanted into the first ion implantation region and the second ion implantation region are diffused in a lateral direction by heat treatment to form the well region.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: The first ion implantation region having a relatively narrow width is formed at a position overlapping with the channel formation region sandwiched between the adjacent drift regions.

6. The method for manufacturing a semiconductor device according to claim 4 or 5, wherein: The second ion implantation region is formed so as to be connected to an end portion of the first ion implantation region having a relatively narrow width.

7. The method for manufacturing a semiconductor device according to claim 4 or 5, wherein: The second ion implantation region is formed so as to be separated from an end portion of the first ion implantation region having a relatively narrow width.

8. The method for manufacturing a semiconductor device according to claim 4 or 5, wherein: A plurality of the second ion implantation regions are formed so as to be separated from each other in a direction orthogonal to the one direction.

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