Semiconductor structure

Abstract

The invention discloses a semiconductor structure, and the semiconductor structure comprises a substrate which is provided with a heavily doped region; the epitaxial layer is located on the substrate, and a functional area is arranged on the epitaxial layer; the transistor unit comprises a PMOS tube and an NMOS tube which are formed on the functional region; and the electric connection structure penetrates through the epitaxial layer and is electrically connected with the heavily doped region, the electric connection structure is arranged outside the functional region and is electrically isolated from the transistor unit, and bias voltage is applied to the electric connection structure. According to the semiconductor structure, the single-particle latch-up effect can be effectively protected.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a semiconductor structure. Background Art

[0002] There are a large number of high-energy particles in outer space, such as protons, electrons, and heavy ions. When bombarded by these high-energy particles, integrated circuits composed of PMOS and NMOS transistors can experience single-event latch-up, which can have a significant negative impact on the normal operation of the integrated circuits. When integrated circuits are used in aviation and aerospace, they are even more susceptible to this radiation-induced single-event latch-up, causing unstable operation. Therefore, the development of advanced radiation hardening technologies in integrated circuits is particularly important.

[0003] The radiation hardening technology commonly used in the prior art is to add a protection circuit to the integrated circuit design. Once a large latch-up current is generated in the integrated circuit due to radiation, the designed protection circuit immediately cuts off the large latch-up current, preventing the components in the integrated circuit from burning out and causing failures, thereby protecting the components in the integrated circuit. Another commonly used radiation hardening technology is to increase the size of the key parameters of the components in the design guidelines of the existing components to avoid the latch-up effect. In addition, the radiation hardening technology in the prior art also forms a semiconductor structure that can resist the latch-up effect by adding many other redundant designs to avoid a single circuit failure that leads to the failure of the entire system. In short, whether it is adding redundant designs or increasing the layout of components in the integrated circuit, traditional radiation hardening technology will significantly increase the area of the integrated device after integration, and the overall layout needs to be adjusted in real time according to different designs, which increases time costs.

[0004] Therefore, in order to solve the above technical problems, it is necessary to provide a semiconductor structure. Summary of the Invention

[0005] An object of the present invention is to provide a semiconductor structure capable of enhancing the ability of an integrated circuit to resist single event latch-up.

[0006] In order to achieve the above-mentioned purpose, the technical solution provided by one embodiment of the present invention is as follows:

[0007] A semiconductor structure, comprising:

[0008] a substrate having a heavily doped region formed thereon;

[0009] an epitaxial layer located on the substrate, wherein a functional region is provided on the epitaxial layer;

[0010] A transistor unit, comprising a PMOS transistor and an NMOS transistor formed on the functional area;

[0011] An electrical connection structure, wherein the electrical connection structure penetrates the epitaxial layer and is electrically connected to the heavily doped region, the electrical connection structure is arranged outside the functional region and is electrically isolated from the transistor unit, and a bias voltage is applied to the electrical connection structure.

[0012] In one embodiment, the heavily doped region is a P-type heavily doped region, and the electrical connection structure is connected to a reference potential.

[0013] In one embodiment, the heavily doped region is an N-type heavily doped region, and the electrical connection structure is connected to a high potential.

[0014] In one embodiment, the heavily doped region includes a P-type heavily doped region and an N-type heavily doped region, the electrical connection structure includes a P-type electrical connection structure and an N-type electrical connection structure, the P-type heavily doped region is electrically connected to the P-type electrical connection structure, the N-type heavily doped region is electrically connected to the N-type electrical connection structure, the P-type electrical connection structure is connected to a reference potential, and the N-type electrical connection structure is connected to a high potential.

[0015] In one embodiment, the concentration of the heavily doped region is 1E14 cm -3 ~1E20cm -3 ;or,

[0016] The concentration of the heavily doped region is greater than or equal to 1E20 cm -3 .

[0017] In one embodiment, the heavily doped region includes a first region and a second region extending outward from the first region, the second region is located in the substrate at least below a portion of the functional region, and the shape of the second region is comb-shaped, spiral-shaped, rectangular or circular.

[0018] In one embodiment, the electrical connection structure is a metal structure; or,

[0019] The electrical connection structure is a polysilicon structure; or,

[0020] The electrical connection structure includes, from bottom to top, a first doping layer, a second doping layer and a third doping layer formed in the epitaxial layer, wherein the first doping layer is in contact with the heavily doped region.

[0021] In one embodiment, the electrical connection structure includes, from bottom to top, a first doping layer, a second doping layer, and a third doping layer formed in the epitaxial layer, the first doping layer is in contact with the heavily doped region, and the doping concentration of the first doping layer is greater than or equal to 1E17 cm -3 .

[0022] In one embodiment, a first guard ring is formed on the epitaxial layer and surrounds the PMOS transistor, and the first guard ring is N-type doped; and / or,

[0023] A second guard ring is formed on the epitaxial layer and surrounds the NMOS transistor. The second guard ring is P-type doped.

[0024] In one embodiment, a P-well is formed in the epitaxial layer below the functional area, and the NMOS transistor is formed in the P-well; and / or,

[0025] An N-well is formed in the epitaxial layer below the functional area, and the PMOS transistor is formed in the N-well.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] The present invention adds a heavily doped region to the substrate, integrates the device on the epitaxial layer on the substrate, and leads the heavily doped region out through an electrical connection structure. At the same time, a bias voltage is applied to the electrical connection structure. When a single-event latch-up effect occurs in the circuit, the large latch-up current can be quickly eliminated, thus effectively protecting the devices in the circuit.

[0028] The semiconductor structure of the present invention not only plays an effective role in radiation resistance reinforcement, but also avoids the area effect caused by relaxing the device layout in the prior art, simplifies the design process, and reduces costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 Schematic diagram of the semiconductor structure in Example 1 of the present invention;

[0031] Figure 2 The design layout of the semiconductor structure in Example 1 of the present invention;

[0032] Figure 3 is a design layout of another semiconductor structure in Example 1 of the present invention;

[0033] Figure 4 is a schematic structural diagram of another semiconductor structure in Example 1 of the present invention;

[0034] Figure 5 The design layout of the semiconductor structure in Example 2 of the present invention;

[0035] Figure 6 The design layout of the semiconductor structure in Example 3 of the present invention;

[0036] Figures 7a to 7c The design layout of the semiconductor structure with the electrical connection structure at different positions in Example 3 of the present invention;

[0037] Figure 8 The design layout of the semiconductor structure in Example 4 of the present invention;

[0038] Figures 9a to 9c The design layout of the semiconductor structure with the electrical connection structure at different positions in Example 4 of the present invention;

[0039] Figure 10 The design layout of the semiconductor structure in Example 5 of the present invention;

[0040] Figure 11 The design layout of the semiconductor structure in Example 7 of the present invention;

[0041] Figure 12 This is the design layout of the semiconductor structure in Comparative Example 1 of the present invention;

[0042] Figure 13 is a schematic diagram of radiation incident on a semiconductor structure at point A in the present invention;

[0043] Figure 14 : This is the simulation result of the semiconductor structure in Comparative Example 1 when the radiation in the present invention is incident at point A;

[0044] Figure 15 : is the simulation result of the semiconductor structure in Example 1 when the radiation in the present invention is incident at point A;

[0045] Figure 16 : This is the simulation result of the semiconductor structure in Example 6 when the radiation is incident at point A in the present invention;

[0046] Figure 17 This is the simulation result of the semiconductor structure in Example 7 when the radiation is incident at point A in the present invention.

[0047] Description of main reference numerals:

[0048] 10-substrate, 101-heavily doped region, 20-epitaxial layer, 201-N well, 202-P well, 301-PMOS transistor, 302-NMOS transistor, 40-electrical connection structure, 401-first doped layer, 402-second doped layer, 403-third doped layer, 501-first guard ring, 502-second guard ring, 60-isolation region, 21-first epitaxial layer, 22-second epitaxial layer, 4011-first doped portion, 4012-second doped portion, 1011-first region, 1012-second region, 41-first electrical connection structure, 42-second electrical connection structure. DETAILED DESCRIPTION

[0049] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0050] The present invention discloses a semiconductor structure, comprising:

[0051] a substrate having a heavily doped region formed thereon;

[0052] An epitaxial layer is located on the substrate, and a functional region is provided on the epitaxial layer;

[0053] A transistor unit, comprising a PMOS transistor and an NMOS transistor formed on the functional area;

[0054] The electrical connection structure penetrates the epitaxial layer and is electrically connected to the heavily doped region. The electrical connection structure is arranged outside the functional region and is electrically isolated from the transistor unit. A bias voltage is applied to the electrical connection structure.

[0055] The semiconductor structure of the present invention is applied to an integrated circuit. When the circuit is exposed to radiation and a single-particle latch-up effect occurs, and holes and electron pairs appear in the semiconductor structure, or a large number of holes and electrons are derived, the generated holes and electrons can be absorbed by the heavily doped region below and conducted out through the electrical connection structure, without causing damage to the devices in the integrated circuit and leading to functional failure of the circuit.

[0056] It is worth noting that the semiconductor structure of the present invention is mainly used to protect against single event latch-up effects caused by radiation in integrated circuits, but it can also protect against conventional latch-up effects.

[0057] The present invention is further described below with reference to specific examples.

[0058] Example 1:

[0059] Ginseng Figure 1 As shown, the semiconductor structure in this embodiment includes:

[0060] A substrate 10 having a heavily doped region 101 formed thereon;

[0061] The epitaxial layer 20 is located on the substrate 10 and has a functional area.

[0062] A transistor unit, comprising a PMOS transistor 301 and an NMOS transistor 302 formed on a functional region;

[0063] The electrical connection structure 40 penetrates the epitaxial layer 20 and is electrically connected to the heavily doped region 101 . The electrical connection structure 40 is disposed outside the functional region and is electrically isolated from the transistor unit. A bias voltage is applied to the electrical connection structure 40 .

[0064] In this embodiment, the substrate 10 is a P-type substrate, the heavily doped region 101 is a P-type heavily doped region, and the dopant includes but is not limited to B dopant, BF2 dopant or In dopant, and the doping concentration is 1E14cm -3 ~1E20cm -3 , or the doping concentration is greater than or equal to 1E20cm -3 .

[0065] The heavily doped region 101 can be prepared first, and then the epitaxial layer 20 can be prepared on the substrate 10, or the epitaxial layer 20 can be prepared first, and then during the process of preparing the electrical connection structure 40, the implantation amount at the bottom of the electrical connection structure 40 can be increased to form the heavily doped region 101 on the substrate 10. In this embodiment, the heavily doped region 10 is provided in the substrate 10 below the epitaxial layer 20, and the subsequent preparation process of the transistor on the surface of the epitaxial layer 20 and the performance of the transistor will not be affected by the heavily doped region 101.

[0066] In addition, combined Figure 2 As shown, the heavily doped region 101 includes a first region 1011 and a second region 1012 extending outward from the first region 1011. The second region 1012 is located in the substrate below at least part of the functional region, and the shape of the second region is comb-shaped, spiral-shaped, rectangular or circular.

[0067] Preferably, in this embodiment, the shape of the second region is comb-shaped, and the second region 1012 is along the first direction ( Figure 2 The substrate 10 extends in the Y direction to the bottom of the functional area.

[0068] In this embodiment, the epitaxial layer 20 can be a P-type epitaxial layer or an N-type epitaxial layer, and the thickness of the epitaxial layer 20 is greater than or equal to 1 μm. In this embodiment, an N-well 201 and a P-well 202 are formed in the epitaxial layer 20 below the functional area. The P-well 202 and the N-well 201 are connected along a first direction. The NMOS transistor is formed in the P-well, and the PMOS transistor is formed in the N-well.

[0069] In other embodiments, the P-well and the N-well may be spaced apart, or an N-type epitaxial layer may be used, with the P-well formed only in the epitaxial layer below the functional region, the NMOS tube being formed in the P-well, and the PMOS tube being formed in the N-type epitaxial layer outside the P-well; or a P-type epitaxial layer may be used, with the N-well formed only in the epitaxial layer below the functional region, the PMOS tube being formed in the N-well, and the NMOS tube being formed in the P-type epitaxial layer outside the N-well.

[0070] It should be understood that the PMOS transistor 301 and the NMOS transistor 302 respectively include a source, a drain and a gate (not shown), and the PMOS transistor 301 and the NMOS transistor 302 can be high-voltage MOS transistors or low-voltage MOS transistors respectively or simultaneously.

[0071] The semiconductor structure in this embodiment also includes a first guard ring 501 surrounding the PMOS transistor 301 and a second guard ring 502 surrounding the NMOS transistor 302. The first guard ring 501 is formed in the N-well 201, and the second guard ring 502 is formed in the P-well 202. The first guard ring 501 is doped with N-type, forming an N+ guard ring, while the second guard ring 502 is doped with P-type, forming a P+ guard ring. In this embodiment, the first guard ring 501 and the second guard ring 502 serve as N-well and P-well contacts, respectively, electrically connected to an external power supply, providing a certain degree of protection against latch-up.

[0072] It should be understood that in other embodiments, only a first guard ring surrounding the PMOS transistor may be formed on the epitaxial layer, or only a second guard ring surrounding the NMOS transistor may be formed on the epitaxial layer.

[0073] Specifically, the semiconductor structure in this embodiment includes two electrical connection structures 40 symmetrically arranged on both sides of the functional area, and a P-type heavily doped region is provided directly below the two electrical connection structures. The electrical connection structure 40 is in contact with the P-type heavily doped region. The electrical connection structure 40 and the P-type heavily doped region are both long strips. Figure 2 (in the X direction) settings.

[0074] The heavily doped regions 101 in this embodiment are all P-type heavily doped regions, the electrical connection structures 40 are all P-type electrical connection structures, and the electrical connection structures 40 are all connected to a reference potential.

[0075] It is worth mentioning that Figure 3 As shown, the electrical connection structure 40 can be arranged adjacent to the functional area, or a large distance can be left between the functional area and the electrical connection structure 40.

[0076] More specifically, the electrical connection structure 40 in this embodiment includes, from bottom to top, a first doping layer 401 , a second doping layer 402 and a third doping layer 403 formed in the epitaxial layer 20 , and the first doping layer 401 is in contact with the heavily doped region 101 .

[0077] The first doping layer 401 is a deep P-well, the second doping layer 402 is a P-well, and the third doping layer 403 is a P-type heavily doped layer. The concentration of the first doping layer 401 is greater than or equal to 1E17 cm -3 , ensuring that the doping layer is at high concentration and low resistance, making it easy to conduct.

[0078] It is worth noting that in other embodiments, the electrical connection structure 40 may also be a metal structure or a P+ polysilicon structure. The metal structure has the lowest resistance and the best electrical connection effect. In comparison, the method of gradually forming the first doped layer 401, the second doped layer 402, and the third doped layer 403 by implantation is more convenient to prepare, without the need for etching and then metal deposition. However, as the depth increases, the energy required for doping will also increase, and the doping concentration will also decrease accordingly.

[0079] In addition, since the conventional epitaxial layer 20 is relatively thick, it is difficult to achieve a good quality deep well structure with the existing doping technology. Figure 4 As shown, in another embodiment, a first epitaxial layer 21 can be prepared first, and the first epitaxial layer 21 is injected once to form a first doped portion 4011 of the first doped layer. Then, a second epitaxial layer 22 is prepared on the first epitaxial layer 21, and injected twice to form a second doped portion 4012 of the first doped layer, a second doped layer 402 and a third doped layer 403. An electrical connection structure in contact with the heavily doped region is formed by the two injections.

[0080] Combine Figure 1 As shown, in this embodiment, isolation regions 60 are provided between the various devices and between the MOS tubes and the guard rings. Preferably, isolation regions 60 are also provided between the functional areas and the electrical connection structures. Surface isolation between the various structures is performed by shallow trench isolation to prevent surface breakdown.

[0081] Example 2:

[0082] Ginseng Figure 5 As shown, the semiconductor structure in this embodiment is substantially the same as that in embodiment 1, except that the heavily doped region in this embodiment only includes a first region located directly below the electrical connection structure and in contact with the electrical connection structure, and does not include a second region extending outward from the first region.

[0083] Example 3:

[0084] Ginseng Figure 6 As shown, the semiconductor structure in this embodiment is substantially the same as that in embodiment 1, except that the semiconductor structure in this embodiment includes only one P-type heavily doped region and an electrical connection structure electrically connected to the P-type heavily doped region.

[0085] It is worth noting that, combined with Figure 7a to Figure 7c As shown, the heavily doped region and the electrical connection structure do not need to be limited to a fixed position. The heavily doped region and the electrical connection structure can be arranged on one side of the functional region along the second direction, or on one side of the functional region along the first direction. The second region of the heavily doped region extends outward in a direction perpendicular to the first region to the substrate below the functional region.

[0086] Example 4:

[0087] Ginseng Figure 8 As shown, the semiconductor structure in this embodiment is substantially the same as that in Example 1, except that the semiconductor structure in this embodiment includes only one P-type heavily doped region and an electrical connection structure electrically connected to the P-type heavily doped region, and the heavily doped region includes only a first region located directly below the electrical connection structure and in contact with the electrical connection structure, and does not include a second region extending outward from the first region.

[0088] It is worth noting that, combined with Figure 9a to Figure 9c As shown, the heavily doped region and the electrical connection structure do not need to be limited to a fixed position. The heavily doped region and the electrical connection structure can be arranged on one side of the functional region along the second direction or along the first direction.

[0089] Example 5:

[0090] Ginseng Figure 10 As shown, the semiconductor structure in this embodiment is substantially the same as that in embodiment 1, except that the semiconductor structure includes two groups of symmetrically arranged electrical connection structures, each of which is electrically connected to a heavily doped region, and the heavily doped region includes a first region and a second region extending outward from the first region, the second region being located in the substrate below at least part of the functional region, and the shape of the second region is comb-tooth-shaped, spiral-shaped, rectangular or circular.

[0091] Specifically, a group of electrical connection structures are symmetrically arranged on both sides of the functional area along a first direction, and a group of electrical connection structures are symmetrically arranged on both sides of the functional area along a second direction. The second region of the heavily doped region electrically connected to the electrical connection structures arranged along the first direction has a comb-tooth shape and extends along the second direction; the second region of the heavily doped region electrically connected to the electrical connection structures arranged along the second direction also has a comb-tooth shape and extends along the first direction.

[0092] Example 6:

[0093] The semiconductor structure in this embodiment is substantially the same as that in embodiment 1, except that the heavily doped region is an N-type heavily doped region, the first doped layer in the electrical connection structure is an N-deep well, the second doped layer is an N-well, and the third doped layer is an N-type heavily doped layer.

[0094] The heavily doped regions in this embodiment are all N-type heavily doped regions, the dopants are P dopants, As dopants or Sb dopants, the electrical connection structures are all N-type electrical connection structures, and the electrical connection structures are all connected to a high potential.

[0095] Example 7:

[0096] Ginseng Figure 11As shown, the semiconductor structure in this embodiment is substantially the same as that in Example 1, except that the heavily doped region in this embodiment includes a first heavily doped region 1011 and a second heavily doped region 1012. The first heavily doped region 1011 is a P-type heavily doped region, and the second heavily doped region 1012 is an N-type heavily doped region. The electrical connection structure includes a first electrical connection structure 41 and a second electrical connection structure 42. The first electrical connection structure 41 is a P-type electrical connection structure, and the second electrical connection structure 42 is an N-type electrical connection structure. The first electrical connection structure 41 is electrically connected to the first heavily doped region 1011, and the second electrical connection structure 42 is electrically connected to the second heavily doped region 1012. The first electrical connection structure 41 is connected to a reference point, and the second electrical connection structure 42 is connected to a high potential.

[0097] It should be understood that the voltage between the first electrical connection structure and the second electrical connection structure needs to be adjusted according to the operating voltage of the MOS tube in the actual circuit, and must not exceed the maximum operating voltage of the MOS tube.

[0098] The P-type heavily doped region and the N-type heavily doped region in this embodiment respectively include a first region and a second region. The second region is comb-shaped, spiral-shaped, rectangular or circular, preferably comb-shaped, and extends into the substrate below the P-well and N-well.

[0099] The substrate in this embodiment is a P-type substrate or an N-type substrate. A P-type heavily doped region and an N-type heavily doped region can be formed on the substrate respectively through photolithography and implantation processes. Alternatively, only N-type dopants can be directly implanted on the P-type substrate to form only N-type heavily doped regions, or only P-type dopants can be directly implanted on the N-type substrate to form only P-type heavily doped regions.

[0100] It should be understood that the width of each tooth of the comb-shaped second region is not limited, and the teeth of adjacent single P-type heavily doped regions and single N-type heavily doped regions may be spaced apart or directly connected.

[0101] Comparative Example 1:

[0102] Ginseng Figure 12 The figure shows the design layout of a semiconductor structure with PMOS and NMOS transistor units in a conventional integrated circuit. The semiconductor structure in this layout does not have a heavily doped region in the substrate, nor is there an electrical connection structure in the epitaxial layer electrically connected to the heavily doped region. It is protected only by a guard ring.

[0103] The present invention simulates the radiation hardening effect of the semiconductor structures in Comparative Example 1, Example 1, Example 6 and Example 7. In an integrated circuit, the most dangerous situation is when space radiation is incident from the boundary between the N-well and P-well of the semiconductor structure. Figure 13As shown, in the present invention, point A is used as the incident point of radiation to simulate the radiation hardening effect of the semiconductor structure.

[0104] Ginseng Figure 14 The figure shows the simulation results of the semiconductor structure in comparative example 1. The results show that after the latch-up current appears in the semiconductor structure in comparative example 1, the latch-up current still cannot decrease after 100ns.

[0105] Ginseng Figure 15 As shown, compared with Comparative Example 1, the semiconductor structure in Example 1 has a large latch-up current that decreases after 5 ns, which can effectively protect against the single-particle latch-up effect.

[0106] Ginseng Figure 16 and Figure 17 As shown, when the single-particle latch effect occurs, the semiconductor structures in Examples 6 and 7 can also lead out a large number of derived holes and electrons in a short time and quickly eliminate the large latch current.

[0107] It can be seen from the above technical solution that the present invention has the following beneficial effects:

[0108] The present invention adds a heavily doped region to the substrate, integrates the device on the epitaxial layer on the substrate, and leads the heavily doped region out through an electrical connection structure. At the same time, a bias voltage is applied to the electrical connection structure. When a single-event latch-up effect occurs in the circuit, the large latch-up current can be quickly eliminated, thus effectively protecting the devices in the circuit.

[0109] The semiconductor structure of the present invention not only plays an effective role in radiation resistance reinforcement, but also avoids the area effect caused by relaxing the device layout in the prior art, simplifies the design process, and reduces costs.

[0110] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0111] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A semiconductor structure, characterized in that The semiconductor structure comprises: a substrate having a heavily doped region formed thereon; an epitaxial layer located on the substrate, wherein a functional region is provided on the epitaxial layer; A transistor unit, comprising a PMOS transistor and an NMOS transistor formed on the functional area; An electrical connection structure, wherein the electrical connection structure penetrates the epitaxial layer and is electrically connected to the heavily doped region, the electrical connection structure is arranged outside the functional region and is electrically isolated from the transistor unit, and a bias voltage is applied to the electrical connection structure.

2. The semiconductor structure according to claim 1, wherein: The heavily doped region is a P-type heavily doped region, and the electrical connection structure is connected to a reference potential.

3. The semiconductor structure according to claim 1, wherein: The heavily doped region is an N-type heavily doped region, and the electrical connection structure is connected to a high potential.

4. The semiconductor structure according to claim 1, wherein: The heavily doped region includes a P-type heavily doped region and an N-type heavily doped region, the electrical connection structure includes a P-type electrical connection structure and an N-type electrical connection structure, the P-type heavily doped region is electrically connected to the P-type electrical connection structure, the N-type heavily doped region is electrically connected to the N-type electrical connection structure, the P-type electrical connection structure is connected to a reference potential, and the N-type electrical connection structure is connected to a high potential.

5. The semiconductor structure according to claim 1, wherein: The concentration of the heavily doped region is 1E14 cm -3 ~1E20cm -3 ;or, The concentration of the heavily doped region is greater than or equal to 1E20 cm -3 . The semiconductor structure according to claim 1 , wherein: The heavily doped region includes a first region and a second region extending outward from the first region. The second region is located in the substrate below at least part of the functional region. The shape of the second region is comb-shaped, spiral-shaped, rectangular or circular.

7. The semiconductor structure according to claim 1, wherein: The electrical connection structure is a metal structure; or, The electrical connection structure is a polysilicon structure; or, The electrical connection structure includes, from bottom to top, a first doping layer, a second doping layer and a third doping layer formed in the epitaxial layer, wherein the first doping layer is in contact with the heavily doped region.

8. The semiconductor structure according to claim 1, wherein: The electrical connection structure includes, from bottom to top, a first doping layer, a second doping layer, and a third doping layer formed in the epitaxial layer, wherein the first doping layer contacts the heavily doped region, and the doping concentration of the first doping layer is greater than or equal to 1E17 cm -3 .

9. The semiconductor structure according to claim 1, wherein: A first guard ring is formed on the epitaxial layer and surrounds the PMOS transistor, and the first guard ring is N-type doped; and / or, A second guard ring is formed on the epitaxial layer and surrounds the NMOS transistor. The second guard ring is P-type doped.

10. The semiconductor structure according to claim 1, wherein: A P-well is formed in the epitaxial layer below the functional area, and the NMOS transistor is formed in the P-well; and / or, An N-well is formed in the epitaxial layer below the functional area, and the PMOS transistor is formed in the N-well.

Images