Embedded cooling assembly for advanced device package and method of manufacturing same

Abstract

A device package may include a package substrate, a package cover disposed on the package substrate, and an integrated cooling assembly disposed between the package substrate and the package cover. The encapsulation cover generally has an inlet opening and an outlet opening disposed through the encapsulation cover. The integrated cooling assembly includes a semiconductor device and a cold plate attached to the semiconductor device. The device package may include a material layer between the package cover and the cold plate. The cold plate may include a patterned first side and an opposing second side. The patterned first side may include a substrate surface and a sidewall extending downwardly from the substrate surface, wherein the substrate surface is spaced apart from the semiconductor device to collectively define a coolant channel. Here, the coolant channels are in fluid communication with the inlet opening and the outlet opening through openings disposed through respective portions of the material layer.

Description

Technical Field

[0001] The present disclosure relates to advanced packaging for microelectronic devices, and more particularly to embedded cooling systems for device packages and methods of making the same. Background Art

[0002] Energy consumption poses a key challenge to the future of large-scale computing, as the world's computing energy requirements are rising at a rate that most consider unsustainable. Some models predict that by 2030, the information and communications technology (ICT) ecosystem could account for more than 20% of global electricity consumption, with large-scale computing centers directly consuming more than one-third of this energy. Cooling costs constitute a significant portion of computing center energy requirements, as even small increases in operating temperature can adversely affect the performance of microprocessors, memory devices, and other electronic components.

[0003] Heat dissipation in high power density chips is also a key challenge because improvements in chip performance (e.g., through increased gate density and multi-core microprocessors) have led to increased power density and a corresponding increase in heat flux that contributes to high chip temperatures. These high temperatures are undesirable because they may reduce the operating performance, efficiency, and reliability of the chip. Cooling systems used to maintain the chip at a desired operating temperature typically use one or more heat dissipation devices (e.g., heat spreaders, heat pipes, cold pipes, and heat sinks) to remove heat, and the heat dissipation devices are thermally coupled to the chip using a compliant thermally conductive material (TIM) (e.g., thermal glue, thermal adhesive, thermal gap filler, etc.). The thermal interface material maintains thermal contact with the surface of the chip and the (multiple) heat dissipation devices to promote heat transfer therebetween. Unfortunately, the combined thermal resistance of the thermal interface material and the thermal resistance at the interface boundary area can inhibit heat transfer from the chip to the heat dissipation device, thereby undesirably reducing the cooling efficiency of the cooling system.

[0004] Therefore, there is a need in the art for improved high performance cooling systems and methods of making the same. Summary of the Invention

[0005] Embodiments herein provide an integrated device cooling assembly embedded in an advanced device package. Advantageously, the integrated device cooling assembly shortens the thermal resistance path between the device and the coolant fluid and reduces thermal communication between devices disposed in the same package.

[0006] In one general aspect, a device package may include a package substrate, a package cover disposed on the package substrate, and an integrated cooling assembly disposed between the package substrate and the package cover. The package cover typically has an inlet opening and an outlet opening disposed through the package cover. The integrated cooling assembly includes a semiconductor device and a cold plate attached to the semiconductor device. The device package may further include a material layer disposed between the package cover and the cold plate. The cold plate may include a patterned first side and an opposing second side. The patterned first side may include a base surface and a sidewall extending downward from the base surface, wherein the base surface is spaced apart from the semiconductor device to jointly define a coolant channel therebetween. Here, the coolant channel is in fluid communication with the inlet opening and the outlet opening through an opening disposed through a corresponding portion of the material layer.

[0007] Implementations may include a method of manufacturing a device assembly, wherein the method includes: directly bonding a first substrate having a semiconductor device to a second substrate having a cold plate; and singulating an integrated cooling assembly having the semiconductor device and the cold plate from the bonded first and second substrates. The method may also include: sealingly attaching a package cover to the second side using a material layer; and forming an opening in the material layer before or after attaching the package cover to the second side. Here, the cold plate may have a first side directly bonded to the semiconductor device and a second side opposite the first side. Generally speaking, one or more surfaces of the first side are spaced apart from the semiconductor device to define a coolant channel therebetween. The package cover may have an inlet opening and an outlet opening. The opening in the material layer may fluidly connect the inlet opening and the outlet opening to the coolant channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other objects and advantages of the present disclosure will become apparent upon consideration of the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a schematic plan view of an example of a system panel according to an embodiment of the present disclosure;

[0010] Figure 2 yes Figure 1 a schematic partial cross-sectional side view of a portion of a system panel;

[0011] Figure 3A is a schematic exploded isometric view of an example device package according to an embodiment of the present disclosure;

[0012] Figure 3B It is along Figure 3A A schematic cross-sectional view of the device package taken along line AA';

[0013] Figure 3C yes Figure 3B A schematic exploded bottom-up isometric view of the integrated cooling assembly illustrated in FIG;

[0014] Figure 4A is a schematic cross-sectional view of a device package that may be used with a system panel according to another embodiment;

[0015] Figure 4B yes Figure 4A An exploded bottom-up isometric view of the integrated cooling assembly shown in FIG;

[0016] Figure 5 is a schematic side cross-sectional view of an example of a multi-component device package including a cold plate directly bonded to backside surfaces of two or more devices;

[0017] Figure 6 is a schematic side cross-sectional view of an example multi-component device package according to an embodiment of the present disclosure;

[0018] Figure 7 is a schematic side cross-sectional view of a 3DIC device package according to an embodiment of the present disclosure;

[0019] Figure 8 is a schematic side cross-sectional view of a device package according to an embodiment of the present disclosure;

[0020] Figure 9 A method that can be used to manufacture the device packages described herein is shown; and

[0021] Figure 10 The device package is shown at various stages of fabrication to illustrate aspects of the method.

[0022] The drawings herein depict various embodiments of the present disclosure for purposes of illustration only. It should be understood that additional or alternative structures, components, systems, and methods can be implemented within the principles set forth herein. DETAILED DESCRIPTION

[0023] The embodiments herein provide an integrated cooling assembly embedded in a device package. The embedded cooling assembly shortens the thermal resistance path between the device and the heat sink and reduces thermal communication between devices disposed in the same package.

[0024] As used herein, the term "substrate" means and includes any workpiece, wafer, or article that provides a base material or supporting surface from which or upon which components, elements, devices, assemblies, modules, systems, or features of the heat-generating devices, packaging components, and cooling assembly components described herein may be formed. The term substrate also includes a "semiconductor substrate" that provides a supporting material on which components of a semiconductor device are fabricated or attached; and any material layers, features, and / or electronic devices formed thereon, in, or through it.

[0025] As described below, the semiconductor substrate herein generally has a "device side," e.g., a side on which semiconductor device components such as transistors, resistors, and capacitors are fabricated, and a "back side" opposite the device side. The term "active side" should be understood to include the surface of the device side of the substrate, and may include the device side surface of the semiconductor substrate and / or the surface of any material layer, device component, or feature formed thereon or extending outward therefrom and / or any opening formed therein. Thus, it should be understood that the material(s) forming the active side may change depending on the stage of device fabrication and assembly. Similarly, the term "non-active side" (opposite to the active side) includes the non-active side of the substrate at any stage of device fabrication, including the surface of any material layer, any feature formed thereon or extending outward therefrom, and / or any opening formed therein. Thus, the term "active side" or "non-active side" may include the corresponding surface of the semiconductor substrate at the beginning of device fabrication and any surface formed during material removal (e.g., after a substrate thinning operation). Depending on the stage of device fabrication or assembly, the terms "active" and "inactive side" are also used to describe the surface of a material layer or feature formed on, in, or through a semiconductor substrate, regardless of whether the material layer or feature ultimately exists in the device being fabricated or assembled.

[0026] Spatially relative terms are used herein to describe relationships between elements, such as relationships between substrates, heat-generating devices, cooling assembly components, device packaging components, and other features described below. Unless a relationship is defined otherwise, terms such as "above," "above...", "upper," "upward," "outward," "on...", "below," "under...", "under...", "lower," and similar terms are generally referred to as such with reference to the X, Y, and Z directions set forth in the accompanying drawings. Therefore, it should be understood that the spatially relative terms used herein are intended to cover different orientations of the substrate, and unless otherwise indicated, the terms are not limited by the direction of gravity. Unless a relationship is defined otherwise, terms such as "disposed on...", "embedded in...", "coupled to...", "connected by...", "attached to...", "engaged to...", alone or in combination with spatially relative terms that describe relationships between elements include both relationships with intervening components and direct relationships in the absence of intervening components.

[0027] Unless otherwise noted, the term "cold plate" generally refers to a base plate that can be bonded to a semiconductor device or a stack of base plates that are directly bonded to each other. The cold plate may include material layers and / or metal features formed on or in the surface of a base plate or base plate stack that facilitate direct dielectric bonding or hybrid bonding with the semiconductor device. The term "integrated cooling assembly" generally refers to a cold plate attached to a semiconductor device that is attached to form a single-piece structure, such as by using a direct bonding method described below. The direct bonding method enables heat from the semiconductor device to be transferred through the cold plate to a coolant fluid flowing over it without the use of a thermal interface material. Unless otherwise noted, the device packages and cold plates described herein can be used with any desired fluid coolant (e.g., liquid, gas, and / or vapor phase coolant). Therefore, the term should not be interpreted as limiting the coolant to any one fluid phase.

[0028] Typically, device packages for high heat flux devices are cooled by an external heat sink attached to a heat spreader forming a package lid. The devices in the device package are thermally coupled to the package lid using one or more thermal interface materials (e.g., a TIM layer disposed therebetween), wherein the TIM layer comprises a flexible material such as a thermal paste, grease, adhesive material, or other thermally conductive material such as a fusible metal alloy and the like, e.g., solder, or a combination thereof. Unfortunately, as heat flux density increases with shrinking device size, the cumulative thermal resistance of the components of such device packages becomes increasingly problematic because the heat cannot be dissipated quickly enough to allow the device to operate at optimal power, thereby reducing the energy efficiency of the device. Also problematic is the transfer of heat between devices within a single package, where heat can follow a thermal path from a device with high heat flux, such as a CPU or GPU, to one or more devices with low heat flux, such as memory.

[0029] Typically, the thermal resistance of the TIM layer accounts for 80% or more of the cumulative thermal resistance of the heat transfer path between the device and the external heat sink, which limits the level of cooling efficiency expected from next-generation device packages. Therefore, embodiments herein provide an integrated cooling assembly embedded within a device package that shortens the thermal resistance path between the device and the heat sink and reduces thermal connectivity between devices housed in the same package.

[0030] Figure 1 1 is a schematic plan view of an example of a system panel 100 according to an embodiment of the present disclosure. Here, the system panel 100 includes a printed circuit board (here, PCB 102), a plurality of device packages 301 mounted to the PCB 102, and a plurality of coolant lines 108 fluidically coupling each of the device packages 301 to a coolant source 110. It is contemplated that the coolant can be delivered to each of the device packages 301 in any desired fluid phase (e.g., liquid, vapor, gas, or a combination thereof) and can flow from the device packages 301 in the same phase or in different phases. In some embodiments, the coolant is delivered to the device packages 301 and returned from the device packages as a liquid, and the coolant source 110 can include a heat exchanger or chiller to maintain the coolant at a desired temperature. In other embodiments, the coolant can be delivered to the device packages 301 as a liquid, vaporize to a liquid within the device packages, and return to the coolant source 110 as a vapor. In some embodiments, the device package 301 may be fluidly coupled in parallel to the coolant source 110 , and the coolant source 110 may include or further include a compressor (not shown) for condensing the received vapor into liquid form.

[0031] Figure 2 yes Figure 1 FIG1 is a schematic partial cross-sectional side view of a portion of a system panel 100. As shown, each device package 301 is disposed in a receptacle 204 of a PCB 102 and connected to the receptacle 204 using a plurality of pins 202 or by other suitable connection methods, such as solder bumps (not shown). The device package 301 can be placed in the receptacle 204 and secured to the PCB 102 using a mounting frame 106 and a plurality of fasteners 112 (e.g., compression screws) configured to apply a relatively uniform downward force to the upward-facing edge of the device package 301. This uniform downward force ensures proper pin contact between the device package 301 and the receptacle 204.

[0032] Figure 3A is a schematic exploded isometric view of an example device package 301 according to an embodiment of the present disclosure. Figure 3B It is along Figure 3ASchematic cross-sectional view of the device package 301 taken along line A-A' of FIG. 1 . In general, the device package 301 includes a packaging substrate 302, an integrated cooling assembly 303 disposed on the packaging substrate 302, and a packaging cover 308 disposed on a peripheral portion of the packaging substrate 302 and extending above the integrated cooling assembly 303 so that the integrated cooling assembly 303 is disposed between the packaging substrate 302 and the packaging cover 308. As shown, the device package 301 also includes a sealing material layer 322 that forms a coolant-impermeable barrier between the packaging cover 308 and the integrated cooling assembly 303. The coolant is delivered to the integrated cooling assembly 303 via inlet / outlet openings 312 in the packaging cover 308 and corresponding openings 322A formed through the sealing material layer 322. In some embodiments, the device package 301 may also include a support member 307 attached to the integrated cooling assembly 303.

[0033] Generally speaking, package substrate 302 comprises a rigid material, such as an epoxy or resin-based laminate, that supports integrated cooling assembly 303 and package lid 308. Package substrate 302 may include conductive features disposed in or on the rigid material that electrically couple integrated cooling assembly 303 to a system panel, such as PCB 102.

[0034] Figure 3C yes Figure 3B , a schematic exploded bottom-up isometric view of an integrated cooling assembly 303 is shown in FIG. As shown, the integrated cooling assembly 303 can include a semiconductor device, here, device 304, and a cold plate 306 bonded to the device 304. Here, the device 304 includes an active side 318, which includes device components formed thereon or therein, such as transistors, resistors, and capacitors; and an inactive side, here, a device backside 320 opposite the active side 318. As shown, the active side 318 is positioned adjacent to and facing the package substrate 302. The active side 318 can be electrically connected to the package substrate 302 using conductive bumps 319, which are encapsulated by a first underfill layer 321 disposed between the device 304 and the package substrate 302. The first underfill layer 321 can include a cured polymer resin or epoxy resin that provides mechanical support for the conductive bumps 319 and prevents thermal fatigue.

[0035] like Figures 3B to 3CAs shown in FIG, cold plate 306 generally includes a patterned side that faces toward device 304 and defines an upper portion of coolant channels 310 when cold plate 306 is attached to device backside 320, and an opposing side that faces toward package lid 308. Here, the patterned side forms a device-facing cavity that includes a base surface 309 and sidewalls 311 surrounding base surface 309 and projecting downwardly therefrom. When attached to device 304 disposed thereunder, sidewalls 311 form the perimeter of coolant channels 310, and base surface 309 forms the uppermost surface of coolant channels 310. Device backside 320 forms the bottom of coolant channels 310 and is in direct thermal contact with the coolant flowing therethrough. Here, the coolant circulates through coolant channels 310 through openings disposed through cold plate 306, shown here as openings 306A disposed between downward-facing base surface 309 and an opposing, upward-facing surface. The opening 306A is in fluid communication with the inlet / outlet opening 312 of the package cover 308 through an opening 322A formed in the sealing material layer 322 and disposed between the opening 306A and the inlet / outlet opening 312 .

[0036] In some embodiments, the cold plate 306 includes a plurality of protruding features 324, such as fins, bars, or struts extending downward from the base surface 309. The protruding features 324 can be attached to the device 304 or extend proximate to the device to interrupt laminar fluid flow at the interface of the coolant and the device back side 320, thereby generating increased heat transfer therebetween. To further increase heat dissipation from the device 304, the protruding features 324 can include and / or be formed from a thermally conductive metal such as copper. The protruding features 324 can be arranged in a repeating pattern as shown or can be a random or non-repeating pattern. It is contemplated that each embodiment of the device package described herein can include a cold plate having a patterned side including the base surface 309, the sidewalls 311, and the plurality of protruding features 324, without requiring explicit recitation.

[0037] Here, the cold plate 306 is attached to the device back side 320 without the use of an intervening adhesive material. For example, the cold plate 306 can be directly bonded to the device back side 320 so that the cold plate 306 is in direct thermal contact with the device back side 320. In some embodiments, the cold plate 306 is attached to the device back side 320 using a direct dielectric bonding process. In other embodiments, the cold plate 306 is attached to the device back side 320 using a hybrid of direct dielectric bonding and direct metal bonding formed between the cold plate 306 and the device back side 320. For example, in some embodiments, one or both of the device back side 320 and the device-facing side of the cold plate 306 include dielectric material layers, such as first dielectric material layer 334A and second dielectric material layer 334B, respectively, and the cold plate 306 is directly bonded to the device back side 320 through bonds formed between the dielectric material layers 334A and 334B. In some embodiments, cold plate 306 is directly bonded to device backside 320 using a hybrid bonding technique, wherein a bond is formed between dielectric material layers 334A- 334B and between metal features disposed in dielectric material layers 334A- 334B, such as between first metal pad 336A and second metal pad 336B.

[0038] Suitable dielectrics that can be used as dielectric material layers 334A-334B include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, metal oxide, metal nitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, diamond-like carbon (DLC), or combinations thereof. In some embodiments, one or both of dielectric material layers 334A-334B are formed from an inorganic dielectric material, i.e., a dielectric material that is substantially free of organic polymers. Typically, one or both of dielectric layers 334A-334B are deposited to a thickness greater than the thickness of a native oxide, such as approximately 1 nm or greater, 5 nm or greater, 10 nm or greater, 50 nm or greater, 100 nm or greater, or 100 nm or greater. In some embodiments, one or both of layers 334A-334B are deposited to a thickness of 300 nm or less, such as 100 nm or less, 100 nm or less, or 50 nm or less.

[0039] In some embodiments, cold plate 306 is formed from a material having a coefficient of thermal expansion (CTE) substantially similar to that of the bulk semiconductor substrate of device 304. For example, in some embodiments, device 304 may be formed on a single crystal silicon substrate, and cold plate 306 may be formed from a single crystal silicon or polycrystalline silicon substrate. Forming cold plate 306 from a CTE-matched material (relative to the bulk substrate material of device 304) prevents undesirable separation of device 304 and cold plate 306 during repeated thermal cycling.

[0040] In some embodiments, the cold plate 306 can be formed of an amorphous silicon material, such as a bulk substrate material including a metal, a metal alloy, a ceramic, a composite material, or other low CTE material suitable for bonding using the methods described below. For example, the cold plate 306 can be formed of a bulk material selected from the group consisting of copper, aluminum, a copper alloy (e.g., a copper-molybdenum alloy and a copper-tungsten alloy), an iron-cobalt-nickel alloy (e.g., an iron-cobalt-nickel alloy from Magellan Industrial Trading Co., Inc. of South Norwalk Connecticut USA), or a copper-cobalt-nickel alloy (e.g., an iron-cobalt-nickel alloy from Magellan Industrial Trading Co., Inc. of South Norwalk Connecticut USA). ), iron-cobalt-nickel-silver alloys, iron-nickel alloys (such as those from Magellan Superalloys), iron-nickel-silicon alloys, aluminum silicon carbide, aluminum silicon alloys, beryllium, beryllium oxide, composites of beryllium and beryllium oxide, aluminum graphite fibers, copper graphite fibers, metal diamond composites (e.g., aluminum diamond composites and silver diamond composites), metal oxides, metal nitrides, and combinations thereof. Non-silicon substrate materials can be prepared for bonding as described below and may or may not include a layer of dielectric material deposited on the side facing the device to form the bonding surface. Methods for forming direct dielectric bonds and hybrid bonds are described below.

[0041] Beneficially, device package 301 provides reduced thermal resistance in heat transfer path 326 compared to a heat transfer path to an external heat sink. In some embodiments, the cumulative thermal resistance of heat transfer path 326 is reduced by a factor of 50 or more compared to the cumulative resistance of a device package cooled using an external heat sink.

[0042] The package lid 308 typically includes one or more vertical or angled sidewall portions 308A and a transverse portion 308B that spans and connects the sidewall portions 308A. The sidewall portion 308A extends upward from the peripheral surface of the package substrate 302 to surround the device 304 and the cold plate 306 disposed on the package substrate 302. The transverse portion 308B is disposed above the cold plate 306 and is typically spaced apart from the cold plate 306 by a gap corresponding to the thickness of the sealing material layer 322. Coolant circulates through the coolant channels 310 through inlet / outlet openings 312 formed through the transverse portion 308B. In each of the embodiments described herein, the coolant line 108 can be attached to the device package 301 using connector features formed in the package lid 308, such as threads formed in the sidewalls of the inlet / outlet openings 312 and / or protruding features 314 surrounding the openings 312 and extending upward from the surface of the transverse portion 308B.

[0043] Typically, the packaging cover 308 is formed of a semi-rigid or rigid material so that it can be mounted on the mounting frame 106 ( Figure 2) At least a portion of the downward force applied to package lid 308 is transferred to the supporting surface of package substrate 302, rather than to cold plate 306 and the underlying device 304. In some embodiments, package lid 308 is formed of a thermally conductive metal such as aluminum or copper. In some embodiments, package lid 308 acts as a heat spreader to redistribute heat from one or more electronic components within a multi-component device package, such as described below.

[0044] The sealing material layer 322 forms an impermeable barrier between the integrated cooling assembly 303 and the packaging lid 308, which prevents coolant from reaching the active side 318 of the device 304 and causing damage thereto. In some embodiments, the sealing material layer 322 comprises a polymer or epoxy material that extends upward from the packaging substrate 302 to encapsulate and / or surround at least a portion of the device 304. In other embodiments, the sealing material layer 322 may be disposed only between the upward-facing surface of the cold plate 306 and the portion of the packaging lid 308 disposed thereon. In some embodiments, the sealing material layer is formed of a molding compound (e.g., a thermosetting resin) that, when polymerized, forms an airtight seal between the packaging lid 308 and the cold plate 306. Here, the coolant is delivered to the cold plate 306 through openings 322A disposed through the sealing material layer 322. As shown, opening 322A is aligned with and in fluid communication with inlet / outlet opening 312 of package cover 308 above it and inlet / outlet opening 306A in cold plate 306 below it. Typically, coolant line 108 is attached to device package 301 using connector features formed in package cover 308, such as threads formed in the sidewalls of inlet / outlet opening 312 and / or protruding features 314 surrounding inlet / outlet opening 312 and extending upwardly from a surface of lateral portion 308B.

[0045] Beneficially, the sealing material layer 322 provides mechanical support that improves system reliability and extends the useful life of the device package 301. For example, the second sealing material layer 322 can reduce mechanical stresses that may weaken interface bonds and / or electrical connections between electrical components of the device package 301, such as stresses caused by vibration, mechanical and thermal shock, and / or fatigue caused by repeated thermal cycling. In some embodiments, the sealing material layer 322 can be a thermally conductive material, such as a polymer or epoxy with one or more thermally conductive additives (such as silver and / or graphite). In some embodiments, the device package 301 also includes a support member 307 attached to the upward-facing side of the cold plate 306. The support member 307 can be formed of a rigid material (e.g., a metal or ceramic plate) that provides mechanical support to the cold plate 306. The support member 307 can be attached to the cold plate 306 using a direct bonding method or by using an intervening adhesive layer (not shown).

[0046] Figure 4A FIG2 is a schematic cross-sectional view of a device package 401 according to another embodiment that can be used with the system panel 100. Here, the device package 401 includes a package substrate 302, a package lid 308, an integrated cooling assembly 403 disposed between the package substrate 302 and the package lid 308, and a sealing material layer 422 disposed between the integrated cooling assembly 403 and the package lid 308.

[0047] Figure 4B yes Figure 4A , an exploded bottom-up isometric view of an integrated cooling assembly 403 is shown in FIG. The cooling assembly 403 generally includes a device 304 and a cold plate 406 attached to the back side of the device 304, for example, by using the direct bonding method described above. The cold plate 406 generally includes a patterned side facing the device 304 and defining an upper portion of a coolant channel 410, and an opposing side facing the package lid 308. Here, the patterned side forms a device-facing cavity that includes a base surface 409 and opposing sidewalls 411 that protrude downwardly from the base surface 409. When attached to the device 304 disposed below the sidewalls 411, for example, by direct bonding of the side surfaces 413 to the device back side 320, the sidewalls 411 define the sides of the coolant channel 410, with the base surface 309 forming the uppermost surface of the coolant channel 410 and the device back side 320 forming the bottom surface of the coolant channel 410. Here, coolant circulates through coolant passages 410 through openings 406A provided on opposite ends of cooling assembly 403 .

[0048] As shown, openings 406A each comprise a gap between the cooling assembly 403 and the underlying device backside 320. The gap is formed at an end of the cold plate 406 that does not include a sidewall (as shown) or includes a sidewall that extends only partially toward the backside of the device 304 and does not engage therewith. Openings 406A are in fluid communication with the inlet / outlet openings 312 of the package lid 308 through openings 422A formed in the sealing material layer 422. As shown, the length of the cold plate 406 in the X-direction is less than the length of the device 304, and the openings 422A through the sealing material layer 422 extend from the package lid 308 to an end portion of the underlying device backside. In other embodiments, the sidewalls 411 can have substantially the same length as the device 304, as shown in dashed lines, and the base surface 409 can have a length less than the length of the device 304. In either embodiment, the device back side 320 is in direct thermal contact with the coolant circulating through the coolant channels 410 and with the coolant entering and exiting the coolant channels 410 on either side of the opening 406A. Figures 4A to 4B The cooling assembly 403 and sealing material layer 422 illustrated in FIG. 4 may be used with any of the device packages described herein.

[0049] Figure 5 FIG2 is a schematic side cross-sectional view of an example of a multi-component device package 501 including a cold plate 506 directly bonded to the backside surfaces of two or more devices. As shown, device package 501 includes a package substrate 502 (e.g., an interposer that facilitates communication between device 304 and device stack 504), an integrated cooling assembly 503, a package lid 308, and a layer of encapsulation material 522. Integrated cooling assembly 503 may include: a plurality of devices 304 (one shown), which may be singulated and / or arranged in a vertical device stack 504 (one shown); and a cold plate 306 attached to each of the devices 304 and device stack 504, for example, by direct bonding methods as described herein. In some embodiments, device 304 may include a processor and device stack 504 may include multiple memory devices. Here, devices 304 and device stack 504 are arranged in a side-by-side arrangement on package substrate 302 and are in electrical communication with each other via conductive elements formed in, on, or through package substrate 502. Here, the cold plate 506 is sized to provide an engagement surface for attachment to both the device 304 and the device stack 504, but can be otherwise the same or substantially similar to other cold plates described herein. For example, here the cold plate 506 includes a patterned side that includes a base surface 509 and sidewalls 511 extending downwardly from the base surface 509 to define a cavity. The cavity can be closed, for example, as shown surrounded by the sidewalls 511, or can be as shown. Figures 4A to 4B 504 . The bottom surface 509 defines the uppermost surface of the coolant channel 510, and the sidewalls 511 can define the perimeter or side boundaries of the coolant channel 510. Here, the device 304 and the device stack 504 define respective portions of the bottom of the coolant channel 510, and a second underfill layer 521 or other molding material disposed in the gap region between the device 304 and the device stack 504 provides an intervening bottom portion of the coolant channel disposed between the device 304 and the device stack 504.

[0050] A sealing material layer 522 disposed between the cold plate 506 and the package lid 308 attaches the cold plate 506 to the package lid 308 and forms a coolant-impermeable barrier therebetween. Coolant circulates to the device package 501 through the inlet / outlet openings 312 of the package lid 308 and flows through the coolant channels 510 via the openings 506A in the cooling assembly 503 and corresponding openings 522A formed through the sealing material layer 522. Here, the sealing material layer 522 may be formed of a polymer or epoxy molding material such as described above, or a compliant adhesive layer such as a TIM layer.

[0051] Figure 6 6 is a schematic side cross-sectional view of an example multi-component device package according to an embodiment of the present disclosure. Here, device package 601 includes a package substrate 502, an integrated cooling assembly 303, one or more second devices (here shown as a device stack 604), and a package lid 608. Device package 601 also includes a sealing material layer 622 disposed between the integrated cooling assembly 303 and a portion of the package lid 608 disposed thereon. Sealing material layer 622 forms a coolant-impermeable barrier between the cold plate 306 and the package lid 608. Here, device stack 604 is disposed on package substrate 502 in a side-by-side configuration with device 304. Heat generated by device 304 is dissipated to coolant circulating through coolant channels 310. Here, the coolant circulates through inlet / outlet openings 312 in package lid 608, openings 622A disposed through sealing material layer 622 aligned with and in fluid communication with inlet / outlet openings 312, and openings 306A in cold plate 306 in fluid communication with openings 622A.

[0052] The package lid 608 can be formed of a thermally conductive material and act as a heat spreader. Advantageously, the cold plate 306 blocks the thermal path between the device 304 and the device stack 604 to prevent heat from being transferred therebetween. Thus, heat generated by the device stack 604 can be dissipated to the coolant via the package lid 608, which is thermally coupled to the device stack 604 using the TIM layer 616. Thus, the device package 601 can be advantageously used to facilitate closely spaced devices (such as high-power devices and memory stacks) on an interposer to achieve reduced latency while eliminating undesirable heat transfer therebetween. In some embodiments, the device package 601 further includes a heat sink 608A disposed on a portion of the package lid 608 above the device stack 604. The heat sink 608A can be thermally coupled to the package lid 608 using a TIM layer (not shown) or by direct bonding using the methods described herein.

[0053] Figure 7is a schematic side cross-sectional view of a 3DIC device package 701 according to an embodiment of the present disclosure. Generally speaking, the device package 701 includes: an integrated cooling assembly 703, which is disposed on and electrically connected to the package substrate 302; a package cover 708, which is disposed above the integrated cooling assembly 703; and a sealing material layer 722, which is disposed between the cooling assembly 703 and the package cover 708. Here, the integrated cooling assembly 703 includes a 3DIC device 704, which includes a first device 704A, one or more second devices 704B (one is shown), and one or more cold plates 706 (two are shown). Here, the first device 704A is disposed facing the package substrate 302, that is, with the active side facing down, and the second device 704B is disposed on a portion of the back side of the first device 704A and bonded to the portion. The package substrate 302 and the second device 704B and / or the first device 704A and the second device 704B can be interconnected using a plurality of through-substrate vias (TSVs 718) disposed through the first device 704A and hybrid bonding formed between the active side of the second device 704B and the backside of the first device 704A. In some embodiments, one or more second devices 704B include a device stack, such as the device stack 604, that is directly bonded to and interconnected with the first device 704A using direct hybrid bonding.

[0054] Here, a first device 704A is cooled using one or more cold plates 706, which are positioned on and bonded to the backside of the first device 704A in a side-by-side arrangement with a second device 704B. Each of the one or more cold plates 706 is attached to the package cover 708 using a sealing material layer 722, wherein the sealing material layer 722 forms a coolant-impermeable barrier between the cold plate 706 and the package cover 708.

[0055] Here, each of the cold plates 706 includes a base surface 709 and sidewalls 711 extending downwardly from the base surface 709, wherein the sidewalls 711 are attached to the first device 704A, for example, by using a direct bonding method, to form coolant channels 710 between the cold plate 706 and the portion of the first device 704A disposed thereunder. Heat generated by the corresponding portion of the first device 704A is dissipated from the device package 701 via coolant flowing through the coolant channels 710. Here, the coolant is delivered to each of the coolant channels 710 through a flow path that includes the inlet / outlet openings 312 in the package cover 708, the openings 722A in the sealing material layer 722, and the openings 706A in the cold plate 706.

[0056] Here, the second device 704B is thermally coupled to the package lid 708 using a TIM layer 716, and the sealing material layer 722 and the package lid 708 each include a thermally conductive material. Thus, heat generated by the second device 704B is transferred to the coolant in the coolant channel 710 via a heat transfer path that includes the TIM layer 716, the package lid 708, the sealing material layer 722, and the cold plate 706. In some embodiments, the heat from the second device 704B is dissipated using a heat sink attached to a portion of the package lid 708 disposed above the second device 704B, such as the heat sink 608A described above.

[0057] In each of the embodiments described above, the sealing material layer and the openings disposed therethrough facilitate delivery of coolant to the integrated device assembly without requiring coolant lines to be attached directly thereto. Attaching the coolant lines to the package lid reduces manufacturing complexity and cost because the package lid is typically formed of a less brittle material than the material used to form the cold plate and is therefore less susceptible to breakage.

[0058] Figure 8 is a schematic side cross-sectional view of a device package 801 according to an embodiment of the present disclosure. Here, the device package 801 includes a package substrate 302, a cooling assembly 303 disposed on the package substrate 302, and a material layer 822 disposed above the cooling assembly 303 and at least partially encapsulating the cooling assembly. The material layer 822 forms a coolant-impermeable seal with the cooling assembly 303 and may include a polymer or epoxy formed from a resin or molding compound. The coolant is delivered to the cooling assembly 303 and circulates therethrough via openings 822A disposed through the material layer 822. Here, the material layer 822 includes one or more features 814, such as threads or protrusions extending upward to surround each of the openings 822A, wherein the features 814 enable the coolant line 108 (shown in phantom) to be directly connected to the material layer 822. In some embodiments, the device package 801 also includes a package cover (not shown), and the coolant line is connected to the material layer 822 through an opening disposed in the package cover.

[0059] Figure 9 A method 900 is shown that may be used to manufacture the device packages described herein. Figure 10 The device package 301 is shown at various stages of manufacture to illustrate aspects of the method 900. It is contemplated that the method 900 may be used to manufacture any of the device packages described herein. To reduce visual clutter, Figure 10 Some features of the device package 301 illustrated in FIG. 3 are denoted by reference numerals that are common to FIG. 3 .

[0060] At block 902, the method 900 includes aligning a first substrate 1004 with a second substrate 1006, wherein the first substrate 1004 includes a plurality of dies to be singulated, such as devices 304, and the second substrate 1006 includes a plurality of cold plates to be singulated 306. As shown, the first substrate 1004 includes the plurality of devices 304 arranged in a rectangular array and separated from each other by a plurality of cut lines 1008 extending in the X and Y directions to form a grid pattern.

[0061] The first substrate 1004 may include a bulk material and multiple material layers disposed on the bulk material. The bulk material may include any semiconductor material suitable for fabricating semiconductor devices, such as silicon, silicon germanium, germanium, Group III-V semiconductor materials, Group II-VI semiconductor materials, or combinations thereof. For example, in some embodiments, the first substrate 1004 may include: a single crystal wafer, such as a silicon wafer; multiple device components formed in or on the silicon wafer; and multiple interconnect layers formed above the multiple device components. In other embodiments, the substrate may include a reconstituted substrate, such as a substrate formed from multiple singulated devices embedded in a support material.

[0062] The bulk material of the first substrate 1004 may be thinned after forming the device 304 using one or more back grinding, etching, and polishing operations to remove material from the back side. Thinning the first substrate 1004 may include using a combination of grinding and etching processes to reduce the thickness (in the Z direction) to about 450 μm or less, such as about 301 μm or less, or about 150 μm or less. After thinning, the back side may be polished to a desired smoothness using a chemical mechanical polishing (CMP) process, and a dielectric material layer may be deposited thereon. In some embodiments, the dielectric material layer may be polished to a desired smoothness to prepare the first substrate 1004 for a bonding process. In some embodiments, the method 900 includes forming a plurality of metal features in the dielectric material layer in preparation for a hybrid bonding process, such as by using a metal damascene process.

[0063] In some embodiments, the active side is temporarily bonded to a carrier substrate (not shown) before or after the thinning process. When used, the carrier substrate provides support for the thinning operation and / or the thinned material to facilitate substrate handling during one or more of the subsequent manufacturing operations described herein. In some embodiments, the second substrate 1006 is formed from a plurality of substrates (not shown), each of which comprises a unitary bulk material patterned to define a plurality of base plates that, when bonded to one another, collectively form a plurality of cold plates 306. Each of the plurality of substrates can have substantially the same size and shape as the first substrate 1004 when viewed from above (in the Z direction), such that the interfacing surfaces are substantially coextensive with one another. In some embodiments, the thickness (in the Z direction) of each of the substrates is between about 0.5 mm and about 10 mm, or between about 1 mm and about 8 mm, or between about 1 mm and 6 mm, such as about 0.5 mm or greater, such as about 1 mm or greater, or about 2 mm or greater, or about 10 mm or less, such as about 8 mm or less, or about 6 mm or less.

[0064] In some embodiments, the second substrate 1006 is formed from a bulk material having a substantially similar CTE to the bulk material of the first substrate 1004, where the CTE is a fractional change in the length of the material (in the XY plane) as a function of the degree of temperature change. In some embodiments, the CTEs of the first and second substrates are matched such that, when measured across a desired temperature range, the CTE of the second substrate 1006 is within approximately + / - 20% or less of the CTE of the first substrate 1004, such as within + / - 15% or less, within + / - 10% or less, or within approximately + / - 5% or less. In some embodiments, the CTEs are matched across a temperature range of approximately -60°C to approximately 100°C or approximately 60°C to approximately 175°C. In one exemplary embodiment, the matched CTE materials each comprise silicon. For example, the bulk material of the first substrate 1004 can comprise single crystal silicon, and the bulk material of the second substrate 1006 can comprise single crystal silicon or polycrystalline silicon. In some embodiments, method 900 includes forming a dielectric material layer and optionally a plurality of metal features on a lower surface of a second substrate 1006. In some embodiments, the method includes patterning the second substrate 1006, for example by using photolithography and etching processes, to form the corresponding surfaces, sidewalls, and protruding features of the cold plate described herein.

[0065] At block 904, method 900 includes directly bonding a plurality of cold plates 306 formed in the second substrate 1006 to the plurality of devices 304 in the first substrate 1004. As described above, the bonding surfaces can each include a dielectric material layer, and directly bonding the first substrate 1004 and the second substrate 1006 includes forming a dielectric bond between the first dielectric material layer 334A and the second dielectric material layer 334B. Alternatively, the first substrate 1004 and the second substrate 1006 can be directly bonded using a hybrid of dielectric bonds and metallic bonds formed between metallic features.

[0066] In general, directly bonding the surfaces (of the dielectric material layer) includes preparing, aligning, and contacting the surfaces. Preparing the surfaces can include smoothing the respective surfaces to achieve a desired surface roughness, such as between 0.1 nm RMS and 3.0 nm RMS; activating the surfaces to weaken or open chemical bonds in the dielectric material; and terminating the surfaces with desired species. Smoothing the surfaces can include polishing the substrates 1004, 1006 using a CMP process. Activating the surfaces and terminating the surfaces with desired species can include exposing the surfaces to free radical species formed in a plasma.

[0067] In some embodiments, a nitrogen-containing gas (e.g., N2) is used to form the plasma, and the terminating species include nitrogen and hydrogen. In some embodiments, a wet cleaning process may be used, such as by exposing the surface to an aqueous ammonia solution to activate the surface. In some embodiments, a dielectric bond may be formed using a dielectric material layer deposited on only one of substrates 1004, 1006, but not both. In those embodiments, a direct dielectric bond may be formed by directly contacting a deposited dielectric material layer of one substrate with a bulk material surface of another substrate (e.g., a bulk semiconductor or polysilicon material surface). In such embodiments, the bulk material surface may include a thin native oxide layer or may be cleaned prior to contact so that it is substantially free of native oxide.

[0068] At block 904, directly forming a direct dielectric bond between the substrates includes directly contacting the prepared and aligned surfaces at a temperature below 150° C., such as below 100° C., for example below 30° C., or at about room temperature (e.g., between 20° C. and 30° C.). Without being bound by theory, it is believed that hydrogen-terminated species diffuse from the interface bonding surfaces and chemical bonds are formed between the remaining nitrogen species during the direct bonding process. In some embodiments, the direct bond is strengthened using an annealing process in which the substrates are heated to a temperature above about 30° C. and below about 450° C. (e.g., above about 50° C. and below about 250° C., or about 150° C.) for a duration of about 5 minutes or more (e.g., about 15 minutes). Typically, the bond strengthens over time even without applying heat. Therefore, in some embodiments, method 900 does not include heating the substrates.

[0069] In embodiments where hybrid dielectric and metal bonding is used to bond the substrates, the method may further include planarizing or recessing the metal features below the field surface prior to contacting and bonding the dielectric material layer. After forming the dielectric bond, the substrates 1004, 1006 may be heated to a temperature of 150°C or greater and maintained at the elevated temperature for a duration of about 1 hour or longer, such as between 8 hours and 24 hours, to form a direct metallurgical bond between the metal features. Suitable direct dielectric bonding and hybrid bonding techniques that may be used to perform aspects of the methods described herein include: and Each can be purchased from Adeia Holding Corp., San Jose, CA, USA.

[0070] At block 906, method 900 includes singulating the integrated cooling assembly 303 from the bonded substrates. Because the bonding surface of each cold plate 306 has the same perimeter as the backside of the device 304 bonded thereto, singulation after bonding imparts unique structural properties to the integrated cooling assembly 303. Consequently, the sidewalls of the cold plates 306 are typically flush with the edges of the devices 304 around their common perimeter. In some embodiments, the cold plates 306 are singulated from the second substrate 1006 using a process that cuts or divides the second substrate 1006 in a vertical plane (i.e., parallel to the Z direction). In those embodiments, the sides of the cold plates 306 are substantially perpendicular to the backside of the devices, i.e., the horizontal (XY) plane of the attachment interface between the devices 304 and the cold plates 306. In some embodiments, the cold plates 306 are singulated using a sawing or laser cutting process.

[0071] At block 908, method 900 includes attaching the integrated cooling assembly to package substrate 302 and sealing package lid 308 to integrated cooling assembly 303 using a mold compound that, when cured, forms sealing material layer 322. In some embodiments, method 900 also includes forming opening 322A in sealing material layer 322.

[0072] The method described above advantageously implements an embedded cold plate that eliminates and / or substantially reduces the thermal resistance path typically associated with cooling systems attached to the outside of the device package. The cold plate can be attached to the semiconductor device using direct dielectric or hybrid dielectric and metal bonding methods. When compared to conventional silicon-to-silicon bonding methods (such as thermocompression bonding methods), such bonding methods allow for a relatively low thermal budget while providing substantially increased bond strength.

[0073] The cold plate and semiconductor device can be formed from CTE-matched materials, eliminating the need for an intervening TIM layer. In some embodiments, the integrated cooling assembly and package lid can be formed from CTE-mismatched materials and attached to each other using a flexible material to form a sealing material layer, or by using a decoupling adhesive layer disposed between the sealing material layer and either the cold plate or package lid. The flexible material can absorb differences in linear expansion between the package lid and the cold plate during repeated thermal cycling, extending the life of the device package.

[0074] The embodiments discussed above are intended to be illustrative and not restrictive. Those skilled in the art will appreciate that individual aspects of the cooling assembly, device package, and method discussed herein may be omitted, modified, combined, and / or reconfigured without departing from the scope of the present disclosure. Only the following claims are intended to set the boundaries of what is encompassed by the present invention.

Claims

1. A device package comprising: Package substrate; an encapsulation cover disposed on the encapsulation substrate, the encapsulation cover having an inlet opening and an outlet opening disposed therethrough; an integrated cooling assembly disposed between the package substrate and the package lid, the integrated cooling assembly comprising a semiconductor device and a cold plate attached to the semiconductor device; as well as A material layer is disposed between the package cover and the cold plate, wherein: The cold plate includes a patterned first side and an opposing second side; The patterned first side includes a base surface and sidewalls extending downwardly from the base surface; The substrate surface is spaced apart from the semiconductor device to collectively define a coolant channel therebetween; and The coolant passage is in fluid communication with the inlet opening and the outlet opening through openings provided through respective portions of the material layer. 2 . The device package of claim 1 , the cold plate being attached to the semiconductor device by direct dielectric bonding. 3 . The device package of claim 1 , wherein the cold plate is attached to the semiconductor device by direct hybrid bonding. 4 . The device package of claim 1 , further comprising a coolant fluid disposed in the coolant channel.

5. The device package of claim 1, wherein the opening in the integrated cooling assembly comprises a portion of a fluid path, the fluid path further comprising the inlet opening and the outlet opening, the opening disposed through the material layer, and the coolant channel. 6 . The device package of claim 5 , wherein the opening in the integrated cooling assembly extends between the first side and the second side of the cold plate. 7 . The device package of claim 5 , wherein the opening in the integrated cooling assembly comprises a gap between the first side of the cold plate and the semiconductor device.

8. The device package of claim 5, wherein the first side of the cold plate further comprises a plurality of protruding features extending downwardly from the base surface to interrupt at least a portion of the fluid flow path through the coolant channel. 9 . The device package of claim 8 , wherein the protruding feature is directly bonded to the semiconductor device.

10. The device package of claim 7, wherein the gaps are provided at opposite ends of the substrate surface.

11. The device package of claim 1 , wherein the package cover includes one or more coolant line attachment features. 12 . The device package of claim 1 , further comprising an underfill layer at least partially enclosing the integrated cooling assembly in an area outside of the coolant channel.

13. The device package of claim 1, wherein the material layer forms an impermeable barrier between the package lid and the cold plate. 14 . The device package of claim 1 , wherein side surfaces of the cold plate and the semiconductor device are substantially flush with each other.

15. The device package according to any one of claims 1 to 13, wherein: The semiconductor device is a first semiconductor device, and the integrated cooling assembly further comprises a plurality of second semiconductor devices arranged vertically as a device stack; and The device stack is attached to the first side of the cold plate in a side-by-side arrangement with the first semiconductor device. 16 . The device package of claim 15 , wherein the cold plate is attached to the second semiconductor device by direct dielectric bonding.

17. The device package of claim 15, wherein the cold plate is attached to the second semiconductor device by direct hybrid bonding.

18. The device package according to any one of claims 1 to 13, wherein the semiconductor device is a first semiconductor device, and the device package further comprises: a device stack electrically connected to the packaging substrate in a side-by-side arrangement with the integrated cooling assembly; as well as A first TIM layer is disposed between the device stack and the package lid.

19. The device package of claim 18, wherein the package lid comprises a thermally conductive metal that forms a portion of a heat transfer path between the device stack and the coolant channel.

20. The device package of claim 18, further comprising a heat sink thermally coupled to an exterior surface of the package lid, wherein the package lid comprises a thermally conductive metal that forms a portion of a heat transfer path between the device stack and the heat sink.

21. The device package according to any one of claims 1 to 13, wherein: The semiconductor device includes a first device and a second device directly bonded to the first device; The integrated cooling assembly includes one or more cold plates attached to the first device; and Each of the one or more cold plates is sealed to the encapsulation cover by an adhesive layer to define a perimeter of the coolant channels respectively disposed therebetween.

22. The device package of claim 21, wherein the second device is thermally coupled to the package lid by a TIM layer disposed between the second device and the package lid.

23. A method of manufacturing a device package according to any one of claims 21 to 22, the method comprising: directly bonding a first substrate comprising a semiconductor device to a second substrate comprising a cold plate; singulating an integrated cooling assembly comprising the semiconductor device and the cold plate from the bonded first and second substrates, the cold plate comprising a first side directly bonded to the semiconductor device and a second side opposite the first side, wherein one or more surfaces of the first side are spaced apart from the semiconductor device to define a coolant channel therebetween; sealingly attaching the encapsulating cover to the second side using a layer of material disposed between the encapsulating cover and the second side, the encapsulating cover including an inlet opening and an outlet opening; as well as Before or after attaching the packaging cover to the second side, openings are formed in the material layer to fluidly connect the inlet opening and the outlet opening to the coolant channel.

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