Chip package with core embedded chiplet

Abstract

Chip packages are described herein that include chiplets embedded in a substrate of the chip package, such as a package substrate or a core of an interposer. In one example, the chiplet includes a voltage regulation circuit coupled through a substrate core embedded inductor to an integrated circuit (IC) die mounted to the substrate.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to chip packages having chiplets embedded in a core of a substrate, and particularly to chip packages having voltage regulator chiplets embedded in a core of a substrate of the chip package, such as a package substrate or an interposer. Background Art

[0002] Electronic devices such as tablet computers, computers, copiers, digital cameras, smart phones, control systems, ATMs, data centers, artificial intelligence systems, and machine learning systems typically use electronic components that utilize chip package assemblies to increase functionality and improve component density. Conventional chip packaging solutions typically utilize a package substrate (typically combined with a through-silicon via (TSV) interposer substrate) to enable multiple integrated circuit (IC) dies to be mounted to a single package substrate. The IC die is mounted to the top side (i.e., top surface) of the package substrate, while the bottom side (i.e., bottom surface) of the package substrate is mounted to a printed circuit board (PCB). The IC die may include memory, logic components, or other IC devices.

[0003] Chip packages, particularly those used in AI / ML and server applications, tend to include integrated voltage regulator systems. Power delivery via voltage regulators within chip packages typically requires multiple voltage regulators to support each power rail, significantly increasing cost and requiring a significantly higher number of package pins to deliver power at an input voltage of approximately 1V.

[0004] To improve voltage regulator performance, some chip packages incorporate the voltage regulator (power field-effect transistor (FET)) as part of the system-on-chip (SoC) and place the inductor in the core area of the package substrate. This solution is less efficient due to the IR drop connection between the SoC and the embedded inductor, as well as the return path from the inductor to the SoC. Undesirably, this solution also requires custom SoC development for each product, as the power FET is part of the SoC design.

[0005] Other chip packages place the inductor or voltage regulator chiplet on the backside of the package or on the backside of a printed circuit board (PCB). Such solutions increase the package footprint and undesirably reduce the number of available package pins. Placing the inductor or voltage regulator chiplet on the backside of the package or PCB also presents thermal challenges, requiring a custom backside cooling solution.

[0006] Therefore, there is a need for a chip package with an improved voltage regulator power delivery design. Summary of the Invention

[0007] A chip package is described herein that includes a chiplet embedded in a core of a substrate of the chip package, such as a package substrate or an interposer. In one example, the chiplet includes a voltage regulation circuit coupled to an integrated circuit (IC) die mounted to the substrate through a substrate core-embedded inductor.

[0008] In one example, a chip package is provided that includes an integrated circuit (IC) die having functional circuitry, a substrate, and a chiplet. The IC die is mounted on the substrate. The substrate includes a core sandwiched between an upper buildup layer and a lower buildup layer. The core includes at least a first cavity, a plurality of signal transmission vias, a plurality of grounds, and a plurality of ground and power wiring vias. The upper buildup layer is disposed on the core between the core and the IC die. The upper buildup layer includes wiring that couples the inductor wiring vias, the signal transmission vias, and the ground and power wiring vias to the functional circuitry of the IC die. The lower buildup layer is disposed on a side of the core opposite to the upper buildup layer. The lower buildup layer includes wiring that couples to the functional circuitry of the IC die through the vias of the core and the wiring of the upper buildup layer. The chiplet is disposed in a first cavity formed in the core. The chiplet is coupled to the functional circuitry of the IC die through the upper buildup layer.

[0009] In some examples, the chiplet includes a voltage regulator circuit.

[0010] In some examples, the voltage regulator circuit of the chiplet is coupled to an inductor disposed in the substrate.

[0011] The inductor may be made of a magnetic material surrounding a conductor.

[0012] The chiplet may include a backside metal layer.

[0013] The backside metal layer can be connected to a thermal via that conducts heat from the chiplet to the IC die or to one of the stiffeners of a lid covering the IC die.

[0014] The chiplet and inductor may reside in the same or different cavities formed in the core of the substrate.

[0015] In another example, a chip package is provided that includes an integrated circuit (IC) die having functional circuitry, a substrate, and a chiplet. The IC die is mounted on the substrate. The substrate includes a core, an upper buildup layer, and a lower buildup layer. The core has one or more cavities, a plurality of signal transmission vias, a plurality of grounds, and a plurality of ground and power wiring vias. The upper buildup layer is disposed on the core between the core and the IC die. The upper buildup layer includes wiring for coupling the inductor wiring vias, the signal transmission vias, and the ground and power wiring vias to the functional circuitry of the IC die. The lower buildup layer is disposed on a side of the core opposite the upper buildup layer. The lower buildup layer includes wiring for coupling to the functional circuitry of the IC die through the vias of the core and the wiring of the upper buildup layer. The chiplet is disposed in the one or more cavities formed in the core. The chiplet has a voltage regulation circuit coupled to the functional circuitry of the IC die through the upper buildup layer. An inductor is also disposed in one or more cavities formed in the core. The inductor has an input and an output. The input of the inductor is coupled to an outlet of the voltage regulator circuit, and the output of the inductor is coupled to the functional circuit of the IC die.

[0016] In yet another example, a method for manufacturing a chip package is provided. The method includes: securing a chiplet and an inductor in a cavity formed in a substrate; forming a buildup layer on the substrate over the chiplet and the inductor, the buildup layer including wiring electrically coupled to the chiplet and the inductor; and mounting an integrated circuit (IC) die on the buildup layer, the IC die including functional circuitry coupled to the chiplet and the inductor via the wiring of the buildup layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order that the manner in which the above-described features of the present invention may be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the invention and are therefore not to be considered limiting of the scope of the invention, as the invention may admit to other equally effective embodiments.

[0018] Figure 1 is a schematic cross-sectional view of one example of a chip package having a chiplet disposed in a core of a substrate.

[0019] Figure 2 is a schematic cross-sectional view of another example of a chip package having a chiplet disposed in a core of a substrate.

[0020] Figures 3A to 3I Describes the available Figure 1 A substrate used in a chip package.

[0021] Figure 4 is a block diagram of a method for manufacturing a chip package.

[0022] Figures 5A to 5F Describes the available Figures 1 to 2 Magnetic inductors used in chip packages.

[0023] Figure 6 is a block diagram of a method for manufacturing an inductor.

[0024] 7A to 7D Describes the available Figures 1 to 2 A substrate having a magnetic inductor used in a chip package.

[0025] Figure 8 is a block diagram of a method for fabricating a substrate having a magnetic inductor.

[0026] 9A to 9D Describes the available Figures 1 to 2 Another substrate having a magnetic inductor is used in the chip package.

[0027] Figure 10 is a block diagram of a method for fabricating a substrate having a magnetic inductor.

[0028] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one embodiment may be beneficially incorporated in other embodiments. DETAILED DESCRIPTION

[0029] A chip package and method for manufacturing the same are provided, the chip package including a chiplet embedded in a core of a substrate of the chip package, such as a package substrate or an interposer. The embedded chiplet may include a voltage regulator circuit that is routed through a companion inductor before being connected to the IC die of the chip package. The voltage regulator circuit includes a power routing field effect transistor (FET). The companion inductor may also be embedded in the core of the substrate. The companion inductor may be an air core inductor, a magnetic inductor, or other suitable inductor.

[0030] The integrated voltage regulator solution described herein has a variety of different components, most or all of which are embedded in the substrate core of the package. The embedded components include at least an inductor and a voltage regulator (VR) chiplet. The capacitors of the integrated voltage regulator solution may also be embedded in the substrate core of the package, or alternatively may be surface mounted near the chip package or the PCB to which the chip package is mounted. The components are spread out in the substrate core to optimize power delivery to the chip attached to the substrate. By having multiple VR chiplets and inductors, heat dissipation is managed to avoid hot spots. A novel multi-layer core architecture is used to optimize the embedding process and incorporate the silicon chiplets into a thick core package. The thickness of the multi-layer core is adjusted to improve the manufacturability of the embedding process while still meeting the overall package thermo-mechanical warpage requirements. The use of the multi-layer core architecture provides short lateral connections between the inductor and the VR chiplet. In one example, a magnetic material is used to fabricate the inductor to improve the efficiency of the voltage regulator and maximize current density.

[0031] In some embodiments, the magnetic material is embedded in the substrate core after the inductor is manufactured, which avoids leaching of the magnetic material. For example, the inductor can be manufactured using a pre-cured magnetic block (through which the wiring is formed), and then the inductor can be installed as a finished inductor into a cavity formed in the substrate.

[0032] In some embodiments, a novel backside thermal via solution is provided to improve heat conduction from an embedded VR chiplet. For example, a backside metal layer is deposited in the VR chiplet, and after the VR chiplet is embedded in the core of the substrate, thermal vias are formed in the backside metal layer through the upper buildup layer of the substrate to allow heat generated by the VR chiplet to reach the upper surface of the substrate. From the upper surface of the substrate, heat can be dissipated through the IC die and / or through stiffeners to the lid of the package substrate. To improve thermal conduction, stiffeners can be integrated into the lid.

[0033] In some embodiments, the VR chiplet and the inductor are disposed side-by-side in the same cavity of the substrate core. The resulting close proximity of the VR chiplet and the inductor beneficially provides a very short lateral path between the VR chiplet and the inductor, which improves performance.

[0034] Multi-layer core and embedding technology enables silicon components to be embedded in thick-core packages, which provides high inductance while meeting package thermo-mechanical warpage requirements.

[0035] Some additional benefits include one or more of the following: allowing high power (750W to 1000W) delivery while maintaining package footprint; reducing the number of onboard voltage regulators, which reduces the overall cost of the graphics card; improving overall power delivery efficiency and product performance by moving the power delivery components closer to the IC die within the chip package; enabling modular chiplet designs where the number and location of VR chiplets can be optimized for each product without the need for a new SoC tapeout; enabling the embedding of silicon components such as VR chiplets, inductors, silicon capacitors by using a multi-layer core architecture where the internal core thickness is adjusted to match the thickness of the embedded components; enabling effective heat dissipation by incorporating thermal vias on the back side of the VR chiplet; achieving improved performance by using short lateral connections between the inductor and VR chiplet by using a multi-layer core architecture; improving the efficiency of the power delivery solution by using embedded magnetic material inductors in the core of the substrate; and increasing current density by using high inductance magnetic inductors.

[0036] In some examples, improved efficiency of the voltage regulator is achieved by optimally placing the VR chiplet and inductor directly below the IC die within the chip package. The package size growth from other solutions (such as on-board VR or back-side VR) is essentially prevented. The modular solution described herein allows the use of the same VR chiplet on multiple products, thereby avoiding the need for custom SOC tapeouts. Additionally, the use of pre-fabricated magnetic boards improves inductance and efficiency and also mitigates the risk of contamination of the substrate production line due to leaching of uncured magnetic material.

[0037] Now go to Figure 1 , a chip package 100 is illustrated having at least one IC die 102 mounted on a substrate 104 . Figure 1 The substrate 104 illustrated in FIG is a package substrate 104. However, the substrate 104 may alternatively be an interposer that is then mounted to a package substrate. Figure 1 Only one IC die 102 is shown in FIG, but the number of IC dies 102 can range from one to as many as can be assembled in the chip package 100. The IC die 102 can be a programmable logic device such as a field programmable gate array (FPGA), a memory device, an optical device, a logic device, a processor, a math engine, or other IC logic structures. Optical devices include light detectors, lasers, light sources, etc. Figure 1 In the depicted embodiment, after the chip package 100 is installed in an electronic device (not shown), the IC die 102 is mounted to the top surface 140 of the substrate 104 via solder connections that enable communication between the IC die 102 and a printed circuit board (PCB) 106.

[0038] The chip package 100 further includes a stiffener 108 and a lid 110. The lid 110 is disposed above the top surface 130 of the IC die 102. The stiffener 108 is coupled to the substrate 104 and surrounds the IC die 102. The stiffener 108 may extend to the peripheral edge 142 of the substrate 104 to provide mechanical support, which helps prevent the chip package 100 from bending and warping. The stiffener 108 may be a single-layer structure or a multi-layer structure. The stiffener 108 may also be part of the lid 110. To facilitate heat transfer from the IC die 102 and other components of the chip package 100 to the lid 110, the lid 110 and the stiffener 108 may be made of a thermally conductive material, such as copper, aluminum, copper-clad aluminum, nickel-plated copper or aluminum, and other suitable materials.

[0039] The substrate 104 typically includes a core 112 sandwiched between an upper buildup layer 114 and a lower buildup layer 116. The core 112 is typically made of silicon or other rigid dielectric materials. In one example, the core 112 is made of an inorganic material. The core 112 includes conductive vias 124 for transmitting power, ground, and data signals between the substrate 104 and the IC die 102.

[0040] The upper buildup layer 114 includes patterned wiring 118 formed from multiple metal layers separated by dielectric layers. The patterned wiring 118 typically includes conductive lines 120 formed from the metal layers connected by conductive vias 122. The wiring 118 in the upper buildup layer 114 typically couples the vias 124 formed in the core 112 to exposed pads 126 formed on the top surface 140 of the substrate 104. The exposed pads 126 are connected to the IC die 102 through solder balls 128 or other suitable connections so that functional circuitry 132 residing on the IC die 102 can receive power, ground, and data signals through the substrate 104.

[0041] Lower buildup layer 116 is typically fabricated identically to upper buildup layer 114. Wiring 134 in lower buildup layer 116 typically couples vias 124 formed in core 112 to exposed pads 146 formed on a bottom surface 144 of substrate 104. Exposed pads 146 connect to PCB 106 via solder balls 148 or other suitable connections so that functional circuitry 132 of IC die 102 can communicate with circuitry of PCB 106 through substrate 104 (i.e., through circuitry of substrate 104 formed by wiring 118, 134 of upper and lower buildup layers 114, 116 and vias 124 formed in core 112).

[0042] The core 112 of the substrate 104 has one or more cavities 150 in which one or more chiplets 152 are embedded. The chiplets 152 are configured to provide predefined functions utilized by the IC die 102. Figure 1In the example depicted in FIG, a chiplet 152 has an integrated voltage regulator circuit 154. The voltage regulator circuit 154 includes a power wiring field effect transistor (power FET). The integrated voltage regulator (IVR) chiplet 152 is preformed and mounted in a cavity 150 formed in the core 112 of the substrate 104. The IVR chiplet 152 is connected to the V provided by the PCB 106 through the wiring 134 of the lower buildup layer 116. in The output of the IVR chiplet 152 is connected to the input of an inductor 160. The output of the inductor 160 is connected to the functional circuitry 132 of the IC die 102 through wiring 118 of the upper buildup layer 114. The inductor 160 can be an air core inductor formed in the substrate 104 or a preformed inductor disposed in a cavity of the core 112 of the substrate 104. In one example, the inductor 160 is made of a preformed magnetic material.

[0043] A dielectric filler 156 fills the one or more cavities 150 holding the inductor 160 and the chiplet 152. The dielectric filler 156 may be an epoxy or other suitable potting compound. The inductor 160 and the connected IVR chiplet 152 may reside in the same or different cavities 150. Figure 1 In the example depicted in , the inductor 160 and connected IVR chiplet 152 reside in a common cavity 150 located directly beneath the IC die 102 to minimize wiring length and improve performance.

[0044] Capacitor 158 is also coupled to wiring extending between the output of the inductor and IC die 102. Capacitor 158 may be located in a cavity formed in core 112 of substrate 104, surface mounted to the exterior of substrate 104, or mounted or formed in another location within chip package 100. Figure 1 , capacitor 158 is shown in two alternative locations, namely, within core 112 of substrate 104 and surface mounted to top surface 104 of substrate 140 .

[0045] The IVR chiplet includes a backside material layer. The backside material layer is connected to electrically floating wiring formed in upper buildup layer 114, which serves as a thermal via. The thermal via effectively transfers heat from the backside material layer to the silicon of IC die 102, through which the heat can be transferred to lid 110, thereby cooling the IVR chiplet.

[0046] Figure 2 is another example of a chip package 200 , which is illustrated as having at least one IC die 102 mounted on a substrate 204 having a die-embedded chiplet 152 . Figure 2 The chip package 200 is constructed with Figure 1The chip package 100 is substantially the same as the IC die 102 except that the IVR chiplet 152 is disposed laterally outside the IC die 102. The inductor 160 coupled to the IVR chiplet 152 can optionally be disposed in the same cavity 150 as the IVR chiplet 152, or as Figure 2 As illustrated, the inductor 160 may be disposed directly below the IC die 102. Figure 2 The capacitor 158 is not shown, but it should be understood that the capacitor 158 is Figure 1 Any way described to connect to Figure 2 The output of the inductor 160.

[0047] Continue to refer Figure 2 , the IVR chiplet 152 is located below the stiffener 108, and in one example, directly below the stiffener 108, further outside of the IC die 102. The IVR chiplet 152 includes a backside material layer 210. Electrically floating wiring 212 formed in the upper buildup layer 114 is connected to the backside material layer 210 disposed on the IVR chip 152. The electrically floating wiring 212 extends upward through the upper buildup layer 114 to the stiffener 108. Thus, the electrically floating wiring 212 provides a conductive heat transfer path from the backside material layer 210 disposed on the IVR chip 152, through the stiffener 108, directly to the lid 110. This improves thermal regulation of the IVR chip 152, although in some examples, performance may not be as good as Figure 1 As robust as the configuration.

[0048] Figures 3A to 3I Depicted in Figure 4 The different stages of the manufacturing method 400 depicted in FIG. Figure 1 The substrate 104 is used in the chip package 100 . Figure 2 The chip package 200 can be similarly manufactured, except that the inductor 160 and the IVR chiplet 152 do not share a common cavity 150 within the core 112 of the substrate 104. The method 400 can be used for other substrates used in chip packages having different configurations.

[0049] Operation 402 of the manufacturing method 400 begins with pre-patterning the core 112, such as Figure 3A The pre-patterned core 112 includes the core 112 itself and the conductive vias 124 formed therein. The portion of the core 112 above the conductive vias includes a patterned metal layer that will later be part of the routing of the upper and lower buildup layers 116.

[0050] Operation 402 of the manufacturing method 400 continues by: Figure 3BAs shown, the pre-patterned core 112 is laminated with a tape 302 (such as a die attach tape) and a cavity 150 is formed in the core 112. The cavity 150 may be formed by drilling, milling, laser ablation, or other suitable techniques. Figure 3B One cavity 150 is shown in FIG, but many cavities are formed in the substrate 104.

[0051] The manufacturing method 400 continues at operation 404 by securing the IVR chiplet 152 (or other type of chiplet) in the cavity 150 by attaching the IVR chiplet 152 to the portion of the tape 302 exposed at the bottom of the cavity 150, as shown. Figure 3C Similarly, at operation 404, the inductor 160 is also secured in the cavity 150 by attaching the inductor 160 along with the chiplet 152 to the ribbon 302. Figure 3C In the embodiment, both the inductor 160 and the IVR chiplet 152 are disposed in the same cavity 150. It is also contemplated that, for example, when configured for Figure 2 In the illustrated substrate 104 of the chip package 200 , the inductor 160 and the IVR chiplet 152 are disposed in separate cavities 150 .

[0052] The manufacturing method 400 continues at operation 406 by: Figure 3D As shown, the cavity is filled with a dielectric filler 156. The dielectric filler 156 also extends over the core 112 of the substrate 104 and the portion of the metal layer exposed on top of the via 124. The dielectric filler 156 secures the IVR chiplet 152 and the inductor 160 in the cavity 150. The manufacturing method 400 continues at operation 408 by: Figure 3E As shown, the tape 302 is removed from the substrate 104 , which exposes the terminals 304 of the IVR chiplet 152 and the input 306 of the inductor 160 disposed in the cavity 150 .

[0053] The manufacturing method 400 continues at operation 410 by: Figure 3F As shown, a dielectric layer 308 is disposed on the bottom surface 410 of the substrate core 112. The dielectric layer 308 covers the terminals 404 of the IVR chiplet 152 and the input 406 of the inductor 160 that were previously covered by the tape 302.

[0054] The manufacturing method 400 continues at operation 412 where a via opening 312 is formed in the dielectric filler 156 and the dielectric layer 408, as shown in FIG. Figure 3GAs shown. The via opening 312 may be formed by drilling or other suitable techniques. The via opening 312 exposes a portion of the metal layer formed over the via 124 on the bottom surface 144 of the substrate 104, as well as the terminal 404 of the IVR chiplet 152 and the input 406 of the inductor 160 on the bottom surface 144 of the substrate 104. The via opening 312 also exposes a portion of the metal layer formed over the via 124 on the top surface 140 of the substrate 104, as well as the backside metal layer 210 disposed on the IVR chiplet 152 and the output 314 of the inductor 160 exposed on the top surface 140 of the substrate 104.

[0055] The manufacturing method 400 continues at operation 414 by depositing a conductive seed layer 316 over the via opening 312 and the exposed surfaces of the filler 156 and the dielectric layer 308, as shown in FIG. Figure 3H The conductive seed layer 316 contacts the portion of the metal layer formed over the via 124 on the bottom surface 310 of the substrate 104, the terminal 404 of the IVR chiplet 152 exposed by the via opening 312 on the bottom surface 310 of the substrate 104, and the input 406 of the inductor 160. The conductive seed layer 316 also contacts the portion of the metal layer formed over the via 124 on the top surface 140 of the substrate 104, the backside metal layer 210 disposed on the IVR chiplet 152 exposed by the via opening 312 on the top surface 140 of the substrate 104, and the output 314 of the inductor 160.

[0056] After the seed layer is deposited, photolithographic patterning and plating processes are performed at operation 416 to form metal lines and vias, such as Figure 3I As shown. Some of the metal lines and vias contact the backside metal layer 210 of the IVR chiplet 152 to form thermal vias. Some of the other metal lines and vias form wiring 118, 134 of the upper and lower buildup layers 116. At least some of the other metal lines and vias form wiring that connects the output terminal 304 of the IVR chiplet 152 to the input 406 of the inductor 160. At this point, at operation 416, the IC die 102 can be secured to the upper buildup layer 114 to form the circuit shown in FIG. Figures 1 to 2 The chip packages 100 and 200 are shown as examples.

[0057] Figures 5A to 5F Depicted in Figure 6 The different stages of the manufacturing method 600 depicted in FIG. Figure 1 The magnetic inductor 500 used in the chip package 100 can be used as Figures 1 to 2The inductor 160 is shown in the illustrated chip packages 100 and 200. The inductor 500 manufactured using the method 600 can be used in other substrates used in chip packages having different configurations, or for other desired applications.

[0058] The manufacturing method 600 of the magnetic inductor 500 is as follows Figure 5A The diagram begins with a sheet of magnetic material 502. In one example, the magnetic material is a pre-cured ferrite sheet 502, but other magnetic materials can be used. At operation 602, a hole 504 is formed through the sheet 502. The hole 504 can be formed by drilling, laser cutting, milling, or other suitable techniques.

[0059] At operation 604, a seed layer 506 is deposited on the magnetic material sheet 502, such as Figure 5C Seed layer 506 also covers sidewalls 508 of hole 504 passing through sheet 502 .

[0060] At operation 606, the seed layer 506 is patterned and etched, leaving the seed layer 506 covering the sidewalls 508 of the hole 504 through the sheet 502. At operation 608, a first conductive material 510 is then deposited on the seed layer 506, as shown in FIG. Figure 5D In one example, a first conductive material 510 is then plated on the seed layer 506. The first conductive material 510 plated on the seed layer 506 can be copper or other suitable conductive materials.

[0061] At operation 610, the plated through-holes 504 are then plugged with a dielectric material 512. The dielectric material 512 is then ground flat to expose the ends 514 of the first conductive material 510 disposed within the through-holes 504 at the top 516 and bottom 518 of the sheet 502. A second conductive layer 520 is then deposited on both sides of the sheet 502. In one example, the second conductive layer 520 is plated on both sides of the sheet 502. The second conductive layer 520 disposed on the top 516 and bottom 518 of the magnetic material sheet 502 contacts the exposed ends 514 of the plated conductive material 510 disposed within the through-holes 504. Thus, the second conductive layer 520 on the top 516 and bottom 518 of the magnetic material sheet 502 is electrically connected through the first conductive material 510 disposed within the through-holes, as shown in FIG. Figure 5E shown.

[0062] At operation 612, the plated sheet 502 is then cut to form a magnetic inductor 500, wherein the second conductive layer 520 disposed on the bottom 518 of the magnetic material sheet 502 forms the input terminal of the inductor 500, the second conductive layer 520 disposed on the top 516 of the magnetic material sheet 502 forms the output terminal of the inductor, and the input terminal and the output terminal are connected through the plated hole surrounded by the magnetic material, as shown in FIG. Figure 5F Optionally, the obstruction can be removed.

[0063] Once the inductor 500 is formed, the inductor 500 may be disposed in a substrate as described above with reference to the above-described fabrication method 400 or by a suitable alternative technique.

[0064] 7A to 7D Depicted in Figure 8 The various stages of the manufacturing method 800 depicted in FIG. Figures 1 to 2 A substrate 700 having a magnetic inductor 710 is provided for use in the chip packages 100 and 200 of the present invention. The substrate 700 may alternatively be used in other chip packages.

[0065] The method 800 begins at operation 802 by forming a cavity 750 in the core 730 of the substrate 700, such as Figure 7A Cavity 750 may be formed as described above with reference to cavity 150. Cavity 750 may also be formed by alternative suitable techniques.

[0066] At operation 804, a block of magnetic material 710 is placed in the cavity 750, as shown in FIG. Figure 7B Block 710 may be secured in cavity 750 by any suitable technique, such as, for example, using a potting compound.

[0067] At operation 806, Figure 7C As illustrated, a via 712 is formed through a block of magnetic material 710. A via 702 is also formed through a core 730 of a substrate 700. Vias 702 and 712 may be formed by drilling or other suitable techniques. Vias 702 and 712 may be formed simultaneously or at different times. Vias 702 are used to route signals, ground, and power through the substrate to the IC die of the chip package.

[0068] At operation 808, Figure 7D As illustrated, vias 702, 712 are filled with conductive material 704, 714. Vias 702, 712 may be filled with conductive material 704, 714 by plating. A seed layer (not shown) may be disposed between conductive material 704, 714 and core 730 and block of magnetic material 710. In one example, conductive material 704, 714 is copper. Alternatively, conductive material 704, 714 may be another metal suitable for signal and / or power transmission.

[0069] After operation 808, the chiplet is similarly secured to the core 730 of the substrate 700, and then a buildup layer is formed on the core 730 of the substrate 700, such as described above with reference to Figure 4 After forming buildup layers and wiring on the core, the substrate 700 is used to manufacture a chip package, such as but not limited to the chip packages 100 and 200 described above.

[0070] 9A to 9D Depicted in Figure 10 The various stages of the manufacturing method 1000 depicted in FIG. Figures 1 to 2 A substrate 900 having a magnetic inductor 910 is provided for use in the chip packages 100 and 200 of the present invention. The substrate 900 may alternatively be used in other chip packages.

[0071] The method 1000 begins at operation 1002 by forming a cavity 950 in a core 930 of a substrate 900, such as Figure 9A Cavity 950 may be formed as described above.

[0072] At operation 1004, a block of magnetic material 910 is placed in the cavity 950, as shown in FIG. Figure 9B Block 910 may be secured in cavity 950 by any suitable technique, such as, for example, using a potting compound. Block 910 of magnetic material includes preformed vias 912 .

[0073] At operation 1006, Figure 9C As illustrated, a via 902 is formed through the core 930 of the substrate 900. The via 902 may be formed by drilling or other suitable techniques. The via 902 may be formed before or after the block 910 is secured within the cavity 950 of the core 930 of the substrate 900.

[0074] At operation 1008, Figure 9D As illustrated, vias 902, 912 are filled with conductive material 904, 914. Vias 902, 912 may be filled with conductive material 904, 914 by plating. A seed layer (not shown) may be disposed between conductive material 904, 914 and core 930 and block of magnetic material 910. In one example, conductive material 904, 914 is copper. Alternatively, conductive material 904, 914 may be another metal suitable for signal and / or power transmission.

[0075] Before or after any one or more of operations 1002, 1004, 1006, and / or 1008, the chiplet is similarly secured to the core 930 of the substrate 900. After securing the chiplet to the core 930 of the substrate 900, a buildup layer is formed on the core 930 of the substrate 900, for example, as described above with reference to Figure 4After forming buildup layers and wiring on the core, the substrate 900 is used to manufacture a chip package, such as but not limited to the chip packages 100 and 200 described above.

[0076] While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope of the invention is determined by the claims that follow.

Claims

1. A chip package, comprising: an integrated circuit (IC) die having functional circuitry; A substrate on which the IC die is mounted, the substrate comprising: a core having at least a first cavity, an inductor routing via, a plurality of signal transmission vias, a plurality of ground routing vias, and a plurality of power routing vias; an upper buildup layer disposed on the core between the core and the IC die, the upper buildup layer including wiring that couples the inductor wiring vias, the signal transmission vias, and the ground and power wiring vias to the functional circuits of the IC die; and a lower buildup layer disposed on a side of the core opposite the upper buildup layer, the lower buildup layer including wiring coupled to the functional circuitry of the IC die through the vias of the core and the wiring of the upper buildup layer; and A chiplet is disposed in a first cavity formed in the core, the chiplet being coupled to the functional circuitry of the IC die through an upper buildup layer. 2 . The chip package of claim 1 , wherein the chiplet comprises a voltage regulator circuit.

3. The chip package according to claim 2, further comprising: An inductor has an input and an output, the input coupled to the outlet of the voltage regulator circuit and the output coupled to the functional circuit of the IC die. 4 . The chip package of claim 3 , wherein the inductor is coupled to the voltage regulator circuit through the wiring of the lower build-up layer. The chip package according to claim 4 , wherein the inductor is disposed in the first cavity.

6. The chip package according to claim 4, wherein the inductor is disposed in a second cavity formed in the core; and The chiplet further includes a backside metal layer.

7. The chip package according to claim 6, wherein the upper buildup layer further comprises: A thermal via is formed on the backside metal layer.

8. The chip package according to claim 7, further comprising: a reinforcement member, the reinforcement member being disposed on the substrate and located directly above the thermal via; as well as A lid is disposed over the IC die and the stiffener, wherein the stiffener and the thermal vias provide a conductive path operable to conduct heat from the backside metal layer to the lid.

9. The chip package of claim 5 , wherein the chiplet further comprises: Backside metal layer.

10. The chip package according to claim 9, wherein the upper build-up layer further comprises: A thermal via is formed on the backside metal layer and extends to a top surface of the substrate. 11 . The chip package of claim 5 , wherein the inductor is a pre-fabricated component and is fixed in the substrate by a dielectric filler.

12. The chip package according to claim 3, further comprising: A capacitor has one terminal coupled to both the functional circuit of the IC die and the output of the inductor.

13. A chip package, comprising: an integrated circuit (IC) die having functional circuitry; A substrate on which the IC die is mounted, the substrate comprising: a core having one or more cavities, a plurality of signal routing vias, an inductor routing via, a plurality of ground routing vias, and a plurality of power routing vias; an upper buildup layer disposed on the core between the core and the IC die, the upper buildup layer including wiring that couples the inductor wiring vias, the signal transmission vias, and the ground and power wiring vias to the functional circuits of the IC die; and a lower buildup layer disposed on a side of the core opposite the upper buildup layer, the lower buildup layer including wiring coupled to the functional circuitry of the IC die through the vias of the core and the wiring of the upper buildup layer; a chiplet disposed in the one or more cavities formed in the core, the chiplet having voltage regulation circuitry coupled to the functional circuitry of the IC die through an upper buildup layer; and An inductor is disposed in the one or more cavities formed in the core, the inductor having an input and an output, the input coupled to the outlet of the voltage regulator circuit and the output coupled to the functional circuit of the IC die. 14 . The chip package of claim 13 , wherein the inductor and the chiplet are disposed in a common cavity of the one or more cavities formed in the core, the common cavity being disposed directly beneath the IC die. 15 . The chip package according to claim 13 , further comprising: a stiffener disposed on the substrate directly above the one or more cavities in which the chiplets reside; a backside metal layer formed on the chiplet; a thermal via, wherein the thermal via is formed on the back metal layer and is disposed directly below the reinforcement; as well as A lid is disposed over the IC die and the stiffener, wherein the stiffener and the thermal vias provide a conductive path operable to conduct heat from the backside metal layer to the lid.

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